JP2008060298A - Semiconductor constitutional body and its manufacturing method, and semiconductor device and its manufacturing method - Google Patents

Semiconductor constitutional body and its manufacturing method, and semiconductor device and its manufacturing method Download PDF

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JP2008060298A
JP2008060298A JP2006235011A JP2006235011A JP2008060298A JP 2008060298 A JP2008060298 A JP 2008060298A JP 2006235011 A JP2006235011 A JP 2006235011A JP 2006235011 A JP2006235011 A JP 2006235011A JP 2008060298 A JP2008060298 A JP 2008060298A
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columnar electrode
wiring
electrode portion
semiconductor
semiconductor structure
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Shinji Wakizaka
伸治 脇坂
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

<P>PROBLEM TO BE SOLVED: To enlarge a diameter in an upper surface of a columnar electrode and to widen an interval between connecting pads of wiring even if a pitch of the columnar electrode is fixed in a semiconductor device, wherein a semiconductor constitutional body with a columnar electrode in an upper surface of the connection pads of wiring is arranged on a base board. <P>SOLUTION: A columnar electrode 12 of a semiconductor constitutional body 2 has a two-step structure of a lower columnar electrode 12a, and an upper columnar electrode 12b whose diameter is larger than that of the lower columnar electrode 12a. Consequently, it is possible to widen a clearance between connection pads 11b of a wiring 11 supporting the lower columnar electrode 12a, and to arrange two taking-around lines 11c of the wiring 11. Furthermore, it is possible to enlarge a diameter of the upper columnar electrode 12b, and to enlarge a diameter of an opening 16 formed by laser processing by irradiation of laser beam in an upper layer insulating film 15 provided thereon. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

この発明は半導体構成体およびその製造方法並びに半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor structure, a manufacturing method thereof, a semiconductor device, and a manufacturing method thereof.

従来の半導体装置には、例えば図１８に示すように、半導体基板５１上に複数の柱状電極５２を有する半導体構成体５３をそれよりも平面サイズの大きいベース板５４上に接着層５５を介して配置し、半導体構成体５３の周囲におけるベース板５４上に絶縁層５６を設け、半導体構成体５３および絶縁層５６上に上層絶縁膜５７を設け、上層絶縁膜５７上に上層配線５８を半導体構成体５３の柱状電極５２に接続させて設け、上層配線５８の接続パッド部を除く部分をオーバーコート膜５９で覆い、上層配線５８の接続パッド部上に半田ボール６０を設けたものがある（例えば、特許文献１参照）。   In a conventional semiconductor device, for example, as shown in FIG. 18, a semiconductor structure 53 having a plurality of columnar electrodes 52 on a semiconductor substrate 51 is placed on a base plate 54 having a larger planar size via an adhesive layer 55. The insulating layer 56 is provided on the base plate 54 around the semiconductor structure 53, the upper insulating film 57 is provided on the semiconductor structure 53 and the insulating layer 56, and the upper wiring 58 is provided on the upper insulating film 57 in the semiconductor structure. In some cases, the body 53 is connected to the columnar electrode 52, the portion excluding the connection pad portion of the upper wiring 58 is covered with an overcoat film 59, and the solder ball 60 is provided on the connection pad portion of the upper wiring 58 (for example, , See Patent Document 1).

特開２００５−１４２４６６号公報JP 2005-142466 A

上記従来の半導体装置における半導体構成体５３は、一般的にはＣＳＰ(chip size package)と呼ばれるものであり、上面に複数の接続パッド６１を有する半導体基板５１上に絶縁膜６２および保護膜６３が設けられ、保護膜６３上に下地金属層６４を含む配線６５が接続パッド６１に接続されて設けられ、配線６５の接続パッド部上面に柱状電極５２が設けられ、配線６５を含む保護膜６３上に封止膜６６がその上面が柱状電極５２の上面と面一となるように設けられた構造となっている。   The semiconductor structure 53 in the conventional semiconductor device is generally called a CSP (chip size package), and an insulating film 62 and a protective film 63 are formed on a semiconductor substrate 51 having a plurality of connection pads 61 on the upper surface. The wiring 65 including the base metal layer 64 is provided on the protective film 63 so as to be connected to the connection pad 61, the columnar electrode 52 is provided on the upper surface of the connection pad portion of the wiring 65, and on the protective film 63 including the wiring 65. The sealing film 66 has a structure in which the upper surface thereof is flush with the upper surface of the columnar electrode 52.

この場合、配線６５（下地金属層６４を含む）は、接続パッド６１に接続された接続部６５ａと、先端の平面円形状の接続パッド部６５ｂと、その間の引き回し線部６５ｃとからなっている。配線６５の平面円形状の接続パッド部６５ｂ上面に設けられた柱状電極５２は円柱形状である。上層下地金属層７１を含む上層配線５８の一端部は、上層絶縁膜５７にレーザビームの照射によるレーザ加工により形成された円形状の開口部７２を介して柱状電極５２の上面に接続されている。   In this case, the wiring 65 (including the base metal layer 64) includes a connection portion 65a connected to the connection pad 61, a planar circular connection pad portion 65b at the tip, and a lead wire portion 65c therebetween. . The columnar electrode 52 provided on the upper surface of the planar circular connection pad portion 65b of the wiring 65 has a cylindrical shape. One end of the upper wiring 58 including the upper base metal layer 71 is connected to the upper surface of the columnar electrode 52 through a circular opening 72 formed in the upper insulating film 57 by laser processing by laser beam irradiation. .

ここで、上記構成の半導体構成体５３の寸法の一例について説明する。配線６５の引き回し線部６５ｃの線幅および配線６５間の間隔が最小寸法で共に２０μｍ（図１８では２ｍｍに相当する、以下同じ）であるとき、柱状電極５２のピッチを２５０μｍとした場合には、柱状電極５２の直径を１５０μｍとすると、柱状電極５２を支持する配線６５の接続パッド部６５ｂの直径が（片側での許容精度が１０μｍであると両側で２０μｍとなるので）１７０μｍとなり、相隣接する配線６５の接続パッド部６５ｂ間の間隔が８０μｍとなり、相隣接する配線６５の接続パッド部６５ｂ間に配置し得る配線６５の引き回し線部６５ｃの本数が１本となる。   Here, an example of the dimensions of the semiconductor structure 53 having the above configuration will be described. When the line width of the lead-out line portion 65c of the wiring 65 and the interval between the wirings 65 are both 20 μm (corresponding to 2 mm in FIG. 18, the same applies hereinafter) in the minimum dimension, the pitch of the columnar electrodes 52 is 250 μm. When the diameter of the columnar electrode 52 is 150 μm, the diameter of the connection pad portion 65b of the wiring 65 supporting the columnar electrode 52 is 170 μm (because the allowable accuracy on one side is 20 μm on both sides) and is 170 μm. The interval between the connection pad portions 65b of the wiring 65 to be connected is 80 μm, and the number of the routing line portions 65c of the wiring 65 that can be arranged between the connection pad portions 65b of the adjacent wirings 65 is one.

ところで、柱状電極５２の直径は、大きいほど、上層絶縁膜５７にレーザビームの照射によるレーザ加工により形成される円形状の開口部７２の直径を大きくすることができ、上層下地金属層７１を含む上層配線５８の一端部の当該開口部７２を介しての柱状電極５２の上面に対する接合の信頼性が向上し、また当該開口部７２の柱状電極５２に対する位置ずれの許容精度を大きくすることができる。   By the way, the larger the diameter of the columnar electrode 52, the larger the diameter of the circular opening 72 formed in the upper insulating film 57 by laser processing by laser beam irradiation, and the upper base metal layer 71 is included. The reliability of joining the upper end of the upper wiring 58 to the upper surface of the columnar electrode 52 through the opening 72 can be improved, and the tolerance of positional deviation of the opening 72 with respect to the columnar electrode 52 can be increased. .

しかしながら、柱状電極５２のピッチを２５０μｍとした場合において、柱状電極５２の直径を１５０μｍと大きくすると、柱状電極５２を支持する配線６５の接続パッド部６５ｂの直径も１７０μｍと大きくなり、相隣接する配線６５の接続パッド部６５ｂ間の間隔が８０μｍと狭くなり、相隣接する配線６５の接続パッド部６５ｂ間に配置し得る配線６５の引き回し線部６５ｃの本数が１本と少なくなり、配線６５の引き回しに制約を受けることになる。   However, when the pitch of the columnar electrodes 52 is 250 μm, when the diameter of the columnar electrodes 52 is increased to 150 μm, the diameter of the connection pad portion 65b of the wiring 65 supporting the columnar electrode 52 is also increased to 170 μm. The spacing between the 65 connection pad portions 65b is as narrow as 80 μm, and the number of the routing line portions 65c of the wiring 65 that can be disposed between the connection pad portions 65b of the adjacent wirings 65 is reduced to one. Will be subject to restrictions.

一方、柱状電極５２のピッチを２５０μｍとした場合において、配線６５の数が多くなり、相隣接する配線６５の接続パッド部６５ｂ間に配置すべき配線６５の引き回し線部６５ｃの本数を例えば２本と多くすると、相隣接する配線６５の接続パッド部６５ｂ間の間隔を１００μｍ以上と広くしなければならず、ひいては柱状電極５２の直径を小さくしなければならず、上層絶縁膜５７にレーザビームの照射によるレーザ加工により形成される円形状の開口部７２の直径も小さくしなければならず、また当該開口部７２の柱状電極５２に対する位置精度として高いものが要求されることになる。   On the other hand, when the pitch of the columnar electrodes 52 is 250 μm, the number of the wirings 65 increases, and the number of the lead-out line portions 65c of the wiring 65 to be arranged between the connection pad portions 65b of the adjacent wirings 65 is, for example, two If the number is larger, the distance between the connection pad portions 65b of the adjacent wirings 65b must be widened to 100 μm or more, and the diameter of the columnar electrode 52 must be reduced, and the laser beam is applied to the upper insulating film 57. The diameter of the circular opening 72 formed by laser processing by irradiation must also be reduced, and a high positional accuracy of the opening 72 with respect to the columnar electrode 52 is required.

そこで、この発明は、柱状電極の上面における直径を大きくすることができ、且つ、柱状電極を支持する配線の接続パッド部間の間隔を広くすることができる半導体構成体およびその製造方法を提供することを目的とする。
また、この発明は、半導体構成体上に設けられる上層絶縁膜の半導体構成体の柱状電極の上面中央部に対応する部分に形成される開口部の直径を大きくすることができる半導体装置およびその製造方法を提供することを目的とする。 Accordingly, the present invention provides a semiconductor structure that can increase the diameter of the upper surface of the columnar electrode and can increase the interval between connection pad portions of the wiring that supports the columnar electrode, and a method for manufacturing the same. For the purpose.
The present invention also provides a semiconductor device capable of increasing the diameter of an opening formed in a portion corresponding to the central portion of the upper surface of the columnar electrode of the semiconductor structure of the semiconductor structure of the upper insulating film provided on the semiconductor structure, and its manufacture It aims to provide a method.

この発明は、上記目的を達成するため、半導体構成体の柱状電極を下部柱状電極部および該下部柱状電極部よりも大径の上部柱状電極部からなる２段構造としたことを特徴とするものである。   In order to achieve the above object, the present invention is characterized in that the columnar electrode of the semiconductor structure has a two-stage structure including a lower columnar electrode portion and an upper columnar electrode portion having a larger diameter than the lower columnar electrode portion. It is.

この発明によれば、半導体構成体の柱状電極を下部柱状電極部および該下部柱状電極部よりも大径の上部柱状電極部からなる２段構造としているので、下部柱状電極部よりも大径の上部柱状電極の直径を比較的大きくすることができ、且つ、上部柱状電極よりも小径の下部柱状電極部を支持する配線の接続パッド部間の間隔を比較的広くすることができる。この結果、相隣接する配線の接続パッド部間に配線の引き回し線部を２本と多く配置することが可能となり、且つ、半導体構成体上に設けられる上層絶縁膜の半導体構成体の柱状電極の上面中央部に対応する部分に形成される開口部の直径を大きくすることが可能となる。   According to the present invention, the columnar electrode of the semiconductor structure has a two-stage structure including the lower columnar electrode portion and the upper columnar electrode portion having a larger diameter than the lower columnar electrode portion. The diameter of the upper columnar electrode can be made relatively large, and the interval between the connection pad portions of the wiring supporting the lower columnar electrode portion having a smaller diameter than the upper columnar electrode can be made relatively wide. As a result, it is possible to arrange as many as two wiring lead lines between the connection pads of adjacent wirings, and the columnar electrodes of the semiconductor structure of the upper insulating film provided on the semiconductor structure. It becomes possible to increase the diameter of the opening formed in the portion corresponding to the central portion of the upper surface.

（第１実施形態）
図１はこの発明の第１実施形態としての半導体装置の断面図を示す。この半導体装置は、ガラス布基材エポキシ樹脂等からなる平面方形状のベース板１を備えている。ベース板１の上面には、ベース板１のサイズよりもある程度小さいサイズの平面方形状の半導体構成体２の下面がダイボンド材からなる接着層３を介して接着されている。 (First embodiment)
FIG. 1 is a sectional view of a semiconductor device as a first embodiment of the present invention. This semiconductor device includes a planar rectangular base plate 1 made of a glass cloth base epoxy resin or the like. On the upper surface of the base plate 1, the lower surface of a planar rectangular semiconductor structure 2 having a size somewhat smaller than the size of the base plate 1 is bonded via an adhesive layer 3 made of a die bond material.

半導体構成体２は、一般的にはＣＳＰと呼ばれるものであり、シリコン基板（半導体基板）４を備えている。シリコン基板４の下面は接着層３を介してベース板１の上面に接着されている。シリコン基板４の上面には所定の機能の集積回路（図示せず）が設けられ、上面周辺部にはアルミニウム系金属等からなる複数の接続パッド５が集積回路に接続されて設けられている。   The semiconductor structure 2 is generally called a CSP and includes a silicon substrate (semiconductor substrate) 4. The lower surface of the silicon substrate 4 is bonded to the upper surface of the base plate 1 via the adhesive layer 3. An integrated circuit (not shown) having a predetermined function is provided on the upper surface of the silicon substrate 4, and a plurality of connection pads 5 made of aluminum-based metal or the like are provided on the periphery of the upper surface so as to be connected to the integrated circuit.

接続パッド５の中央部を除くシリコン基板４の上面には酸化シリコン等からなる絶縁膜６が設けられ、接続パッド５の中央部は絶縁膜６に設けられた開口部７を介して露出されている。絶縁膜６の上面にはポリイミド系樹脂等からなる保護膜８が設けられている。絶縁膜６の開口部７に対応する部分における保護膜８には開口部９が設けられている。   An insulating film 6 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 4 excluding the central portion of the connection pad 5, and the central portion of the connection pad 5 is exposed through an opening 7 provided in the insulating film 6. Yes. A protective film 8 made of polyimide resin or the like is provided on the upper surface of the insulating film 6. An opening 9 is provided in the protective film 8 at a portion corresponding to the opening 7 of the insulating film 6.

保護膜８の上面には銅等からなる下地金属層１０が設けられている。下地金属層１０の上面全体には銅からなる配線１１が設けられている。下地金属層１０を含む配線１１の一端部は、絶縁膜６および保護膜８の開口部７、９を介して接続パッド５に接続されている。ここで、配線１１（下地金属層１０を含む）は、接続パッド５に接続された接続部１１ａと、先端の平面円形状の接続パッド部１１ｂと、その間の引き回し線部１１ｃとからなっている。   A base metal layer 10 made of copper or the like is provided on the upper surface of the protective film 8. A wiring 11 made of copper is provided on the entire upper surface of the base metal layer 10. One end of the wiring 11 including the base metal layer 10 is connected to the connection pad 5 through the openings 7 and 9 of the insulating film 6 and the protective film 8. Here, the wiring 11 (including the base metal layer 10) includes a connection part 11a connected to the connection pad 5, a planar circular connection pad part 11b at the tip, and a lead line part 11c therebetween. .

配線１１の接続パッド部１１ｂ上面には銅からなる柱状電極１２が設けられている。この場合、柱状電極１２は、円柱形状の下部柱状電極部１２ａの上面に該下部柱状電極部１２ａよりも大径の円柱形状の上部柱状電極部１２ｂが設けられた２段構造となっている。上部柱状電極部１２ｂの高さは下部柱状電極部１２ａの高さよりも低くなっている。   A columnar electrode 12 made of copper is provided on the upper surface of the connection pad portion 11 b of the wiring 11. In this case, the columnar electrode 12 has a two-stage structure in which a columnar upper columnar electrode portion 12b having a larger diameter than the lower columnar electrode portion 12a is provided on the upper surface of the columnar lower columnar electrode portion 12a. The height of the upper columnar electrode portion 12b is lower than the height of the lower columnar electrode portion 12a.

配線１１を含む保護膜８の上面にはエポキシ系樹脂等からなる封止膜１３がその上面が柱状電極１２の上面と面一となるように設けられている。ここで、半導体構成体２は、シリコン基板４、接続パッド５、絶縁膜６、保護膜８、下地金属層１０、配線１１、柱状電極１２、封止膜１３により構成されている。   A sealing film 13 made of an epoxy resin or the like is provided on the upper surface of the protective film 8 including the wiring 11 so that the upper surface is flush with the upper surface of the columnar electrode 12. Here, the semiconductor structure 2 includes a silicon substrate 4, a connection pad 5, an insulating film 6, a protective film 8, a base metal layer 10, a wiring 11, a columnar electrode 12, and a sealing film 13.

半導体構成体２の周囲におけるベース板１の上面には方形枠状の絶縁層１４が設けられている。絶縁層１４は、例えば、エポキシ系樹脂やポリイミド系樹脂等の熱硬化性樹脂中にシリカフィラー等の無機材料からなる補強材を分散させたもの、あるいは、エポキシ系樹脂等の熱硬化性樹脂のみからなっている。   A rectangular frame-shaped insulating layer 14 is provided on the upper surface of the base plate 1 around the semiconductor structure 2. For example, the insulating layer 14 is obtained by dispersing a reinforcing material made of an inorganic material such as silica filler in a thermosetting resin such as an epoxy resin or a polyimide resin, or only a thermosetting resin such as an epoxy resin. It is made up of.

半導体構成体２および絶縁層１４の上面には上層絶縁膜１５がその上面を平坦とされて設けられている。上層絶縁膜１５は、例えば、ガラス布やガラス繊維等からなる基材にエポキシ系樹脂やポリイミド系樹脂等の熱硬化性樹脂を含浸させたもの、あるいは、エポキシ系樹脂等の熱硬化性樹脂のみからなっている。   An upper insulating film 15 is provided on the upper surfaces of the semiconductor structure 2 and the insulating layer 14 with the upper surfaces thereof being flat. The upper insulating film 15 is, for example, a substrate made of glass cloth or glass fiber impregnated with a thermosetting resin such as an epoxy resin or a polyimide resin, or a thermosetting resin such as an epoxy resin only. It is made up of.

半導体構成体２の柱状電極１２の上部柱状電極部１２ｂの上面中央部に対応する部分における上層絶縁膜１５には円形状の開口部１６が設けられている。上層絶縁膜１５の上面には銅等からなる上層下地金属層１７が設けられている。上層下地金属層１７の上面全体には銅からなる上層配線１８が設けられている。上層下地金属層１７を含む上層配線１８の一端部は、上層絶縁膜１５の開口部１６を介して半導体構成体２の柱状電極１２の上部柱状電極部１２ｂの上面に接続されている。   A circular opening 16 is provided in the upper insulating film 15 in a portion corresponding to the central portion of the upper surface of the upper columnar electrode portion 12b of the columnar electrode 12 of the semiconductor structure 2. An upper base metal layer 17 made of copper or the like is provided on the upper surface of the upper insulating film 15. An upper wiring 18 made of copper is provided on the entire upper surface of the upper base metal layer 17. One end portion of the upper wiring 18 including the upper base metal layer 17 is connected to the upper surface of the upper columnar electrode portion 12 b of the columnar electrode 12 of the semiconductor structure 2 through the opening 16 of the upper insulating film 15.

上層配線１８を含む上層絶縁膜１５の上面にはソルダーレジスト等からなるオーバーコート膜１９が設けられている。上層配線１８の接続パッド部に対応する部分におけるオーバーコート膜１９には開口部２０が設けられている。開口部２０内およびその上方には半田ボール２１が上層配線１８の接続パッド部に接続されて設けられている。   An overcoat film 19 made of a solder resist or the like is provided on the upper surface of the upper insulating film 15 including the upper wiring 18. An opening 20 is provided in the overcoat film 19 in a portion corresponding to the connection pad portion of the upper wiring 18. Solder balls 21 are provided in the upper portion 20 and above the openings 20 so as to be connected to the connection pad portions of the upper wiring 18.

次に、この半導体装置の製造方法の一例について説明するに、まず、半導体構成体２の製造方法の一例について説明する。この場合、まず、図２に示すように、ウエハ状態のシリコン基板（半導体基板）４上にアルミニウム系金属等からなる接続パッド５、酸化シリコン等からなる絶縁膜６およびポリイミド系樹脂等からなる保護膜８が設けられ、接続パッド５の中央部が絶縁膜６および保護膜８に形成された開口部７、９を介して露出されたものを用意する。   Next, an example of a method for manufacturing the semiconductor device 2 will be described. In this case, first, as shown in FIG. 2, on a silicon substrate (semiconductor substrate) 4 in a wafer state, a connection pad 5 made of aluminum metal, an insulating film 6 made of silicon oxide, etc., and a protection made of polyimide resin, etc. A film 8 is provided, and a central portion of the connection pad 5 is exposed through openings 7 and 9 formed in the insulating film 6 and the protective film 8.

次に、図３に示すように、絶縁膜６および保護膜８の開口部７、９を介して露出された接続パッド５の上面を含む保護膜８の上面全体に下地金属層１０を形成する。この場合、下地金属層１０は、無電解メッキにより形成された銅層のみであってもよく、またスパッタにより形成された銅層のみであってもよく、さらにスパッタにより形成されたチタン等の薄膜層上にスパッタにより銅層を形成したものであってもよい。   Next, as shown in FIG. 3, a base metal layer 10 is formed on the entire upper surface of the protective film 8 including the upper surfaces of the connection pads 5 exposed through the openings 7 and 9 of the insulating film 6 and the protective film 8. . In this case, the base metal layer 10 may be only a copper layer formed by electroless plating, or may be only a copper layer formed by sputtering, and a thin film such as titanium formed by sputtering. A copper layer may be formed on the layer by sputtering.

次に、下地金属層１０の上面にメッキレジスト膜３１をパターン形成する。この場合、配線１１形成領域に対応する部分におけるメッキレジスト膜３１には開口部３２が形成されている。次に、下地金属層１０をメッキ電流路として銅の電解メッキを行なうことにより、メッキレジスト膜３１の開口部３２内の下地金属層１０の上面に配線１１を形成する。次に、メッキレジスト膜３１を剥離する。   Next, a plating resist film 31 is pattern-formed on the upper surface of the base metal layer 10. In this case, an opening 32 is formed in the plating resist film 31 in a portion corresponding to the wiring 11 formation region. Next, by performing electrolytic plating of copper using the base metal layer 10 as a plating current path, the wiring 11 is formed on the upper surface of the base metal layer 10 in the opening 32 of the plating resist film 31. Next, the plating resist film 31 is peeled off.

次に、図４に示すように、配線１１を含む下地金属層１０の上面にネガ型の下層メッキレジスト膜３３をパターン形成する。この場合、柱状電極１２の下部柱状電極部１２ａ形成領域に対応する部分における下層メッキレジスト膜３３には円形状の開口部３４が形成されている。次に、下層メッキレジスト膜３３の上面にネガ型の上層メッキレジスト膜３５をパターン形成する。この場合、柱状電極１２の上部柱状電極部１２ｂ形成領域に対応する部分における上層メッキレジスト膜３５には、下層メッキレジスト膜３３の開口部３４よりも大径の円形状の開口部３６が形成されている。   Next, as shown in FIG. 4, a negative type lower plating resist film 33 is formed on the upper surface of the base metal layer 10 including the wiring 11. In this case, a circular opening 34 is formed in the lower plating resist film 33 in a portion corresponding to the formation region of the lower columnar electrode portion 12 a of the columnar electrode 12. Next, a negative upper plating resist film 35 is formed on the upper surface of the lower plating resist film 33 by patterning. In this case, a circular opening 36 having a larger diameter than the opening 34 of the lower plating resist film 33 is formed in the upper plating resist film 35 in the portion corresponding to the upper columnar electrode portion 12b formation region of the columnar electrode 12. ing.

次に、図５に示すように、下地金属層１０をメッキ電流路として銅の電解メッキを行なうことにより、下層メッキレジスト膜３３の開口部３４内の配線１１の接続パッド部１１ｂ上面に下部柱状電極部１２ａを形成し、さらに、上層メッキレジスト膜３５の開口部３６内の下部柱状電極部１２ａの上面に上部柱状電極部１２ｂを連続して形成する。   Next, as shown in FIG. 5, by performing electrolytic plating of copper using the base metal layer 10 as a plating current path, a lower columnar shape is formed on the upper surface of the connection pad portion 11b of the wiring 11 in the opening 34 of the lower plating resist film 33 The electrode portion 12a is formed, and the upper columnar electrode portion 12b is continuously formed on the upper surface of the lower columnar electrode portion 12a in the opening 36 of the upper plating resist film 35.

この場合、上層メッキレジスト膜３５の開口部３６の直径は下層メッキレジスト膜３３の開口部３４の直径よりも大きいので、上層メッキレジスト膜３５の開口部３６内においてはメッキが等方的に推積される。このため、上層メッキレジスト膜３５の開口部３６内に形成される上部柱状電極部１２ｂの上部は盛り上がった形状となる。   In this case, since the diameter of the opening 36 of the upper plating resist film 35 is larger than the diameter of the opening 34 of the lower plating resist film 33, the plating isotropically promoted in the opening 36 of the upper plating resist film 35. Stacked. For this reason, the upper part of the upper columnar electrode part 12b formed in the opening part 36 of the upper plating resist film 35 has a raised shape.

また、大径の上部柱状電極部１２ｂの高さは小径の下部柱状電極部１２ａの高さよりも低いので、その合計の高さが一定である場合には、大径の上部柱状電極部１２ｂの高さが小径の下部柱状電極部１２ａの高さよりも高い場合と比較して、メッキ処理時間を短縮することができる。   Moreover, since the height of the large-diameter upper columnar electrode portion 12b is lower than the height of the small-diameter lower columnar electrode portion 12a, when the total height is constant, the large-diameter upper columnar electrode portion 12b Compared with the case where the height is higher than the height of the lower columnar electrode portion 12a having a small diameter, the plating processing time can be shortened.

次に、上層メッキレジスト膜３５および下層メッキレジスト膜３３を剥離し、次いで、配線１１をマスクとして下地金属層１０の不要な部分をエッチングして除去すると、図６に示すように、配線１１下にのみ下地金属層１０が残存される。この状態では、配線１１の接続パッド部１１ｂ上面には、下部柱状電極部１２ａと上部柱状電極部１２ｂとからなる２段構造の柱状電極１２が形成されている。この場合、上部柱状電極部１２ｂの上部は盛り上がっているので、２段構造の柱状電極１２はきのこ形状となっている。   Next, the upper plating resist film 35 and the lower plating resist film 33 are peeled off, and then unnecessary portions of the base metal layer 10 are removed by etching using the wiring 11 as a mask, as shown in FIG. Only the base metal layer 10 remains. In this state, a columnar electrode 12 having a two-stage structure including a lower columnar electrode portion 12 a and an upper columnar electrode portion 12 b is formed on the upper surface of the connection pad portion 11 b of the wiring 11. In this case, since the upper part of the upper columnar electrode portion 12b is raised, the columnar electrode 12 having a two-stage structure has a mushroom shape.

次に、図７に示すように、柱状電極１２および配線１１を含む保護膜８の上面に、スピンコート法、トランスファモールド法等により、エポキシ系樹脂等からなる封止膜１３をその厚さが柱状電極１２の高さとほぼ同じかそれよりもやや厚くなるように形成する。この場合、上部柱状電極部１２ｂの高さが下部柱状電極部１２ａの高さよりも低いので、封止膜１３を形成するための液状樹脂が上部柱状電極部１２ｂのきのこ状の傘部下に回り込みやすくすることができる。   Next, as shown in FIG. 7, a sealing film 13 made of epoxy resin or the like is formed on the upper surface of the protective film 8 including the columnar electrode 12 and the wiring 11 by spin coating, transfer molding, or the like. The columnar electrode 12 is formed so as to be almost the same as or slightly thicker than the height thereof. In this case, since the height of the upper columnar electrode portion 12b is lower than the height of the lower columnar electrode portion 12a, the liquid resin for forming the sealing film 13 easily wraps around the mushroom-shaped umbrella portion of the upper columnar electrode portion 12b. can do.

次に、封止膜１３の上面側および柱状電極１２の上部柱状電極部１２ｂの少なくとも盛り上がった上部を研磨し、図８に示すように、柱状電極１２の上部柱状電極部１２ｂの上面を含む封止膜１３の上面を平坦化する。   Next, the upper surface side of the sealing film 13 and at least the raised upper portion of the upper columnar electrode portion 12b of the columnar electrode 12 are polished, and the sealing including the upper surface of the upper columnar electrode portion 12b of the columnar electrode 12 as shown in FIG. The upper surface of the stop film 13 is flattened.

次に、図９に示すように、シリコン基板４の下面に接着層３を接着する。接着層３は、エポキシ系樹脂、ポリイミド系樹脂等のダイボンド材からなるものであり、加熱加圧により、半硬化した状態でシリコン基板４に固着する。次に、シリコン基板４の下面に固着された接着層３をダイシングテープ（図示せず）に貼り付け、ダイシング工程を経た後に、ダイシングテープから剥がすと、図１０に示すように、シリコン基板４の下面に接着層３を有する半導体構成体２が複数個得られる。   Next, as shown in FIG. 9, the adhesive layer 3 is bonded to the lower surface of the silicon substrate 4. The adhesive layer 3 is made of a die bond material such as an epoxy resin or a polyimide resin, and is fixed to the silicon substrate 4 in a semi-cured state by heating and pressing. Next, the adhesive layer 3 fixed to the lower surface of the silicon substrate 4 is affixed to a dicing tape (not shown), passed through a dicing process, and then peeled off from the dicing tape. As shown in FIG. A plurality of semiconductor structures 2 having the adhesive layer 3 on the lower surface are obtained.

ここで、このようにして得られた半導体構成体２の寸法の一例について説明する。配線１１の引き回し線部１１ｃの線幅および配線１１間の間隔が最小寸法で共に２０μｍ（図１０では２ｍｍに相当する、以下同じ）であるとき、柱状電極１２のピッチを２５０μｍとした場合には、柱状電極１２の下部柱状電極部１２ａの直径を１００μｍとすると、柱状電極１２の下部柱状電極部１２ａを支持する配線１１の接続パッド部１１ｂの直径が（片側での許容精度が１０μｍであると両側で２０μｍとなるので）１２０μｍとなり、相隣接する配線１１の接続パッド部１１ｂ間の間隔が１３０μｍとなり、相隣接する配線１１の接続パッド部１１ｂ間に配置し得る配線１１の引き回し線部１１ｃの本数が２本となる。   Here, an example of the dimensions of the semiconductor structure 2 obtained in this way will be described. When the line width of the lead-out line portion 11c of the wiring 11 and the distance between the wirings 11 are both 20 μm (corresponding to 2 mm in FIG. 10, the same applies hereinafter) in the minimum dimension, when the pitch of the columnar electrodes 12 is 250 μm When the diameter of the lower columnar electrode portion 12a of the columnar electrode 12 is 100 μm, the diameter of the connection pad portion 11b of the wiring 11 supporting the lower columnar electrode portion 12a of the columnar electrode 12 (the allowable accuracy on one side is 10 μm) 120 μm, and the distance between the connection pad portions 11 b of the adjacent wirings 11 is 130 μm, and the wiring line 11 c of the wiring 11 that can be disposed between the connection pad portions 11 b of the adjacent wirings 11. The number is two.

このように、この半導体構成体２では、柱状電極１２のピッチを２５０μｍとした場合において、下部柱状電極部１２ａの直径を１００μｍとし、下部柱状電極部１２ａを支持する配線１１の接続パッド部１１ｂの直径を１２０μｍとすると、配線１１の接続パッド部１１ｂ間の間隔を１３０μｍと広くすることができる。この結果、相隣接する配線１１の接続パッド部１１ｂ間に配線１１の引き回し線部１１ｃを２本と多く配置することが可能となる。   Thus, in this semiconductor structure 2, when the pitch of the columnar electrodes 12 is 250 μm, the diameter of the lower columnar electrode portion 12a is 100 μm, and the connection pad portion 11b of the wiring 11 that supports the lower columnar electrode portion 12a is formed. When the diameter is 120 μm, the interval between the connection pad portions 11 b of the wiring 11 can be increased to 130 μm. As a result, it is possible to arrange as many as two lead wire portions 11c of the wiring 11 between the connection pad portions 11b of the wirings 11 adjacent to each other.

一方、柱状電極１２のピッチを２５０μｍとした場合において、相隣接する柱状電極１２の上部柱状電極部１２ｂ間の間隔を５０μｍとすると、柱状電極１２の上部柱状電極部１２ｂの直径は２００μｍとなる。したがって、この半導体構成体２では、相隣接する配線１１の接続パッド部１１ｂ間に配線１１の引き回し線部１１ｃを２本と多く配置することが可能となる上、柱状電極１２の上部柱状電極部１２ｂの直径を２００μｍと大きくすることができる。   On the other hand, when the pitch of the columnar electrodes 12 is 250 μm and the interval between the upper columnar electrode portions 12b of the adjacent columnar electrodes 12 is 50 μm, the diameter of the upper columnar electrode portions 12b of the columnar electrodes 12 is 200 μm. Therefore, in this semiconductor structure 2, it is possible to dispose as many as two lead wire portions 11 c of the wiring 11 between the connection pad portions 11 b of the adjacent wirings 11, and the upper columnar electrode portion of the columnar electrode 12. The diameter of 12b can be increased to 200 μm.

次に、図１０に示す半導体構成体２を用いて、図１に示す半導体装置を製造する場合の一例について説明する。まず、図１１に示すように、図１に示す完成された半導体装置を複数個形成することが可能な面積を有するガラス布基材エポキシ樹脂等からなるベース板１を用意する。ベース板１は、限定する意味ではないが、例えば、平面方形状である。   Next, an example of manufacturing the semiconductor device shown in FIG. 1 using the semiconductor structure 2 shown in FIG. 10 will be described. First, as shown in FIG. 11, a base plate 1 made of a glass cloth base epoxy resin or the like having an area capable of forming a plurality of completed semiconductor devices shown in FIG. 1 is prepared. Although the base plate 1 is not limited, for example, the base plate 1 has a planar rectangular shape.

次に、ベース板１の上面の所定の複数箇所に複数の半導体構成体２のシリコン基板４の下面に固着された接着層３を相互に離間させて接着する。ここでの接着は、加熱加圧により、接着層３を本硬化させる。   Next, the adhesive layers 3 fixed to the lower surfaces of the silicon substrates 4 of the plurality of semiconductor structures 2 are adhered to each other at predetermined locations on the upper surface of the base plate 1 while being separated from each other. In this bonding, the adhesive layer 3 is fully cured by heating and pressing.

次に、図１２に示すように、半導体構成体２の周囲におけるベース板１の上面に格子状の絶縁層形成用シート１４ａをピン等で位置決めしながら配置する。格子状の絶縁層形成用シート１４ａは、例えば、エポキシ系樹脂等の熱硬化性樹脂中に補強材を分散させ、熱硬化性樹脂を半硬化状態にしてシート状となしたものである。   Next, as shown in FIG. 12, a lattice-shaped insulating layer forming sheet 14 a is disposed on the upper surface of the base plate 1 around the semiconductor structure 2 while being positioned with pins or the like. The lattice-shaped insulating layer forming sheet 14a is, for example, a sheet-like material in which a reinforcing material is dispersed in a thermosetting resin such as an epoxy resin and the thermosetting resin is semi-cured.

次に、半導体構成体２および絶縁層形成用シート１４ａの上面に上層絶縁膜形成用シート１５ａを配置する。上層絶縁膜形成用シート１５ａは、例えば、ガラス布等にエポキシ系樹脂等の熱硬化性樹脂を含浸させ、熱硬化性樹脂を半硬化状態にしてシート状となしたものである。   Next, the upper insulating film forming sheet 15a is disposed on the upper surfaces of the semiconductor structure 2 and the insulating layer forming sheet 14a. The upper insulating film forming sheet 15a is formed, for example, by impregnating a glass cloth or the like with a thermosetting resin such as an epoxy resin and making the thermosetting resin semi-cured into a sheet shape.

次に、一対の加熱加圧板３７、３８を用いて上下から絶縁層形成用シート１４ａおよび上層絶縁膜形成用シート１５ａを加熱加圧する。そして、その後の冷却により、半導体構成体２の周囲におけるベース板１の上面に絶縁層１４が形成され、また、半導体構成体２および絶縁層１４の上面に上層絶縁膜１５が形成される。この場合、上層絶縁膜１５の上面は、上側の加熱加圧板３７の下面によって押さえ付けられるため、平坦面となる。したがって、上層絶縁膜１５の上面を平坦化するための研磨工程は不要である。   Next, the insulating layer forming sheet 14a and the upper insulating film forming sheet 15a are heated and pressed from above and below using a pair of heating and pressing plates 37 and 38. Then, by subsequent cooling, an insulating layer 14 is formed on the upper surface of the base plate 1 around the semiconductor structure 2, and an upper insulating film 15 is formed on the upper surfaces of the semiconductor structure 2 and the insulating layer 14. In this case, since the upper surface of the upper insulating film 15 is pressed by the lower surface of the upper heating / pressing plate 37, it becomes a flat surface. Therefore, a polishing process for flattening the upper surface of the upper insulating film 15 is unnecessary.

次に、図１３に示すように、半導体構成体２の柱状電極１２の上部柱状電極部１２ｂの上面中央部に対応する部分における上層絶縁膜１５に、レーザビームを照射するレーザ加工により、開口部１６を形成する。次に、必要に応じて、上層絶縁膜１５の開口部１６内等に発生したエポキシスミア等をデスミア処理により除去する。   Next, as shown in FIG. 13, the opening is formed by laser processing that irradiates the upper insulating film 15 in the portion corresponding to the center of the upper surface of the upper columnar electrode portion 12 b of the columnar electrode 12 of the semiconductor structure 2. 16 is formed. Next, if necessary, epoxy smear or the like generated in the opening 16 of the upper insulating film 15 or the like is removed by a desmear process.

ここで、上述の如く、半導体構成体２の柱状電極１２の上部柱状電極部１２ｂの直径を２００μｍと大きくすることができるので、上層絶縁膜１５にレーザビームの照射によるレーザ加工により形成される円形状の開口部１６の直径を大きくすることができ、また当該開口部１６の柱状電極１２の上部柱状電極部１２ｂに対する位置ずれの許容精度を大きくすることができる。   Here, as described above, since the diameter of the upper columnar electrode portion 12b of the columnar electrode 12 of the semiconductor structure 2 can be increased to 200 μm, the upper insulating layer 15 is formed by laser processing by laser beam irradiation. The diameter of the opening 16 having a shape can be increased, and the tolerance of the positional deviation of the columnar electrode 12 of the opening 16 with respect to the upper columnar electrode portion 12b can be increased.

次に、図１４に示すように、上層絶縁膜１５の開口部１６を介して露出された柱状電極１２の上部柱状電極部１２ｂの上面を含む上層絶縁膜１５の上面全体に、銅の無電解メッキ等により、上層下地金属層１７を形成する。次に、上層下地金属層１７の上面にメッキレジスト膜３９をパターン形成する。この場合、上層配線１８形成領域に対応する部分におけるメッキレジスト膜３９には開口部４０が形成されている。   Next, as shown in FIG. 14, copper is electrolessly applied to the entire upper surface of the upper insulating film 15 including the upper surface of the upper columnar electrode portion 12 b of the columnar electrode 12 exposed through the opening 16 of the upper layer insulating film 15. The upper base metal layer 17 is formed by plating or the like. Next, a plating resist film 39 is pattern-formed on the upper surface of the upper base metal layer 17. In this case, an opening 40 is formed in the plating resist film 39 in a portion corresponding to the upper layer wiring 18 formation region.

次に、上層下地金属層１７をメッキ電流路として銅の電解メッキを行なうことにより、メッキレジスト膜３９の開口部４０内の上層下地金属層１７の上面に上層配線１８を形成する。次に、メッキレジスト膜３９を剥離し、次いで、上層配線１８をマスクとして上層下地金属層１７の不要な部分をエッチングして除去すると、図１５に示すように、上層配線１８下にのみ上層下地金属層１７が残存される。   Next, by performing copper electroplating using the upper base metal layer 17 as a plating current path, the upper wiring 18 is formed on the upper surface of the upper base metal layer 17 in the opening 40 of the plating resist film 39. Next, the plating resist film 39 is peeled off, and then unnecessary portions of the upper base metal layer 17 are removed by etching using the upper layer wiring 18 as a mask. As shown in FIG. The metal layer 17 remains.

次に、図１６に示すように、上層配線１８を含む上層絶縁膜１５の上面に、スクリーン印刷法やスピンコート法等により、ソルダーレジスト等からなるオーバーコート膜１９を形成する。この場合、上層配線１８の接続パッド部に対応する部分におけるオーバーコート膜１９には開口部２０が形成されている。   Next, as shown in FIG. 16, an overcoat film 19 made of a solder resist or the like is formed on the upper surface of the upper insulating film 15 including the upper wiring 18 by a screen printing method, a spin coating method, or the like. In this case, an opening 20 is formed in the overcoat film 19 in a portion corresponding to the connection pad portion of the upper layer wiring 18.

次に、オーバーコート膜１９の開口部２０内およびその上方に半田ボール２１を上層配線１８の接続パッド部に接続させて形成する。次に、互いに隣接する半導体構成体２間において、オーバーコート膜１９、上層絶縁膜１５、絶縁層１４およびベース板１を切断すると、図１に示す半導体装置が複数個得られる。   Next, a solder ball 21 is formed in the opening 20 of the overcoat film 19 and above it by connecting it to the connection pad of the upper wiring 18. Next, when the overcoat film 19, the upper insulating film 15, the insulating layer 14, and the base plate 1 are cut between adjacent semiconductor structures 2, a plurality of semiconductor devices shown in FIG. 1 are obtained.

（第２実施形態）
図１７はこの発明の第２実施形態としての半導体装置の断面図を示す。この半導体装置において、図１に示す半導体装置と異なる点は、図１７において左側に示すように、下地金属層１０を含む配線１１の一部を、絶縁膜６および保護膜８の開口部７、９を介して接続パッド５に接続された接続パッド部１１ｂのみとした点である。 (Second Embodiment)
FIG. 17 is a sectional view of a semiconductor device as a second embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that, as shown on the left side in FIG. 17, a part of the wiring 11 including the base metal layer 10 is replaced with the openings 7 of the insulating film 6 and the protective film 8. 9, only the connection pad portion 11 b connected to the connection pad 5 via 9 is used.

この発明の第１実施形態としての半導体装置の断面図。1 is a cross-sectional view of a semiconductor device as a first embodiment of the present invention. 図１に示す半導体装置の製造方法の一例において、当初用意したものの断面 図。Sectional drawing of what was prepared initially in an example of the manufacturing method of the semiconductor device shown in FIG. 図２に続く工程の断面図。Sectional drawing of the process following FIG. 図３に続く工程の断面図。Sectional drawing of the process following FIG. 図４に続く工程の断面図。Sectional drawing of the process following FIG. 図５に続く工程の断面図。Sectional drawing of the process following FIG. 図６に続く工程の断面図。Sectional drawing of the process following FIG. 図７に続く工程の断面図。Sectional drawing of the process following FIG. 図８に続く工程の断面図。FIG. 9 is a cross-sectional view of the process following FIG. 8. 図９に続く工程の断面図。Sectional drawing of the process following FIG. 図１０に続く工程の断面図。Sectional drawing of the process following FIG. 図１１に続く工程の断面図。Sectional drawing of the process following FIG. 図１２に続く工程の断面図。Sectional drawing of the process following FIG. 図１３に続く工程の断面図。Sectional drawing of the process following FIG. 図１４に続く工程の断面図。FIG. 15 is a sectional view of a step following FIG. 14. 図１５に続く工程の断面図。FIG. 16 is a cross-sectional view of the process following FIG. 15. この発明の第２実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 2nd Embodiment of this invention. 従来の半導体装置の一例の断面図。Sectional drawing of an example of the conventional semiconductor device.

符号の説明Explanation of symbols

１ ベース板
２ 半導体構成体
３ 接着層
４ シリコン基板
５ 接続パッド
６ 絶縁膜
７ 開口部
８ 保護膜
９ 開口部
１０ 下地金属層
１１ 配線
１１ａ 接続部
１１ｂ 接続パッド部
１１ｃ 引き回し線部
１２ 柱状電極
１２ａ 下部柱状電極部
１２ｂ 上部柱状電極部
１３ 封止膜
１４ 絶縁層
１５ 上層絶縁膜
１６ 開口部
１７ 上層下地金属層
１８ 上層配線
１９ オーバーコート膜
２０ 開口部
２１ 半田ボール DESCRIPTION OF SYMBOLS 1 Base board 2 Semiconductor structure 3 Adhesion layer 4 Silicon substrate 5 Connection pad 6 Insulating film 7 Opening part 8 Protective film 9 Opening part 10 Base metal layer 11 Wiring 11a Connection part 11b Connection pad part 11c Leading line part 12 Columnar electrode 12a Lower Columnar electrode portion 12b Upper columnar electrode portion 13 Sealing film 14 Insulating layer 15 Upper layer insulating film 16 Opening portion 17 Upper layer underlying metal layer 18 Upper layer wiring 19 Overcoat film 20 Opening portion 21 Solder ball

Claims (16)

半導体基板上に設けられた複数の配線の接続パッド部上に柱状電極が設けられた半導体構成体において、前記柱状電極は、前記配線の接続パッドに接続された下部柱状電極部と、該下部柱状電極部上に設けられた該下部柱状電極部よりも大径の上部柱状電極部とからなることを特徴とする半導体構成体。   In a semiconductor structure in which a columnar electrode is provided on a connection pad portion of a plurality of wirings provided on a semiconductor substrate, the columnar electrode includes a lower columnar electrode portion connected to the connection pad of the wiring, and the lower columnar electrode A semiconductor structure comprising an upper columnar electrode portion having a diameter larger than that of the lower columnar electrode portion provided on the electrode portion. 請求項１に記載の発明において、前記上部柱状電極部の高さは前記下部柱状電極部の高さよりも低くなっていることを特徴とする半導体構成体。   2. The semiconductor structure according to claim 1, wherein the height of the upper columnar electrode portion is lower than the height of the lower columnar electrode portion. 請求項１に記載の発明において、相隣接する前記配線の接続パッド部間に前記配線の引き回し線部が２本配置されていることを特徴とする半導体構成体。   2. The semiconductor structure according to claim 1, wherein two lead-out line portions of the wiring are arranged between connection pad portions of the wirings adjacent to each other. 請求項１に記載の発明において、前記配線を含む前記半導体基板上に封止膜が前記柱状電極の周囲を覆うように設けられていることを特徴とする半導体構成体。   The semiconductor structure according to claim 1, wherein a sealing film is provided on the semiconductor substrate including the wiring so as to cover the periphery of the columnar electrode. 半導体基板上に複数の配線を形成する工程と、
前記配線の接続パッドに接続された下部柱状電極部を形成する工程と、
前記下部柱状電極部上に該下部柱状電極部よりも大径の上部柱状電極部を形成する工程と、
を含むことを特徴とする半導体構成体の製造方法。 Forming a plurality of wirings on a semiconductor substrate;
Forming a lower columnar electrode portion connected to the connection pad of the wiring;
Forming an upper columnar electrode portion having a larger diameter than the lower columnar electrode portion on the lower columnar electrode portion;
The manufacturing method of the semiconductor structure characterized by including. 請求項５に記載の発明において、前記下部柱状電極部および前記上部柱状電極部を形成する工程は、前記配線を含む前記半導体基板上に下部柱状電極部形成用の開口部を有する下層メッキレジスト膜を形成し、前記下層メッキレジスト膜上に上部柱状電極部形成用の開口部を有する上層メッキレジスト膜を形成し、電解メッキにより、前記両メッキレジスト膜の開口部内に前記下部柱状電極部および前記上部柱状電極部を連続して形成し、前記両メッキレジスト膜を剥離する、工程であることを特徴とする半導体構成体の製造方法。   6. The lower plating resist film according to claim 5, wherein the step of forming the lower columnar electrode portion and the upper columnar electrode portion includes an opening for forming the lower columnar electrode portion on the semiconductor substrate including the wiring. Forming an upper plating resist film having an opening for forming an upper columnar electrode portion on the lower plating resist film, and electrolytic plating to form the lower columnar electrode portion and the above in the opening portions of the two plating resist films. A method of manufacturing a semiconductor structure, which is a step of continuously forming upper columnar electrode portions and peeling off both plating resist films. 請求項５に記載の発明において、前記上部柱状電極部をその高さが前記下部柱状電極部の高さよりも低くなるように形成することを特徴とする半導体構成体の製造方法。   6. The method of manufacturing a semiconductor structure according to claim 5, wherein the upper columnar electrode portion is formed such that a height thereof is lower than a height of the lower columnar electrode portion. 請求項５に記載の発明において、前記配線を含む前記半導体基板上に封止膜を前記柱状電極の周囲を覆うように形成する工程を有することを特徴とする半導体構成体の製造方法。   6. The method of manufacturing a semiconductor structure according to claim 5, further comprising a step of forming a sealing film on the semiconductor substrate including the wiring so as to cover the periphery of the columnar electrode. ベース板と、前記ベース板上に設けられ、半導体基板、該半導体基板上に設けられた複数の配線、該配線の接続パッドに接続された下部柱状電極部および該下部柱状電極部よりも大径の上部柱状電極部からなる２段構造の柱状電極を有する半導体構成体と、前記半導体構成体の周囲における前記ベース板上に設けられた絶縁層と、前記半導体構成体および前記絶縁層上に設けられ、前記半導体構成体の柱状電極の上部柱状電極部の上面中央部に対応する部分に開口部を有する上層絶縁膜と、前記上層絶縁膜上に該上層絶縁膜の開口部を介して前記半導体構成体の柱状電極の上部柱状電極部の上面に接続されて設けられた上層配線とを具備することを特徴とする半導体装置。   A base plate; a semiconductor substrate provided on the base plate; a plurality of wirings provided on the semiconductor substrate; a lower columnar electrode portion connected to a connection pad of the wiring; and a larger diameter than the lower columnar electrode portion A semiconductor structure having a columnar electrode having a two-stage structure composed of upper columnar electrode portions, an insulating layer provided on the base plate around the semiconductor structure, and provided on the semiconductor structure and the insulating layer And an upper insulating film having an opening in a portion corresponding to the center of the upper surface of the upper columnar electrode portion of the columnar electrode of the semiconductor structure, and the semiconductor via the opening of the upper insulating film on the upper insulating film A semiconductor device comprising: an upper layer wiring connected to the upper surface of the upper columnar electrode portion of the columnar electrode of the structure. 請求項９に記載の発明において、前記半導体構成体において、前記上部柱状電極部の高さは前記下部柱状電極部の高さよりも低くなっていることを特徴とする半導体装置。   10. The semiconductor device according to claim 9, wherein in the semiconductor structure, the height of the upper columnar electrode portion is lower than the height of the lower columnar electrode portion. 請求項９に記載の発明において、前記半導体構成体は、前記配線を含む前記半導体基板上に前記柱状電極の周囲を覆うように設けられた封止膜を有することを特徴とする半導体装置。   10. The semiconductor device according to claim 9, wherein the semiconductor structure has a sealing film provided on the semiconductor substrate including the wiring so as to cover the periphery of the columnar electrode. ベース板上に、各々が、半導体基板、該半導体基板上に設けられた複数の配線、該配線の接続パッドに接続された下部柱状電極部および該下部柱状電極部よりも大径の上部柱状電極部からなる２段構造の柱状電極を有する複数の半導体構成体を相互に離間させて配置する工程と、
前記半導体構成体の周囲における前記ベース板上に絶縁層を形成し、且つ、前記半導体構成体および前記絶縁層上に上層絶縁膜を形成する工程と、
前記半導体構成体の柱状電極の上部柱状電極部の上面中央部に対応する部分における前記上層絶縁膜に開口部を形成する工程と、
前記上層絶縁膜上に上層配線を前記上層絶縁膜の開口部を介して前記半導体構成体の柱状電極の上部柱状電極部の上面に接続させて形成する工程と、
前記半導体構成体間における前記上層絶縁膜、前記絶縁層および前記ベース板を切断して半導体装置を複数個得る工程と、
を含むことを特徴とする半導体装置の製造方法。 On the base plate, each is a semiconductor substrate, a plurality of wirings provided on the semiconductor substrate, a lower columnar electrode part connected to a connection pad of the wiring, and an upper columnar electrode having a larger diameter than the lower columnar electrode part A step of disposing a plurality of semiconductor structures having a columnar electrode having a two-stage structure composed of a portion,
Forming an insulating layer on the base plate around the semiconductor structure, and forming an upper insulating film on the semiconductor structure and the insulating layer;
Forming an opening in the upper insulating film in a portion corresponding to the center of the upper surface of the upper columnar electrode portion of the columnar electrode of the semiconductor structure;
Forming an upper wiring on the upper insulating film by connecting the upper wiring to the upper surface of the upper columnar electrode portion of the columnar electrode of the semiconductor structure via the opening of the upper insulating film;
Cutting the upper insulating film, the insulating layer, and the base plate between the semiconductor structures to obtain a plurality of semiconductor devices;
A method for manufacturing a semiconductor device, comprising: 請求項１２に記載の発明において、前記上層絶縁膜への前記開口部の形成はレーザビームの照射によるレーザ加工によって行なうことを特徴とする半導体装置の製造方法。   13. The method of manufacturing a semiconductor device according to claim 12, wherein the opening is formed in the upper insulating film by laser processing by laser beam irradiation. 請求項１２に記載の発明において、前記半導体構成体は、前記配線を含む前記半導体基板上に前記柱状電極の周囲を覆うように設けられた封止膜を有することを特徴とする半導体装置の製造方法。   13. The semiconductor device according to claim 12, wherein the semiconductor structure includes a sealing film provided on the semiconductor substrate including the wiring so as to cover the periphery of the columnar electrode. Method. 請求項１２に記載の発明において、前記上層配線の接続パッドを除く部分を覆うオーバーコート膜を形成する工程を有することを特徴とする半導体装置の製造方法。   13. The method of manufacturing a semiconductor device according to claim 12, further comprising a step of forming an overcoat film that covers a portion of the upper wiring except for the connection pads. 請求項１５に記載の発明において、前記上層配線の接続パッド上に半田ボールを形成する工程を有することを特徴とする半導体装置の製造方法。   16. The method of manufacturing a semiconductor device according to claim 15, further comprising a step of forming a solder ball on the connection pad of the upper wiring.
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