JP4135390B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP4135390B2
JP4135390B2 JP2002117307A JP2002117307A JP4135390B2 JP 4135390 B2 JP4135390 B2 JP 4135390B2 JP 2002117307 A JP2002117307 A JP 2002117307A JP 2002117307 A JP2002117307 A JP 2002117307A JP 4135390 B2 JP4135390 B2 JP 4135390B2
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insulating film
protruding electrode
semiconductor chip
semiconductor
protruding
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JP2003318323A (en
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猛 若林
一郎 三原
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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Priority to JP2002117307A priority Critical patent/JP4135390B2/en
Priority to TW092102111A priority patent/TW577160B/en
Priority to CNB038001284A priority patent/CN100358118C/en
Priority to US10/472,803 priority patent/US7190064B2/en
Priority to PCT/JP2003/001061 priority patent/WO2003067648A2/en
Priority to KR1020037012972A priority patent/KR100548668B1/en
Priority to EP03737462A priority patent/EP1472724A2/en
Priority to MXPA03009043A priority patent/MXPA03009043A/en
Priority to CA002443149A priority patent/CA2443149C/en
Priority to AU2003244348A priority patent/AU2003244348A1/en
Priority to NO20034441A priority patent/NO20034441L/en
Publication of JP2003318323A publication Critical patent/JP2003318323A/en
Priority to US11/429,368 priority patent/US20060202353A1/en
Priority to US11/588,647 priority patent/US7514335B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【０００１】
【発明の属する技術分野】
この発明は半導体装置およびその製造方法に関する。
【０００２】
【従来の技術】
例えばＢＧＡ(ball grid array)と呼ばれる半導体装置には、ＬＳＩ等からなる半導体チップを該半導体チップのサイズよりもやや大きいサイズの中継基板(インターポーザ)の上面中央部に搭載し、中継基板の下面に半田ボールによる接続端子をマトリクス状に配置したものがある。
【０００３】
図１８は従来のこのような半導体装置の一例の断面図を示したものである。半導体チップ１は、半導体基板２の上面周辺部に複数のバンプ電極３が設けられた構造となっている。
【０００４】
中継基板４は、サイズが半導体チップ１の半導体基板２のサイズよりもやや大きいベースフィルム５を備えている。ベースフィルム５の上面には、半導体チップ１のバンプ電極３に接続される再配線６が設けられている。
【０００５】
再配線６は、半導体チップ１のバンプ電極３に対応して設けられた第１の接続パッド７と、マトリクス状に設けられた第２の接続パッド８と、第１と第２の接続パッド７、８を接続する引き回し線９とからなっている。第２の接続パッド８の中央部に対応する部分におけるベースフィルム５には円孔１０が設けられている。
【０００６】
そして、半導体チップ１は中継基板４の上面中央部に異方性導電接着剤１１を介して搭載されている。異方性導電接着剤１１は、熱硬化性樹脂１２中に多数の導電性粒子１３を含有させたものからなっている。
【０００７】
半導体チップ１を中継基板４上に搭載する場合には、まず、中継基板４の上面中央部にシート状の異方性導電接着剤１１を介して半導体チップ１を位置合わせしてただ単に載置する。
【０００８】
次に、熱硬化性樹脂１２が硬化する温度にて所定の圧力を加えてボンディングする。すると、バンプ電極３が熱硬化性樹脂１２を押し退けて第１の接続パッド７の上面に導電性粒子１３を介して導電接続され、且つ、半導体チップ１の下面が中継基板４の上面に熱硬化性樹脂１２を介して接着される。
【０００９】
次に、半導体チップ１を含む中継基板４の上面全体にエポキシ系樹脂からなる樹脂封止膜１４を形成する。次に、円孔１０内およびその下方に半田ボール１５を第２の接続パッド８に接続させて形成する。この場合、第２の接続パッド８はマトリクス状に配置されているため、半田ボール１５もマトリクス状に配置される。
【００１０】
ここで、半田ボール１５のサイズは半導体チップ１のバンプ電極３のサイズより大きく、また、各半田ボール１５相互の接触を避けるため、その配置間隔をバンプ電極３の配置間隔より大きくする必要がある。そこで、半導体チップ１のバンプ電極３の数が増大した場合、各半田ボール１５に必要な配置間隔を得るため、配置領域を半導体チップ１のサイズより大きくすることが必要となり、そのために、中継基板４のサイズを半導体チップ１のサイズよりもやや大きくしている。したがって、マトリクス状に配置された半田ボール１５のうち、周辺部の半田ボール１５は半導体チップ１の周囲に配置されている。
【００１１】
【発明が解決しようとする課題】
ところで、上記のように半田ボール１５による接続端子を半導体チップ１の周囲にも備える従来の半導体装置では、再配線６が形成された中継基板４を用い、ボンディングにより、半導体チップ１のバンプ電極３の下面を中継基板４の再配線６の第１の接続電極７の上面に異方性導電接着剤１１の導電性粒子１３を介して導電接続する構成としているので、ボンディング状態により接続不良が発生する可能性があるという問題があった。また、半導体チップ１を１つずつ中継基板４上にボンディングして搭載しなければならず、製造工程が煩雑であるという問題があった。
【００１２】
そこで、この発明は、接続端子を半導体チップの周囲にも備える半導体装置において、中継基板を用いることなく、半導体チップと再配線とを確実に導電接続することができる、半導体装置およびその製造方法を提供することを目的とする。また、この発明は、複数の半導体装置を一括して製造することができる、半導体装置の製造方法を提供することを目的とする。
【００１３】
【課題を解決するための手段】
請求項１の記載の発明に係る半導体装置は、上面、該上面に対向する下面および前記上面および前記下面間に介在された周側面を有し且つ前記上面上に接続パッドを有する半導体チップと、該半導体チップの少なくとも前記上面および前記周側面を覆うように設けられ、前記接続パッドに対応する第１の開口部と、前記半導体チップの前記周側面より外側に前記半導体チップの下面側に向けて開口する第２の開口部を有する絶縁膜と、該絶縁膜の上面に設けられ、前記第１の開口部内に前記半導体チップの接続パッドに接続されて設けられた第１のパッド部、前記絶縁膜に形成された第２の開口部内に該第２の開口部の底部を塞いで設けられた突起電極に接続された第２のパッド部を有し、前記両パッド部および前記突起電極が同一材料により一体的に形成された再配線と、前記突起電極の下面に設けられた半田ボールとを備えていることを特徴とするものである。
請求項２の記載の発明に係る半導体装置は、請求項１に記載の発明において、前記突起電極が形成された前記再配線に、前記突起電極とは反対方向に突き出す第２の突起電極が形成されていることを特徴とするものである。
請求項３の記載の発明に係る半導体装置は、請求項１に記載の発明において、さらに、前記再配線が接続されていない前記接続パッドに接続された第２の再配線が前記絶縁膜の上面に形成され、該第２の再配線のパッド部上に前記突起電極とは反対方向に突き出す第２の突起電極が形成されていることを特徴とするものである。
請求項４の記載の発明に係る半導体装置は、請求項２または３に記載の発明において、前記絶縁膜上に前記第２の突起電極の周囲を覆う第２の絶縁膜が形成されていることを特徴とするものである。
請求項５の記載の発明に係る半導体装置は、請求項１に記載の発明において、さらに、前記接続パッドに接続されない突起電極を有することを特徴とするものである。
請求項６の記載の発明に係る半導体装置の製造方法は、一面、該一面に対向する他面および前記一面および前記他面間に介在された周側面を有し且つ前記一面上に接続パッドを有する複数の半導体チップをベース板に固着する工程と、前記複数の半導体チップを含む前記ベース板上に絶縁膜を形成する工程と、前記各半導体チップの周側面より外側における前記絶縁膜に前記半導体チップの他面側に向けて開口する開口部を形成する工程と、前記絶縁膜の上面に、各々が前記各半導体チップの接続パッドに接続されて設けられたパッド部、前記絶縁膜に形成された開口部に対応するパッド部および前記半導体チップの他面側に露出する下面を有する突起電極を有する複数組の再配線を同一材料により一体的に形成する工程と、前記ベース板を剥がして、前記突起電極の下面に半田ボールを設ける工程と、前記各組の半導体チップ間における前記絶縁膜を切断して前記各半導体チップの周囲に前記突起電極が形成された半導体装置を複数個得る工程とを有することを特徴とするものである。
請求項７の記載の発明に係る半導体装置の製造方法は、請求項６に記載の発明において、前記半導体チップを前記ベース板から剥がした後、前記各再配線の突起電極の下面に半田ボールを形成する前に前記突起電極の下面に付着している異物を除去する工程を有することを特徴とするものである。
請求項８の記載の発明に係る半導体装置の製造方法は、請求項６に記載の発明において、さらに、前記半導体チップの他面側に露出する下面を有する突起電極を有していない前記再配線のパッド部上に、前記突起電極とは反対方向に突き出す第２の突起電極を形成する工程と、前記絶縁膜上に前記突起電極の周囲を覆う第２の絶縁膜を形成する工程とを有することを特徴とするものである。
【００１４】
【発明の実施の形態】
図１（Ａ）〜（Ｃ）はこの発明の一実施形態としての半導体装置を示すものであり、図１（Ａ）は同半導体装置の拡大平面図、図１（Ｂ）は同半導体装置の裏面側の配線状態を説明するためのもので、図１（Ａ）のＩB−ＩBに沿う拡大断面図、図１（Ｃ）は同半導体装置の表面側の配線状態を説明するためのもので、図１（Ａ）のＩC−ＩCに沿う拡大断面図である。
【００１５】
この半導体装置は、ＬＳＩ等からなる半導体チップ１１を備えている。半導体チップ２１は、シリコン等からなる半導体基板２２の上面周辺部に複数の接続パッド２３が設けられ、接続パッド２３の中央部を除く半導体基板２２の上面に酸化シリコン等からなる絶縁膜２４が設けられ、接続パッド２３の中央部が絶縁膜２４に設けられた開口部２５を介して露出された構造となっている。
【００１６】
半導体チップ２１には、その下面を除いて、上面および周側面にポリイミド系樹脂、エポキシ系樹脂、ＰＢＯ（ポリベンザオキシドール）系樹脂等からなる絶縁膜２６が被着されている。絶縁膜２６は、その上面を平坦とされ、且つ、その下面が半導体基板２２の下面と面一となるように設けられている。この場合、絶縁膜２６の半導体チップ２１の開口部２５に対応する部分には開口部２７が設けられている。また、半導体チップ２１の周側面より外側における絶縁膜２６の所定の複数箇所にはスルーホール（開口部）２８が設けられている。
【００１７】
図１（Ａ）、（Ｂ）に示すように、半導体チップ２１の相対向する一対の辺側に配列され、両開口部２５、２７を介して露出された接続パッド２３の上面から絶縁膜２６の上面およびスルーホール２８の内壁面と内底部に亘り第１の下地金属層３１が設けられている。この場合、スルーホール２８の内底部に設けられた第１の下地金属層３１の下面は絶縁膜２６の下面と面一となっている。第１の下地金属層３１の上面には第１の再配線３２が設けられている。
【００１８】
ここで、スルーホール２８内に設けられた第１の下地金属層３１および第１の再配線３２は、後述する如く、外部回路に接続される接続端子部の機能を有する第１の突起電極３３を構成している。したがって、第１の再配線３２は、半導体チップ２１の接続パッド２３に接続された部分からなるパッド部と、スルーホール２８上に配置されて第１の突起電極３３に一体的に接続された部分からなるパッド部と、両パッド部を接続する引き回し線とからなっている。そして、スルーホール２８の内底部に設けられた第１の下地金属層３１の下面、すなわち、第１の突起電極３３の下面には第１の半田ボール３４が設けられている。
【００１９】
図１（Ａ）、（Ｃ）に示すように、半導体チップ２１の相対向する他の一対の辺側に配列され、両開口部２５、２７を介して露出された接続パッド２３の上面から絶縁膜２６の上面の他の箇所にかけて第２の下地金属層３５が設けられている。第２の下地金属層３５の上面には第２の再配線３６が設けられている。第２の再配線３６の先端部上には柱状の第２の突起電極３７が設けられている。ここで、第２の再配線３６は、半導体チップ２１の接続パッド２３に接続された部分からなるパッド部と、第２の突起電極３７に接続された部分からなるパッド部と、両パッド部を接続する引き回し線とからなっている。後述する如く、第２の下地金属層３５および第２の再配線３６は、それぞれ、第１の下地金属層３１および第１の再配線３２と同一工程で形成されるもので、材料、膜厚は、それぞれ、同一である。
【００２０】
第２の突起電極３７の上面には第２の半田ボール３８が設けられている。第２の突起電極３７を除いて両再配線３２、３６を含む絶縁膜２６の上面にはポリイミド系樹脂、エポキシ系樹脂、ＰＢＯ系樹脂等からなる絶縁膜（封止膜）３９がその上面が第２の突起電極３７の上面と面一となるように設けられている。
【００２１】
このように、この半導体装置では、上・下面側に第１および第２の突起電極３３、３７が形成され、各第１および第２の突起電極３３、３７に接合された第１および第２の半田ボール３４、３８を備えているので、該半導体装置の一面側の第１の半田ボール３４を回路基板または他の電子部品に接合し、他面側の第２の半田ボール３８を他の回路基板または電子部品に直接接合することが可能になり、生産効率およびコスト面で有利となるばかりでなく、実装密度を向上することが可能となる。
【００２２】
また、上記実施形態では、上・下面の第１および第２の半田ボール３４、３８を半導体チップ２１の外周部に配置しているので、第１および第２の半田ボール３４、３８間のピッチを大きくすることが可能となるので、半導体チップ２１の接続パッド２３のピッチが小さい場合でも、接続部間の短絡を防止することができる。
【００２３】
なお、上記実施形態においては、半導体装置の上・下面に配列される第１および第２の半田ボール３４、３８を半導体チップ２１の外周部に１列だけ配列したものとしているが、複数列配列することもできる。また、半導体装置の上面側に配列する第２の半田ボール３８は、半導体チップ２１の外周部のみでなく、半導体チップ２１に対応する領域上にも、例えば、マトリクス状等の配列にして形成することができる。
【００２４】
次に、この半導体装置の製造方法の一例について説明する。まず、図２に示すように、紫外線透過性のガラス板、透明金属板、透明樹脂板等からなるベース板４１の上面に紫外線の照射により接着力が低下する接着層４２が設けられたものを用意する。そして、接着層４２の上面の所定の複数箇所にそれぞれ半導体チップ２１を構成する半導体基板２２の下面を接着する。半導体チップ２１の厚さは２０〜５０μｍ程度である。この場合、ベース板４１にダイシングにより分離された個々の半導体チップ２１を搭載する方法に替えて、ベース板４１に半導体ウエハを接着し、ブレード等により各半導体チップ２１が分離されるように半導体ウエハを切除するようにしてもよい。なお、以下の製造方法を説明する各図においては、中央部の半導体チップ２１の領域は、図１（Ａ）のＩB−ＩB線に沿う断面を、また、その両側の半導体チップ２１の領域は図１（Ａ）のＩC−ＩC線に沿う断面を示している。
【００２５】
次に、複数の半導体チップ２１を含む接着層４２の上面にポリイミド系樹脂、エポキシ系樹脂、ＰＢＯ系樹脂等からなる絶縁膜２６をスピンコート法や印刷法等により塗布し、これを乾燥した後に、フォトレジストを塗布し、フォトリソグラフィー法により絶縁膜２６を図３に示すようにパターニングする。この場合、絶縁膜２６の上面は平坦であり、その半導体チップ２１の開口部２５に対応する部分には開口部２７が形成され、また中央部の半導体チップ２１の周囲における絶縁膜２６の所定の複数箇所にはスルーホール２８が形成されている。絶縁膜２６をパターニングした後、フォトレジストを剥離する。
【００２６】
次に、図４に示すように、スルーホール２８内および両開口部２５、２７を介して露出された接続パッド２３の上面を含む絶縁膜２６の上面に下地金属層４３を形成する。下地金属層４３は、例えば、スパッタにより形成された銅層のみであってもよく、またスパッタにより形成されたチタン等の薄膜層上にスパッタにより銅層を形成したものであってもよい。
【００２７】
次に、下地金属層４３の上面にメッキレジスト膜４４をパターン形成する。この場合、第１および第２の再配線３２、３６形成領域に対応する部分におけるメッキレジスト膜４４には開口部４５が形成されている。次に、下地金属層４３をメッキ電流路として銅等の電解メッキを行うことにより、メッキレジスト膜４４の開口部４５内の下地金属層４３の上面に第１および第２の再配線３２、３６を形成する。
【００２８】
これにより、第１の再配線３２は、半導体チップ２１の接続パッド２３に接続された部分からなるパッド部と、スルーホール２８上に配置されて第１の突起電極３３に一体的に接続された部分からなるパッド部と、両パッド部を接続する引き回し線とから構成され、第２の再配線３６は、半導体チップ２１の接続パッド２３に接続された部分からなるパッド部と、後述する第２の突起電極３７に接続される部分からなるパッド部と、両パッド部を接続する引き回し線とから構成される。次に、メッキレジスト膜４４を剥離する。
【００２９】
第１の再配線３２の形成において、絶縁膜２６の開口部２７に対応するパッド部は、第１の突起電極３３に一体的に設けられるので、生産が、大変効率的である。しかし、第１の突起電極３３を構成する第１の再配線３２のパッド部の上部側は、メッキ時に窪んで形成される。もし、第１の突起電極３３の上部側を引き回し線と平坦になるように形成することを望むならば、図３において、絶縁膜２６にスルーホール２８を形成せず、半導体チップ２１の開口部２５に対応する部分には開口部２７のみを形成し、下地金属層４３を形成し、メッキレジスト膜４４をパターン形成し、下地金属層４３をメッキ電流路として銅等の電解メッキを行うことにより、第１および第２の再配線３２、３６を形成してから、絶縁膜２６にスルーホール２８を形成し（ベース板４１を剥がして行う）、メッキ等によりスルーホール２８内の第１の再配線３２のパッド部上に第１の突起電極３３を形成するようにしてもよい。
【００３０】
次に、図５に示すように、第１および第２の再配線３２、３６を含む下地金属層４３の上面にメッキレジスト膜４６をパターン形成する。この場合、第２の再配線３６のパッド部に対応する部分におけるメッキレジスト膜４６には開口部４７が形成されている。次に、下地金属層４３をメッキ電流路として銅等の電解メッキを行うことにより、メッキレジスト膜４６の開口部４７内の第２の再配線３６のパッド部の上面に第２の突起電極３７を高さ１００〜１５０μｍ程度に形成する。次に、メッキレジスト膜４６を剥離する。
【００３１】
次に、第１および第２の再配線３２、３６をマスクとして下地金属層４３の不要な部分をエッチングして除去する（この場合、マスクとなる第１および第２の再配線３２、３６も同時にエッチングされるが、下地金属層４３に比し厚さが厚いので、下地金属層４３がエッチングされた時点でエッチングをやめればよい）と、図６に示すように、第１および第２の再配線３２、３６下にのみ第１および第２の下地金属層３１、３５が残存される。
【００３２】
ここで、スルーホール２８内に形成された第１の下地金属層３１および第１の再配線３２からなる第１の突起電極３３の高さは、半導体チップ２１の厚さ（２０〜５０μｍ程度）と絶縁膜２６の厚さ（例えば半導体チップ２１上で１０μｍ程度）との合計厚さ（３０〜６０μｍ程度）であり、第２の突起電極３７の高さ（１００〜１５０μｍ程度）よりも低くなっている。
【００３３】
次に、図７に示すように、第２の突起電極３７、第１および第２の再配線３２、３６を含む絶縁膜２６の上面にポリイミド系樹脂、エポキシ系樹脂、ＰＢＯ系樹脂等からなる絶縁膜３９をディスペンサ法、印刷法、トランスファモールド法等によりその厚さが第２の突起電極３７の高さよりもやや厚くなるように形成する。したがって、この状態では、第２の突起電極３７の上面は絶縁膜３９によって覆われている。
【００３４】
次に、絶縁膜３９の上面側を適宜に研磨することにより、図８に示すように、第２の突起電極３７の上面を露出させる。次に、図９に示すように、第２の突起電極３７の上面に第２の半田ボール３８を形成する。第２の半田ボール３８の形成は、第２の半田ボール３８を吸着具で吸着して第２の突起電極３７上に載置し、リフローを行う方法、印刷等により第２の突起電極３７の上面に半田層を被着し、リフローにより第２の半田ボール３８を形成する方法等による。
【００３５】
次に、ベース板４１の下面側から紫外線を照射し、接着層４２の接着力を低下させ、ベース板４１および接着層４２を剥がすと、図１０に示すようになる。この状態では、絶縁膜２６の下面および第１の突起電極３３の下面は半導体基板２２の下面と面一となっている。ここで、第１の突起電極３３の下面に、接着剤や異物等が付着している場合には、プラズマエッチング等を行って除去する。
【００３６】
次に、図１１に示すように、第１の突起電極３３下に第１の半田ボール３４を形成する。次に、図１２に示すように、互いに隣接する半導体チップ２１、２１間において絶縁膜２６および絶縁膜３９を切断すると、図１（Ａ）、（Ｂ）、（Ｃ）に示す半導体装置が複数個得られる。
【００３７】
このようにして得られた半導体装置では、半導体チップ２１の接続パッド２３に接続される第１、第２の下地金属層３１、３５および第１、第２の再配線３２、３６をスパッタおよび電解メッキにより形成しているので、半導体チップ２１の接続パッド２３と第１および第２の再配線３２、３６との間の導電接続を確実とすることができる。
【００３８】
また、本実施形態の製造方法では、ベース板４１上の接着層４２上の所定の複数箇所にそれぞれ半導体チップ２１を接着して配置し、複数の半導体チップ２１に対して絶縁膜１６、３９、第１、第２の下地金属層３１、３５、第１、第２の再配線３２、３６、第１、第２の突起電極３３、３７および第１、第２の半田ボール３４、３８の形成を一括して行い、その後に分断して複数個の半導体装置を得ているので、製造工程を簡略化することができる。
【００３９】
また、ベース板４１と共に複数の半導体チップ２１を搬送することができるので、これによっても製造工程を簡略化することができる。さらに、ベース板４１の外形寸法を一定にすると、製造すべき半導体装置の外形寸法に関係なく、搬送系を共有化することができる。
【００４０】
なお、上記実施形態では、例えば図９に示すように、ベース板４１の上面全体に接着層４２を設けた場合について説明したが、これに限らず、例えば図１３に示す他の製造方法のように、半導体チップ２１の半導体基板２２の下面のみを接着層４２を介してベース板４１上に接着するようにしてもよい。ただし、この場合、ベース板４１および接着層４２を剥がすと、絶縁膜２６の下面および第１の突起電極３３の下面が半導体基板２２の下面から突出するので、実装時の必要性に応じてこれらの突出部を研磨して除去してもよい。また、接着層４２の代わりに、ダイシングテープのように引き延ばして半導体基板２２等から剥離するものを用いてもよい。
【００４１】
また、上記実施形態では、図１（Ａ）、（Ｂ）、（Ｃ）に示すように、第１の再配線３２のパッド部下に第１の突起電極３３を形成し、第２の再配線３６のパッド部上に第２の突起電極３７を形成した場合について説明したが、これに限定されるものではない。例えば、図１４に示すこの発明の他の実施形態のように、第１の再配線３２のパッド部上に第２の突起電極３７を形成するようにしてもよい。この場合、第１の突起電極３３と第２の突起電極３７は同じ位置に形成されるので、図１５に図示するように、半田ボール３４を半導体装置の一面側、例えば、第１の突起電極３３側上のみに形成しておけば、他面側の第２の突起電極３７上に第２の半田ボール３８を形成せずとも、この上に同様な半導体装置を積層することもできる。
【００４２】
さらに、図示していないが、第１の突起電極３３下に半田ボールを形成せずに、第２の突起電極３７上にのみ半田ボールを形成するようにしてもよい。また、図１４および図１５に図示された構造の変形例として、全ての再配線に第１、第２の突起電極３３、３７を形成するのではなく、一部は、図１（Ｃ）に示すような、第２の再配線３６を形成し、そのパッド部上に第２の突起電極３７を有するものとしたり、また、第１の再配線３２を形成し、図１（Ｂ）に示すような、第１の突起電極３３のみを有するようにもよい。
【００４３】
次に、図１６は複数の例えば３個の半導体装置を回路基板上に積層して実装した場合の一例の断面図を示したものである。この例では、第１番目の半導体装置５１は、その半田ボール３４が回路基板５４上の接続端子５５に接合されていることにより、回路基板５４上に搭載されている。第２番目の半導体装置５２は、その半田ボール３４が第１番目の半導体装置５１の突起電極３７上に接合されていることにより、第１番目の半導体装置５１上に搭載されている。第３番目の半導体装置５３は、その半田ボール３４が第２番目の半導体装置５２の突起電極３７上に接合されていることにより、第２番目の半導体装置５２上に搭載されている。
【００４４】
この場合、一番上の第３番目の半導体装置５３は、例えば、図１（Ｂ）に示すような第１の再配線３２および第１の突起電極３３のみを有し、第２の再配線３６および第２の突起電極３７を備えていないものからなっている。なお、回路基板５４上に４個以上の半導体装置を積層して実装する場合には、当然のことながら、第３番目の半導体装置５３は第２の突起電極３７を備えている。
【００４５】
また、第１番目と第２番目の半導体装置５１、５２は、第３番目の半導体装置５３への中継端子の機能のみを有する突起電極を数本有する。すなわち、図１６において左側に示すように、第１の突起電極３３と第２の突起電極３７とは、当該半導体装置に内蔵された半導体チップ２１のいずれの接続パッド２３にも接続されていないフローティング状態の下地金属層５６および中継パッド部５７を介して接続された構造となっている。この場合、図１６において、このような中継端子の機能を有する突起電極に接続される回路基板５４の接続端子５５（図１６における左側）には、第３番目の半導体装置５３のセレクト信号、リセット信号等の制御信号や、場合により駆動電圧が供給される。
【００４６】
また、図１７に示す他の例のように、回路基板５４の左側の接続端子５５がＧＮＤ端子である場合には、第１番目と第２番目の半導体装置５１、５２において、左側の第１の再配線３２のパッド部上に第２の突起電極３７を設けるようにしてもよい。ただし、この場合、第３番目の半導体装置５３は、例えば、図１（Ｃ）に示すような第２の再配線３６および第２の突起電極３７のみを有し、第１の再配線３２および第１の突起電極３３を備えていないものからなっている。この場合、第２番目の半導体装置５２の突起電極２７と第３番目の突起電極２７とを接続するための半田ボール３４は、第２番目の半導体装置５２の突起電極２７上または第３番目の半導体装置５３の突起電極２７下に予め形成しておく。
【００４７】
さらに、例えば、図１７において、第１番目の半導体装置５１の第１の突起電極３３下および第２の突起電極３７上にそれぞれ半田ボール３４を予め形成しておくようにしてもよい。この場合、実装形態等に応じて、回路基板５４の接続端子５５に接合される半田ボール３４の高さをやや高くし、第２番目の半導体装置５２の第１の突起電極３３に接合される半田ボール３４の高さをやや低くするようにしてもよい。
【００４８】
なお、図１（Ａ）において、第１の突起電極３３を半導体チップ２１の相対向する一対の辺に配列し、第２の突起電極３７を半導体チップ２１の相対向する他の一対の辺に配列したものとしているが、第１の突起電極３３および第２の突起電極３７を半導体チップ２１の隣接する辺に配列したり、全ての辺に配列することも可能である。
【００４９】
また、機器への実装の都合で、半導体装置を細長状にするために、第１の突起電極３３および第２の突起電極３７を一対の辺にのみ配列し、他の辺には配列しないようにしたり、あるいはボンディング時に各突起電極にかかる荷重を均一にするため、各半導体装置に内蔵される半導体チップ２１のいずれの接続パッド２３にも接続されない、あるいは他の突起電極と共通の接続パッドに接続されるダミーの突起電極を形成してもよい。
【００５０】
さらに、各半導体装置に内蔵される半導体チップ２１はその底面が露出された状態で第１の突起電極３３に第１の半田ボール３４を接合したが、第１の半田ボール３４を接合する前に半導体チップ２１の底面を絶縁膜（封止材）で被覆し、該絶縁膜の各第１の突起電極３３と対応する領域にスルーホールを形成し、必要に応じ、該スルーホール内にメッキをした上、第１の半田ボール３４を接合してもよく、本発明の趣旨を逸脱しない範囲内で適宜変形することが可能である。
【００５１】
【発明の効果】
以上説明したように、この発明によれば、上面、該上面に対向する下面および前記上面および前記下面間に介在された周側面を有し且つ前記上面上に接続パッドを有する半導体チップと、該半導体チップの少なくとも前記上面および前記周側面を覆うように設けられ、前記接続パッドに対応する第１の開口部と、前記半導体チップの前記周側面より外側に前記半導体チップの下面側に向けて開口する第２の開口部を有する絶縁膜と、該絶縁膜の上面に設けられ、前記第１の開口部内に前記半導体チップの接続パッドに接続されて設けられた第１のパッド部、前記絶縁膜に形成された第２の開口部内に該第２の開口部の底部を塞いで設けられた突起電極に接続された第２のパッド部を有し、前記両パッド部および前記突起電極が同一材料により一体的に形成された再配線と、前記突起電極の下面に設けられた半田ボールとを備えているので、中継基板を用いることなく、半導体チップと再配線とを確実に導電接続することができるという効果を奏する。また、この発明によれば、一面、該一面に対向する他面および前記一面および前記他面間に介在された周側面を有し且つ前記一面上に接続パッドを有する複数の半導体チップをベース板に固着する工程と、前記複数の半導体チップを含む前記ベース板上に絶縁膜を形成する工程と、前記各半導体チップの周側面より外側における前記絶縁膜に前記半導体チップの他面側に向けて開口する開口部を形成する工程と、前記絶縁膜の上面に、各々が前記各半導体チップの接続パッドに接続されて設けられたパッド部、前記絶縁膜に形成された開口部に対応するパッド部および前記半導体チップの他面側に露出する下面を有する突起電極を有する複数組の再配線を同一材料により一体的に形成する工程と、前記ベース板を剥がして、前記突起電極の下面に半田ボールを設ける工程と、前記各組の半導体チップ間における前記絶縁膜を切断して前記各半導体チップの周囲に前記突起電極が形成された半導体装置を複数個得る工程とを有するので、複数の半導体装置を一括して製造することができるという効果を奏する。
【図面の簡単な説明】
【図１】（Ａ）はこの発明の一実施形態としての半導体装置の拡大平面図、（Ｂ）はそのＩB−ＩBに沿う拡大断面図、（Ｃ）はそのＩC−ＩCに沿う拡大断面図。
【図２】図１に示す半導体装置の製造方法の一例において、当初の製造工程の断面図。
【図３】図２に続く製造工程の断面図。
【図４】図３に続く製造工程の断面図。
【図５】図４に続く製造工程の断面図。
【図６】図５に続く製造工程の断面図。
【図７】図６に続く製造工程の断面図。
【図８】図７に続く製造工程の断面図。
【図９】図８に続く製造工程の断面図。
【図１０】図９に続く製造工程の断面図。
【図１１】図１０に続く製造工程の断面図。
【図１２】図１１に続く製造工程の断面図。
【図１３】図１に示す半導体装置の製造方法の他の例を説明するために示す断面図。
【図１４】この発明の他の実施形態としての半導体装置の断面図。
【図１５】この発明のさらに他の実施形態としての半導体装置の断面図。
【図１６】複数の半導体装置を回路基板上に積層して実装した場合の一例の断面図。
【図１７】複数の半導体装置を回路基板上に積層して実装した場合の他の例の断面図。
【図１８】従来の半導体装置の一例の断面図。
【符号の説明】
２１ 半導体チップ
２２ 半導体基板
２３ 接続パッド
２４ 絶縁膜
２６ 絶縁膜
２８ スルーホール
３１ 第１の下地金属層
３２ 第１の再配線
３３ 突起電極
３４ 第１の半田ボール
３５ 第２の下地金属層
３６ 第２の再配線
３７ 第２の突起電極
３８ 第２の半田ボール
３９ 絶縁膜
４１ ベース板
４２ 接着層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof.
[0002]
[Prior art]
For example, in a semiconductor device called a BGA (ball grid array), a semiconductor chip made of LSI or the like is mounted on the center of the upper surface of a relay substrate (interposer) that is slightly larger than the size of the semiconductor chip, and is mounted on the lower surface of the relay substrate. There is one in which connection terminals by solder balls are arranged in a matrix.
[0003]
FIG. 18 shows a sectional view of an example of such a conventional semiconductor device. The semiconductor chip 1 has a structure in which a plurality of bump electrodes 3 are provided around the upper surface of a semiconductor substrate 2.
[0004]
The relay substrate 4 includes a base film 5 whose size is slightly larger than the size of the semiconductor substrate 2 of the semiconductor chip 1. A rewiring 6 connected to the bump electrode 3 of the semiconductor chip 1 is provided on the upper surface of the base film 5.
[0005]
The rewiring 6 includes a first connection pad 7 provided corresponding to the bump electrode 3 of the semiconductor chip 1, a second connection pad 8 provided in a matrix, and the first and second connection pads 7. , 8 and a lead-out line 9 connecting them. A circular hole 10 is provided in the base film 5 in a portion corresponding to the central portion of the second connection pad 8.
[0006]
  The semiconductor chip 1 is mounted on the center of the upper surface of the relay substrate 4 via an anisotropic conductive adhesive 11. The anisotropic conductive adhesive 11 is made of a thermosetting resin 12 containing a large number of conductive particles 13.
[0007]
When the semiconductor chip 1 is mounted on the relay substrate 4, first, the semiconductor chip 1 is simply placed on the center of the upper surface of the relay substrate 4 with the sheet-like anisotropic conductive adhesive 11 being positioned. To do.
[0008]
Next, bonding is performed by applying a predetermined pressure at a temperature at which the thermosetting resin 12 is cured. Then, the bump electrode 3 pushes away the thermosetting resin 12 and is conductively connected to the upper surface of the first connection pad 7 via the conductive particles 13, and the lower surface of the semiconductor chip 1 is thermoset to the upper surface of the relay substrate 4. It adheres via the adhesive resin 12.
[0009]
Next, a resin sealing film 14 made of an epoxy resin is formed on the entire top surface of the relay substrate 4 including the semiconductor chip 1. Next, solder balls 15 are formed in the circular hole 10 and below the circular holes 10 by being connected to the second connection pads 8. In this case, since the second connection pads 8 are arranged in a matrix, the solder balls 15 are also arranged in a matrix.
[0010]
Here, the size of the solder balls 15 is larger than the size of the bump electrodes 3 of the semiconductor chip 1, and it is necessary to make the arrangement interval larger than the arrangement interval of the bump electrodes 3 in order to avoid contact between the solder balls 15. . Therefore, when the number of bump electrodes 3 of the semiconductor chip 1 is increased, it is necessary to make the arrangement region larger than the size of the semiconductor chip 1 in order to obtain a necessary arrangement interval for each solder ball 15, and for this reason, The size of 4 is slightly larger than the size of the semiconductor chip 1. Therefore, among the solder balls 15 arranged in a matrix, the peripheral solder balls 15 are arranged around the semiconductor chip 1.
[0011]
[Problems to be solved by the invention]
By the way, in the conventional semiconductor device having the connection terminals by the solder balls 15 also around the semiconductor chip 1 as described above, the bump electrode 3 of the semiconductor chip 1 is bonded by using the relay substrate 4 on which the rewiring 6 is formed. Is connected to the upper surface of the first connection electrode 7 of the rewiring 6 of the relay substrate 4 through the conductive particles 13 of the anisotropic conductive adhesive 11, so that connection failure occurs depending on the bonding state. There was a problem that could be. In addition, the semiconductor chips 1 must be bonded and mounted on the relay substrate 4 one by one, resulting in a problem that the manufacturing process is complicated.
[0012]
  Accordingly, the present invention provides a semiconductor device having a connection terminal also around the semiconductor chip, and reliably connects the semiconductor chip and the rewiring without using a relay substrate.InIt is an object of the present invention to provide a semiconductor device and a manufacturing method thereof that can be conductively connected. Another object of the present invention is to provide a semiconductor device manufacturing method capable of manufacturing a plurality of semiconductor devices at once.
[0013]
[Means for Solving the Problems]
  A semiconductor device according to the invention of claim 1 is provided.An upper surface, a lower surface facing the upper surface, and a peripheral side surface interposed between the upper surface and the lower surface;A semiconductor chip having connection pads on the surface, and at least the semiconductor chip;UpProvided to cover the surface and the peripheral side surface,A first opening corresponding to the connection pad, and a second opening that opens outward from the peripheral side surface of the semiconductor chip toward the lower surface side of the semiconductor chip.An insulating film having an opening and an upper surface of the insulating film;Provided in the first opening.Provided connected to the connection pad of the semiconductor chipA first pad portion, and a second pad portion connected to a protruding electrode provided by closing a bottom portion of the second opening portion in a second opening portion formed in the insulating film, A rewiring in which both pad portions and the protruding electrode are integrally formed of the same material, and a solder ball provided on the lower surface of the protruding electrodeIt is characterized by havingThe
Claim2In the semiconductor device according to claim 1, in the invention according to claim 1, a second protruding electrode protruding in a direction opposite to the protruding electrode is formed on the rewiring on which the protruding electrode is formed. It is characterized byThe
   Claim3The semiconductor device according to the invention described in claim 1, in the invention according to claim 1,The rewiring is connected to the connection pad that is not connectedThe second rewiringOn top of the insulating filmA second protruding electrode formed and protruding in a direction opposite to the protruding electrode is formed on the pad portion of the second rewiring.
   Claim4A semiconductor device according to the invention described in claim2Or3In the invention described in item 2, a second insulating film covering the periphery of the second protruding electrode is formed on the insulating film.
   Claim5The semiconductor device according to the invention described in claim 1 further includes a protruding electrode that is not connected to the connection pad.The
   Claim6A method for manufacturing a semiconductor device according to the invention described in 1The other surface opposite to the one surface and the peripheral surface interposed between the one surface and the other surface, and the one surfaceA step of fixing a plurality of semiconductor chips having connection pads thereon to a base plate; a step of forming an insulating film on the base plate including the plurality of semiconductor chips; and the outside of a peripheral side surface of each semiconductor chip. Insulating filmOpening toward the other side of the semiconductor chipA step of forming an opening; and an upper surface of the insulating film, each connected to a connection pad of each semiconductor chip.Pad part,Pad portion corresponding to the opening formed in the insulating filmAnd a protruding electrode having a lower surface exposed on the other surface side of the semiconductor chip.Multiple sets of rewiringIntegrated with the same materialForming, andPeeling the base plate and providing solder balls on the lower surface of the protruding electrodes;And cutting the insulating film between the semiconductor chips of each set to obtain a plurality of semiconductor devices in which the protruding electrodes are formed around the semiconductor chips.
   Claim7A method of manufacturing a semiconductor device according to the invention described in claim6In the invention described inRemoving the foreign matter adhering to the lower surface of the projecting electrode after forming the solder ball on the lower surface of the projecting electrode of each rewiring after peeling the semiconductor chip from the base plate;It is characterized by having.
   A method of manufacturing a semiconductor device according to the invention described in claim 8 is provided.6In the invention described in the above,Forming a second protruding electrode protruding in a direction opposite to the protruding electrode on a pad portion of the rewiring not having a protruding electrode having a lower surface exposed on the other surface side of the semiconductor chip;Forming a second insulating film covering the periphery of the protruding electrode on the insulating filmWhenIt is characterized by having.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
1A to 1C show a semiconductor device as an embodiment of the present invention. FIG. 1A is an enlarged plan view of the semiconductor device, and FIG. This is for explaining the wiring state on the back surface side, and is shown by I in FIG.B-IBFIG. 1C is an enlarged cross-sectional view taken along the line A and FIG. 1C is for explaining a wiring state on the surface side of the semiconductor device.C-ICFIG.
[0015]
This semiconductor device includes a semiconductor chip 11 made of an LSI or the like. The semiconductor chip 21 is provided with a plurality of connection pads 23 on the periphery of the upper surface of a semiconductor substrate 22 made of silicon or the like, and an insulating film 24 made of silicon oxide or the like is provided on the upper surface of the semiconductor substrate 22 excluding the central portion of the connection pads 23. Thus, the central portion of the connection pad 23 is exposed through an opening 25 provided in the insulating film 24.
[0016]
The semiconductor chip 21 is covered with an insulating film 26 made of polyimide resin, epoxy resin, PBO (polybenzoxide) resin or the like on the upper surface and the peripheral side surface except for the lower surface. The insulating film 26 is provided such that its upper surface is flat and its lower surface is flush with the lower surface of the semiconductor substrate 22. In this case, an opening 27 is provided in a portion of the insulating film 26 corresponding to the opening 25 of the semiconductor chip 21. In addition, through holes (openings) 28 are provided at predetermined plural positions of the insulating film 26 outside the peripheral side surface of the semiconductor chip 21.
[0017]
As shown in FIGS. 1A and 1B, the insulating film 26 is arranged from the upper surface of the connection pad 23 that is arranged on a pair of opposite sides of the semiconductor chip 21 and exposed through both openings 25 and 27. A first base metal layer 31 is provided across the top surface of the through hole 28 and the inner wall surface and inner bottom portion of the through hole 28. In this case, the lower surface of the first base metal layer 31 provided on the inner bottom portion of the through hole 28 is flush with the lower surface of the insulating film 26. A first rewiring 32 is provided on the upper surface of the first base metal layer 31.
[0018]
Here, the first base metal layer 31 and the first rewiring 32 provided in the through hole 28 are, as will be described later, a first protruding electrode 33 having a function of a connection terminal portion connected to an external circuit. Is configured. Accordingly, the first rewiring 32 includes a pad portion formed of a portion connected to the connection pad 23 of the semiconductor chip 21 and a portion disposed on the through hole 28 and integrally connected to the first protruding electrode 33. And a lead line connecting the two pad portions. A first solder ball 34 is provided on the lower surface of the first base metal layer 31 provided at the inner bottom of the through hole 28, that is, on the lower surface of the first protruding electrode 33.
[0019]
As shown in FIGS. 1A and 1C, the semiconductor chip 21 is insulated from the upper surface of the connection pad 23 arranged on the other pair of sides facing each other and exposed through the openings 25 and 27. A second base metal layer 35 is provided over another portion of the upper surface of the film 26. A second rewiring 36 is provided on the upper surface of the second base metal layer 35. A columnar second protruding electrode 37 is provided on the tip of the second rewiring 36. Here, the second rewiring 36 includes a pad portion formed of a portion connected to the connection pad 23 of the semiconductor chip 21, a pad portion formed of a portion connected to the second protruding electrode 37, and both pad portions. It consists of a lead wire to connect. As will be described later, the second base metal layer 35 and the second rewiring 36 are formed in the same process as the first base metal layer 31 and the first rewiring 32, respectively. Are the same.
[0020]
A second solder ball 38 is provided on the upper surface of the second protruding electrode 37. An insulating film (sealing film) 39 made of polyimide resin, epoxy resin, PBO resin or the like is formed on the upper surface of the insulating film 26 including both the rewirings 32 and 36 except for the second protruding electrode 37. The second protrusion electrode 37 is provided so as to be flush with the upper surface.
[0021]
As described above, in this semiconductor device, the first and second protruding electrodes 33 and 37 are formed on the upper and lower surfaces, and the first and second protruding electrodes 33 and 37 joined to the first and second protruding electrodes 33 and 37, respectively. Therefore, the first solder ball 34 on the one surface side of the semiconductor device is joined to the circuit board or other electronic component, and the second solder ball 38 on the other surface side is connected to the other solder balls 34, 38. It becomes possible to directly bond to a circuit board or an electronic component, which is advantageous not only in terms of production efficiency and cost but also in improving the mounting density.
[0022]
In the above embodiment, since the first and second solder balls 34 and 38 on the upper and lower surfaces are arranged on the outer periphery of the semiconductor chip 21, the pitch between the first and second solder balls 34 and 38 is set. Therefore, even when the pitch of the connection pads 23 of the semiconductor chip 21 is small, a short circuit between the connection portions can be prevented.
[0023]
In the above embodiment, the first and second solder balls 34 and 38 arranged on the upper and lower surfaces of the semiconductor device are arranged in one row on the outer peripheral portion of the semiconductor chip 21. You can also Further, the second solder balls 38 arranged on the upper surface side of the semiconductor device are formed not only on the outer peripheral portion of the semiconductor chip 21 but also on an area corresponding to the semiconductor chip 21 in an array such as a matrix. be able to.
[0024]
Next, an example of a method for manufacturing this semiconductor device will be described. First, as shown in FIG. 2, a base plate 41 made of an ultraviolet transmissive glass plate, a transparent metal plate, a transparent resin plate, or the like is provided with an adhesive layer 42 whose adhesive strength is reduced by irradiation of ultraviolet rays. prepare. Then, the lower surface of the semiconductor substrate 22 constituting the semiconductor chip 21 is bonded to a plurality of predetermined positions on the upper surface of the adhesive layer 42. The thickness of the semiconductor chip 21 is about 20 to 50 μm. In this case, instead of the method of mounting the individual semiconductor chips 21 separated by dicing on the base plate 41, the semiconductor wafer is bonded to the base plate 41 and the semiconductor chips 21 are separated by a blade or the like. May be excised. In each drawing explaining the following manufacturing method, the region of the semiconductor chip 21 in the center is I in FIG.B-IBThe cross section taken along the line and the region of the semiconductor chip 21 on both sides thereof are indicated by I in FIG.C-ICA cross section along the line is shown.
[0025]
Next, an insulating film 26 made of polyimide resin, epoxy resin, PBO resin, or the like is applied to the upper surface of the adhesive layer 42 including the plurality of semiconductor chips 21 by spin coating or printing, and dried. Then, a photoresist is applied, and the insulating film 26 is patterned as shown in FIG. 3 by photolithography. In this case, the upper surface of the insulating film 26 is flat, an opening 27 is formed in a portion corresponding to the opening 25 of the semiconductor chip 21, and a predetermined portion of the insulating film 26 around the semiconductor chip 21 in the central portion is formed. Through holes 28 are formed at a plurality of locations. After patterning the insulating film 26, the photoresist is peeled off.
[0026]
Next, as shown in FIG. 4, a base metal layer 43 is formed on the upper surface of the insulating film 26 including the upper surfaces of the connection pads 23 exposed in the through holes 28 and through the openings 25 and 27. The underlying metal layer 43 may be, for example, only a copper layer formed by sputtering, or may be a copper layer formed by sputtering on a thin film layer such as titanium formed by sputtering.
[0027]
Next, a plating resist film 44 is patterned on the upper surface of the base metal layer 43. In this case, an opening 45 is formed in the plating resist film 44 in a portion corresponding to the region where the first and second rewirings 32 and 36 are formed. Next, the first and second rewirings 32 and 36 are formed on the upper surface of the base metal layer 43 in the opening 45 of the plating resist film 44 by performing electrolytic plating of copper or the like using the base metal layer 43 as a plating current path. Form.
[0028]
As a result, the first rewiring 32 is integrally connected to the first protruding electrode 33 disposed on the through hole 28 and the pad portion formed of the portion connected to the connection pad 23 of the semiconductor chip 21. The second rewiring 36 is composed of a pad portion formed of a portion connected to the connection pad 23 of the semiconductor chip 21 and a second portion to be described later. The pad portion is composed of a portion connected to the protruding electrode 37, and a lead line connecting the two pad portions. Next, the plating resist film 44 is peeled off.
[0029]
In the formation of the first rewiring 32, the pad portion corresponding to the opening 27 of the insulating film 26 is provided integrally with the first protruding electrode 33, so that the production is very efficient. However, the upper side of the pad portion of the first rewiring 32 constituting the first protruding electrode 33 is formed to be depressed during plating. If it is desired to form the upper side of the first protruding electrode 33 so as to be flat with the lead line, the through hole 28 is not formed in the insulating film 26 in FIG. In the portion corresponding to 25, only the opening 27 is formed, the base metal layer 43 is formed, the plating resist film 44 is patterned, and electrolytic plating such as copper is performed using the base metal layer 43 as a plating current path. After the first and second rewirings 32 and 36 are formed, the through hole 28 is formed in the insulating film 26 (performed by removing the base plate 41), and the first re-wiring in the through hole 28 is formed by plating or the like. The first protruding electrode 33 may be formed on the pad portion of the wiring 32.
[0030]
Next, as shown in FIG. 5, a plating resist film 46 is patterned on the upper surface of the base metal layer 43 including the first and second rewirings 32 and 36. In this case, an opening 47 is formed in the plating resist film 46 in a portion corresponding to the pad portion of the second rewiring 36. Next, the second protruding electrode 37 is formed on the upper surface of the pad portion of the second rewiring 36 in the opening 47 of the plating resist film 46 by performing electrolytic plating of copper or the like using the base metal layer 43 as a plating current path. Is formed to a height of about 100 to 150 μm. Next, the plating resist film 46 is peeled off.
[0031]
Next, unnecessary portions of the base metal layer 43 are removed by etching using the first and second rewirings 32 and 36 as a mask (in this case, the first and second rewirings 32 and 36 serving as masks are also removed). Etching is performed at the same time, but since the thickness is larger than that of the base metal layer 43, the etching should be stopped when the base metal layer 43 is etched). As shown in FIG. The first and second base metal layers 31 and 35 remain only under the rewirings 32 and 36.
[0032]
Here, the height of the first protruding electrode 33 formed of the first base metal layer 31 and the first rewiring 32 formed in the through hole 28 is the thickness of the semiconductor chip 21 (about 20 to 50 μm). And the thickness of the insulating film 26 (for example, about 10 μm on the semiconductor chip 21), which is lower than the height of the second protruding electrode 37 (about 100 to 150 μm). ing.
[0033]
Next, as shown in FIG. 7, the upper surface of the insulating film 26 including the second protruding electrode 37 and the first and second rewirings 32 and 36 is made of polyimide resin, epoxy resin, PBO resin, or the like. The insulating film 39 is formed by a dispenser method, a printing method, a transfer mold method or the like so that its thickness is slightly larger than the height of the second protruding electrode 37. Therefore, in this state, the upper surface of the second protruding electrode 37 is covered with the insulating film 39.
[0034]
Next, the upper surface side of the insulating film 39 is appropriately polished to expose the upper surface of the second protruding electrode 37 as shown in FIG. Next, as shown in FIG. 9, the second solder ball 38 is formed on the upper surface of the second protruding electrode 37. The second solder ball 38 is formed by adsorbing the second solder ball 38 with an adsorbing tool and placing the second solder ball 38 on the second protruding electrode 37, performing reflow, printing, or the like. For example, a solder layer is deposited on the upper surface and the second solder balls 38 are formed by reflow.
[0035]
Next, when ultraviolet rays are irradiated from the lower surface side of the base plate 41 to reduce the adhesive force of the adhesive layer 42 and the base plate 41 and the adhesive layer 42 are peeled off, the result is as shown in FIG. In this state, the lower surface of the insulating film 26 and the lower surface of the first protruding electrode 33 are flush with the lower surface of the semiconductor substrate 22. Here, when an adhesive or a foreign substance adheres to the lower surface of the first protruding electrode 33, it is removed by plasma etching or the like.
[0036]
Next, as shown in FIG. 11, a first solder ball 34 is formed under the first protruding electrode 33. Next, as shown in FIG. 12, when the insulating film 26 and the insulating film 39 are cut between the adjacent semiconductor chips 21, 21, a plurality of semiconductor devices shown in FIGS. 1A, 1B, 1C are obtained. Can be obtained.
[0037]
In the semiconductor device thus obtained, the first and second base metal layers 31 and 35 and the first and second rewirings 32 and 36 connected to the connection pads 23 of the semiconductor chip 21 are sputtered and electrolyzed. Since it is formed by plating, the conductive connection between the connection pad 23 of the semiconductor chip 21 and the first and second rewirings 32 and 36 can be ensured.
[0038]
Further, in the manufacturing method of the present embodiment, the semiconductor chip 21 is adhered and arranged at a plurality of predetermined positions on the adhesive layer 42 on the base plate 41, and the insulating films 16, 39, Formation of first and second base metal layers 31 and 35, first and second rewirings 32 and 36, first and second protruding electrodes 33 and 37, and first and second solder balls 34 and 38 Are performed in a lump and then divided into a plurality of semiconductor devices, so that the manufacturing process can be simplified.
[0039]
Moreover, since the several semiconductor chip 21 can be conveyed with the base plate 41, a manufacturing process can also be simplified by this. Furthermore, if the outer dimensions of the base plate 41 are made constant, the transport system can be shared regardless of the outer dimensions of the semiconductor device to be manufactured.
[0040]
In the above embodiment, for example, as shown in FIG. 9, the case where the adhesive layer 42 is provided on the entire upper surface of the base plate 41 has been described. However, the present invention is not limited to this. In addition, only the lower surface of the semiconductor substrate 22 of the semiconductor chip 21 may be bonded onto the base plate 41 via the adhesive layer 42. However, in this case, if the base plate 41 and the adhesive layer 42 are peeled off, the lower surface of the insulating film 26 and the lower surface of the first protruding electrode 33 protrude from the lower surface of the semiconductor substrate 22. You may grind | polish and remove the protrusion part. Further, instead of the adhesive layer 42, a material that is stretched like a dicing tape and peeled from the semiconductor substrate 22 or the like may be used.
[0041]
Moreover, in the said embodiment, as shown to FIG. 1 (A), (B), (C), the 1st protruding electrode 33 is formed under the pad part of the 1st rewiring 32, and 2nd rewiring is carried out. Although the case where the second protruding electrode 37 is formed on the pad portion 36 has been described, the present invention is not limited to this. For example, the second protruding electrode 37 may be formed on the pad portion of the first rewiring 32 as in another embodiment of the present invention shown in FIG. In this case, since the first protruding electrode 33 and the second protruding electrode 37 are formed at the same position, as shown in FIG. 15, the solder ball 34 is placed on one side of the semiconductor device, for example, the first protruding electrode. If it is formed only on the 33 side, a similar semiconductor device can be laminated on the second protruding electrode 37 on the other side without forming the second solder ball 38.
[0042]
Further, although not shown, a solder ball may be formed only on the second protruding electrode 37 without forming a solder ball under the first protruding electrode 33. Further, as a modification of the structure shown in FIGS. 14 and 15, the first and second protruding electrodes 33 and 37 are not formed on all the rewirings, but a part thereof is shown in FIG. As shown in FIG. 1B, a second rewiring 36 is formed and a second protruding electrode 37 is formed on the pad portion, or a first rewiring 32 is formed. Only the first protruding electrode 33 may be provided.
[0043]
Next, FIG. 16 shows a cross-sectional view of an example when a plurality of, for example, three semiconductor devices are stacked and mounted on a circuit board. In this example, the first semiconductor device 51 is mounted on the circuit board 54 by the solder balls 34 being bonded to the connection terminals 55 on the circuit board 54. The second semiconductor device 52 is mounted on the first semiconductor device 51 by bonding the solder balls 34 onto the protruding electrodes 37 of the first semiconductor device 51. The third semiconductor device 53 is mounted on the second semiconductor device 52 by the solder ball 34 being bonded onto the protruding electrode 37 of the second semiconductor device 52.
[0044]
In this case, the uppermost third semiconductor device 53 has only the first rewiring 32 and the first protruding electrode 33 as shown in FIG. 1B, for example, and the second rewiring. 36 and the second protruding electrode 37 are not provided. In the case where four or more semiconductor devices are stacked and mounted on the circuit board 54, the third semiconductor device 53 is provided with the second protruding electrode 37 as a matter of course.
[0045]
In addition, the first and second semiconductor devices 51 and 52 have several protruding electrodes having only a function of a relay terminal to the third semiconductor device 53. That is, as shown on the left side in FIG. 16, the first protruding electrode 33 and the second protruding electrode 37 are not connected to any connection pad 23 of the semiconductor chip 21 incorporated in the semiconductor device. The structure is connected via the underlying metal layer 56 and the relay pad portion 57 in the state. In this case, in FIG. 16, the select signal and reset of the third semiconductor device 53 are connected to the connection terminal 55 (the left side in FIG. 16) of the circuit board 54 connected to the protruding electrode having the function of the relay terminal. A control signal such as a signal, and in some cases a drive voltage is supplied.
[0046]
Further, as in the other example shown in FIG. 17, when the left connection terminal 55 of the circuit board 54 is a GND terminal, the first and second semiconductor devices 51 and 52 have the left first A second protruding electrode 37 may be provided on the pad portion of the rewiring 32. However, in this case, the third semiconductor device 53 has only the second rewiring 36 and the second protruding electrode 37 as shown in FIG. 1C, for example, and the first rewiring 32 and The first protrusion electrode 33 is not provided. In this case, the solder ball 34 for connecting the protruding electrode 27 of the second semiconductor device 52 and the third protruding electrode 27 is on the protruding electrode 27 of the second semiconductor device 52 or the third one. It is formed in advance under the bump electrode 27 of the semiconductor device 53.
[0047]
Further, for example, in FIG. 17, solder balls 34 may be formed in advance under the first protruding electrode 33 and the second protruding electrode 37 of the first semiconductor device 51, respectively. In this case, the height of the solder ball 34 bonded to the connection terminal 55 of the circuit board 54 is slightly increased according to the mounting form and the like, and is bonded to the first protruding electrode 33 of the second semiconductor device 52. The height of the solder ball 34 may be slightly lowered.
[0048]
In FIG. 1A, the first protruding electrodes 33 are arranged on a pair of opposite sides of the semiconductor chip 21, and the second protruding electrodes 37 are arranged on the other pair of opposite sides of the semiconductor chip 21. Although the arrangement is such that the first protruding electrode 33 and the second protruding electrode 37 are arranged on adjacent sides of the semiconductor chip 21 or arranged on all sides.
[0049]
Further, for the convenience of mounting on equipment, in order to make the semiconductor device elongated, the first protruding electrode 33 and the second protruding electrode 37 are arranged only on a pair of sides and not on the other sides. In order to make the load applied to each protruding electrode uniform during bonding, it is not connected to any connection pad 23 of the semiconductor chip 21 incorporated in each semiconductor device, or is connected to a common connection pad with other protruding electrodes A dummy protruding electrode to be connected may be formed.
[0050]
Further, the first solder ball 34 is bonded to the first protruding electrode 33 with the bottom surface of the semiconductor chip 21 incorporated in each semiconductor device exposed, but before the first solder ball 34 is bonded. The bottom surface of the semiconductor chip 21 is covered with an insulating film (sealing material), a through hole is formed in a region corresponding to each first protruding electrode 33 of the insulating film, and plating is performed in the through hole as necessary. In addition, the first solder balls 34 may be joined and can be appropriately modified without departing from the spirit of the present invention.
[0051]
【The invention's effect】
  As explained above, according to the present invention,A semiconductor chip having an upper surface, a lower surface facing the upper surface, a peripheral side surface interposed between the upper surface and the lower surface, and having a connection pad on the upper surface, and covering at least the upper surface and the peripheral side surface of the semiconductor chip A first opening corresponding to the connection pad, and an insulating film having a second opening that opens outward from the peripheral side surface of the semiconductor chip toward the lower surface side of the semiconductor chip; A first pad portion provided on an upper surface of the insulating film and connected to a connection pad of the semiconductor chip in the first opening portion; and a second opening portion formed in the insulating film. A re-wiring having a second pad portion connected to a protruding electrode provided by closing a bottom portion of the two opening portions, wherein both the pad portion and the protruding electrode are integrally formed of the same material; Bump Since a solder ball provided on the lower surface of an effect that it is possible to reliably connect the conductive and without the semiconductor chip and the rewiring using relay substrate. Further, according to the present invention, a base plate includes a plurality of semiconductor chips having one surface, another surface facing the one surface, a peripheral side surface interposed between the one surface and the other surface, and having connection pads on the one surface. Fixing to the base plate, forming the insulating film on the base plate including the plurality of semiconductor chips, and facing the other side of the semiconductor chip toward the insulating film outside the peripheral side surface of each semiconductor chip. A step of forming an opening to be opened; a pad portion provided on the upper surface of the insulating film, each connected to a connection pad of each semiconductor chip; and a pad portion corresponding to the opening formed in the insulating film And a step of integrally forming a plurality of sets of rewirings having a protruding electrode having a lower surface exposed on the other surface side of the semiconductor chip from the same material; Providing a plurality of semiconductor devices in which the protruding electrodes are formed around the semiconductor chips by cutting the insulating film between the semiconductor chips of each set. Manufacturing of all semiconductor devicesThere is an effect that can be done.
[Brief description of the drawings]
FIG. 1A is an enlarged plan view of a semiconductor device as an embodiment of the present invention, and FIG.B-IB(C) is the IC-ICFIG.
2 is a cross-sectional view of an initial manufacturing process in the example of the method for manufacturing the semiconductor device shown in FIG. 1;
FIG. 3 is a cross-sectional view of the manufacturing process following FIG. 2;
FIG. 4 is a cross-sectional view of the manufacturing process following FIG. 3;
FIG. 5 is a cross-sectional view of the manufacturing process following FIG. 4;
6 is a cross-sectional view of the manufacturing process following FIG. 5. FIG.
7 is a cross-sectional view of a manufacturing step that follows FIG. 6. FIG.
FIG. 8 is a cross-sectional view of the manufacturing process following FIG. 7;
FIG. 9 is a cross-sectional view of the manufacturing process following FIG. 8;
10 is a cross-sectional view of a manufacturing step that follows FIG. 9; FIG.
FIG. 11 is a cross-sectional view of the manufacturing process following FIG. 10;
FIG. 12 is a cross-sectional view of the manufacturing process following FIG. 11;
13 is a cross-sectional view for explaining another example of the method for manufacturing the semiconductor device shown in FIG. 1. FIG.
FIG. 14 is a cross-sectional view of a semiconductor device as another embodiment of the present invention.
FIG. 15 is a sectional view of a semiconductor device as still another embodiment of the present invention.
FIG. 16 is a cross-sectional view of an example when a plurality of semiconductor devices are stacked and mounted on a circuit board.
FIG. 17 is a cross-sectional view of another example when a plurality of semiconductor devices are stacked and mounted on a circuit board.
FIG. 18 is a cross-sectional view of an example of a conventional semiconductor device.
[Explanation of symbols]
21 Semiconductor chip
22 Semiconductor substrate
23 connection pads
24 Insulating film
26 Insulating film
28 Through hole
31 First base metal layer
32 First rewiring
33 Projection electrode
34 First solder ball
35 Second base metal layer
36 Second rewiring
37 Second protruding electrode
38 Second solder ball
39 Insulating film
41 Base plate
42 Adhesive layer

Claims (8)

上面、該上面に対向する下面および前記上面および前記下面間に介在された周側面を有し且つ前記上面上に接続パッドを有する半導体チップと、該半導体チップの少なくとも前記上面および前記周側面を覆うように設けられ、前記接続パッドに対応する第１の開口部と、前記半導体チップの前記周側面より外側に前記半導体チップの下面側に向けて開口する第２の開口部を有する絶縁膜と、該絶縁膜の上面に設けられ、前記第１の開口部内に前記半導体チップの接続パッドに接続されて設けられた第１のパッド部、前記絶縁膜に形成された第２の開口部内に該第２の開口部の底部を塞いで設けられた突起電極に接続された第２のパッド部を有し、前記両パッド部および前記突起電極が同一材料により一体的に形成された再配線と、前記突起電極の下面に設けられた半田ボールとを備えていることを特徴とする半導体装置。 Upper surface, a semiconductor chip having connection pads on the lower surface and having interposed a peripheral side surface between the upper surface and the lower surface and on the upper surface opposed to the upper surface, the semiconductor chip of at least the upper provided so as to cover the surface and the peripheral side surface, and a first opening corresponding to the connection pad, a second which opens toward the lower surface side of the semiconductor chip from outside the peripheral side surface of said semiconductor chip an insulating film having an opening, provided on the upper surface of the insulating film, a first pad portion connected provided the connection pads of the semiconductor chip to the first opening portion, formed in the insulating film A second pad portion connected to a protruding electrode provided by closing the bottom of the second opening in the second opening , and the two pad portions and the protruding electrode are integrally formed of the same material; The rewiring formed on the A semiconductor device characterized by comprising a solder ball provided on the lower surface of the. 請求項１に記載の発明において、前記突起電極が形成された前記再配線に、前記突起電極とは反対方向に突き出す第２の突起電極が形成されていることを特徴とする半導体装置。 2. The semiconductor device according to claim 1, wherein a second protruding electrode protruding in a direction opposite to the protruding electrode is formed on the rewiring on which the protruding electrode is formed. 請求項１に記載の発明において、さらに、前記再配線が接続されていない前記接続パッドに接続された第２の再配線が前記絶縁膜の上面に形成され、該第２の再配線のパッド部上に前記突起電極とは反対方向に突き出す第２の突起電極が形成されていることを特徴とする半導体装置。The second rewiring connected to the connection pad to which the rewiring is not connected is formed on the upper surface of the insulating film, and the pad portion of the second rewiring is further provided. A semiconductor device, wherein a second protruding electrode protruding in a direction opposite to the protruding electrode is formed thereon. 請求項２または３に記載の発明において、前記絶縁膜上に前記第２の突起電極の周囲を覆う第２の絶縁膜が形成されていることを特徴とする半導体装置。 4. The semiconductor device according to claim 2, wherein a second insulating film that covers the periphery of the second protruding electrode is formed on the insulating film. 請求項１に記載の発明において、さらに、前記接続パッドに接続されない突起電極を有することを特徴とする半導体装置。 2. The semiconductor device according to claim 1, further comprising a protruding electrode that is not connected to the connection pad. 一面、該一面に対向する他面および前記一面および前記他面間に介在された周側面を有し且つ前記一面上に接続パッドを有する複数の半導体チップをベース板に固着する工程と、前記複数の半導体チップを含む前記ベース板上に絶縁膜を形成する工程と、前記各半導体チップの周側面より外側における前記絶縁膜に前記半導体チップの他面側に向けて開口する開口部を形成する工程と、前記絶縁膜の上面に、各々が前記各半導体チップの接続パッドに接続されて設けられたパッド部、前記絶縁膜に形成された開口部に対応するパッド部および前記半導体チップの他面側に露出する下面を有する突起電極を有する複数組の再配線を同一材料により一体的に形成する工程と、前記ベース板を剥がして、前記突起電極の下面に半田ボールを設ける工程と、前記各組の半導体チップ間における前記絶縁膜を切断して前記各半導体チップの周囲に前記突起電極が形成された半導体装置を複数個得る工程とを有することを特徴とする半導体装置の製造方法。 Fixing a plurality of semiconductor chips having one surface, another surface opposite to the one surface, a peripheral side surface interposed between the one surface and the other surface, and having a connection pad on the one surface to the base plate; Forming an insulating film on the base plate including the semiconductor chip, and forming an opening that opens toward the other surface of the semiconductor chip in the insulating film outside the peripheral side surface of each semiconductor chip. And a pad portion provided on the upper surface of the insulating film so as to be connected to a connection pad of each semiconductor chip, a pad portion corresponding to an opening formed in the insulating film, and the other surface side of the semiconductor chip A step of integrally forming a plurality of sets of rewirings having protruding electrodes having lower surfaces exposed on the same material, and a step of peeling the base plate and providing solder balls on the lower surfaces of the protruding electrodes And a step of cutting the insulating film between the semiconductor chips of each set to obtain a plurality of semiconductor devices in which the protruding electrodes are formed around the semiconductor chips. Method. 請求項６に記載の発明において、前記半導体チップを前記ベース板から剥がした後、前記各再配線の突起電極の下面に半田ボールを形成する前に前記突起電極の下面に付着している異物を除去する工程を有することを特徴とする半導体装置の製造方法。In the invention according to claim 6, after peeling off the semiconductor chip from the base plate, the foreign matter adhered to the lower surface of the protruding electrode before forming the solder ball the the lower surface of the bump electrode of the rewiring A method for manufacturing a semiconductor device, comprising a step of removing. 請求項６に記載の発明において、さらに、前記半導体チップの他面側に露出する下面を有する突起電極を有していない前記再配線のパッド部上に、前記突起電極とは反対方向に突き出す第２の突起電極を形成する工程と、前記絶縁膜上に前記突起電極の周囲を覆う第２の絶縁膜を形成する工程とを有することを特徴とする半導体装置の製造方法。7. The method according to claim 6, further comprising a step of protruding in a direction opposite to the protruding electrode on the pad portion of the rewiring not having the protruding electrode having a lower surface exposed on the other surface side of the semiconductor chip. forming a second protruding electrode, a method of manufacturing a semiconductor device characterized by a step of forming a second insulating film covering the periphery of the protruding electrode on the insulating film.
JP2002117307A 2002-02-04 2002-04-19 Semiconductor device and manufacturing method thereof Expired - Fee Related JP4135390B2 (en)

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JP2002117307A JP4135390B2 (en) 2002-04-19 2002-04-19 Semiconductor device and manufacturing method thereof
TW092102111A TW577160B (en) 2002-02-04 2003-01-30 Semiconductor device and manufacturing method thereof
AU2003244348A AU2003244348A1 (en) 2002-02-04 2003-02-03 Semiconductor device and method of manufacturing the same
PCT/JP2003/001061 WO2003067648A2 (en) 2002-02-04 2003-02-03 Semiconductor device and method of manufacturing the same
KR1020037012972A KR100548668B1 (en) 2002-02-04 2003-02-03 Semiconductor device and method of manufacturing the same
EP03737462A EP1472724A2 (en) 2002-02-04 2003-02-03 Semiconductor device and method of manufacturing the same
CNB038001284A CN100358118C (en) 2002-02-04 2003-02-03 Semiconductor device and method of manufacturing the same
CA002443149A CA2443149C (en) 2002-02-04 2003-02-03 Semiconductor device and method of manufacturing the same
US10/472,803 US7190064B2 (en) 2002-02-04 2003-02-03 Semiconductor device and method of manufacturing the same
MXPA03009043A MXPA03009043A (en) 2002-02-04 2003-02-03 Semiconductor device and method of manufacturing the same.
NO20034441A NO20034441L (en) 2002-02-04 2003-10-03 Semiconductor device and method for manufacturing the same
US11/429,368 US20060202353A1 (en) 2002-02-04 2006-05-05 Semiconductor device and method of manufacturing the same
US11/588,647 US7514335B2 (en) 2002-02-04 2006-10-27 Semiconductor device and method of manufacturing the same

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JP2006041438A (en) 2004-07-30 2006-02-09 Shinko Electric Ind Co Ltd Semiconductor chip built-in substrate, and its manufacturing method
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