CN111668168B - Packaging structure and forming method thereof - Google Patents
Packaging structure and forming method thereof Download PDFInfo
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- CN111668168B CN111668168B CN201910174500.XA CN201910174500A CN111668168B CN 111668168 B CN111668168 B CN 111668168B CN 201910174500 A CN201910174500 A CN 201910174500A CN 111668168 B CN111668168 B CN 111668168B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
Abstract
The invention discloses a packaging structure and a forming method thereof, wherein the packaging structure comprises at least one chip, a rewiring stack layer, a metal column and an external pin, wherein the chip is provided with a plurality of electrodes; the rewiring stacking layer is connected with the chip and comprises at least one insulating layer and at least one rewiring layer, and the rewiring layer is communicated with the electrodes; the metal column is communicated with the rewiring layer; the external pin is communicated with the rewiring layer through the metal column. The redistribution layer and the external pins of the packaging structure are connected through the metal columns, so that on one hand, the reliability of signal transmission and the ductility of a circuit can be improved, and further, the electrical performance, the reliability and the heat dissipation performance of the packaging structure are greatly improved, on the other hand, the metal columns can be used for determining the arrangement positions of the external pins, the forming of the external pins is facilitated, the process can be simplified, on the other hand, the appearance characteristics of the metal columns are obvious, and the metal columns can be used for identification reference in the subsequent analysis and detection stage.
Description
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a packaging structure and a forming method thereof.
Background
With the trend of multi-functionalization and miniaturization of electronic products, high-density microelectronic assembly technology is becoming mainstream in new generation of electronic products. In order to match the development of the new generation of electronic products, especially the development of products such as smart phones, palm computers, super books and the like, the size of the chip is developed towards the directions of higher density, higher speed, smaller size, lower cost and the like.
The emergence of Fan-out Wafer Level Chip Packaging technology (FOWLCSP) meets the characteristics of thinner Chip product size, material saving, etc., but how to improve the reliability and electrical performance of Fan-out Wafer Level Packaging products becomes a direction to be researched.
Disclosure of Invention
The invention aims to provide a packaging structure and a forming method thereof, which can improve the reliability and the electrical performance of the packaging structure.
To achieve one of the above objects, an embodiment of the present invention provides a package structure, including:
at least one chip, the chip is provided with a plurality of electrodes;
the rewiring stacking layer is connected with the chip and comprises at least one insulating layer and at least one rewiring layer, and the rewiring layer is communicated with the electrodes;
the metal column is communicated with the heavy wiring layer;
and the external pin is communicated with the redistribution layer through the metal column.
As a further improvement of an embodiment of the present invention, the redistribution layer is a copper layer, the metal pillar is a copper pillar, and the external pin is a ball.
As a further improvement of an embodiment of the present invention, the package structure further includes a molding compound layer, the molding compound layer encapsulates the chip, the redistribution layer, and the metal pillar, and at least a portion of the external pin protrudes out of the molding compound layer.
As a further improvement of an embodiment of the present invention, the insulating layer and the molding layer have different parameters, and the parameters include at least one of a thermal expansion coefficient, an elongation, a transparency, and a thickness.
As a further improvement of one embodiment of the invention, the thickness of the insulating layer is in a range of 5-20 um, the thermal expansion coefficient of the insulating layer is in a range of 30-70 ppm/K, the thickness of the plastic packaging layer is in a range of 15-100 um, the thermal expansion coefficient of the plastic packaging layer is in a range of 7-20 ppm/K, the elongation of the insulating layer is higher than that of the plastic packaging layer, and the transparency of the insulating layer is higher than that of the plastic packaging layer.
As a further improvement of the embodiment of the present invention, the plastic package layer includes a first plastic package layer and a second plastic package layer connected to each other, the first plastic package layer at least covers the chip, the second plastic package layer at least covers the metal pillar, in a first direction, a connected overlapping region is provided between the insulating layer and the first plastic package layer and/or a connected overlapping region is provided between the first plastic package layer and the second plastic package layer, and the first direction is an extending direction of the redistribution layer.
As a further improvement of the embodiment of the present invention, the redistribution layer stack includes a first insulating layer, a first redistribution layer and a second insulating layer, which are sequentially stacked on the chip and penetrate through the first insulating layer to connect the electrodes, and in the first direction, at least a portion of the second insulating layer and the first plastic package layer have a connected overlapping region therebetween.
As a further improvement of the embodiment of the invention, the redistribution layer stack further includes a second redistribution layer penetrating through the second insulating layer to communicate with the first redistribution layer, the second molding compound layer covers the second redistribution layer and a portion of the second insulating layer, and in the first direction, a portion of the second insulating layer extends on a surface of the first molding compound layer.
As a further improvement of the embodiment of the present invention, the first plastic package layer protrudes out of the redistribution layer stack along the second direction, and in both the first direction and the second direction, there is a connected overlapping region between the second plastic package layer and the first plastic package layer, and the second direction is a direction of the chip facing the redistribution layer stack.
In order to achieve one of the above objectives, an embodiment of the present invention provides a method for forming a package structure, including the steps of:
Providing at least one chip, wherein the chip is provided with a plurality of electrodes;
forming a rewiring stacking layer connected with the chip, wherein the rewiring stacking layer comprises at least one insulating layer and at least one rewiring layer, and the rewiring layer is communicated with a plurality of electrodes;
forming a metal column on the redistribution layer;
and forming an external pin on the metal column.
Compared with the prior art, the invention has the beneficial effects that: the redistribution layer and the external pins of the packaging structure are connected through the metal columns, so that on one hand, the reliability of signal transmission and the ductility of a circuit can be improved, and further, the electrical performance, the reliability and the heat dissipation performance of the packaging structure are greatly improved, on the other hand, the metal columns can be used for determining the arrangement positions of the external pins, the forming of the external pins is facilitated, the process can be simplified, on the other hand, the appearance characteristics of the metal columns are obvious, and the metal columns can be used for identification reference in the subsequent analysis and detection stage.
Drawings
Fig. 1 is a schematic diagram of a package structure of a first specific example of the present invention;
fig. 2 is a schematic diagram of a package structure of a second specific example of the present invention;
fig. 3 is a schematic diagram of a package structure of a third specific example of the present invention;
Fig. 4 is a schematic diagram of a package structure of a fourth specific example of the present invention;
fig. 5 is a schematic diagram of a package structure of a fifth specific example of the present invention;
FIG. 6 is a method step diagram of forming a package structure according to an embodiment of the invention;
fig. 7 to 13 are schematic views illustrating a molding method of a package structure according to an embodiment of the invention.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments do not limit the present invention, and structural, methodological, or functional changes made by those skilled in the art based on these embodiments, particularly the combinations between the various embodiments, are included in the scope of the present invention.
In the various illustrations of the present application, certain dimensions of structures or portions may be exaggerated relative to other structures or portions for ease of illustration and, thus, are provided to illustrate only the basic structure of the subject matter of the present application.
Also, terms used herein such as "upper," "above," "lower," "below," and the like, denote relative spatial positions of one element or feature with respect to another element or feature as illustrated in the figures for ease of description. The spatially relative positional terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Referring to fig. 1, a package structure 100 according to an embodiment of the invention is shown.
The package structure 100 includes a chip 10, a redistribution layer stack 20, metal posts 30, and external pins 40.
One side of the chip 10 has several electrodes 101.
The redistribution layer 20 is connected to the chip 10, the redistribution layer 20 includes at least one insulation layer 21 and at least one redistribution layer 22, and the redistribution layer 22 is connected to the plurality of electrodes 101.
Here, an insulating layer 21 is disposed on the upper surface of the chip 10 (i.e., the side surface of the chip 10 on which the electrode 101 is disposed), a redistribution layer 22 is disposed on the side surface of the insulating layer 21 away from the chip 10, and a portion of the insulating layer 21 is removed by an etching process, such as UV exposure followed by wet chemical development, or laser (U or excimer laser) via drilling only, to expose the electrode 101 for communication with the redistribution layer 22.
In addition, the number of the insulating layers 21 and the redistribution layers 22 included in the redistribution layer stack 20 may be determined according to actual requirements, and when there are a plurality of insulating layers 21 and a plurality of redistribution layers 22, the insulating layers 21 and the redistribution layers 22 are arranged at intervals one by one, and the redistribution layers 22 are mutually conducted to form a channel for power signal transmission. In other embodiments, the surfaces of the insulating layer 21 and the redistribution layer 22 may be substantially even, for example, a damascoce process is used to realize the layout of the fine line width pitch.
The metal posts 30 communicate with the redistribution layer 22.
Here, the metal pillar 30 may be designed to be wider or narrower than the redistribution layer 22, but not limited thereto, and may be determined according to the actual situation.
The external pins 40 are connected to the redistribution layer 22 through the metal posts 30.
In this embodiment, the redistribution process is used to implement redistribution of the I/O terminals of the chip 10, and then the external pins 40 are combined to combine the package structure 100 with external components (e.g., a circuit board, etc.) to implement signal transmission of the chip 10, where the redistribution layer 22 and the external pins 40 are connected by the metal posts 30, on one hand, reliability of signal transmission and ductility of lines can be improved, and further, electrical performance, reliability and heat dissipation performance of the package structure 100 are greatly improved, on the other hand, the metal posts 30 can be used to determine the arrangement positions of the external pins 40, which is convenient for molding the external pins 40, and can simplify the process, and on the other hand, the metal posts 30 have obvious appearance characteristics and can be used for identification and reference in the subsequent analysis and detection stage.
The package structure 100 of the present embodiment is applicable to Fan-out Wafer Level Chip Scale Packaging (FOWLCSP), Embedded Wafer Level Chip Scale Packaging (EWLCSP), and the like, but is not limited thereto.
In the present embodiment, the redistribution layer 22 is a copper layer, the bottom of the redistribution layer 22 is provided with a metal bonding layer, the metal pillar 30 is a copper pillar, the bottom of the metal pillar 30 is provided with a metal bonding layer, the external pin 40 is a ball, specifically, a metal ball, it can be seen that the redistribution layer 22 and the metal pillar 30 are both made of copper material and both have metal bonding layers, the bonding strength between the redistribution layer 22, the metal pillar 30 and the electrode 101 is high, the electrical signal transmission performance among the redistribution layer 22, the metal pillar 30 and the electrode 101 can be greatly improved, and of course, the redistribution layer 22 and the metal pillar 30 can also be made of other metal materials.
In this embodiment, the package structure 100 further includes a molding layer 50.
The plastic package layer 50 may be an emc (epoxy Molding compound) plastic package layer, and the plastic package layer 50 may be formed by wafer-level or board-level plastic package, compression plastic package film, hot-press plastic package, or injection Molding plastic package.
The molding compound layer 50 covers the chip 10, the redistribution layer stack 20, and the metal pillar 30.
Here, "cover" means that the molding compound 50 covers at least a partial region of the corresponding component, for example, the molding compound 50 covers only the peripheral region of the chip 10 and does not cover the lower surface of the chip 10 (i.e., the surface of the chip 10 on which the electrode 101 is not provided), and the molding compound 50 covers at least four side surfaces of the chip 10 (i.e., the peripheral region of the chip 10) and the side surfaces of the metal posts 30 (i.e., the peripheral region of the metal posts 30).
The outer leads 40 at least partially protrude out of the molding layer 50.
Here, in the actual manufacturing process, when the molding layer 50 covers the metal pillar 30, a portion of the molding layer 50 may be removed by wafer-level thinning or etching, laser drilling, or the like to expose an upper end surface of the metal pillar 30 away from the redistribution layer stack 20, where the upper end surface is subsequently used for bearing the external pin 40.
In the present embodiment, the molding layer 50 and the insulating layer 21 have different parameters, and the parameters include at least one of the coefficient of thermal expansion CTE, elongation, transparency, and thickness.
That is, the molding compound layer 50 and the insulating layer 21 are made of different insulating materials, so that the insulating portion of the entire package structure 100 is a heterostructure, which can improve the board-level thermal cycle reliability of the entire package structure 100.
Here, the insulating layer 21 may be made of a dielectric material, such as a low temperature curing negative type PI, a positive type PBO, a non-photosensitive polymer dielectric with or without a filler, polyimide, or other suitable dielectric materials, and preferably, the insulating layer 21 is a high-molecular organic insulating layer with high elongation, high strength, and at least semi-transparency.
Specifically, the thickness range of the insulating layer 21 is 5-20 um, the CTE range of the insulating layer 21 is 30-70 ppm/K, the thickness range of the plastic package layer 50 is 15-100 um, the CTE range of the plastic package layer 50 is 7-20 ppm/K, the elongation of the insulating layer 21 is higher than that of the plastic package layer 50, and the transparency of the insulating layer 21 is higher than that of the plastic package layer 50 (the insulating layer 21 is in a semitransparent state, and the plastic package layer 50 is in an opaque state).
The benefit of so setting up is: (1) the insulating layer 21 (especially, the bottommost insulating layer 21) is an organic insulating layer 21 with high strength and high elongation, and the combination of the organic insulating layer 21 and the plastic package layer 50 can provide effective protection for the chip 10, improve the environmental adaptability, thermal and electrical reliability, and the like of the package structure 100; (2) the CTE difference between the insulating layer 21 and the molding layer 50 forms a graded CTE structure that reduces stress caused by CTE mismatch between the insulating layer 21 and the molding layer 50 during temperature cycling (e.g., during reliability testing), which can improve board level thermal cycling reliability of the overall package structure 100; (3) the insulating layer 21 and the plastic packaging layer 50 are thicker, so that the board-level thermal cycle reliability of the whole packaging structure 100 can be further improved; (4) the insulating layer 21 is made of semitransparent materials, so that subsequent detection, failure analysis and other processes are facilitated, and the efficiency of the detection, failure analysis and other processes can be greatly improved by matching with the metal column 30.
It should be noted that the embodiment may include the molding compound layer 50 and the insulating layer 21 with various parameters, or alternatively, a part of the molding compound layer 50 has parameters similar to those of the insulating layer 21, and only a heterostructure is formed between the molding compound layer 50 and the insulating layer 21.
In this embodiment, the molding compound layer 50 includes a first molding compound layer 51 and a second molding compound layer 52 connected to each other, the first molding compound layer 51 covers at least the chip 20, and the second molding compound layer 52 covers at least the metal pillar 30.
That is to say, the first plastic package layer 51 and the second plastic package layer 52 are substantially located at two sides of the package structure 100, and the first plastic package layer 51 and the second plastic package layer 52 are connected to each other to realize the plastic package protection of the whole package structure 100.
Next, several specific examples of the package structure 100 of the present embodiment are described in detail, and for convenience of description, a first direction a and a second direction B are defined, where the first direction a is an extending direction of the rewiring layer 22, i.e., a horizontal direction, and the second direction B is a direction in which the chip 10 faces the rewiring stacked layer 20, i.e., a vertical upward direction, and in addition, similar components in a plurality of specific examples are given similar reference numerals and similar names.
In a first specific example, referring to fig. 1, the package structure 100 includes a chip 10, a redistribution layer stack 20, a metal pillar 30, an external pin 40, and a molding compound layer 50.
One side of the chip 10 has several electrodes 101.
The rewiring stack layer 20 is connected to the chip 10, and the rewiring stack layer 20 includes a first insulating layer 211 sequentially stacked on the chip 10 and a first rewiring layer 221 penetrating the first insulating layer 211 to communicate with the electrodes 101.
The metal pillar 30 is connected to the first redistribution layer 221.
The external pin 40 is connected to the first redistribution layer 221 through the metal pillar 30.
The molding layer 50 includes a first molding layer 51 and a second molding layer 52.
The first plastic package layer 51 covers the peripheral region and the lower surface of the chip 10 (i.e., the surface of the chip 10 on the side where the electrode 101 is not disposed), the upper end surface of the first plastic package layer 51 is flush with the upper surface of the chip 10 (i.e., the surface of the chip 10 on the side where the electrode 101 is disposed), and the first insulating layer 211 extends to the upper end surface of the first plastic package layer 51 along the first direction a, but not limited thereto.
The second molding compound 52 covers the redistribution layer stack 20 and the metal pillar 30, and the second molding compound 52 is connected to the first molding compound 51.
Here, the first plastic package layer 51, the second plastic package layer 52 and the first insulating layer 211 are connected two by two to form a reliable heterostructure, and other descriptions of the heterostructure can refer to the foregoing description and are not repeated herein.
In addition, the upper end surface of the metal pillar 30 in this example is flush with the upper end surface of the second molding layer 52, in other words, the upper end surface of the metal pillar 30 can be exposed by thinning with a grinding plate or the like (the second molding layer 52 and the metal pillar 30 can be ground flat at the same time) to connect the external lead 40.
In a second specific example, referring to fig. 2, the package structure 100a includes a chip 10a, a redistribution layer stack 20a, a metal pillar 30a, an external pin 40a, and a molding layer 50 a.
One side of the chip 10a has several electrodes 101 a.
The rewiring stack layer 20a is connected to the chip 10a, and the rewiring stack layer 20a includes a first insulating layer 211a sequentially stacked on the chip 10a and a first rewiring layer 221a penetrating the first insulating layer 211a to communicate with the electrodes 101 a.
The metal pillar 30a communicates with the first redistribution layer 221 a.
The external lead 40a is connected to the first redistribution layer 221a through the metal pillar 30 a.
The molding layer 50a includes a first molding layer 51a and a second molding layer 52 a.
The first plastic sealing layer 51a covers the peripheral edge region of the chip 10a, the upper end surface of the first plastic sealing layer 51a is flush with the upper surface of the chip 10a (i.e., the surface of the chip 10a on which the electrode 101a is disposed), and the first insulating layer 211a extends to the upper end surface of the first plastic sealing layer 51a along the first direction a, but not limited thereto.
Here, the first molding compound 51a does not cover the lower surface of the chip 10a (i.e., the surface of the chip 10a on which the electrode 101a is not disposed), but a protective film 60a is disposed on the lower surface of the chip 10a, and the protective film 60a can be used to improve the heat dissipation effect of the package structure 100a, for example.
The second molding compound 52a covers the redistribution layer stack 20a and the metal pillar 30a, and the second molding compound 52a is connected to the first molding compound 51 a.
Here, the first plastic package layer 51a, the second plastic package layer 52a and the first insulating layer 211a are connected two by two to form a reliable heterostructure, and other descriptions of the heterostructure can refer to the foregoing description and are not repeated herein.
In addition, the upper end surface of the second molding layer 52a in this example protrudes out of the upper end surface of the metal pillar 30a along the second direction B, in other words, the upper end surface of the metal pillar 30a may be exposed by etching or laser drilling, etc. to connect the external lead 40 a.
Here, the upper end surface of a portion of the metal pillar 30a may still be covered by the second molding layer 52a for protection, so as to avoid the metal pillar 30a from being exposed too much to affect the circuit structure inside the package structure 100 a.
In a third specific example, referring to fig. 3, the package structure 100b includes a chip 10b, a redistribution layer stack 20b, a metal pillar 30b, an external pin 40b, and a molding layer 50 b.
One side of the chip 10b has several electrodes 101 b.
The rewiring stack layer 20b is connected to the chip 10b, and the rewiring stack layer 20b includes a first insulating layer 211b sequentially stacked on the chip 10b and a first rewiring layer 221b penetrating the first insulating layer 211b to communicate with the electrodes 101 b.
The metal pillar 30b communicates with the first redistribution layer 221 b.
The external lead 40b is connected to the first redistribution layer 221b through the metal pillar 30 b.
The molding layer 50b includes a first molding layer 51b and a second molding layer 52 b.
The first molding compound layer 51B covers the peripheral edge region of the chip 10B, the upper end surface of the first molding compound layer 51B is flush with the upper surface of the chip 10B (i.e., the surface of the chip 10B on which the electrode 101B is disposed), and the first insulating layer 211B extends to the upper end surface of the first molding compound layer 51B along the first direction B, but not limited thereto.
Here, the first molding compound 51b does not cover the lower surface of the chip 10b (i.e., the surface of the chip 10b on which the electrode 101b is not disposed), but a protective film 60b is disposed on the lower surface of the chip 10b, and the protective film 60b can be used to improve the heat dissipation effect of the package structure 100b, for example.
The second molding compound 52b covers the redistribution layer stack 20b and the metal pillar 30b, and the second molding compound 52b is connected to the first molding compound 51 b.
Here, the first plastic package layer 51b, the second plastic package layer 52b and the first insulating layer 211b are connected two by two to form a reliable heterostructure, and other descriptions of the heterostructure can refer to the foregoing description and are not repeated herein.
In addition, the upper end surface of the metal pillar 30b in this example is flush with the upper end surface of the second plastic-sealed layer 52b, and an external insulating layer 70b covers the upper end surface of the metal pillar 30b and the upper end surface of the second plastic-sealed layer 52b, and the upper end surface of the metal pillar 30b may be exposed by etching or laser drilling to connect the external pin 40 b.
Here, an external insulating layer 70b is further connected to one side of the second plastic package layer 52b, a heterostructure can be formed between the second plastic package layer 52b and the external insulating layer 70b to further improve the reliability of the package structure 100b, the package structure 100b can be prevented from warping, and the package structure 100b with high strength is realized, and moreover, the upper end surfaces of part of the metal posts 30b can still be covered by the external insulating layer 70b to realize protection, so that the influence of the excessive exposure of the metal posts 30b on the circuit structure inside the package structure 100b can be avoided.
In a fourth specific example, referring to fig. 4, the package structure 100c includes a chip 10c, a redistribution layer stack 20c, a metal pillar 30c, an external pin 40c, and a molding layer 50 c.
One side of the chip 10c has several electrodes 101 c.
The rewiring stack layer 20c is connected to the chip 10c, and the rewiring stack layer 20c includes a first insulating layer 211c, a first rewiring layer 221c penetrating the first insulating layer 211c to communicate with the electrodes 101c, a second insulating layer 212c, and a second rewiring layer 222c penetrating the second insulating layer 212c to communicate with the first rewiring layer 221c, which are sequentially stacked on the chip 10 c.
The metal pillar 30c is connected to the second redistribution layer 222 c.
The external pin 40c is connected to the second redistribution layer 222c through the metal pillar 30 c.
The molding layer 50c includes a first molding layer 51c and a second molding layer 52 c.
The first molding compound layer 51c covers the peripheral region of the chip 10c, the lower surface of the chip 10c (i.e., the surface of the chip 10c on the side where the electrode 101c is not disposed), and a portion of the redistribution layer stack 20c, the second molding compound layer 52c covers the metal pillar 30c and a portion of the redistribution layer stack 20c, and the second molding compound layer 52c is connected to the first molding compound layer 51 c.
Specifically, in the first direction a, a connected overlapping region is provided between the insulating layer 21c and the first plastic package layer 51c and/or a connected overlapping region is provided between the first plastic package layer 51c and the second plastic package layer 52c, that is, the insulating layer 21c, the first plastic package layer 51c and the second plastic package layer 52c have a mutually matched region not only in the second direction B, but also in the first direction a, i.e., a heterostructure is formed in both the first direction a and the second direction B, which greatly enhances the reliability of the heterostructure and improves the protection effect on the chip 10 c.
In this example, it is taken as an example that at least a part of the second insulating layer 212c and the first molding layer 51c have a continuous overlapping area in the first direction a.
Here, a portion of the second insulating layer 212c extends in a direction opposite to the second direction B, the portion of the second insulating layer 212c is connected to the first insulating layer 211c and covers the first rewiring layer 221c, the upper end surface of the first insulating layer 211c is lower than the upper end surface of the first plastic package layer 51c, the periphery of the portion of the second insulating layer 212c is connected to the first plastic package layer 51c, and another portion of the second insulating layer 212c extends along the first direction a on the upper surface of the first plastic package layer 51c, that is, the first plastic package layer 51c in this example protrudes upward from the upper surface of the chip 10c (i.e., the side surface of the chip 10c where the electrode 101c is provided) along the second direction B and is connected to the second insulating layer 212 c.
The second molding compound layer 52c covers the second redistribution layer 222c and a portion of the second insulating layer 212c in addition to the metal pillar 30 c.
In addition, the upper end surface of the metal pillar 30c in this example is flush with the upper end surface of the second molding layer 52c, in other words, the upper end surface of the metal pillar 30c may be exposed by grinding and thinning or the like (the second molding layer 52c and the metal pillar 30c may be ground flat at the same time) to connect the external lead 40 c.
In a fifth specific example, referring to fig. 5, the package structure 100d includes a chip 10d, a redistribution layer stack 20d, a metal pillar 30d, an external pin 40d, and a molding layer 50 d.
One side of the chip 10d has several electrodes 101 d.
The rewiring stack layer 20d is connected to the chip 10d, and the rewiring stack layer 20d includes a first insulating layer 211d, a first rewiring layer 221d penetrating the first insulating layer 211d to communicate with the electrodes 101d, and a second insulating layer 212d, which are sequentially stacked on the chip 10 d.
The metal pillar 30d communicates with the first redistribution layer 221d, and here, a portion of the second insulating layer 212d is removed by etching, laser drilling, or the like to expose the first redistribution layer 221 d.
The external lead 40d is connected to the first redistribution layer 221d through the metal pillar 30 d.
The molding layer 50d includes a first molding layer 51d and a second molding layer 52 d.
The first molding compound layer 51d covers the peripheral region of the chip 10d, the lower surface of the chip 10d (i.e., the surface of the chip 10d on the side where the electrode 101d is not disposed), and the peripheral region of the redistribution layer 20d, the second molding compound layer 52d covers the metal pillar 30d and the upper end surface of the redistribution layer 20d, and the second molding compound layer 52d is connected to the first molding compound layer 51 d.
Specifically, in the first direction a, there is a connected overlapping region between the insulating layer 21d and the first plastic package layer 51d and/or a connected overlapping region between the first plastic package layer 51d and the second plastic package layer 52d, that is, the insulating layer 21d, the first plastic package layer 51d, and the second plastic package layer 52d have a mutually matched region not only in the second direction B, but also in the first direction a, i.e., a heterostructure is formed in both the first direction a and the second direction B, which greatly enhances the reliability of the heterostructure and improves the protection effect on the chip 10 d.
In this example, it is taken as an example that in the first direction a, the second insulating layer 212d and the first molding layer 51d have a connected overlapping region, and the first molding layer 51d and the second molding layer 52d have a connected overlapping region therebetween.
Here, a part of the second insulating layer 212d extends in a direction opposite to the second direction B, the part of the second insulating layer 212d connects the first insulating layer 211d and covers the first rewiring layer 221d, and the periphery of the part of the second insulating layer 212d is connected to the first molding layer 51d, that is, the first molding layer 51d of the present example protrudes upward in the second direction B from the upper surface of the chip 10d (i.e., the side surface of the chip 10d where the electrode 101d is provided) to be connected to the second insulating layer 212d, and the first molding layer 51d also protrudes from the upper end surface of the rewiring stacked layer 20d in the second direction B, that is, the upper end surface of the rewiring stacked layer 20d is lower than the upper end surface of the first molding layer 51 d.
In the first direction a and the second direction B, there are connected overlapping regions between the second molding layer 52d and the first molding layer 51d, in other words, in the actual process, the first molding layer 51d, the redistribution stacked layer 20d and the metal posts 30d may be formed first, and then the second molding layer 52d is formed between the adjacent metal posts 30d, and the second molding layer 52d extends to the upper surface of the first molding layer 51 d.
In addition, the upper end surface of the second molding layer 52d in this example protrudes out of the upper end surface of the metal pillar 30d along the second direction B, in other words, the upper end surface of the metal pillar 30d may be exposed by etching or laser drilling, etc. to connect the external lead 40 d.
Here, the upper end surface of the metal pillar 30d may be higher, lower, or even with the upper end surface of the first molding layer 51 d.
The upper end surface of a portion of the metal pillar 30d can still be covered by the second molding layer 52d for protection, so as to prevent the metal pillar 30d from being exposed too much to affect the circuit structure inside the package structure 100 d.
Here, the outer lead 40d may be formed before the second molding layer 52d is formed, or may be formed after the second molding layer 52d is formed, which may be determined according to the actual situation.
It is understood that the present embodiment provides several specific examples of the package structure 100, and those skilled in the art can obtain other examples based on the foregoing specific examples and the conventional technical means in the art, and all of them should fall into the protection scope of the present invention, for example, changing the number of layers of the redistribution layer stack 20, changing the specific matching structure of the insulating layer 21 and the injection molding layer 51, and so on.
An embodiment of the present invention further provides a method for forming a package structure 100, where, taking the package structure 100 of the first specific example as an example for description, with reference to the description of the package structure 100 and fig. 6 to 13, the method for forming the package structure 100 includes the steps of:
Referring to fig. 7, at least one chip 10 is provided, the chip 10 having a plurality of electrodes 101;
with reference to fig. 8 and 9, a redistribution layer stack 20 connected to the chip 10 is formed, where the redistribution layer stack 20 includes at least one insulating layer 21 and at least one redistribution layer 22, and the redistribution layer 22 is connected to the plurality of electrodes 101;
specifically, with reference to fig. 8, a first plastic package layer 51 is formed to cover the chip 10, the first plastic package layer 51 covers the peripheral region of the chip 10 and the lower surface of the chip 10 (i.e., the surface of the chip 10 on the side where the electrode 101 is not disposed), with reference to fig. 9, a first insulating layer 211 is formed above the first plastic package layer 51 and the chip 10, a portion of the first insulating layer 211 is removed by etching or laser drilling to expose the electrode 101, a first redistribution layer 221 is formed above the first insulating layer 211, and the first redistribution layer 221 is connected to the electrodes 101.
With reference to fig. 10, a metal pillar 30 is formed on the first redistribution layer 221;
with reference to fig. 11 to 13, an external lead 40 is formed on the metal pillar 30.
Specifically, with reference to fig. 11, a second molding layer 52 is formed to cover the redistribution layer stack 20 and the metal posts 30, and with reference to fig. 12, the upper end surfaces of the metal posts 30 are exposed (the second molding layer 52 and the metal posts 30 can be simultaneously polished) by a lapping thinning method or the like, and with reference to fig. 13, the external leads 40 are formed on the upper end surfaces of the metal posts 30.
The redistribution layer 22 and the external pins 40 of the forming method of the embodiment are connected through the metal posts 30, on one hand, the reliability of signal transmission and the ductility of a circuit can be improved, and further, the electrical performance, the reliability and the heat dissipation performance of the package structure 100 are greatly improved, on the other hand, the metal posts 30 can be used for determining the arrangement positions of the external pins 40, so that the forming of the external pins 40 is facilitated, the process can be simplified, and on the other hand, the appearance characteristics of the metal posts 30 are obvious, and can be used for identification reference in the subsequent analysis and detection stage.
In addition, for the molding method of the package structure 100 of other examples of the present invention, reference may also be made to the molding method of the package structure 100 of the first specific example, which is not described herein again.
In summary, the present invention can implement redistribution of the I/O terminals of the chip 10 by using the redistribution process, and then combine the external pins 40 to combine the package structure 100 with external components (such as a circuit board, etc.) to implement signal transmission of the chip 10, where the redistribution layer 22 and the external pins 40 are connected by the metal posts 30, on one hand, reliability of signal transmission and ductility of the circuit can be improved, so as to greatly improve electrical performance, reliability and heat dissipation performance of the package structure 100, on the other hand, the metal posts 30 can be used to determine the arrangement positions of the external pins 40, so as to facilitate molding of the external pins 40, simplify the process, and on the other hand, the metal posts 30 have obvious appearance characteristics, and can be used for identification reference in the subsequent analysis and detection stage.
In addition, the plastic package layer 50 and the insulating layer 21 of the present invention are made of different insulating materials, so that the insulating part of the whole package structure 100 is a heterostructure, which can improve the board-level thermal cycle reliability of the whole package structure 100, and the benefit of such arrangement is that: (1) the insulating layer 21 (especially, the bottommost insulating layer 21) is an organic insulating layer 21 with high strength and high elongation, and the combination of the organic insulating layer 21 and the plastic package layer 50 can provide effective protection for the chip 10, thereby improving the environmental adaptability, thermal and electrical reliability, and the like of the package structure 100; (2) the CTE difference between the insulating layer 21 and the molding layer 50 forms a graded CTE structure that reduces stress caused by CTE mismatch between the insulating layer 21 and the molding layer 50 during temperature cycling (e.g., during reliability testing), which can improve board level thermal cycling reliability of the overall package structure 100; (3) the insulating layer 21 and the plastic packaging layer 50 are thicker, so that the board-level thermal cycle reliability of the whole packaging structure 100 can be further improved; (4) the insulating layer 21 is made of a semitransparent material, so that subsequent detection, failure analysis and other processes are facilitated, and the efficiency of the detection, failure analysis and other processes can be greatly improved by matching with the metal column 30.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention, and they are not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the scope of the present invention.
Claims (8)
1. A package structure, comprising:
at least one chip, the chip is provided with a plurality of electrodes;
the rewiring stacking layer is connected with the chip and comprises at least one insulating layer and at least one rewiring layer, the rewiring layer is communicated with the electrodes, and the insulating layer is made of a semitransparent material;
the metal column is communicated with the heavy wiring layer;
an external pin which is communicated with the redistribution layer through the metal column,
The packaging structure further comprises a plastic packaging layer, the plastic packaging layer coats the chip, the rewiring stacking layer and the metal column, at least part of external pins protrudes out of the plastic packaging layer, the plastic packaging layer comprises a first plastic packaging layer and a second plastic packaging layer which are connected, the first plastic packaging layer at least coats the chip, the second plastic packaging layer at least coats the metal column, in a first direction, a connected overlapping area is arranged between the insulating layer and the first plastic packaging layer, the first plastic packaging layer and the second plastic packaging layer have a connected overlapping area, and the first direction is the extension direction of the rewiring layer.
2. The package structure of claim 1, wherein the redistribution layer is a copper layer, the metal pillar is a copper pillar, and the external pin is a ball.
3. The package structure of claim 1, wherein the insulating layer and the molding layer have different parameters, and the parameters comprise at least one of a thermal expansion coefficient, an elongation, a transparency, and a thickness.
4. The package structure of claim 3, wherein the thickness of the insulating layer ranges from 5 um to 20um, the thermal expansion coefficient of the insulating layer ranges from 30 ppm to 70ppm/K, the thickness of the plastic package layer ranges from 15 um to 100um, the thermal expansion coefficient of the plastic package layer ranges from 7 ppm to 20ppm/K, the elongation of the insulating layer is higher than that of the plastic package layer, and the transparency of the insulating layer is higher than that of the plastic package layer.
5. The package structure of claim 1, wherein the redistribution layer stack comprises a first insulating layer, a first redistribution layer and a second insulating layer sequentially stacked on the chip, the first redistribution layer penetrating the first insulating layer to connect the plurality of electrodes, and at least a portion of the second insulating layer has a connected overlap region with the first molding compound layer in the first direction.
6. The package structure of claim 5, wherein the redistribution layer stack further comprises a second redistribution layer penetrating the second insulating layer to communicate with the first redistribution layer, the second molding compound covers the second redistribution layer and a portion of the second insulating layer, and a portion of the second insulating layer extends on a surface of the first molding compound in the first direction.
7. The package structure according to claim 5, wherein the first molding compound protrudes out of the redistribution layer stack along a second direction, and the second molding compound and the first molding compound have a connected overlapping region therebetween in both the first direction and the second direction, and the second direction is a direction of the chip toward the redistribution layer stack.
8. A molding method of a packaging structure is characterized by comprising the following steps:
Providing at least one chip, wherein the chip is provided with a plurality of electrodes;
forming a rewiring stacking layer connected with the chip, wherein the rewiring stacking layer comprises at least one insulating layer and at least one rewiring layer, the rewiring layer is communicated with a plurality of electrodes, and the insulating layer is made of a semitransparent material;
forming a metal column on the redistribution layer;
forming an external pin on the metal column;
wherein, fashioned packaging structure still includes the plastic envelope layer, the plastic envelope layer cladding the chip the rewiring stacks the layer and the metal post, outside pin is at least partly protruding to stretch out the plastic envelope layer, the plastic envelope layer is including continuous first plastic envelope layer and second plastic envelope layer, first plastic envelope layer cladding at least the chip, the second plastic envelope layer cladding at least the metal post in the first direction, the insulating layer with continuous overlap region has between the first plastic envelope layer, just first plastic envelope layer with continuous overlap region has between the second plastic envelope layer, first direction is the extension direction of rewiring layer.
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| CN1835196A (en) * | 2005-03-16 | 2006-09-20 | 雅马哈株式会社 | Method for manufacturing semiconductor device and semiconductor device |
| JP2007123941A (en) * | 2007-02-09 | 2007-05-17 | Casio Comput Co Ltd | Method of manufacturing semiconductor device |
| US20150228632A1 (en) * | 2014-02-13 | 2015-08-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged Semiconductor Devices and Methods of Packaging Semiconductor Devices |
| US20170084591A1 (en) * | 2015-09-21 | 2017-03-23 | Freescale Semiconductor, Inc. | Localized redistribution layer structure for embedded component package and method |
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| CN1835196A (en) * | 2005-03-16 | 2006-09-20 | 雅马哈株式会社 | Method for manufacturing semiconductor device and semiconductor device |
| JP2007123941A (en) * | 2007-02-09 | 2007-05-17 | Casio Comput Co Ltd | Method of manufacturing semiconductor device |
| US20150228632A1 (en) * | 2014-02-13 | 2015-08-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged Semiconductor Devices and Methods of Packaging Semiconductor Devices |
| US20170084591A1 (en) * | 2015-09-21 | 2017-03-23 | Freescale Semiconductor, Inc. | Localized redistribution layer structure for embedded component package and method |
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