CN116936488A - Chip packaging structure and packaging method - Google Patents
Chip packaging structure and packaging method Download PDFInfo
- Publication number
- CN116936488A CN116936488A CN202210373729.8A CN202210373729A CN116936488A CN 116936488 A CN116936488 A CN 116936488A CN 202210373729 A CN202210373729 A CN 202210373729A CN 116936488 A CN116936488 A CN 116936488A
- Authority
- CN
- China
- Prior art keywords
- chip
- layer
- rewiring layer
- rewiring
- welding spot
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 97
- 238000000034 method Methods 0.000 title claims abstract description 67
- 239000004033 plastic Substances 0.000 claims abstract description 87
- 238000003466 welding Methods 0.000 claims abstract description 83
- 238000007789 sealing Methods 0.000 claims abstract description 42
- 239000010410 layer Substances 0.000 claims description 605
- 229910000679 solder Inorganic materials 0.000 claims description 157
- 238000000465 moulding Methods 0.000 claims description 66
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 13
- 239000012778 molding material Substances 0.000 claims description 12
- 238000001746 injection moulding Methods 0.000 claims description 11
- 239000011241 protective layer Substances 0.000 claims description 8
- 238000005266 casting Methods 0.000 claims description 4
- 238000004381 surface treatment Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 229910052751 metal Inorganic materials 0.000 description 45
- 239000002184 metal Substances 0.000 description 45
- 230000008569 process Effects 0.000 description 37
- 239000000463 material Substances 0.000 description 33
- 239000010949 copper Substances 0.000 description 31
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 23
- 229910052802 copper Inorganic materials 0.000 description 23
- 230000035882 stress Effects 0.000 description 19
- 238000005476 soldering Methods 0.000 description 16
- 238000004377 microelectronic Methods 0.000 description 12
- 238000000227 grinding Methods 0.000 description 11
- 238000005520 cutting process Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 10
- 238000003698 laser cutting Methods 0.000 description 10
- 239000002344 surface layer Substances 0.000 description 10
- 230000010354 integration Effects 0.000 description 9
- 238000012858 packaging process Methods 0.000 description 9
- 230000017525 heat dissipation Effects 0.000 description 8
- 229910003460 diamond Inorganic materials 0.000 description 7
- 239000010432 diamond Substances 0.000 description 7
- 229920006336 epoxy molding compound Polymers 0.000 description 7
- 239000004642 Polyimide Substances 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 6
- 238000001465 metallisation Methods 0.000 description 6
- 229920003217 poly(methylsilsesquioxane) Polymers 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000011282 treatment Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000003755 preservative agent Substances 0.000 description 5
- 230000002335 preservative effect Effects 0.000 description 5
- 230000008707 rearrangement Effects 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 238000009736 wetting Methods 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical group [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 230000006355 external stress Effects 0.000 description 3
- 230000002349 favourable effect Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000005549 size reduction Methods 0.000 description 3
- 102100025947 Insulin-like growth factor II Human genes 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910001096 P alloy Inorganic materials 0.000 description 2
- 101800001717 Preptin Proteins 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- OFNHPGDEEMZPFG-UHFFFAOYSA-N phosphanylidynenickel Chemical compound [P].[Ni] OFNHPGDEEMZPFG-UHFFFAOYSA-N 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 239000002313 adhesive film Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The application relates to the technical field of semiconductors, in particular to a chip packaging structure and a packaging method. The chip packaging structure comprises: the chip is provided with an upper surface and a lower surface which are opposite, wherein the upper surface is provided with at least one first welding spot; a plastic layer covering the upper surface, the lower surface and the side surfaces of the chip; wherein, the upper end of the first welding spot is exposed on the upper surface of the plastic sealing layer; the upper end of the first welding spot is one end of the first welding spot far away from the chip; a rewiring layer located on and in contact with the first pad, wherein the contact is such that the first pad and the rewiring layer form an electrical connection; and at least one second pad on and electrically connected to the rewiring layer. The chip packaging structure can effectively protect the chip in the chip packaging structure, and improves the reliability, performance and service life of the chip.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a chip packaging structure and a packaging method.
Background
Integrated circuit packages seek higher density, more reliable circuits. Currently, a commonly used chip packaging process is wafer level chip scale packaging (wafer level chip scale packaging, WLCSP). Unlike conventional chip packaging processes, WLCSP processes can perform overall packaging and testing on a whole wafer containing multiple chips, and then dicing into individual chip particles, which can make the packaged chip size equivalent to the pre-package size.
As shown in fig. 1, the chip packaging structure packaged by WLCSP has a thinner protective layer only on the back surface, and has low overall strength, which is prone to breakage due to surface collision during transportation and application. In addition, the chip packaged by the WLCSP process has poor temperature impact resistance, temperature cycle resistance and the like, so that the chip is easy to fail. One of the failures is represented by: stress is transferred from the solder balls (solder) to the front side of the chip, causing the chip to fail.
Disclosure of Invention
The chip packaging structure provided by the embodiment of the application can effectively protect the chip in the chip packaging structure, and improves the reliability and service life of the chip.
In a first aspect, a chip package structure is provided, including: the chip is provided with an upper surface and a lower surface which are opposite, wherein the upper surface is provided with at least one first welding spot; a plastic layer covering the upper surface, the lower surface and the side surfaces of the chip; wherein, the upper end of the first welding spot is exposed on the upper surface of the plastic sealing layer; the upper end of the first welding spot is one end of the first welding spot far away from the chip; a rewiring layer located on and in contact with the first pad, wherein the contact is such that the first pad and the rewiring layer form an electrical connection; and at least one second pad on and electrically connected to the rewiring layer.
In the chip packaging structure, the upper surface, the lower surface and the side surfaces of the chip are covered with the plastic sealing layer, so that the upper surface, the lower surface and the side surfaces of the chip are effectively protected, and particularly, the plastic sealing layer part of the upper surface of the chip can effectively buffer or reduce the stress from above the chip, and microelectronic components integrated on the upper surface of the chip can be effectively protected. In addition, the upper surface, the lower surface and the side surfaces of the chip are effectively protected, so that the placement orientation of the chip packaging structure is not limited, namely, the chip packaging structure is placed according to a certain orientation without being scratched to reduce the damage of stress from a certain aspect to the chip.
In addition, the chip packaging structure achieves the effect, and meanwhile, the chip and the rewiring layer are not required to be electrically connected through soldering, so that unstable electrical connection between the chip and the rewiring layer caused by the problems of non-wetting soldering and the like can be avoided. Therefore, the chip packaging structure provided by the embodiment of the application can improve the chip packaging yield, the reliability, the performance and the service life of the chip.
In one possible embodiment, the projected area of the rewiring layer in the vertical direction is larger than the area of the upper surface of the chip, and the vertical direction is perpendicular to the upper surface of the chip.
In the embodiment, the rewiring layer is fanned out from the chip, the area is larger, more welding spots and other devices can be integrated on the rewiring layer, so that the chip can be electrically connected with more other devices, and the integration level of the chip is improved.
In one possible embodiment, the first solder joint is a pillar structure.
In this embodiment, the heat dissipation performance of the columnar structure is better, and the height of the columnar structure can be flexibly adjusted, for example, the purpose of reducing the chip size can be achieved by reducing the height of the columnar structure. Therefore, the first welding spot adopts a columnar structure, which is favorable for heat dissipation of the chip and size reduction.
In a second aspect, a method for packaging a chip is provided, which can be used to prepare the chip packaging structure provided in the first aspect. The method comprises the following steps: (1) Obtaining a wafer, wherein the wafer comprises a chip, and the chip is provided with an upper surface and a lower surface which are opposite; (2) Preparing at least one first welding spot on the upper surface of the chip; (3) Covering the upper surface, the lower surface and the side surfaces of the chip with a plastic sealing layer, and exposing the upper end of the first welding spot on the upper surface of the plastic sealing layer; the upper end of the first welding spot is one end of the first welding spot far away from the chip; (4) Preparing a rewiring layer in contact with the first solder joint, wherein the contact is such that the first solder joint and the rewiring layer form an electrical connection; (5) At least one second solder joint is prepared on the rewiring layer in electrical connection with the rewiring layer.
The method can efficiently prepare the chip packaging structure provided in the first aspect, is simple and convenient to operate, and is easy to implement industrially.
In one possible embodiment, covering the upper surface, the lower surface, and the side surfaces of the chip with the plastic layer includes: placing the chip on a carrier plate, wherein the upper end of the first welding spot is contacted with the carrier plate; pouring an injection molding material on the chip to form a plastic layer covering the upper surface, the lower surface and the side surfaces of the chip; and removing the carrier plate to expose the upper end of the first welding spot.
According to the scheme of the embodiment, the plastic sealing layers can be efficiently covered on the surfaces of the chips, and six-face protection of the chips is realized.
In one possible embodiment, preparing a rewiring layer in contact with the upper end of the first pad comprises: preparing a dielectric layer on the upper surface of the plastic layer and the upper end of the first welding spot; etching the dielectric layer to expose the upper end of the first welding spot; a rewiring layer is deposited.
In the embodiment, the rewiring layer can be prepared on the first welding spot in a deposition mode, so that the first welding spot and the rewiring layer are integrally connected, the first welding spot and the rewiring layer are not required to be connected through soldering, and the unstable electric connection between the chip and the rewiring layer caused by the problems of non-wetting soldering and the like can be avoided.
In a third aspect, a chip package structure is provided, including: a chip having opposite upper and lower surfaces; a rewiring layer located on the chip and electrically connected to the chip; a first plastic layer covering an upper surface of the rewiring layer and a side surface of the chip, wherein the upper surface of the rewiring layer is a surface, far away from the chip, of an outer surface of the rewiring layer; at least one solder joint located on the rewiring layer and electrically connected with the rewiring layer; the upper end of the welding spot is exposed on the upper surface of the first plastic sealing layer, and the upper end of the welding spot is the end of the welding spot far away from the chip; and a back protective layer covering the lower surface of the chip.
In the chip packaging structure, the upper surface of the chip is covered with the rewiring layer, the upper surface of the rewiring layer is covered with the plastic layer, and the side surface of the chip is directly covered with the plastic layer, so that the upper surface and the side surface of the chip are effectively protected. The plastic sealing layer part on the rewiring layer can effectively buffer or reduce stress from the upper part of the chip, can effectively protect microelectronic components integrated on the upper surface of the chip, and improves the reliability, performance and service life of the chip. In addition, the upper surface and the side surfaces of the chip are effectively protected, so that the placement orientation of the chip packaging structure is less limited, namely, the chip packaging structure is placed according to a certain orientation without deliberately reducing the damage of stress from the upper surface and the side surfaces of the chip to the chip.
In addition, while achieving the above effects, in the chip packaging structure, the rewiring layer is directly contacted with the chip, and welding spots are not needed between the rewiring layer and the chip, that is, the chip packaging structure only needs one layer of welding spots (namely at least one welding spot) and does not need to prepare a plurality of layers of welding spots, so that the height of the chip packaging structure can be reduced, and the size of the chip packaging structure is reduced.
That is, the chip packaging structure provided by the embodiment of the application can improve the reliability, performance and service life of the chip and reduce the size of the chip packaging structure.
In one possible embodiment, the solder joint is a cylindrical structure.
In this embodiment, the heat dissipation performance of the columnar structure is better, and the height and cross-sectional size of the columnar structure can be flexibly adjusted. For example, the object of reducing the chip size can be achieved by reducing the height of the pillar structures. For another example, the area of the cross section of the columnar structure can be reduced, so that the columnar structure is thinner, more welding spots can be integrated on the rewiring layer, and the integration level of the chip is improved. Therefore, the welding spot adopts a cylindrical structure, which is favorable for heat dissipation, size reduction and integration level improvement of the chip.
In one possible embodiment, the upper ends of the solder joints are surface treated or covered with pre-set tin. Exemplary surface treatments include nickel gold (electroless nickel/immersion gold, ENIG) or the provision of an organic solderability preservative (organicsolderability preservative, OSP).
The upper ends of the welding spots are subjected to surface treatment or are covered with preset tin, so that the upper ends of the welding spots can be effectively protected against corrosion, oxidation and the like, and the subsequent welding of the chip packaging structure to other devices (such as a printed circuit board) through the welding spots is facilitated.
In one possible embodiment, the back protective layer is a second plastic layer or a thermally conductive layer.
If the back protection layer is a second plastic sealing layer, effective protection can be formed on the back of the chip, and the reliability of the chip is improved. If the back protection layer is a heat conduction layer, the heat dissipation capability of the chip can be improved.
In a fourth aspect, there is provided a chip packaging method, which can be used to prepare the chip packaging structure of the third aspect, the method comprising: (1) obtaining a wafer, wherein the wafer comprises chips; the chip has opposite upper and lower surfaces; (2) Preparing a rewiring layer electrically connected with the chip on the upper surface of the chip; (3) Preparing at least one solder joint on the rewiring layer, the solder joint being electrically connected with the rewiring layer; (4) Covering the upper surface of the rewiring layer and the side surface of the chip with a first plastic sealing layer; the upper surface of the rewiring layer is the surface, far away from the chip, of the outer surface of the rewiring layer, the upper end of the welding spot is exposed on the upper surface of the first plastic layer, and the upper end of the welding spot is the end, far away from the chip, of the welding spot; (5) preparing a back protective layer covering the lower surface of the chip.
The method can efficiently prepare the chip packaging structure provided by the third aspect, is simple and convenient to operate, and is easy to implement industrially.
In one possible embodiment, the solder joint is a columnar structure, and the method further comprises: and carrying out surface treatment on the upper end of the welding spot, or preparing preset tin on the upper end of the welding spot.
In this method, the upper end of the solder joint may be surface-treated (e.g., nickel-plated gold, provided with an organic solderability resist, etc.), or pre-set tin may be prepared at the upper end of the solder joint, so that the upper end surface, i.e., the upper surface, of the solder joint may be protected and subsequent soldering of the chip package structure to other devices (e.g., a printed circuit board) via the solder joint may be facilitated.
In one possible embodiment, covering the upper surface of the rewiring layer and the chip side with the first molding layer includes: placing the chip on a carrier plate, wherein the lower surface of the chip is contacted with the carrier plate; and pouring an injection molding material on the chip to form a first molding layer covering the upper surface of the new wiring layer and the side surface of the chip.
If the back surface protection layer is a heat conductive layer, in this embodiment, the first plastic sealing layer covering the upper surface of the new wiring layer and the side surface of the chip is formed, and at the same time, the plastic sealing layer is not covered on the lower surface of the chip, so that the back surface protection layer, for example, the heat conductive layer, can be directly prepared on the lower surface of the chip.
In one possible embodiment, covering the upper surface of the rewiring layer and the chip side with the first molding layer includes: placing the chip on a carrier plate, wherein the welding spots are contacted with the carrier plate; and pouring an injection molding material to the chip to form a first injection molding layer covering the upper surface of the rewiring layer and the side surface of the chip.
If the back protective layer is a second molding layer, the second molding layer is also prepared by forming the first molding layer to cover the top surface of the rewiring layer and the chip side in this embodiment.
In a fifth aspect, a chip package structure is provided, including: a chip having opposite upper and lower surfaces; a first rewiring layer covering the upper surface of the chip; a first plastic layer covering at least the side surface of the chip and the lower surface of the chip; at least one first pad located on an upper surface of the first rewiring layer and electrically connected to the first rewiring layer; wherein the upper surface of the first rewiring layer is a surface of the outer surface of the first rewiring layer, which is far away from the chip; a second rewiring layer located on and electrically connected to the at least one first pad; at least one second pad located on the second rewiring layer.
In the chip packaging structure, at least two rewiring layers are arranged on the upper surface of the chip, and can effectively buffer and release external stress, so that microelectronic components integrated on the upper surface of the chip can be effectively protected. The lower surface and the side surfaces of the chip are covered with the plastic sealing layer, so that the lower surface and the side surfaces of the chip are effectively protected. In addition, the upper surface, the lower surface and the side surfaces of the chip are effectively protected, so that the placement orientation of the chip packaging structure can be unlimited, namely, the chip packaging structure is placed according to a certain orientation without being damaged by stress from a certain aspect.
In one possible embodiment, the projected area of the second rewiring layer in the vertical direction is larger than the area of the chip upper surface, and the vertical direction is perpendicular to the chip upper surface.
In the embodiment, at least one rewiring layer fans out from the chip, the area is larger, more welding spots and other devices can be integrated on the rewiring layer, so that the chip can be electrically connected with more other devices, and the integration level of the chip is improved.
In one possible embodiment, the first molding layer also covers an upper surface of the first rewiring layer.
Further, the plastic sealing layer is also arranged above the first rewiring layer, so that the stress from the upper part of the chip can be further buffered and released. Thus, the microelectronic components integrated on the upper surface of the chip can be more effectively protected.
In one possible embodiment, the first solder joint is a pillar structure.
In this embodiment, the heat dissipation performance of the columnar structure is better, and the height of the columnar structure can be flexibly adjusted, for example, the purpose of reducing the chip size can be achieved by reducing the height of the columnar structure. Therefore, the first welding spot adopts a columnar structure, which is favorable for heat dissipation of the chip and size reduction.
In a sixth aspect, a chip packaging method is provided, which can be used to prepare the chip packaging structure provided in the fifth aspect, and the method includes: (1) obtaining a wafer, wherein the wafer comprises chips; the chip has opposite upper and lower surfaces; (2) Preparing a first rewiring layer electrically connected with the chip on the upper surface of the chip; (3) Preparing at least one first solder joint electrically connected with the first rewiring layer on the first rewiring layer; (4) Placing the chip on a carrier plate, wherein the first welding spot is contacted with the carrier plate; (5) Casting an injection molding material to the chip to form a first molding layer covering at least the side surface of the chip and the lower surface of the chip; (6) Removing the carrier plate to expose the upper end of the first welding spot, wherein the upper end of the first welding spot is the end of the first welding spot far away from the chip; (7) A second re-wiring layer is prepared over the first solder joint, and at least one second solder joint is prepared on the second re-wiring layer.
The method can efficiently prepare the chip packaging structure provided in the fifth aspect, is simple and convenient to operate, and is easy to implement industrially.
In one possible embodiment, preparing the second rewiring layer over the first pad comprises: after the height of the first solder joint in the vertical direction is reduced, a second rewiring layer is prepared above the first solder joint, and the vertical direction is perpendicular to the upper surface of the chip.
In this embodiment, the second rewiring layer may be prepared above the first pad after the height of the first pad is reduced, so that the size of the chip package structure may be reduced.
The chip packaging structure provided by the embodiment of the application can form effective protection on the upper surface, the lower surface and the side surface of the chip to cover the plastic sealing layer, so that the upper surface, the lower surface and the side surface of the chip are effectively protected, the reliability of the chip is improved, and the service life of the chip is prolonged. In addition, the upper surface, the lower surface and the side surfaces of the chip are effectively protected, the placement direction of the chip packaging structure can be unrestricted, namely, the chip packaging structure is placed according to a certain direction without being damaged by stress from a certain aspect, and the combination flexibility of the chip packaging structure and other devices is improved.
Drawings
FIG. 1 is a schematic diagram of a chip package structure packaged by a WLCSP process;
FIG. 2A is a schematic diagram of an embedded wafer level ball grid array package;
FIG. 2B is a schematic diagram of a chip package after fan-out;
FIG. 2C is a schematic diagram of a chip package structure packaged by a packaging process;
fig. 3 is a schematic diagram of a chip package structure according to an embodiment of the present application;
fig. 4A, 4B, 4C, 4D, 4E, 4F, 4G, and 4H are flowcharts of a packaging process of the chip package structure shown in fig. 3;
FIG. 5 is a schematic diagram showing the arrangement and distribution of chips on a carrier;
fig. 6 is a schematic diagram of a chip package structure according to an embodiment of the present application;
fig. 7A, 7B, 7C, 7D, 7E, 7F, 7G, 7H, 7I, and 7J are flowcharts of the packaging process of the chip package structure shown in fig. 6;
fig. 8 is a schematic diagram of a chip package structure according to an embodiment of the present application;
fig. 9A, 9B, 9C, 9D, 9E, 9F, 9G, and 9H are flowcharts of a packaging process of the chip package structure shown in fig. 8;
fig. 10 is a schematic diagram of a chip package structure according to an embodiment of the present application;
fig. 11A, 11B, 11C, 11D, 11E, 11F, 11G, 11H, and 11I are flowcharts of the packaging process of the chip package structure shown in fig. 10;
Fig. 12 is a schematic diagram of a chip package structure according to an embodiment of the present application;
fig. 13A, 13B, 13C, 13D, 13E, 13F, 13G, and 13H are flowcharts of the packaging process of the chip package structure shown in fig. 12.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the application.
In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.
It is understood that in the description of embodiments of the application, words such as "exemplary," "such as" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary," "such as" or "for example" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "such as" or "for example," etc., is intended to present related concepts in a concrete fashion.
In the description of the embodiments of the present application, the term "and/or" is merely an association relationship describing an association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a alone, B alone, and both A and B. In addition, unless otherwise indicated, the term "plurality" means two or more. For example, a plurality of systems means two or more systems, and a plurality of terminals means two or more terminals.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating an indicated technical feature. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
Although WLCSP processes can effectively reduce the package volume of chips, they are less reliable. To improve the reliability of the chip and reduce the packaging volume of the chip. The industry proposes the following packaging scheme.
One packaging scheme is the embedded wafer level ball array (embedded wafer level ball grid array, eWLB) package shown in fig. 2A. In this solution, only the lower and side surfaces of the chip are covered with a plastic layer, while the upper surface is not protected by the plastic layer. Therefore, the upper surface of the chip packaged by the scheme has poor strength and low reliability.
One packaging scheme is fan-out chip-last package (FOCLP) shown in fig. 2B. Although in this solution the lower, upper and sides of the chip are covered with a plastic layer for protection, the chip and the rewiring layer (redistribution layer, RDL) are electrically connected by soldering. Soldering often causes problems such as non-wetting, resulting in unstable electrical connection between the chip and the rewiring layer, and eventually resulting in reduced chip packaging yields, reduced chip performance and lifetime.
One packaging scheme is shown in fig. 2C. In this scheme, the lower surface of the chip is covered with a (BSL), and the BSL is relatively thin and has poor stress absorbing performance, and may be broken when an external impact is received, resulting in poor chip reliability.
The embodiment of the application provides a chip packaging structure, which can cover plastic layers on the upper surface, the lower surface and the side surfaces of a chip, so that all the surfaces of the chip are protected by the plastic layers, and simultaneously, the chip and a rewiring layer are well contacted, thereby improving the anti-impact performance and the electrical connection reliability of the chip and improving the reliability of the chip.
In the embodiment of the application, the upper surface and the lower surface of the chip are opposite. The upper surface of the chip can also be called as a front surface and an active surface, and microelectronic components such as a transistor, a resistor, a capacitor and the like are integrated on the upper surface of the chip. The lower surface of the chip may also be referred to as the backside. The side surface of the chip means a surface other than the upper surface and the lower surface of the outer surface of the chip.
In some embodiments, the chip may be a silicon (Si) substrate chip, that is, a chip prepared by integrating a transistor, a resistor, a capacitor, and other microelectronic devices on a silicon substrate. In some embodiments, the chip may be a sapphire (sapphire) substrate chip in particular. In some embodiments, the chip may be a silicon carbide (SiC) substrate chip in particular. In some embodiments, the chip may be specifically a diamond (diamond) substrate chip.
In the embodiment of the application, the chip packaging structure refers to a structure obtained by packaging a chip.
Next, a description is given of a chip package structure provided by an embodiment of the present application with reference to the accompanying drawings.
Referring to fig. 3, an embodiment of the present application provides a chip package structure 300, which includes a chip 310 and a plastic layer 320 covering the upper surface, the lower surface and the sides of the chip 310. Wherein the upper and lower surfaces of the chip 310 are opposite, and the side surfaces are surfaces other than the upper and lower surfaces among the outer surfaces of the chip 310. In the embodiment of the present application, the covering B by a is understood to be that a is attached to the surface of B, or that a is blocked between B and the outside, and the external influence, such as stress, passes through a before reaching B.
In some embodiments, the material of the plastic layer may be an epoxy molding compound (epoxy molding compound, EMC).
The upper surface of the chip 310 has at least one pad 311. Illustratively, the pads 311 may be used as electrodes of the chip 310. The pads 311 may be metal pads, such as aluminum pads, or the like. The microelectronic components integrated on chip 310 may be electrically connected to pads 311 so as to make electrical connection with electronic devices external to chip 310 via pads 311.
In the embodiment of the present application, the electrical connection means that two sides are connected by a conductor or are in contact with each other, and under the condition of corresponding voltage difference, current flowing from one side to the other side can be generated.
In this embodiment of the present application, "contact" refers to physical contact, which is understood to mean "top-up", and generally refers to two objects that are close together in a block or sheet shape, or one of the two objects is located on the surface of the other object. In addition, in embodiments of the present application, "connected" may refer to the direct contact of two objects. "connected" may also mean that two objects are connected by a third object, i.e., one side or end of the third object contacts one of the two objects and the other side or end of the third object contacts the other of the two objects.
With continued reference to fig. 3, the upper surface of the chip 310 is provided with at least one bond pad 330. I.e., chip package structure 300 includes at least one bond pad 330 in contact with the upper surface of chip 310. By way of example, the solder pads 330 may be disposed on the pads 311, i.e., the solder pads 330 are in contact with the pads 311, wherein one solder pad 330 is disposed on one of the pads 311.
In some embodiments, the solder joint 330 may be a columnar structure. By way of example, the cross-section of the columnar structure may be of any shape, such as circular, oval, sector, triangle, regular quadrilateral, diamond, pentagon, hexagon, etc. The cross section of the columnar structure refers to a plane which is generated by cutting a truncated cone by using a plane parallel to the bottom surface of the columnar structure. Wherein the pillar bottom surface refers to the interface of the pillar (i.e., bond pad 330) with the upper surface of die 310.
In one example of these embodiments, as shown in FIG. 3, the solder joint 330 may be of a cylindrical configuration in particular. In another example of these embodiments, the solder joint 330 may be specifically a prismatic structure. I.e. the cross-section of the columnar structure is polygonal, e.g. triangular, quadrangular, pentagonal, hexagonal, etc. And are not listed here.
In some embodiments, the solder joint 330 may be specifically a copper pillar (Cu post).
As shown in fig. 3, the upper ends of the solder joints 330 are exposed at the upper surface of the plastic layer 320. Wherein the upper end of bond pad 330 is the end of bond pad 330 remote from die 310. Specifically, one of the two ends of the solder joint 300 is in contact with the upper surface of the chip 310, and the other end is exposed at the upper surface of the plastic sealing layer 320. The upper surface of the molding layer 320 refers to the surface above the chip 310 among the outer surfaces of the molding layer 320.
With continued reference to fig. 3, the chip package structure 300 may further include a rewiring layer (redistribution layer, RDL) 350 on the bond pads 330 and in contact with the bond pads 330. As described above, the upper ends of the pads 330 are exposed at the upper surface of the molding layer 320, and the rewiring layer 350 is in contact with the upper ends of the pads 330. Wherein contact between bond pad 330 and rewiring layer 350 causes bond pad 330 and rewiring layer 350 to form an electrical connection, thereby causing rewiring layer 350 to form an electrical connection with die 310. The rewiring layer is generally a metal wiring pattern and is used for realizing electric connection of chips and other electronic devices.
In some embodiments, as shown in fig. 3, the area of the upper surface of rewiring layer 350 is greater than the area of the upper surface of chip 310. Specifically, the projected area of the rewiring layer 350 in the vertical direction is larger than the area of the upper surface of the chip 310. That is, the rewiring layer 350 fans out (fan-out) from the chip 310. Wherein the vertical direction refers to a direction perpendicular to the upper surface of the chip 310. The upper surface of the rewiring layer 350 refers to a surface of the outer surface of the rewiring layer 350 that is remote from the chip 310. The area of the upper surface of the rewiring layer 350 is larger than that of the chip 310, so that more welding spots and other devices can be integrated in the rewiring layer 350, the chip can be electrically connected with more other devices, and the integration level of the chip is improved.
In some embodiments, as shown in FIG. 3, a portion of rewiring layer 350 is in contact with bond pad 330, or such portion of rewiring layer 350 is located directly above bond pad 330. In other words, another portion of rewiring layer 350 is not located directly above pad 330. Wherein, a dielectric layer 340 is disposed between the plastic sealing layer 320 and a portion of the rewiring layer 350 not directly above the solder joint 330. Dielectric layer 340 may be understood as an insulating layer made of an insulating material. Illustratively, the dielectric layer 340 may be a Polyimide (PI) layer, i.e., the material of the dielectric layer 340 is polyimide.
Wherein, for solder joint 330, directly above refers to a direction along a vertical direction and away from chip 310. In which, as shown in fig. 3, a direction perpendicular to the upper or lower surface of the chip 310 may be referred to as a vertical direction.
With continued reference to fig. 3, the chip package structure 300 further includes at least one solder joint 360. Wherein solder joint 360 is located on rewiring layer 350 and is electrically connected to rewiring layer 350. The chip package structure 300 may be soldered to a printed circuit board (printed circuit board, PCB) or the like via solder joints 360 to electrically connect the chip 310 to other electronic devices. In some embodiments, the solder joints 360 may be solder balls (holders), such as tin solder balls.
In some embodiments, as shown in fig. 3, an upper surface of the rewiring layer 350 is provided with an under bump metal 370 (UBM). The solder joint 360 is specifically disposed on the under bump metal 370. Solder joints 360 electrically connect rewiring layer 350 through under bump metallization 370. Wherein the upper surface of the rewiring layer 350 refers to a surface of the outer surface of the rewiring layer 350 that is remote from the chip 310.
In some embodiments, there is no under bump metal between bond pads 360 and rewiring layer 350, i.e., bond pads 360 may be disposed directly on rewiring layer 350.
In some embodiments, as shown in fig. 3, the area of the upper surface of the rewiring layer 350 other than the area occupied by the under bump metallization 370 is covered with a dielectric layer 380. Dielectric layer 380 is made of an insulating material. Illustratively, the dielectric layer 380 is polyimide.
In this way, the embodiment of the application provides a chip packaging structure, in which the upper surface, the lower surface and the side surfaces of the chip are covered with the plastic sealing layer, so that the upper surface, the lower surface and the side surfaces of the chip are effectively protected, and particularly, the plastic sealing layer part on the upper surface of the chip can effectively buffer or reduce the stress from above the chip, thereby effectively protecting the microelectronic element integrated on the upper surface of the chip. In addition, the upper surface, the lower surface and the side surfaces of the chip are effectively protected, so that the placement orientation of the chip packaging structure can be unlimited, namely, the chip packaging structure is placed according to a certain orientation without being damaged by stress from a certain aspect. While achieving the foregoing effects, in this structure, there is no need for solder electrical connection between the chip and the rewiring layer, so that unstable electrical connection between the chip and the rewiring layer due to problems such as solder non-wetting can be avoided. Therefore, the chip packaging structure provided by the embodiment of the application can improve the chip packaging yield, the reliability, the performance and the service life of the chip.
The structure of the chip package structure 300 is described above, and next, a method of manufacturing the chip package structure 300, i.e., a packaging method of the chip 310 is described as an example.
A wafer as shown in fig. 4A may be obtained, which may include a plurality of chips including chip 310. The wafer may be 8 inches or 12 inches in size, for example. Wherein the upper surface of the chip 310 has at least one pad 311.
In some embodiments, as shown in fig. 4B, the wafer may be thinned to reduce the thickness of the wafer and meet the packaging requirements. Illustratively, the back side (back) of the wafer may be ground down by a back grinding (back grinding) process. The back surface of the wafer is the back surface or the lower surface of the chip, which is the passive area of the chip, and the thickness of the wafer is reduced by grinding the back surface of the wafer, so that the function of the chip is not affected.
Referring to fig. 4C, solder joints 330 may be prepared on the upper surface of die 310. By way of example, solder joint 330 may be prepared specifically on solder pad 311, i.e., solder joint 330 prepared is in contact with solder joint 330. In some embodiments, the solder joint 330 may be a columnar structure. Bumps (bumping) may be used to prepare bond pads 330 on the top surface of die 310. In one example, the solder joint 330 is a copper pillar. Copper pillars may be fabricated on the upper surface of the chip 310 using a copper pillar bumping (Cu post bumping) process.
In some embodiments, the BSL may also be covered on a lower surface of the wafer, i.e., a lower surface of a plurality of chips included in the wafer. Thus, when the plastic sealing layer material is cast subsequently, the BSL can be encapsulated into the plastic sealing layer. That is, in these embodiments, the portion of the molding layer that covers the lower surface of the chip is directly over the BSL, indirectly over the lower surface of the chip through the BSL. Illustratively, the BSL may be made of glass resin.
Next, referring to fig. 4D, the chip 310 is separated from other portions of the wafer. Specifically, a wafer dicing (die saw) process may be used to separate or dice a plurality of chips included in a wafer to obtain a plurality of individual chips. In some embodiments, a plurality of chips included in the wafer may be cut by laser cutting (laser cutting) or grinding wheel cutting, so as to obtain a plurality of independent single chips.
After separating the chip 310 from the other portions of the wafer, the plastic layer 320 may be covered on the upper surface, the lower surface, and the sides of the chip 310. Specifically, the following is described.
Referring to fig. 4E, a plurality of individual chips including the chip 310 are rearranged on a carrier through a rearrangement (re-layout) process. The result of the re-layout is shown in fig. 5, where the chip-to-chip spacing is maintained to fill the molding material particles and facilitate subsequent dicing. Wherein, the chip is placed on the carrier plate in a mode of chip face down (die face down). The chip is placed on the carrier plate in a manner that the front surface of the chip faces downwards, which means that the front surface or the upper surface of the chip faces towards the carrier plate.
In some embodiments, the carrier may be glass or metal (aluminum, copper, etc.). The surface of the carrier plate is covered with an adhesive film (film) for fixing the chip on the carrier plate. Illustratively, the carrier plate may be shaped to conform to the shape of a wafer. Illustratively, the nature of the carrier plate may conform to the shape of the substrate (panel).
Next, referring to fig. 4F, a molding material (i.e., a material constituting the molding layer, such as an epoxy molding compound) is poured into the chips such as the chips 310 rearranged on the carrier, thereby forming an upper surface, a lower surface, and a side surface covering molding layer 320 covering the chips 310. When the lower surface of the chip 310 is covered with the BSL, the portion of the molding layer covering the lower surface of the chip 310 is directly covered on the BSL, and indirectly covers the lower surface of the chip 310 through the BSL.
After the plastic layer 320 is prepared, a re-wiring layer 350 and the like may be prepared. Specifically, the following is described.
In some embodiments, after carrier removal, dielectric layer 340, rewiring layer 350, under bump metallization 370, dielectric layer 380 may be prepared by a fan out bump (fanout bumping) process. Specifically, after the carrier is removed, the dielectric layer 340 may be prepared on a surface formed by an upper surface of the molding layer 320 and an upper end of the solder joint 330 (it is understood that the upper end of the solder joint 330 is in contact with the carrier when the molding layer material is poured, and thus the upper end of the solder joint 330 is exposed at the upper surface of the molding layer 320), or the like. Next, the dielectric layer 340 is sequentially exposed, developed, and etched to expose the upper ends of the pads 330. A re-wiring layer 350 is deposited on the surface formed by the upper surface pad 330, etc. of the dielectric layer 340. The rewiring layer 350 prepared in this manner contacts the upper end of the bond pad 330, thereby eliminating the need to solder the bond pad and rewiring layer. In addition, the re-wiring layer 350 may be prepared as a fan-out re-wiring layer, i.e., the projected area of the re-wiring layer 350 in the vertical direction is larger than the upper surface area of the chip 310. Dielectric layer 380 may then be prepared on the upper surface of rewiring layer 350 and dielectric layer 380 may be etched to expose a partial area of the upper surface of rewiring layer 350. An under bump metal 370 may then be deposited in the exposed areas in the upper surface of the rewiring layer 350. Thus, a structure as shown in fig. 4G can be prepared.
Note that the upper surface of the molding layer 320 refers to a surface of the outer surface of the portion of the molding layer 320 covering the chip 310, which is away from the chip 310. In other words, the portion of the molding layer 320 covering the chip 310 may be referred to as a portion C1, and the surface of the outer surface of the portion C1 away from the chip 310 is the upper surface of the molding layer 310. That is, the upper surface of the molding layer 320 refers to the surface above the chip 310 among the outer surfaces of the molding layer 320. The upper surface of the dielectric layer refers to the surface of the dielectric layer outer surface that is remote from the chip 310. The upper surface of the rewiring layer refers to the surface of the outer surface of the rewiring layer that is remote from the chip 310.
The specific preparation process of the dielectric layer, the rewiring layer and the under bump metal can be described with reference to the prior art, and will not be described in detail herein.
After the re-wiring layer 350 is prepared, etc., pads 360 electrically connected to the re-wiring layer 350 may be prepared on the re-wiring layer 350. In some embodiments, the solder joints 360 may be solder balls (holders). Referring to fig. 4H, a ball mount (ball mount) process may be used to make solder joints 360 on the under bump metal 370. Wherein the solder joint 360 may be in contact with the under bump metal 370. In addition, the under bump metal 370 contacts the rewiring layer 350. Thereby making electrical connection between rewiring layer 350 and pad 360. And, re-wiring layer 350 is in contact with bond pad 330 such that bond pad 360 is electrically connected to die 310 through under bump metal 370, re-wiring layer 350, and bond pad 330.
In some embodiments, after the above-described packaging process is performed on the chip 310, the chip 310 may be separated from other chips, and a chip packaging structure as shown in fig. 3 may be prepared.
In some embodiments, at least two different chips may be recombined on a carrier, and then integrally encapsulated, to obtain a package structure containing the at least two different chips, so as to realize multi-chip encapsulation.
Referring to fig. 6, an embodiment of the present application provides a chip package structure 600, including a chip 610, and a rewiring layer 640 on the chip 610. Specifically, the upper and lower surfaces of the chip 610 are opposite, and the rewiring layer 640 is located on one side of the upper surface of the chip 610, i.e., the rewiring layer 640 is located above the upper surface of the chip 610. Wherein the rewiring layer 640 is electrically connected to the chip 610.
Wherein a portion of the rewiring layer 640 is in contact with the upper surface of the chip 610 and another portion is spaced from the chip 610. For convenience of description, a portion of the rewiring layer 640 in contact with the upper surface of the chip 610 may be referred to as a portion C2, and a portion having a space from the chip 610 may be referred to as a portion C3. In some embodiments, as shown in fig. 6, the upper surface of the chip 610 has at least one pad 611. The pad 611 may refer to the above description of the pad 311, and will not be described herein. Wherein the portion C2 is in particular in contact with the pad 611. In some embodiments, as shown in fig. 6, the space between chip 610 and portion C3 is filled with a dielectric layer 630. The dielectric layer 630 may refer to the description of the dielectric layer above, and will not be described herein.
As shown in fig. 6, the chip package structure 600 further includes a molding layer 620 covering the upper surface of the rewiring layer 640 and the sides of the chip 610. The material of the plastic layer 620 may be referred to the above description of the material of the plastic layer 320, which is not repeated here. The upper surface of the rewiring layer 640 refers to the surface of the outer surface of the rewiring layer 640 that is remote from the chip 610. The side of the chip 610 refers to a surface other than the upper and lower surfaces of the outer surface of the chip 610. In some embodiments, as shown in fig. 6, there is a dielectric layer 670 between the portion of the molding layer 620 located on the upper surface of the rewiring layer 640 and the upper surface of the rewiring layer 640. In other words, the dielectric layer 670 directly covers the upper surface of the re-wiring layer 640, and the molding layer 620 located on the upper surface of the re-wiring layer 640 partially covers the dielectric layer 670, and further covers the upper surface of the re-wiring layer 640 at intervals.
With continued reference to fig. 6, the chip package structure 600 further includes at least one solder joint 650 on the rewiring layer 640 and electrically connected to the rewiring layer 640. In some embodiments, the solder joint 650 may be a columnar structure. By way of example, the cross-section of the columnar structure may be of any shape, such as circular, oval, sector, triangle, regular quadrilateral, diamond, pentagon, hexagon, etc. The cross section of the columnar structure refers to a plane which is generated by cutting a truncated cone by using a plane parallel to the bottom surface of the columnar structure. Wherein the bottom surface of the columnar structure is parallel to the upper surface of the chip 610. In one example of these embodiments, as shown in FIG. 6, the weld 650 may be specifically a cylindrical structure. In another example of these embodiments, the solder joint 650 may be specifically a prismatic structure. I.e. the cross-section of the columnar structure is polygonal, e.g. triangular, quadrangular, pentagonal, hexagonal, etc. And are not listed here.
In some embodiments, the solder joint 650 may be specifically a copper pillar (Cu post).
The upper ends of the solder joints 650 are exposed at the upper surface of the molding layer 620. Wherein the upper end of bond pad 650 is the end of bond pad 650 remote from die 610.
In some embodiments, the upper end of the weld 650 has a surface layer 680. In one example, the surface layer 680 is pre-set tin. The solder joints 650 have preplaced tin at their upper ends to facilitate subsequent soldering of the chip package structure 600 to other devices (e.g., printed circuit boards) via the solder joints 650. In one example, the surface layer 680 may be a preset treatment of the upper surface of the weld 650. This pre-set process may facilitate subsequent soldering of the chip package structure 600 to other devices (e.g., a printed circuit board) via the solder joints 650, as well as protecting the upper ends of the solder joints 650.
For example, the preset treatment on the upper surface of the welding spot may be nickel-plating (ENIG) treatment, specifically, the surface of the welding spot is replaced with palladium by chemical reaction, then a nickel-phosphorus alloy layer is chemically plated on the basis of palladium core, and then a gold layer is plated on the surface of the nickel-phosphorus alloy layer by the replacement reaction. Nickel-plated gold can be used to prevent oxidation or corrosion of the solder joint and can be used for soldering as well as contact. Illustratively, the pre-treatment of the solder joint upper surface may be the provision of an organic solderability preservative (organic solderability preservative, OSP) on the solder joint upper surface. The organic solderability preservative is an organic coating that can be used to prevent oxidation of the upper surface of the solder joint prior to soldering.
In some embodiments, as shown in FIG. 6, there is an under bump metal 660 between the bond pad 650 and the rewiring layer 640. Wherein the under bump metal 660 may be disposed on the rewiring layer 640 and in contact with the rewiring layer 640. The solder joint 650 may be disposed on the under bump metal 660 and in contact with the under bump metal 660.
With continued reference to fig. 6, the lower surface of the chip 610 is covered with a backside layer 690. The back layer 690 may contact the molding layer 620, or be seamlessly connected, so that the back layer 690 combines with the molding layer 620 to achieve a complete encapsulation of the chip 610. In some embodiments, the material of the back layer 690 is glass resin. In some embodiments, the material of the back layer 690 has high thermal conductivity. For example, the material of the back layer 690 may be metal (copper, aluminum, etc.) or ceramic. In this way, the heat dissipation capability of the chip package structure 600 can be improved.
In this way, the embodiment of the application provides a chip packaging structure, in the structure, the upper surface of the chip is covered with the rewiring layer, the upper surface of the rewiring layer is covered with the plastic layer, and the side surface of the chip is directly covered with the plastic layer, so that the upper surface and the side surface of the chip are effectively protected, in particular, the plastic layer part on the rewiring layer can effectively buffer or reduce the stress from above the chip, the microelectronic element integrated on the upper surface of the chip is effectively protected, and the reliability, performance and service life of the chip are improved. In addition, the upper surface and the side surfaces of the chip are effectively protected, so that the placement orientation of the chip packaging structure is less limited, namely, the chip packaging structure is placed according to a certain orientation without deliberately reducing the damage of stress from the upper surface and the side surfaces of the chip to the chip. In the structure, only one layer of welding spots (namely at least one first welding spot) is needed, and a plurality of layers of welding spots do not need to be prepared, so that the height of the chip packaging structure can be reduced, and the size of the chip packaging structure is reduced. That is, the chip packaging structure provided by the embodiment of the application can improve the reliability, performance and service life of the chip and reduce the size of the chip packaging structure.
The structure of the chip package structure 600 is described above, and next, a method of manufacturing the chip package structure 600, i.e., a packaging method of the chip 610 is described as an example.
A wafer as shown in fig. 7A may be obtained, which may include a plurality of chips including chip 610. The wafer may be 8 inches or 12 inches in size, for example. Wherein the upper surface of the chip 610 has at least one pad 611.
In some embodiments, as shown in fig. 7B, the wafer may be thinned to reduce the thickness of the wafer and meet the packaging requirements. Reference is made specifically to the description of the embodiment shown in fig. 4A and will not be repeated here.
Referring to fig. 7C, a re-wiring layer 640, etc. may be prepared on the upper surface of the chip 610. Specifically, the following is described.
In some embodiments, dielectric layer 630, rewiring layer 640, under bump metallization 660, dielectric layer 670 may be prepared by a fan out bump (fanout bumping) process. Specifically, a dielectric layer 630 may be prepared on the upper surface of the chip 610. Next, the dielectric layer 630 is sequentially exposed, developed, and etched to expose the pads 611. A re-routing layer 640 is then deposited over the exposed pads 611 and the upper surface of dielectric layer 630. The rewiring layer 640 prepared in this way is in contact with the pad 611. Dielectric layer 670 may then be prepared on the upper surface of rerouting layer 640 and dielectric layer 670 may be etched to expose a partial area of the upper surface of rerouting layer 640. Then, an under bump metal 660 may be deposited in the exposed areas in the upper surface of the rewiring layer 640. Thus, a structure as shown in fig. 7C can be prepared.
Note that the upper surface of the dielectric layer refers to a surface of the outer surface of the dielectric layer away from the chip 610. The upper surface of the rewiring layer refers to the surface of the outer surface of the rewiring layer that is remote from the chip 610.
Next, referring to fig. 7D, solder bumps 650 can be prepared on the rewiring layer. By way of example, the solder joint 650 may be produced in particular on the under bump metal 660, i.e. the solder joint 650 produced and the under bump metal 660. In some embodiments, the solder joint 650 may be a columnar structure. A bump (bumping) process may be used to make the solder joint 650 on the under bump metal 660. In one example, the solder joint 650 is a copper pillar. Copper pillars may be fabricated on the under bump metal 660 using a copper pillar bumping (Cu post bumping) process.
Thereafter, referring to fig. 7E, the die 610 is separated from the rest of the wafer. Specifically, a wafer dicing (dieseaw) process may be used to separate or dice a plurality of chips included in a wafer to obtain a plurality of individual chips. In some embodiments, a plurality of chips included in the wafer may be cut by laser cutting (laser cutting) or grinding wheel cutting, so as to obtain a plurality of independent single chips.
After separating the chip 610 from the rest of the wafer, a plastic layer 620 may be applied to the upper surface of the rewiring layer 640 and to the sides of the chip 610. Specifically, the following is described.
Referring to fig. 7F, a plurality of individual chips including the chip 610 are rearranged on a carrier (carrier) through a rearrangement process. Wherein, the chip is placed on the carrier plate in a mode of leading the front of the chip to face upwards (die face up). The chip is placed on the carrier plate in a manner that the front surface of the chip faces upwards, which means that the lower surface or the back surface of the chip faces towards the carrier plate. As shown in fig. 7F, the lower surface of the chip is in contact with the carrier plate. The carrier may be implemented with reference to the description of the embodiment shown in fig. 4E, which is not repeated herein.
Next, referring to fig. 7G, a molding layer material (i.e., a material constituting the molding layer, such as an epoxy molding compound) is poured into the chips such as the chips 610 rearranged on the carrier plate, thereby forming a molding layer 620 covering the upper surface of the rewiring layer 640 and the sides of the chips 610.
Referring to fig. 7H, if the cast molding material covers the solder joint 650, the molding material covering the solder joint 650 may be removed to expose the upper end of the solder joint 650. The plastic layer material covering the solder joints 650 may be removed by grinding (polishing). Specifically, the upper ends of the solder joints 650 may be exposed by grinding with a grinding wheel, so that the subsequent soldering of the chip package structure to other devices via the solder joints 650 may be facilitated.
With continued reference to fig. 7H, the carrier plate may also be removed to expose the lower surface of the chip 610.
Referring to fig. 7I, a surface layer 680 may be prepared on top of the solder joint 650. In one example, prep tin may be prepared on top of the solder joint 650 to provide a surface layer 680. In one example, a pre-set treatment process may be performed on the surface of the upper end of solder joint 650 (i.e., the upper surface) to facilitate subsequent soldering of chip package structure 600 to other devices (e.g., a printed circuit board) via solder joint 650, as well as to facilitate protection of the upper end of solder joint 650. The preset process on the upper surface of the solder joint may refer to the description of the embodiment shown in fig. 6, and will not be repeated here.
Referring to fig. 7J, a back layer 690 may be formed on the lower surface of the chip 610. In some embodiments, the back layer 690 is made of glass resin. In some embodiments, the material of the back layer 690 has high thermal conductivity. For example, the material of the back layer 690 may be metal (copper, aluminum, etc.) or ceramic. The back layer 690 may be formed on the lower surface of the chip 610 by deposition or adhesion, etc.
Thus, the chip package structure 600 may be prepared. In some embodiments, the prepared chip package structure 600 may be separated from other chip package structures prepared simultaneously, resulting in a single chip package structure 600.
In some embodiments, at least two different chips may be recombined on a carrier, and then integrally encapsulated, to obtain a package structure containing the at least two different chips, so as to realize multi-chip encapsulation.
Referring to fig. 8, an embodiment of the present application provides a chip package structure 800, including a chip 810, and a rewiring layer 840 on the chip 810. Specifically, the upper and lower surfaces of the chip 810 are opposite, and the rewiring layer 840 is located on one side of the upper surface of the chip 810. Wherein rewiring layer 840 is electrically connected to chip 820.
Wherein a portion of rewiring layer 840 is in contact with the upper surface of chip 810 and another portion is spaced from chip 810. For convenience of description, a portion of the rewiring layer 840 in contact with the upper surface of the chip 810 may be referred to as a portion C4, and a portion having a space from the chip 610 may be referred to as a portion C5. In some embodiments, the upper surface of the chip 810 has at least one pad 811. The pad 811 may refer to the description of the pad 311 above, and will not be described again. Wherein the portion C4 is in particular in contact with the pad 811. In some embodiments, as shown in fig. 8, the space between chip 810 and portion C5 is filled with a dielectric layer 830. The dielectric layer 830 may refer to the description of the dielectric layer above, and will not be described herein.
As shown in fig. 8, the chip package structure 800 further includes a plastic layer 820 covering the upper surface of the rewiring layer 840, the sides of the chip 810, and the lower surface of the chip 810. The material of the plastic layer 820 may be referred to the above description of the material of the plastic layer 320, and will not be repeated here. The portion of the molding layer 820 that covers the lower surface of the chip 810 may also be referred to as a back side protection layer. The upper surface of the rewiring layer 840 refers to the surface of the outer surface of the rewiring layer 840 that is remote from the chip 610. The side of the chip 810 refers to a surface other than the upper and lower surfaces of the outer surface of the chip 810. In some embodiments, as shown in fig. 8, there is a dielectric layer 870 between the portion of the molding layer 820 located on the upper surface of the rewiring layer 840 and the upper surface of the rewiring layer 840. In other words, the dielectric layer 870 directly covers the upper surface of the re-wiring layer 840, and the molding layer 820 located on the upper surface of the re-wiring layer 840 partially covers the dielectric layer 870, thereby being spaced to cover the upper surface of the re-wiring layer 840.
With continued reference to fig. 8, the chip package structure 800 further includes at least one solder joint 850 located on the rewiring layer 840 and electrically connected to the rewiring layer 840. In some embodiments, the solder joints 850 may be cylindrical structures. By way of example, the cross-section of the columnar structure may be of any shape, such as circular, oval, sector, triangle, regular quadrilateral, diamond, pentagon, hexagon, etc. The cross section of the columnar structure refers to a plane which is generated by cutting a truncated cone by using a plane parallel to the bottom surface of the columnar structure. Wherein the bottom surface of the pillar structures is parallel to the upper surface of the chip 810.
In one example of these embodiments, as shown in FIG. 8, the solder joint 850 may be of a cylindrical configuration in particular. In another example of these embodiments, the solder joints 850 may be specifically prismatic structures. I.e. the cross-section of the columnar structure is polygonal, e.g. triangular, quadrangular, pentagonal, hexagonal, etc. And are not listed here.
In some embodiments, the solder joint 850 may be specifically a copper pillar (Cu post).
The upper ends of the solder joints 850 are exposed at the upper surface of the plastic layer 820. Wherein the upper end of bond pad 850 is the end of bond pad 850 that is distal from die 810.
In some embodiments, the upper end of the solder joint 850 has a surface layer 880. In one example, the surface layer 880 is pre-set tin. The solder joints 850 have preplaced tin at the upper ends that may facilitate subsequent soldering of the chip package structure 800 to other devices (e.g., printed circuit boards) via the solder joints 850. In one example, the surface layer 880 may be a pre-set treatment of the upper surface of the weld 850. This pre-set process may facilitate subsequent soldering of the chip package structure 800 to other devices (e.g., a printed circuit board) via the solder joints 850, as well as protecting the upper ends of the solder joints 850. The preset process on the upper surface of the solder joint may refer to the description of the embodiment shown in fig. 6, and will not be repeated here.
In some embodiments, as shown in FIG. 8, there is an under bump metal 860 between the bond pad 850 and the rewiring layer 840. Wherein the under bump metal 860 may be disposed on the rewiring layer 840 and in contact with the rewiring layer 840. The solder joint 850 may be disposed on the under bump metal 860 and in contact with the under bump metal 860.
In this way, the embodiment of the application provides a chip packaging structure, in the structure, the lower surface and the side surface of the chip are directly covered with the plastic sealing layer, the upper surface of the chip is covered with the rewiring layer, and the upper surface of the rewiring layer is covered with the plastic sealing layer, so that the upper surface, the lower surface and the side surface of the chip are effectively protected, in particular, the plastic sealing layer part on the chip can effectively buffer or reduce the stress from the upper part of the chip, the microelectronic element integrated on the upper surface of the chip is effectively protected, and the reliability, the performance and the service life of the chip are improved. In addition, the upper surface, the lower surface and the side surfaces of the chip are effectively protected, so that the placement orientation of the chip packaging structure can be unlimited, namely, the chip packaging structure is placed according to a certain orientation without being damaged by stress from the upper surface and the side surfaces of the chip. In the structure, only one layer of welding spots (namely at least one first welding spot) is needed, and a plurality of layers of welding spots do not need to be prepared, so that the height of the chip packaging structure can be reduced, and the size of the chip packaging structure is reduced. That is, the chip packaging structure provided by the embodiment of the application can improve the reliability, performance and service life of the chip and reduce the size of the chip packaging structure.
The structure of the chip package structure 800 is described above, and next, a method of manufacturing the chip package structure 800, i.e., a packaging method of the chip 810 is described as an example.
A wafer as shown in fig. 9A may be obtained, which may include a plurality of chips including chip 810. The wafer may be 8 inches or 12 inches in size, for example. Wherein the upper surface of the chip 810 has at least one pad 811.
In some embodiments, as shown in fig. 9B, the wafer may be thinned to reduce the thickness of the wafer, so as to meet the packaging requirements. Reference is made specifically to the description of the embodiment shown in fig. 4B and will not be repeated here.
In some embodiments, the BSL may also be covered on a lower surface of the wafer, i.e., a lower surface of a plurality of chips included in the wafer. Thus, when the plastic sealing layer material is cast subsequently, the BSL can be encapsulated into the plastic sealing layer. That is, in these embodiments, the portion of the molding layer that covers the lower surface of the chip is directly over the BSL, indirectly over the lower surface of the chip through the BSL. Illustratively, the BSL may be made of glass resin.
Referring to fig. 9C, a re-routing layer 840 and the like may be prepared on the upper surface of the chip 810. Specifically, the following is described.
In some embodiments, dielectric layer 830, re-routing layer 840, under bump metallization 860, dielectric layer 870 may be prepared by a fan out bump (fanout bumping) process. Specifically, a dielectric layer 830 may be prepared on the upper surface of the chip 810. Next, dielectric layer 830 is etched to expose pad 811. A re-routing layer 840 is then deposited over the exposed pads 811 and the upper surface of the dielectric layer 830. The rewiring layer 840 prepared in this way is in contact with the pad 811. Dielectric layer 870 may then be fabricated on the upper surface of rerouting layer 840 and dielectric layer 870 may be etched to expose a partial area of the upper surface of rerouting layer 840. An under bump metal 860 may then be deposited in the exposed areas of the upper surface of the rewiring layer 840. Thus, a structure as shown in fig. 9C can be prepared.
Note that the upper surface of the dielectric layer refers to a surface of the outer surface of the dielectric layer away from the chip 810. The upper surface of the rewiring layer refers to the surface of the outer surface of the rewiring layer that is remote from the chip 810.
Next, referring to fig. 9D, solder joints 850 may be prepared on the rewiring layer. By way of example, solder joints 850 may be specifically fabricated on under bump metal 860, i.e., solder joints 850 and under bump metal 860 are fabricated. In some embodiments, the solder joints 850 may be cylindrical structures. A bump (bumping) process may be used to make the solder joints 850 on the under bump metal 860. In one example, the solder joints 850 are copper pillars. Copper pillars may be fabricated on the under bump metal 860 using a copper pillar bumping (Cu post bumping) process.
Thereafter, referring to fig. 9E, the chip 810 is separated from the other portions of the wafer. Specifically, a wafer dicing (die saw) process may be used to separate or dice a plurality of chips included in a wafer to obtain a plurality of individual chips. In some embodiments, a plurality of chips included in the wafer may be cut by laser cutting (laser cutting) or grinding wheel cutting, so as to obtain a plurality of independent single chips.
After separating the chip 810 from the rest of the wafer, a plastic layer 820 may be covered on the upper surface of the rewiring layer 840, the lower surface of the chip 810, and the sides of the chip 810. Specifically, the following is described.
Referring to fig. 9F, a plurality of individual chips including the chip 810 are rearranged on a carrier by a rearrangement process. Wherein, the chip is placed on the carrier plate in a mode of chip face down (die face down). The chip is placed on the carrier plate in a manner that the front surface of the chip faces downwards, which means that the upper surface or the front surface of the chip faces towards the carrier plate. As shown in fig. 9F, the upper ends of the pads 850 are in contact with the carrier plate. The carrier may be implemented with reference to the description of the embodiment shown in fig. 4E, which is not repeated herein.
Next, referring to fig. 9G, a molding layer material (i.e., a material constituting the molding layer, such as an epoxy molding compound) is poured into the chips such as the chips 810 rearranged on the carrier plate, thereby forming a molding layer 820 covering the upper surface of the rewiring layer 840, the lower surface of the chips 810, and the sides of the chips 810. When the lower surface of the chip 310 is covered with the BSL, the portion of the molding layer covering the lower surface of the chip 310 is directly covered on the BSL, and indirectly covers the lower surface of the chip 310 through the BSL.
Referring to fig. 9H, the carrier plate may be removed to expose the upper end of the chip 850. A surface layer 880 may be prepared on top of the solder joints 850. In one example, prep tin may be prepared on top of the solder joint 850 to provide a surface layer 880. In one example, a pre-set treatment process may be performed on the surface of the upper end of the solder joint 850 to facilitate subsequent soldering of the chip package structure 800 to other devices (e.g., a printed circuit board) via the solder joint 850, as well as to facilitate protection of the upper end of the solder joint 850. The preset process on the upper surface of the solder joint may refer to the description of the embodiment shown in fig. 6, and will not be repeated here.
Thus, the chip package structure 800 may be prepared. In some embodiments, the prepared chip package structure 800 may be separated from other chip package structures prepared simultaneously, resulting in a single chip package structure 800.
In some embodiments, at least two different chips may be recombined on a carrier, and then integrally encapsulated, to obtain a package structure containing the at least two different chips, so as to realize multi-chip encapsulation.
Referring to fig. 10, an embodiment of the present application provides a chip package structure 1000 including a chip 1010 and a rewiring layer 1040 on the chip 1010. Specifically, the upper and lower surfaces of the chip 1010 are opposite, and the rewiring layer 1040 is located on one side of the upper surface of the chip 1010, i.e., the rewiring layer 1040 is located above the upper surface of the chip 1010. Wherein the rewiring layer 1040 is electrically connected to the chip 1010.
Wherein a portion of rewiring layer 1040 is in contact with the upper surface of die 1010 and another portion is spaced from die 1010. For convenience of description, a portion of the rewiring layer 1040 that is in contact with the upper surface of the chip 1010 may be referred to as a portion C6, and a portion that is spaced apart from the chip 1010 may be referred to as a portion C7. In some embodiments, as shown in fig. 10, the upper surface of chip 1010 has at least one pad 1011. Pad 1011 may be referred to the description of pad 311 above and will not be described again. Wherein the portion C6 is in particular in contact with the pad 1011. In some embodiments, as shown in fig. 10, the space between chip 1010 and portion C7 is filled with a dielectric layer 1031. The dielectric layer 1031 may refer to the description of the dielectric layer above, and will not be described herein.
With continued reference to fig. 10, the chip package structure 1000 further includes a molding layer 1020 covering the sides and the lower surface of the chip 100. The material of the plastic layer 1020 may be referred to the above description of the material of the plastic layer 320, which is not repeated here. The side of the chip 1010 refers to a surface other than the upper and lower surfaces of the outer surface of the chip 1010.
The chip package structure 1000 also includes at least one bond pad 1050 located on the rewiring 10640 and electrically connected to the rewiring layer 1040. In some embodiments, the pads 1050 may be cylindrical structures. By way of example, the cross-section of the columnar structure may be of any shape, such as circular, oval, sector, triangle, regular quadrilateral, diamond, pentagon, hexagon, etc. The cross section of the columnar structure refers to a plane which is generated by cutting a truncated cone by using a plane parallel to the bottom surface of the columnar structure. Wherein the bottom surface of the columnar structure is parallel to the upper surface of the chip 1010. In one example of these embodiments, as shown in FIG. 10, the weld 1050 may be a cylindrical structure in particular. In another example of these embodiments, the weld 1050 may be specifically a prismatic structure. I.e. the cross-section of the columnar structure is polygonal, e.g. triangular, quadrangular, pentagonal, hexagonal, etc. And are not listed here.
In some embodiments, the pads 1050 may be copper pillars in particular.
In some embodiments, as shown in FIG. 10, the lower end of the pad 1050 is in contact with the upper surface of the rewiring layer 1040. Where the lower end of bond pad 1050 refers to the end of bond pad 1050 that is closer to die 1010 and the upper surface of rewiring layer 1040 refers to the surface of the outer surface of rewiring layer 1040 that is farther from die 1010.
In some embodiments, as shown in FIG. 10, the dielectric layer 1031 is provided on the upper surface of the rewiring layer 1040 except for the area occupied by the pads 1050.
With continued reference to fig. 10, the chip package structure 1000 further includes a rewiring layer 1060 located on the bonding pads 1050 and electrically connected to the bonding pads 1050. Illustratively, the rewiring layer 1060 is in contact with the upper ends of the pads 1050, which enables an electrical connection to be made between the rewiring layer 1060 and the pads 1050.
In some embodiments, the area of the upper surface of rewiring layer 1060 is greater than the area of the upper surface of chip 1010. Specifically, the projected area of the rewiring layer 1060 in the vertical direction is larger than the area of the upper surface of the chip 1010. That is, the rewiring layer 1060 fans out of the chip 1010. The vertical direction refers to a direction perpendicular to the upper surface of the chip 1010. The upper surface of the rewiring layer 1060 refers to a surface of the outer surface of the rewiring layer 1060 that is remote from the chip 1010. The area of the upper surface of the rewiring layer 1060 is larger than that of the chip 1010, so that more welding spots and other devices can be integrated in the rewiring layer 1060, the chip can be electrically connected with more other devices, and the integration level of the chip is improved.
With continued reference to fig. 10, the chip package structure 1000 further includes at least one solder joint 1090. Wherein solder joint 1090 is located on the rewiring layer 1060 and is electrically connected to the rewiring layer 1060. The chip package structure 1000 may be soldered to a device such as a printed circuit board via solder 1090 to electrically connect the chip 1010 to other electronic devices. In some embodiments, bond pads 1090 may be solder balls (holders), such as tin solder balls.
In some embodiments, as shown in FIG. 10, the upper surface of the rewiring layer 1060 is provided with an under bump metallization 1070. Solder joint 1090 is specifically disposed on under bump metal 1070. Solder joint 1090 electrically connects rewiring layer 1060 through under bump metal 1070. Wherein the upper surface of the rewiring layer 1060 refers to a surface of the outer surface of the rewiring layer 1060 that is remote from the chip 1010.
In some embodiments, as shown in FIG. 10, the area of the upper surface of rewiring layer 1060 other than the area occupied by under-bump metal 1070 is covered with a dielectric layer 1080. The material of the dielectric layer may be described above, and will not be described herein.
In this way, the embodiment of the application provides a chip packaging structure, in the structure, at least two rewiring layers are arranged on the upper surface of a chip, and the at least two rewiring layers can effectively buffer and release external stress, so that microelectronic components integrated on the upper surface of the chip can be effectively protected. The lower surface and the side surfaces of the chip are covered with the plastic sealing layer, so that the lower surface and the side surfaces of the chip are effectively protected. In addition, the upper surface, the lower surface and the side surfaces of the chip are effectively protected, so that the placement orientation of the chip packaging structure can be unlimited, namely, the chip packaging structure is placed according to a certain orientation without being damaged by stress from a certain aspect. At the same time of achieving the aforementioned effects, in this structure, at least one of the at least two rewiring layers can fan out, so that the integration level of the chip can be improved.
The structure of the chip package structure 1000 is described above, and next, a method of manufacturing the chip package structure 1000, i.e., a packaging method of the chip 1010 is described as an example.
A wafer as shown in fig. 11A may be obtained, which may include a plurality of chips including chip 1010. The wafer may be 8 inches or 12 inches in size, for example. Wherein the upper surface of the chip 1010 has at least one pad 1011.
Referring to fig. 11B, a re-routing layer 1040 or the like may be prepared on the upper surface of the chip 1010. Specifically, the following is described.
In some embodiments, dielectric layer 1031, rewiring layer 1040, and pads 1050 may be prepared by a fan-out bump process. Specifically, a dielectric layer 1031 may be prepared on the upper surface of the chip 1010. Next, the dielectric layer 1031 is sequentially exposed, developed, and etched to expose the pad 1011. A re-routing layer 1040 is then deposited over the exposed pads 1011 and the upper surface of dielectric layer 1031. The rewiring layer 1040 prepared in this manner is in contact with the pad 1011. Dielectric layer 1032 may then be prepared on the upper surface of rerouting layer 1040 and dielectric layer 1032 may be etched to expose a partial region of the upper surface of rerouting layer 1040. Solder bumps 1050 may then be prepared in the exposed areas of the upper surface of rewiring layer 1040. In one example, the weld 1050 may be a columnar structure. Bump (bumping) process may be used to prepare solder bumps 1050 on exposed areas in the upper surface of rewiring layer 1040. In one example, the pads 1050 are copper pillars. Copper pillars may be fabricated on exposed areas in the upper surface of rewiring layer 1040 using a copper pillar bumping (Cu post bumping) process. Thus, the structure shown in FIG. 11B can be prepared.
The upper surface of the dielectric layer refers to a surface of the outer surface of the dielectric layer away from the chip 1010. The upper surface of the rewiring layer refers to the surface of the outer surface of the rewiring layer that is remote from the chip 1010.
In some embodiments, as shown in fig. 11C, the wafer may be thinned to reduce the thickness of the wafer and meet the packaging requirements. Reference is made specifically to the description of the embodiment shown in fig. 4B and will not be repeated here.
In some embodiments, the BSL may also be covered on a lower surface of the wafer, i.e., a lower surface of a plurality of chips included in the wafer. Thus, when the plastic sealing layer material is cast subsequently, the BSL can be encapsulated into the plastic sealing layer. That is, in these embodiments, the portion of the molding layer that covers the lower surface of the chip is directly over the BSL, indirectly over the lower surface of the chip through the BSL. Illustratively, the BSL may be made of glass resin.
Next, referring to fig. 11D, the die 1010 is separated from the rest of the wafer. Specifically, a wafer dicing (die saw) process may be used to separate or dice a plurality of chips included in a wafer to obtain a plurality of individual chips. In some embodiments, a plurality of chips included in the wafer may be cut by laser cutting (laser cutting) or grinding wheel cutting, so as to obtain a plurality of independent single chips.
After separating the die 1010 from the rest of the wafer, a plastic layer 1220 may be prepared. Specifically, the following is described.
Referring to fig. 11E, a plurality of individual chips including the chip 1010 are rearranged on a carrier by a rearrangement process. Wherein, the chip is placed on the carrier plate in a mode of chip face down (die face down). With a space between adjacent chips. The chip is placed on the carrier plate in a manner that the front surface of the chip faces downwards, which means that the upper surface or the front surface of the chip faces towards the carrier plate. As shown in fig. 11E, the upper ends of the pads 1050 are in contact with the carrier plate. The carrier may be implemented with reference to the description of the embodiment shown in fig. 4E, which is not repeated herein.
Next, referring to fig. 11F, a molding layer material (i.e., a material constituting the molding layer, such as an epoxy molding compound) is poured into the chips such as the chips 1010 rearranged on the carrier board, thereby forming a molding layer 1020 covering at least the lower surface and sides of the chips 1010. When the lower surface of the chip 310 is covered with the BSL, the portion of the molding layer covering the lower surface of the chip 310 is directly covered on the BSL, and indirectly covers the lower surface of the chip 310 through the BSL.
Referring to fig. 11G, the carrier plate may be removed and the portion of the molding layer 1020 above the dielectric layer 1032 may be removed by a polishing process. Wherein, the top of the dielectric layer 1032 refers to the direction away from the chip 1010 along the vertical direction.
After the molding layer 1020 is prepared, the re-routing layer 1060 and the solder joints 1090 may be prepared, as follows,
referring to fig. 11H, a re-routing layer 1060 may be prepared on the upper ends of the exposed pads 1050 and the upper surface of the dielectric layer 1032.
An under bump metal 1070 may then be fabricated on the re-wiring layer 1060. Specifically, a dielectric layer 1080 covering the upper surface of the rewiring layer 1060 may be first prepared. The dielectric layer 1080 may be polyimide or a plastic layer (e.g., EMC). Dielectric layer 1080 is then etched to expose a portion of the upper surface of rewiring layer 1060. Thereafter, an under bump metal 1070 may be prepared in the exposed area in the upper surface of the re-wiring layer 1060.
Referring to FIG. 11I, solder joint 1090 may be prepared on under bump metal 1070.
Thus, the chip package structure 1000 may be prepared. In some embodiments, the chip package structure 1000 may be separated from other package structures that are simultaneously fabricated, resulting in a separate chip package structure 1000.
In some embodiments, at least two different chips may be recombined on a carrier, and then integrally encapsulated, to obtain a package structure containing the at least two different chips, so as to realize multi-chip encapsulation.
Referring to fig. 12, an embodiment of the present application provides a chip package structure 1200 including a chip 1210 and a rewiring layer 1240 on the chip 1210. Specifically, the upper and lower surfaces of chip 1210 are opposite, and re-routing layer 1240 is located on one side of the upper surface of chip 1210, i.e., re-routing layer 1240 is located above the upper surface of chip 1210. Wherein the rewiring layer 1240 and the chip 1210 are electrically connected.
Wherein a portion of rewiring layer 1240 is in contact with the upper surface of chip 1210 and another portion is spaced from chip 1210. For convenience of description, a portion of the rewiring layer 1240 in contact with the upper surface of the chip 1210 may be referred to as a portion C8, and a portion having a space from the chip 1210 may be referred to as a portion C9. In some embodiments, as shown in fig. 12, the upper surface of chip 1210 has at least one pad 1211. Pad 1211 may refer to the description of pad 311 above, and will not be described again. Wherein portion C8 is in particular in contact with pad 1211. In some embodiments, as shown in fig. 12, the space between chip 1210 and portion C9 is filled with a dielectric layer 1231. The dielectric layer 1231 may refer to the description of the dielectric layer above, and will not be described herein.
With continued reference to fig. 12, the chip package structure 1000 further includes a molding layer 1220 that covers the upper surface of the rewiring layer 1240, the sides of the chip 100, and the lower surface of the chip. The material of the plastic layer 1220 may be referred to the above description of the material of the plastic layer 320, and will not be repeated here. The side of the chip 1210 refers to a surface other than the upper and lower surfaces of the outer surface of the chip 1210. The upper surface of the re-wiring layer 1240 refers to the surface of the outer surface of the re-wiring layer 1240 that is remote from the chip 1210.
Chip package structure 1200 also includes at least one bond pad 1250 that is located on rewiring 1240 and that is electrically connected to rewiring layer 1240. In some embodiments, bond pad 1250 may be a columnar structure. By way of example, the cross-section of the columnar structure may be of any shape, such as circular, oval, sector, triangle, regular quadrilateral, diamond, pentagon, hexagon, etc. The cross section of the columnar structure refers to a plane which is generated by cutting a truncated cone by using a plane parallel to the bottom surface of the columnar structure. Wherein the bottom surface of the columnar structure is parallel to the upper surface of the chip 1210. In one example of these embodiments, as shown in FIG. 12, bond pad 1250 may be specifically a cylindrical structure. In another example of these embodiments, bond pad 1250 may be specifically a prismatic structure. I.e. the cross-section of the columnar structure is polygonal, e.g. triangular, quadrangular, pentagonal, hexagonal, etc. And are not listed here.
In some embodiments, bond pad 1250 may be a copper pillar in particular.
In some embodiments, as shown in FIG. 12, the lower end of bond pad 1250 is in contact with the upper surface of rewiring layer 1240. Wherein the lower end of bond pad 1250 refers to the end of bond pad 1250 that is near die 1210.
In some embodiments, as shown in FIG. 12, dielectric layer 1231 is present on areas of the upper surface of rewiring layer 1240 other than the areas occupied by bond pads 1250. Specifically, there is a dielectric layer 1231 between the portion of molding layer 1220 located on the upper surface of re-routing layer 1240 and the upper surface of re-routing layer 1240. In other words, dielectric layer 1231 directly covers the upper surface of re-wiring layer 1240, and molding layer 1220 located on the upper surface of re-wiring layer 1240 partially covers dielectric layer 1231 and is further spaced from the upper surface of re-wiring layer 1240.
With continued reference to fig. 12, the chip package structure 1200 also includes a rewiring layer 1260 located on the bond pads 1250 and electrically connected to the bond pads 1250. Illustratively, rewiring layer 1260 is in contact with the upper end of bond pad 1250, which enables an electrical connection to be made between rewiring layer 1260 and bond pad 1250.
In some embodiments, the area of the upper surface of rewiring layer 1260 is greater than the area of the upper surface of chip 1210. Specifically, the projected area of the rewiring layer 1260 in the vertical direction is larger than the area of the upper surface of the chip 1210. That is, rewiring layer 1260 fans out from chip 1210. Wherein the vertical direction refers to a direction perpendicular to the upper surface of the chip 1210. The upper surface of the rewiring layer 1260 refers to a surface of the outer surface of the rewiring layer 1260 that is remote from the chip 1210. The area of the upper surface of the rewiring layer 1260 is larger than the area of the chip 1210, so that more welding spots and other devices can be integrated in the rewiring layer 1260, the chip can be electrically connected with more other devices, and the integration level of the chip is improved.
With continued reference to fig. 10, the chip package structure 1200 also includes at least one solder joint 1290. Wherein solder joint 1290 is located on rewiring layer 1260 and is electrically connected to rewiring layer 1260. The die package structure 1200 may be soldered to a device such as a printed circuit board via solder joint 1290 to electrically connect the die 1210 to other electronic devices. In some embodiments, solder joint 1290 may be a solder ball (holder), such as a tin solder ball.
In some embodiments, as shown in fig. 12, the upper surface of the rewiring layer 1260 is provided with an under bump metal 1270. Solder joint 1290 is specifically disposed on under bump metal 1270. Solder joint 1290 electrically connects rewiring layer 1260 through under bump metal 1270. Wherein the upper surface of the rewiring layer 1260 refers to a surface of the outer surface of the rewiring layer 1260 that is remote from the chip 1210.
In some embodiments, as shown in fig. 12, the area of the upper surface of rewiring layer 1260 other than the area occupied by under-bump metal 1270 is covered with a dielectric layer 1280. The material of the dielectric layer may be described above, and will not be described herein.
In this way, the embodiment of the application provides a chip packaging structure, in the structure, at least two rewiring layers are arranged on the upper surface of a chip, the at least two rewiring layers can effectively buffer and release external stress, and further, a plastic sealing layer is arranged above the chip, so that the stress from above the chip can be further buffered and released. Thus, the microelectronic components integrated on the upper surface of the chip can be more effectively protected. In addition, the lower surface and the side surfaces of the chip are covered with the plastic sealing layer, so that the lower surface and the side surfaces of the chip are effectively protected. In addition, the upper surface, the lower surface and the side surfaces of the chip are effectively protected, so that the placement orientation of the chip packaging structure can be unlimited, namely, the chip packaging structure is placed according to a certain orientation without being damaged by stress from a certain aspect. At the same time of achieving the aforementioned effects, in this structure, at least one of the at least two rewiring layers can fan out, so that the integration level of the chip can be improved.
The structure of the chip package structure 1200 is described above, and next, a method of manufacturing the chip package structure 1200, i.e., a packaging method of the chip 1210 is described as an example.
A wafer as shown in fig. 13A may be obtained, which may include a plurality of chips including chip 1210. The wafer may be 8 inches or 12 inches in size, for example. Wherein the upper surface of the chip 1210 has at least one pad 1211.
Referring to fig. 13B, a re-wiring layer 1240 or the like may be prepared on the upper surface of chip 1210. Specifically, the following is described.
In some embodiments, dielectric layer 1231, re-routing layer 1240, and bond pads 1250 may be prepared by a fan-out bump process. Specifically, dielectric layer 1231 may be prepared on the upper surface of chip 1210. Next, dielectric layer 1231 is etched to expose pad 1211. A re-routing layer 1240 is then deposited over the exposed pads 1211 and dielectric layer 1231. The re-wiring layer 1240 prepared in this way is in contact with the pads 1211. Dielectric layer 1232 may then be prepared on the upper surface of re-routing layer 1240 and dielectric layer 1232 etched to expose a partial region of the upper surface of re-routing layer 1240. Solder joint 1250 can then be prepared in the exposed areas of the upper surface of rewiring layer 1240. In one example, bond pad 1250 may be a columnar structure. Bump (bumping) process may be used to prepare bond pads 1250 on exposed areas in the upper surface of rewiring layer 1240. In one example, the pads 1050 are copper pillars. Copper pillars may be fabricated on exposed areas in the upper surface of the rewiring layer 1240 using a copper pillar bumping (Cu post bumping) process. Thus, the structure shown in FIG. 13B can be prepared.
The upper surface of the dielectric layer refers to a surface of the outer surface of the dielectric layer away from the chip 1210. The upper surface of the rewiring layer refers to the surface of the outer surface of the rewiring layer that is remote from the chip 1210.
In some embodiments, as shown in fig. 13C, the wafer may be thinned to reduce the thickness of the wafer and meet the packaging requirements. Reference is made specifically to the description of the embodiment shown in fig. 4B and will not be repeated here.
In some embodiments, the BSL may also be covered on a lower surface of the wafer, i.e., a lower surface of a plurality of chips included in the wafer. Thus, when the plastic sealing layer material is cast subsequently, the BSL can be encapsulated into the plastic sealing layer. That is, in these embodiments, the portion of the molding layer that covers the lower surface of the chip is directly over the BSL, indirectly over the lower surface of the chip through the BSL. Illustratively, the BSL may be made of glass resin.
Next, referring to fig. 13D, the die 1010 is separated from the rest of the wafer. Specifically, a wafer dicing (die saw) process may be used to separate or dice a plurality of chips included in a wafer to obtain a plurality of individual chips. In some embodiments, a plurality of chips included in the wafer may be cut by laser cutting (laser cutting) or grinding wheel cutting, so as to obtain a plurality of independent single chips.
After separating the chip 1210 from the rest of the wafer, a plastic layer 1220 may be prepared. Specifically, the following is described.
Referring to fig. 13E, a plurality of individual chips including chip 1210 are rearranged on a carrier by a rearrangement process. Wherein, the chip is placed on the carrier plate in a mode of chip face down (die face down). With a space between adjacent chips. The chip is placed on the carrier plate in a manner that the front surface of the chip faces downwards, which means that the upper surface or the front surface of the chip faces towards the carrier plate. As shown in fig. 13E, the upper ends of bond pads 1250 are in contact with the carrier plate. The carrier may be implemented with reference to the description of the embodiment shown in fig. 4E, which is not repeated herein.
Next, referring to fig. 13F, a molding layer material (i.e., a material constituting the molding layer, such as an epoxy molding compound) is poured onto the chips such as chip 1210, which are rearranged on the carrier, so as to cover the upper surface of rewiring layer 1240, the lower surface of chip 1210, and molding layer 1220 on the sides of chip 1210. When the lower surface of the chip 310 is covered with the BSL, the portion of the molding layer covering the lower surface of the chip 310 is directly covered on the BSL, and indirectly covers the lower surface of the chip 310 through the BSL.
After the molding layer 1220 is prepared, the rewiring layer 1260 and solder joint 1290 may be prepared, as follows,
referring to fig. 13G, a rewiring layer 1260 may be prepared on the upper ends of the bare pads 1250 and the upper surface of the molding layer 1220. The upper surface of the molding layer 1220 refers to an outer surface of the molding layer 1220 located above the chip 1210.
An under bump metal 1270 may then be prepared on the rewiring layer 1260. Specifically, a dielectric layer 1280 covering the upper surface of the rewiring layer 1260 may be prepared first. The dielectric layer 1280 may be polyimide or a plastic layer (e.g., EMC). Dielectric layer 1280 is then etched to expose a portion of the upper surface of rewiring layer 1260. Thereafter, an under bump metal 1270 may be prepared in the exposed areas in the upper surface of the rewiring layer 1260.
Referring to fig. 13H, solder joint 1290 may be prepared on under bump metal 1270.
In this manner, the chip package structure 1200 may be fabricated. In some embodiments, the chip package structure 1200 may be separated from other package structures that are simultaneously fabricated, resulting in a separate chip package structure 1200.
In some embodiments, at least two different chips may be recombined on a carrier, and then integrally encapsulated, to obtain a package structure containing the at least two different chips, so as to realize multi-chip encapsulation.
It should be understood that the above embodiments are only for illustrating the technical solution of the present application, and are not limited thereto; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (20)
1. A chip package structure, comprising:
a chip having opposite upper and lower surfaces, wherein the upper surface is provided with at least one first solder joint;
a plastic layer covering the upper surface, the lower surface and the side surfaces of the chip; the upper end of the first welding spot is exposed on the upper surface of the plastic sealing layer; the upper end of the first welding spot is one end of the first welding spot far away from the chip;
A rewiring layer located on and in contact with the first pad, wherein the contact is such that the first pad and the rewiring layer form an electrical connection;
and at least one second solder joint located on and electrically connected to the rewiring layer.
2. The structure of claim 1, wherein a projected area of the rewiring layer in a vertical direction is larger than an area of an upper surface of the chip, the vertical direction being perpendicular to the upper surface of the chip.
3. The structure of claim 1 or 2, wherein the first solder joint is a cylindrical structure.
4. A method of packaging a chip, comprising the steps of:
(1) Obtaining a wafer, wherein the wafer comprises a chip, and the chip is provided with an upper surface and a lower surface which are opposite;
(2) Preparing at least one first welding spot on the upper surface of the chip;
(3) Covering the upper surface, the lower surface and the side surfaces of the chip with a plastic sealing layer, and exposing the upper end of the first welding spot on the upper surface of the plastic sealing layer; the upper end of the first welding spot is one end of the first welding spot far away from the chip;
(4) Preparing a rewiring layer in contact with the first solder joint, wherein the contact enables the first solder joint and the rewiring layer to form an electrical connection;
(5) At least one second solder joint is prepared on the rewiring layer in electrical connection with the rewiring layer.
5. The method of claim 4, wherein the covering the upper surface, the lower surface, and the side surfaces of the chip with a molding layer comprises:
placing the chip on a carrier plate, wherein the upper end of the first welding spot is contacted with the carrier plate;
pouring an injection molding material on the chip to form a molding layer covering the upper surface, the lower surface and the side surfaces of the chip;
and removing the carrier plate to expose the upper end of the first welding spot.
6. The method of claim 4, wherein preparing a rewiring layer in contact with the first solder joint upper end comprises:
preparing a dielectric layer on the upper surface of the plastic layer and the upper end of the first welding spot;
etching the dielectric layer to expose the upper end of the first welding spot;
the rewiring layer is deposited.
7. A chip package structure, comprising:
A chip having opposite upper and lower surfaces;
a rewiring layer located on the chip and electrically connected to the chip;
a first molding layer covering an upper surface of the rewiring layer and a side surface of the chip, wherein the upper surface of the rewiring layer is a surface of the outer surface of the rewiring layer, which is far away from the chip;
at least one solder joint located on the rewiring layer and electrically connected with the rewiring layer; the upper end of the welding spot is exposed on the upper surface of the first plastic sealing layer, and the upper end of the welding spot is the end of the welding spot far away from the chip;
and a back protective layer covering the lower surface of the chip.
8. The structure of claim 7, wherein the solder joint is a cylindrical structure.
9. The structure of claim 8, wherein the upper ends of the solder joints are surface treated or covered with preplaced tin.
10. The structure of claim 7 or 8, wherein the back protective layer is a second plastic layer or a thermally conductive layer.
11. A method of packaging a chip, comprising the steps of:
(1) Obtaining a wafer, wherein the wafer comprises chips; the chip has opposite upper and lower surfaces;
(2) Preparing a rewiring layer electrically connected with the chip on the upper surface of the chip;
(3) Preparing at least one solder joint on the rewiring layer, wherein the solder joint is electrically connected with the rewiring layer;
(4) Covering a first plastic sealing layer on the upper surface of the rewiring layer and the side surface of the chip; the upper surface of the rewiring layer is the surface, far away from the chip, of the outer surface of the rewiring layer, the upper end of the welding spot is exposed on the upper surface of the first plastic sealing layer, and the upper end of the welding spot is the end, far away from the chip, of the welding spot;
(5) And preparing a back protective layer covering the lower surface of the chip.
12. The method of claim 11, wherein the solder joint is a columnar structure, the method further comprising: and carrying out surface treatment on the upper end of the welding spot, or preparing preset tin on the upper end of the welding spot.
13. The method according to claim 11 or 12, wherein,
the step of covering the first plastic sealing layer on the upper surface of the rewiring layer and the side surface of the chip comprises the following steps:
placing the chip on a carrier plate, wherein the lower surface of the chip is contacted with the carrier plate;
And casting an injection molding material to the chip to form a first injection molding layer covering the upper surface of the rewiring layer and the side surface of the chip.
14. The method of claim 11 or 12, wherein said covering the upper surface of the rewiring layer and the chip side with a first molding layer comprises:
placing the chip on a carrier plate, wherein the welding spots are contacted with the carrier plate;
and casting an injection molding material to the chip to form a first injection molding layer covering the upper surface of the rewiring layer and the side surface of the chip.
15. A chip package structure, comprising:
a chip having opposite upper and lower surfaces;
a first rewiring layer covering an upper surface of the chip;
at least a first plastic sealing layer covering the side surface of the chip and the lower surface of the chip;
at least one first pad on an upper surface of the first rewiring layer and electrically connected to the first rewiring layer; wherein the upper surface of the first rewiring layer is a surface of the first rewiring layer outer surface, which is far away from the chip;
a second rewiring layer located on the at least one first welding spot and electrically connected with the at least one first welding spot;
At least one second pad on the second rewiring layer.
16. The structure of claim 15, wherein a projected area of the second rewiring layer in a vertical direction is larger than an area of the chip upper surface, the vertical direction being perpendicular to the chip upper surface.
17. The structure of claim 15 or 16, wherein the first plastic layer also covers an upper surface of the first rewiring layer.
18. The structure of claim 15 or 16, wherein the first solder joint is a cylindrical structure.
19. A method of packaging a chip, comprising the steps of:
(1) Obtaining a wafer, wherein the wafer comprises chips; the chip has opposite upper and lower surfaces;
(2) Preparing a first rewiring layer electrically connected with the chip on the upper surface of the chip;
(3) Preparing at least one first solder joint on the first rewiring layer, wherein the first solder joint is electrically connected with the first rewiring layer;
(4) Placing the chip on a carrier plate, wherein the first welding spot is contacted with the carrier plate;
(5) Casting an injection molding material to the chip to form a first molding layer covering at least the side surface of the chip and the lower surface of the chip;
(6) Removing the carrier plate to expose the upper end of the first welding spot, wherein the upper end of the first welding spot is the end of the first welding spot far away from the chip;
(7) Preparing a second re-wiring layer over the first solder joint, and preparing at least one second solder joint on the second re-wiring layer.
20. The method of claim 19, wherein the preparing a second rewiring layer over the first pad comprises:
after reducing the height of the first solder joint in a vertical direction, preparing the second rewiring layer above the first solder joint, wherein the vertical direction is perpendicular to the upper surface of the chip.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210373729.8A CN116936488A (en) | 2022-04-11 | 2022-04-11 | Chip packaging structure and packaging method |
| PCT/CN2023/070689 WO2023197701A1 (en) | 2022-04-11 | 2023-01-05 | Chip packaging structure and packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210373729.8A CN116936488A (en) | 2022-04-11 | 2022-04-11 | Chip packaging structure and packaging method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116936488A true CN116936488A (en) | 2023-10-24 |
Family
ID=88328778
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210373729.8A Pending CN116936488A (en) | 2022-04-11 | 2022-04-11 | Chip packaging structure and packaging method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN116936488A (en) |
| WO (1) | WO2023197701A1 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107611092A (en) * | 2017-10-13 | 2018-01-19 | 中芯长电半导体（江阴）有限公司 | Wafer stage chip encapsulating structure and preparation method thereof |
| CN111668168B (en) * | 2019-03-08 | 2022-06-10 | 江苏长电科技股份有限公司 | Packaging structure and forming method thereof |
| CN211017056U (en) * | 2019-12-16 | 2020-07-14 | 江阴长电先进封装有限公司 | Packaging structure of six-face cladding core plate size |
| CN211320091U (en) * | 2020-01-08 | 2020-08-21 | 王之奇 | Fan-out packaging structure of chip |
-
2022
- 2022-04-11 CN CN202210373729.8A patent/CN116936488A/en active Pending
-
2023
- 2023-01-05 WO PCT/CN2023/070689 patent/WO2023197701A1/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| WO2023197701A1 (en) | 2023-10-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11107701B2 (en) | Stiffener package and method of fabricating stiffener package | |
| CN108346646B (en) | Semiconductor device and method for manufacturing the same | |
| US9837376B2 (en) | Manufacturing method of semiconductor device and semiconductor device thereof | |
| US6559528B2 (en) | Semiconductor device and method for the fabrication thereof | |
| US10679930B2 (en) | Metal core solder ball interconnector fan-out wafer level package | |
| TWI626697B (en) | Semiconductor device and method of forming fine pitch rdl over semiconductor die in fan-out package | |
| US8466552B2 (en) | Semiconductor device and method of manufacturing the same | |
| US8264085B2 (en) | Semiconductor device package interconnections | |
| US8227926B2 (en) | Routing layer for mitigating stress in a semiconductor die | |
| TWI502663B (en) | Semiconductor device and method of forming enhanced ubm structure for improving solder joint reliability | |
| CN102543923B (en) | Semiconductor device and manufacture method thereof | |
| US9230901B2 (en) | Semiconductor device having chip embedded in heat spreader and electrically connected to interposer and method of manufacturing the same | |
| US20060292752A1 (en) | Method for fabricating board on chip (BOC) semiconductor package with circuit side polymer layer | |
| US7858512B2 (en) | Semiconductor with bottom-side wrap-around flange contact | |
| JP2009302564A (en) | Ic chip package with directly connected leads | |
| KR20080094251A (en) | Wafer level package and method for the manufacturing same | |
| JP2014516472A (en) | Routing layer to reduce stress in semiconductor dies | |
| TW202238753A (en) | Semiconductor package | |
| KR102619532B1 (en) | Semiconductor Package | |
| KR101684071B1 (en) | Semiconductor device and manufacturing method thereof | |
| CN116936488A (en) | Chip packaging structure and packaging method | |
| KR101631406B1 (en) | Semiconductor package and manufacturing method thereof | |
| JP4631223B2 (en) | Semiconductor package and semiconductor device using the same | |
| CN110660751A (en) | Chip package | |
| KR100830347B1 (en) | Direct chip attaching package, manufacturing method thereof and stacked direct chip attaching package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication |