JP2004072032A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
JP2004072032A
JP2004072032A JP2002232737A JP2002232737A JP2004072032A JP 2004072032 A JP2004072032 A JP 2004072032A JP 2002232737 A JP2002232737 A JP 2002232737A JP 2002232737 A JP2002232737 A JP 2002232737A JP 2004072032 A JP2004072032 A JP 2004072032A
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semiconductor
insulating film
semiconductor device
rewiring
base plate
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JP3951854B2 (en
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Ichiro Mihara
三原　一郎
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP2002232737A priority Critical patent/JP3951854B2/en
Priority to PCT/JP2003/009958 priority patent/WO2004015771A2/en
Priority to CA2464078A priority patent/CA2464078C/en
Priority to AU2003253425A priority patent/AU2003253425C1/en
Priority to CN038012693A priority patent/CN1568546B/en
Priority to KR1020047005322A priority patent/KR100593049B1/en
Priority to EP03784529A priority patent/EP1527480A2/en
Priority to TW092121811A priority patent/TWI231551B/en
Publication of JP2004072032A publication Critical patent/JP2004072032A/en
Priority to US10/826,039 priority patent/US7294922B2/en
Priority to HK05105873.6A priority patent/HK1073389A1/en
Priority to US11/671,318 priority patent/US7547967B2/en
Priority to US11/671,268 priority patent/US7618886B2/en
Publication of JP3951854B2 publication Critical patent/JP3951854B2/en
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Priority to US12/415,782 priority patent/US7737543B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To electrically connect a semiconductor chip and a solder ball without undergoing a bonding step, for example, upon manufacturing a semiconductor device called the BGA (ball grid array). <P>SOLUTION: A plurality of semiconductor structures 22 having a rewiring pattern 30 formed on a silicon substrate (semiconductor chip) 24 are bonded on an adhesive layer 21 on a base plate 20 corresponding to a plurality of semiconductor devices. A sealing film 31 is formed on the structures 22 and on the adhesive layer 21. An upper rewiring pattern 34, an insulating film 35, a solder ball 37, etc. are formed. When the mutually adjacent semiconductor structures are cut therebetween, a plurality of semiconductor devices having the solder ball 37 are obtained. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
この発明は半導体装置およびその製造方法に関する。
【０００２】
【従来の技術】
例えばＢＧＡ（ｂａｌｌ　ｇｒｉｄ　ａｒｒａｙ）と呼ばれる半導体装置には、ＬＳＩなどからなる半導体チップを該半導体チップのサイズよりもやや大きいサイズの中継基板（インターポーザ）の上面中央部に搭載し、中継基板の下面に半田ボールによる接続端子をマトリクス状に配置したものがある。
【０００３】
図２６は従来のこのような半導体装置の一例の断面図を示したものである。半導体チップ１は、シリコン基板２の周辺部に銅などからなる複数のバンプ電極３が設けられた構造となっている。
【０００４】
中継基板４は、サイズが半導体チップ１のシリコン基板２のサイズよりもやや大きいベースフィルム５を備えている。ベースフィルム５の上面には、半導体チップ１のバンプ電極３に接続される再配線６が設けられている。
【０００５】
再配線６は、半導体チップ１のバンプ電極３に対応して設けられた第１の接続パッド７と、マトリクス状に設けられた第２の接続パッド８と、第１と第２の接続パッド７、８を接続する引き回し線９とからなっている。第２の接続パッド８の中央部に対応する部分におけるベースフィルム５には円孔１０が設けられている。
【０００６】
そして、半導体チップ１は中継基板４の上面中央部に異方性導電接着剤１１を介して搭載されている。異方性導電接着剤１１は、熱硬化性樹脂１２中に多数の導電性粒子１３を含有させたものからなっている。
【０００７】
半導体チップ１を中継基板４上に搭載する場合には、まず、中継基板４の上面中央部にシート状の異方性導電接着剤１１を介して半導体チップ１を位置合わせしてただ単に載置する。
【０００８】
次に、熱硬化性樹脂１２が硬化する温度にて所定の圧力を加えてボンディングする。すると、バンプ電極３が熱硬化性樹脂１２を押し退けて第１の接続パッド７の上面に導電性粒子１３を介して導電接続され、且つ、半導体チップ１の下面が中継基板４の上面に熱硬化性樹脂１２を介して接着される。
【０００９】
次に、半導体チップ１を含む中継基板４の上面全体にエポキシ系樹脂からなる封止膜１４を形成する。次に、円孔１０内およびその下方に半田ボール１５を第２の接続パッド８に接続させて形成する。この場合、第２の接続パッド８はマトリクス状に配置されているため、半田ボール１５もマトリクス状に配置される。
【００１０】
ここで、半田ボール１５のサイズは半導体チップ１のバンプ電極３のサイズより大きく、また、各半田ボール１５相互の接触を避けるため、その配置間隔をバンプ電極３の配置間隔より大きくする必要がある。そこで、半導体チップ１のバンプ電極３の数が増大した場合、各半田ボール１５に必要な配置間隔を得るため、その配置領域を半導体チップ１のサイズより大きくすることが必要となり、そのために、中継基板４のサイズを半導体チップ１のサイズよりもやや大きくしている。したがって、マトリクス状に配置された半田ボール１５のうち、周辺部の半田ボール１５は半導体チップ１の周囲に配置されている。
【００１１】
【発明が解決しようとする課題】
ところで、上記従来の半導体装置では、再配線６が形成された中継基板４を用い、位置合わせした後のボンディングにより、半導体チップ１のバンプ電極３の下面を中継基板４の再配線６の第１の接続パッド７の上面に導電接続する構成としているので、半導体チップ１のバンプ電極３の数が増大し、バンプ電極３のサイズおよび配置間隔が小さくなると、位置合わせが極めて大変であるという問題があった。この場合、半導体チップ１のサイズを大きくすれば、バンプ電極３のサイズおよび配置間隔を大きくすることができることは当然であるが、そのようにすると、ウエハ状態からの半導体チップの取り数が激減し、極めて高価なものとなってしまう。また、半導体チップ１を１つずつ中継基板４上にボンディングして搭載しなければならず、製造工程が煩雑であるという問題があった。このようなことは、半導体チップを複数個備えたマルチチップモジュール型の半導体装置の場合も同様である。
【００１２】
そこで、この発明は、ボンディングによることなく外部接続電極の配置間隔を大きくすることができる半導体装置およびその製造方法を提供することを目的とする。
また、この発明は、複数の半導体装置を一括して製造することができる半導体装置の製造方法を提供することを目的とする。
【００１３】
【課題を解決するための手段】
請求項１に記載の発明は、半導体基板上に、それぞれが、パッド部を有する複数の再配線を設けてなる半導体構成体と、前記各パッド部を除いて前記再配線を含む前記半導体構成体の上面全体および前記半導体構成体の周側面より外側の延出部に設けられた絶縁膜と、該絶縁膜上に、前記再配線のパッド部に接続されて設けられ且つ接続パッド部を有する少なくとも一層の上層再配線とを備え、前記上層再配線の中、最上層の上層再配線の少なくとも一部は、前記接続パッド部が、前記半導体構成体の周側面より外側の前記絶縁膜の延出部上に配置されていることを特徴とするものである。
請求項２に記載の発明は、各々が、半導体基板と、該半導体基板の上面に設けられ且つパッド部を有する複数の再配線を有し、互いに離間して配置された複数の半導体構成体と、前記各半導体構成体のパッド部を除いて前記再配線を含む上面全体および前記各半導体構成体の周側面より外側の延出部に設けられた絶縁膜と、該絶縁膜上に、前記パッド部に接続されて設けられ且つ接続パッド部を有する少なくとも一層の上層再配線とを備え、前記上層再配線の中、最上層の上層再配線の少なくとも一部は、前記接続パッド部が前記いずれかの半導体構成体の周側面より外側の前記延出部上に配置されていることを特徴とするものである。
請求項３に記載の発明は、請求項１または２に記載の発明において、前記絶縁膜は前記半導体構成体の周側面を覆って設けられていることを特徴とするものである。
請求項４に記載の発明は、請求項１または２に記載の発明において、前記複数の再配線は、前記半導体基板上に設けられた保護膜上に形成されていることを特徴とするものである。
請求項５に記載の発明は、請求項４に記載の発明において、前記半導体構成体の周側面を覆う前記絶縁膜の下面は前記半導体構成体の下面とほぼ同一の平面上に配置されていることを特徴とするものである。
請求項６に記載の発明は、請求項４に記載の発明において、前記半導体構成体およびその周囲における前記絶縁膜の下面に放熱層が設けられていることを特徴とするものである。
請求項７に記載の発明は、請求項１または２に記載の発明において、前記絶縁膜の延出部の下方には、埋込材が配置されていることを特徴とするものである。請求項８に記載の発明は、請求項７に記載の発明において、前記埋込材は前記半導体基板とほぼ同じ厚さを有することを特徴とするものである。
請求項９に記載の発明は、請求項８に記載の発明において、前記埋込材と前記半導体構成体との間に絶縁膜が充填されていることを特徴とするものである。
請求項１０に記載の発明は、請求項１または２に記載の発明において、前記半導体構成体はベース板上に設けられていることを特徴とするものである。
請求項１１に記載の発明は、請求項１または２に記載の発明において、前記絶縁膜は複数層であり、その層間に、前記半導体構成体の再配線と前記上層再配線とを接続する層間再配線が設けられていることを特徴とするものである。
請求項１２に記載の発明は、請求項１または２に記載の発明において、前記上層再配線を含む前記絶縁膜の上面において前記上層再配線の接続パッド部を除く部分に最上層絶縁膜が設けられていることを特徴とするものである。
請求項１３に記載の発明は、請求項１２に記載の発明において、前記上層再配線の接続パッド部上に突起状の接続端子が設けられていることを特徴とするものである。
請求項１４に記載の発明は、請求項１４に記載の発明において、前記突起状の接続端子は半田ボールであることを特徴とするものである。
請求項１５に記載の発明は、半導体基板上に、それぞれ、パッド部を有する複数の再配線が形成された複数の半導体構成体を相互に離間してベース板上に配置する工程と、前記複数の半導体構成体上を含む前記ベース板の上面全体に絶縁膜を形成する工程と、前記絶縁膜の上面に、接続パッド部を有し且ついずれかの前記半導体構成体の対応する前記パッド部に接続される上層再配線を、少なくともいずれかの前記上層再配線の接続パッド部が前記半導体構成体間に形成された前記絶縁膜上に配置されるように形成する工程と、前記各半導体構成体間における前記絶縁膜を切断して少なくともいずれかの前記上層再配線の接続パッド部が前記半導体構成体より外側の領域の前記絶縁膜上に形成された前記半導体構成体を少なくとも１つ有する半導体装置を複数個得る工程とを有することを特徴とするものである。
請求項１６に記載の発明は、請求項１５に記載の発明において、前記絶縁膜を切断する工程は、前記半導体構成体が複数個含まれるように切断することを特徴とするものである。
請求項１７に記載の発明は、請求項１５に記載の発明において、前記半導体構成体を相互に離間してベース板上に配置する工程は、前記半導体構成体間に埋込材を配置する工程を含むことを特徴とするものである。
請求項１８に記載の発明は、請求項１５に記載の発明において前記複数の再配線は、前記半導体基板上に設けられた保護膜上に形成されていることを特徴とするものである。
請求項１９に記載の発明は、請求項１５に記載の発明において、前記絶縁膜は複数層であり、その層間に、前記各半導体構成体の再配線とそれに対応する前記各組の上層再配線とを接続する複数組の層間再配線を形成する工程を有することを特徴とするものである。
請求項２０に記載の発明は、請求項１５に記載の発明において、前記上層再配線を含む前記絶縁膜の上面において前記上層再配線のパッド部を除く部分に最上層絶縁膜を形成する工程を有することを特徴とするものである。
請求項２１に記載の発明は、請求項２０に記載の発明において、前記上層再配線のパッド部上に突起状の接続端子を形成する工程を有することを特徴とするものである。
請求項２２に記載の発明は、請求項２１に記載の発明において、前記突起状の接続端子は半田ボールであることを特徴とするものである。
請求項２３に記載の発明は、請求項１５に記載の発明において、前記絶縁膜を切断するとともに前記ベース板を切断する工程を有することを特徴とするものである。
請求項２４に記載の発明は、請求項２３に記載の発明において、切断前の前記ベース板下に別のベース板を配置し、前記ベース板を切断した後に、前記別のベース板を取り除く工程を有することを特徴とするものである。
請求項２５に記載の発明は、請求項１５に記載の発明において、　前記半導体構成体を相互に離間してベース板上に配置する工程は、前記半導体構成体間に埋込材を配置する工程を含み、前記各半導体構成体間における前記絶縁膜を切断する工程は、前記埋込材を切断する工程を含むことを特徴とするものである。
請求項２６に記載の発明は、請求項２５に記載の発明において、前記各半導体構成体間における前記絶縁膜を切断する工程は、前記ベース板を切断する工程を含むことを特徴とするものである。
請求項２７に記載の発明は、請求項１５に記載の発明において、前記各半導体構成体間における前記絶縁膜を切断する工程の前に、前記ベース板を取り除く工程を有することを特徴とするものである。
請求項２８に記載の発明は、請求項２６に記載の発明において、前記ベース板を取り除く工程に引き続き、前記半導体基板を薄くする工程を有することを特徴とするものである。
そして、この発明によれば、半導体基板上に再配線を設けてなる複数または複数組の半導体構成体をベース板上に配置し、半導体構成体を含むベース板の上面全体に絶縁膜を形成し、絶縁膜の上面に上層再配線を半導体構成体の再配線に接続させて形成し、絶縁膜を少なくとも切断することにより、半導体構成体を１つまたは１組有し、その周囲に絶縁膜を有するとともに、周囲の絶縁膜上に上層再配線の一部が配置されてなる半導体装置を複数個一括して得ることができ、従来のようなボンディング工程がなく、したがってボンディングによることなく外部接続電極の配置間隔を大きくすることができ、また複数または複数組の半導体構成体に対して絶縁膜および上層再配線の形成を一括して行うことができるので、製造工程を簡略化することができる。
【００１４】
【発明の実施の形態】
（第１実施形態）
図１はこの発明の第１実施形態としての半導体装置の断面図を示したものである。この半導体装置は、シリコン、ガラス、セラミックス、樹脂、金属などからなる平面正方形状のベース板２０を備えている。ベース板２０の上面には、接着剤、粘着シート、両面接着テープなどからなる接着層２１が設けられている。接着層２１の上面中央部には、ベース板２０のサイズよりもやや小さいサイズの平面正方形状の半導体構成体２２の下面が接着されている。
【００１５】
半導体構成体２２は半導体チップ２３を含んでいる。半導体チップ２３は、接着層２１の上面中央部に接着されたシリコン基板２４の上面周辺部にアルミニウムなどからなる複数の接続パッド２５が設けられ、接続パッド２５の中央部を除くシリコン基板２４の上面に酸化シリコンなどからなる絶縁膜２６および感光性ポリイミドなどからなる保護膜２７が設けられ、接続パッド２５の中央部が絶縁膜２６および保護膜２７に形成された開口部２８を介して露出されたものからなっている。
【００１６】
ここで、半導体チップ２３は、通常、ウエハ状態の半導体基板をダイシングして個々の半導体チップとなした場合に得られるものである。しかしながら、この発明では、ウエハ状態の半導体基板上に接続パッド２５、絶縁膜２６および保護膜２７が形成された状態では、ダイシングを行わず、以下に説明するように、再配線を有する半導体構成体２２が得られる状態でウエハ状態の半導体基板をダイシングする。
【００１７】
半導体チップ２３の保護膜２７上には、保護膜２７に形成された開口部２８を介して露出された接続パッド２５の上面から保護膜２７の上面の所定の箇所にかけて下地金属層２９ａが設けられている。下地金属層２９ａの上面には上層金属層２９ｂが設けられ、下地金属層２９ａおよび上層金属層２９ｂにより再配線３０が形成されている。
【００１８】
このように、半導体構成体２２は、接続パッド２５、絶縁膜２６および保護膜２７を有する導体チップ２３を含み、さらに、下地金属層２９ａおよび上層金属層２９ｂからなる封止膜３１を含んで構成されている。図１において、保護膜２７の開口部２８内には下地金属層２９ａのみが形成されているが、これは図示の都合上であって、実際には、上層金属層２９ｂも形成される。
【００１９】
半導体構成体２２の再配線３０を含む保護膜２７の上面および半導体構成体２２の周囲における接着層２１の上面にはエポキシ系樹脂からなる封止膜（絶縁膜）３１が設けられている。封止膜３１の再配線３０のパッド部に対応する部分には開口部３２が設けられている。開口部３２を介して露出された再配線３０のパッド部の上面から封止膜３１の上面の所定の箇所にかけて上層下地金属層３３ａが設けられている。上層下地金属層３３ａの上面全体には上層金属層３９ｂが設けられ、上層下地金属層３３ａおよび上層金属層３９ｂにより再配線３４が形成されている。
【００２０】
上層再配線３４を含む封止膜３１の上面全体にはソルダーレジストなどからなる絶縁膜３５が設けられている。絶縁膜３５の上層再配線３４の接続パッド部３４ａに対応する部分には開口部３６が設けられている。開口部３６内およびその上方には半田ボール（突起状の接続端子）３７が上層再配線３４の接続パッド部３４ａに接続されて設けられている。複数の半田ボール３７は、絶縁膜３５上にマトリクス状に配置されている。
【００２１】
ところで、ベース板２０のサイズを半導体構成体２２のサイズよりもやや大きくしているのは、半導体チップ２３の接続パッド２５の数の増加に応じて、半田ボール３７の配置領域を半導体構成体２２のサイズよりもやや大きくし、これにより、接続パッド３４ａのサイズおよび配置間隔を接続パッド２５のサイズおよび配置間隔よりも大きくするためである。
【００２２】
このため、マトリクス状に配置された上層再配線３４の接続パッド部３４ａは、半導体構成体２２に対応する領域のみでなく、半導体構成体２２の周側面に設けられた絶縁膜３１に対応する領域上にも配置されている。つまり、マトリクス状に配置された半田ボール４７のうち、少なくとも最外周の半田ボール４７は半導体構成体２２よりも外側に位置する周囲に配置されている。
【００２３】
次に、この半導体装置の製造方法の一例について説明するに、まず、半導体構成体２２の製造方法の一例について説明する。まず、図２に示すように、ウエハ状態のシリコン基板（半導体基板）２４上にアルミニウムからなる接続パッド２５、酸化シリコンからなる絶縁膜２６および感光性ポリイミドからなる保護膜２７が設けられ、接続パッド２５の中央部が絶縁膜２６および保護膜２７に形成された開口部２８を介して露出されたものを用意する。
【００２４】
次に、図３に示すように、開口部２８を介して露出された接続パッド２５の上面を含む保護膜２７の上面全体に下地金属層２９ａを形成する。この場合、下地金属層２９ａは、無電解メッキにより形成された銅層のみからなっているが、スパッタにより形成された銅層のみであってもよく、またスパッタにより形成されたチタンなどの薄膜層上にスパッタにより銅層を形成したものであってもよい。これは、後述する上層下地金属層３３ａの場合も同様である。
【００２５】
次に、下地金属層２９のａ上面にメッキレジスト膜４１をパターン形成する。この場合、再配線３０形成領域に対応する部分におけるメッキレジスト膜４１には開口部４２が形成されている。次に、下地金属層２９ａをメッキ電流路として銅の電解メッキを行うことにより、メッキレジスト膜４１の開口部４２内の下地金属層２９ａの上面に上層金属層２９ｂを形成する。
【００２６】
次に、メッキレジスト膜４１を剥離し、次いで、上層金属層２９ｂをマスクとして下地金属層２９ａの不要な部分をエッチングして除去すると、図４に示すように、上層金属層２９ｂ下にのみ下地金属層２９ａが残存され再配線３０が形成される。次に、図５に示すように、ダンシング工程を経ると、半導体チップ２３上に再配線３０を設けてなる半導体構成体２２が複数個得られる。
【００２７】
次に、このようにして得られた半導体構成体２２を用いて、図１に示す半導体装置を製造する場合の一例について説明する。まず、図６に示すように、図１に示すベース板２０を複数枚採取することができるベース板２０の上面全体に接着層２１が設けられたものを用意する。そして、接着層２１の上面の所定の複数箇所にそれぞれ半導体構成体２２のシリコン基板２４の下面を接着する。
【００２８】
次に、図７に示すように、複数の半導体構成体２２を含む接着層２１の上面全体にエポキシ系樹脂からなる封止膜３１を印刷法やモールド法などによりその厚さが半導体構成体２２の高さよりもやや厚くなるように形成する。したがって、この状態では、半導体構成体２２の上面は封止膜３１によって覆われている。次に、必要に応じて、封止膜３１の上面側を適宜に研磨して、封止膜３１の上面を平滑化する。次に、封止膜３１の再配線３０のパッド部に対応する部分に、フォトリソグラフィあるいはＣＯ２レーザの照射により、開口部３２を形成する。
【００２９】
次に、図８に示すように、開口部３２を介して露出された再配線３０のパッド部を含む封止膜３１の上面全体に銅の無電解メッキにより上層下地金属層３３ａを形成する。次に、上層下地金属層３３ａの上面にメッキレジスト膜４３をパターン形成する。この場合、上層再配線３４形成領域に対応する部分におけるメッキレジスト膜４３には開口部４４が形成されている。次に、上層下地金属層３３ａをメッキ電流路として銅の電解メッキを行うことにより、メッキレジスト膜４３の開口部４４内の上層下地金属層３３ａの上面に上層金属層３３ｂを形成する。
【００３０】
次に、メッキレジスト膜４３を剥離し、次いで、上層金属層３３ｂをマスクとして上層下地金属層３３ａの不要な部分をエッチングして除去すると、図９に示すように、上層金属層３３ｂ下にのみ上層下地金属層３３ａが残存された上層再配線３４が形成される。
【００３１】
次に、図１０に示すように、上層再配線３４を含む封止膜３１の上面全体にソルダーレジストからなる絶縁膜３５をパターン形成する。この場合、絶縁膜３５の上層再配線３４の接続パッド部３４ａに対応する部分には開口部３６が形成されている。次に、開口部３６内およびその上方に半田ボール３７を上層再配線３４の接続パッド部３４ａに接続させて形成する。
【００３２】
次に、図１１に示すように、互いに隣接する半導体構成体２２間において、絶縁膜３５、封止膜３１、接着層２１およびベース板２０を切断すると、図１に示す半導体装置が複数個得られる。
【００３３】
このようにして得られた半導体装置では、半導体構成体２２の再配線３０に接続される上層下地金属層３３ａおよび上層金属層３３ｂを無電解メッキ（またはスパッタ）および電解メッキにより形成しているので、ボンディングによらないで、半導体構成体２２の再配線３０と上層再配線３４との間を導電接続することができる。
【００３４】
このように、上層再配線３４が半導体構成体２２の再配線３０のパッド部にメッキにより直接接合されるものであるため、上層絶縁膜３１の開口部３２は、１０μｍ×１０μｍの方形または同面積の円形の面積を有していれば強度的に十分である。
【００３５】
これに対し、図２６に示す従来の半導体チップでは、バンプ電極３の直径は１００〜１５０μｍ程度（ピッチは、通常、この２倍）であるので、従来の、バンプ電極と再配線とをボンディングにより接合する方法と比較すると、接続パッド部３４ａのサイズおよび配置間隔が遙かにすることができ、且つ、プロセスも効率的である。
【００３６】
このように、接続パッド部３４ａのサイズおよび配置間隔を小さいものとすることができるので、上層の再配線を有する本発明の半導体装置のサイズを小さいものとすることができる。
【００３７】
また、上記製造方法では、ベース板２０上の接着層２１上の所定の複数箇所にそれぞれ半導体構成体２２を接着して配置し、複数の半導体構成体２２に対して封止膜３１、上層下地金属層３３、上層再配線３４、絶縁膜３５および半田ボール３７の形成を一括して行い、その後に分断して複数個の半導体装置を得ているので、製造工程を簡略化することができる。
【００３８】
また、ベース板２０と共に複数の半導体構成体２２を搬送することができるので、これによっても製造工程を簡略化することができる。さらに、ベース板２０の外形寸法を一定にすると、製造すべき半導体装置の外形寸法に関係なく、搬送系を共有化することができる。
【００３９】
さらに、図１に示す半導体装置では、シリコン基板２４上に感光性ポリイミドなどからなる保護膜２７、エポキシ系樹脂などからなる封止膜３１および感光性ポリイミドなどからなる絶縁膜３５を積層しているので、この３層の樹脂層により、この半導体装置を半田ボール３７を介して回路基板（図示せず）上に搭載した後において、シリコン基板２４と回路基板との熱膨張係数差に起因する応力をある程度緩和することができる。
【００４０】
次に、図１に示す半導体装置の製造方法の他の例について説明する。まず、図１２に示すように、紫外線透過性の透明樹脂板やガラス板などからなる別のベース板５１の上面全体に紫外線硬化型の粘着シートなどからなる接着層５２を接着し、接着層５２の上面に上述のベース板２０および接着層２１を接着したものを用意する。
【００４１】
そして、図６〜図１０にそれぞれ示す製造工程を経た後に、図１３に示すように、絶縁膜３５、封止膜３１、接着層２１、ベース板２０および接着層５２を切断し、別のベース板５１を切断しない。次に、別のベース板５１の下面側から紫外線を照射し、接着層５２を硬化させる。すると、分断されたベース板２０の下面に対する接着層５２による接着性が低下する。そこで、接着層５２上に存在する個片化されたものを１つずつ剥がしてピックアップすると、図１に示す半導体装置が複数個得られる。
【００４２】
この製造方法では、図１３に示す状態において、接着層５２上に存在する個片化された半導体装置がバラバラとならないので、専用の半導体装置載置用トレーを用いることなく、そのまま、図示しない回路基板上への実装時に１つずつ剥がしてピックアップすることができる。また、別のベース板５１の上面に残存する接着性が低下した接着層５２を剥離すると、別のベース板５１を再利用することができる。さらに、別のベース板５１の外形寸法を一定にすると、製造すべき半導体装置の外形寸法に関係なく、搬送系を共有化することができる。
【００４３】
なお、別のベース板５５として、膨張させることにより半導体装置を取り外す、通常のダイシングテープなどを用いることも可能であり、その場合には、接着層は紫外線硬化型でなくてもよい。また、別のベース板５５を研磨やエッチングにより除去するようにしてもよい。
【００４４】
次に、図１に示す半導体装置の製造方法のさらに他の例について説明する。この製造方法では、図７に示す製造工程後に、図１４に示すように、開口部３２を介して露出された再配線３０の上面を含む封止膜３１の上面全体に銅の無電解メッキにより上層下地金属層３３ａを形成する。次に、上層下地金属層３３ａをメッキ電流路として銅の電解メッキを行うことにより、上層下地金属層３３の上面全体に上層金属層３３ｃを形成する。次に、上層金属層層３３ｃの上面の上層再配線形成領域に対応する部分にレジスト膜５３をパターン形成する。
【００４５】
次に、レジスト膜５３をマスクとして上層金属層３３ｃおよび上層下地金属層３３ａの不要な部分をエッチングして除去すると、図１５に示すように、レジスト膜５３下にのみ上層金属層３３ｃおよび上層下地金属層３３ａが残存され、上層再配線３４が形成される。この後、レジスト膜５３を剥離する。なお、これと同様の形成方法により、半導体構成体２２の上層金属層２９ｂおよび下地金属層２９ａを形成するようにしてもよい。
【００４６】
（第２実施形態）
図６に示す製造工程において、接着層２１を半導体構成体２２のシリコン基板２４の下面に設け、この接着層２１をベース板２０の上面の各所定の箇所に接着した場合には、図１６に示すこの発明の第２実施形態としての半導体装置が得られる。
【００４７】
このようにして得られた半導体装置では、シリコン基板２４の下面が接着層２１を介してベース板２０の上面に接着されているほかに、シリコン基板２４の側面などが封止膜３６を介してベース板２０の上面に接続されているので、半導体構成体２２のベース板２０に対する接合強度をある程度強くすることができる。
【００４８】
（第３、第４実施形態）
図１７はこの発明の第３実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図１に示す半導体装置と異なる点は、ベース板２０および接着層２１を備えていないことである。
【００４９】
この第３実施形態の半導体装置を製造する場合には、例えば図１０に示すように、半田ボール３７を形成した後に、ベース板２０を接着層２１から剥がしたりまたはベース板２０および接着層２１を研磨やエッチングなどにより除去するなどして取り除いた後に、互いに隣接する半導体構成体２２間において、絶縁膜３５および封止膜３１を切断すると、図１７に示す半導体装置が複数個得られる。このようにして得られた半導体装置では、ベース板２０および接着層２１を備えていないので、その分だけ、薄型化することができる。
【００５０】
また、ベース板２０および接着層２１を取り除いた後に、シリコン基板２４および封止膜３１の下面側を適宜に研磨し、次いで互いに隣接する半導体構成体２２間において、絶縁膜３５および封止膜３１を切断すると、図１８に示すこの発明の第４実施形態としての半導体装置が複数個得られる。このようにして得られた半導体装置では、さらに薄型化することができる。
【００５１】
なお、半田ボール３７を形成する前に、ベース板２０および接着層２１を研磨やエッチングなどにより除去し（必要に応じてさらにシリコン基板２４および封止膜３１の下面側を適宜に研磨し）、次いで半田ボール３７を形成し、次いで互いに隣接する半導体構成体２２間において、絶縁膜３５および封止膜３１を切断するようにしてもよい。
【００５２】
（第５実施形態）
図１９はこの発明の第５実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図１に示す半導体装置と異なる点は、接着層２１の下面に放熱用の金属層６１が接着されていることである。金属層６１は、厚さ数十μｍの銅箔などからなっている。
【００５３】
この第５実施形態の半導体装置を製造する場合には、例えば図１０に示すように、半田ボール３７を形成した後に、ベース板２０を研磨やエッチングなどにより除去し、次いで接着層２１の下面全体に金属層６１を接着し、次いで互いに隣接する半導体構成体２２間において、絶縁膜３５、封止膜３１、接着層２１および金属層６１を切断すると、図１８に示す半導体装置が複数個得られる。
【００５４】
なお、接着層２１も研磨やエッチングなどにより除去し（必要に応じてさらにシリコン基板２４および封止膜３１の下面側を適宜に研磨し）、シリコン基板２４および封止膜３１の下面に新たな接着層を介して金属層６１を接着するようにしてもよい。
【００５５】
（第６実施形態）
図１１に示す場合には、互いに隣接する半導体構成体２２間において切断したが、これに限らず、２個またはそれ以上の半導体構成体２２を１組として切断し、例えば、図２０に示すこの発明の第６実施形態のように、３個の半導体構成体２２を１組として切断し、マルチチップモジュール型の半導体装置を得るようにしてもよい。この場合、３個で１組の半導体構成体２２は同種、異種のいずれであってもよい。
【００５６】
（第７実施形態）
図２１はこの発明の第７実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図１に示す半導体装置と異なる点は、半導体構成体２２は、再配線３０を含む保護膜２７の上面に感光性ポリイミドなどからなる上層保護膜６２が設けられ、上層保護膜６２の再配線３０のパッド部に対応する部分に開口部６３が設けられたものからなっていることである。
【００５７】
この第７実施形態の半導体装置を製造する場合には、図４に示す製造工程後に、図２２に示すように、再配線３０を含む保護膜２７の上面に感光性ポリイミドなどからなる上層保護膜６２を形成し、上層保護膜６２の再配線３０のパッド部に対応する部分に開口部６３を形成し、以下、図５〜図１１に示す場合と同様の製造工程を経ると、図２１に示す半導体装置が複数個得られる。
【００５８】
このようにして得られた半導体装置では、シリコン基板２４上に感光性ポリイミドなどからなる保護膜２７、感光性ポリイミドなどからなる上層保護膜６２、エポキシ系樹脂などからなる封止膜３１および感光性ポリイミドなどからなる絶縁膜３５を積層しているので、この４層の樹脂層により、この半導体装置を半田ボール３７を介して回路基板（図示せず）上に搭載した後において、シリコン基板２４と回路基板との熱膨張係数差に起因する応力をより一層緩和することができる。なお、封止膜３１の上面が上層保護膜６２の上面と面一となるようにしてもよい。
【００５９】
（第８実施形態）
図２３はこの発明の第８実施形態としての半導体装置の断面図を示したものである。この半導体装置において、図１に示す半導体装置と異なる点は、半導体構成体２２の周囲における接着層２１の上面に方形枠状の埋込材７１が設けられていることである。
【００６０】
この場合、埋込材７１の厚さは、シリコン基板２４の厚さと同じであってもよく、さらに絶縁膜２５の厚さを加えた厚さと同じであってもよく、さらに保護膜２６の厚さを加えた厚さと同じであってもよく、さらに再配線３０の厚さを加えた厚さと同じであってもよい。したがって、埋込材７１の上面は封止膜３１によって覆われている。また、半導体構成体２２と埋込材７１との間には封止膜３１が充填されている。
【００６１】
この第８実施形態の半導体装置を製造する場合には、図６に示す製造工程おいて、図２４に示すように、接着層２１の上面の所定の複数箇所にそれぞれ半導体構成体２２のシリコン基板２４の下面を接着するとともに、互いに隣接する半導体構成体２２間における接着層２１の上面に格子状の埋込材７１の下面を接着する。
【００６２】
埋込材７１の材料は、ベース板２０と同じであってもよく、また別であってもよい。また、ベース板２０および埋込材７１の材料が熱可塑性樹脂である場合、接着層２１を用いずに、両者を熱圧着し、次いで半導体構成体２２のシリコン基板２４の下面に設けられた接着層２１（図１６参照）をベース板２０の上面に接着するようにしてもよい。また、シート状の埋込材７１を接着層２１の上面全体に接着し（またはベース板２０上に熱圧着し）、座ぐり加工により、格子状の埋込材７１を形成するようにしてもよい。
【００６３】
次に、図２５に示すように、複数の半導体構成体２２および格子状の埋込材７１を含む接着層２１の上面全体にエポキシ系樹脂などからなる封止膜３１を印刷法やモールド法などにより、その厚さが半導体構成体２２の高さよりもやや厚くなるように形成する。次に、必要に応じて、封止膜３１の上面側を適宜に研磨して、封止膜３１の上面を平滑化する。次に、封止膜３１の再配線３０のパッド部に対応する部分に、フォトリソグラフィあるいはＣＯ２レーザの照射により、開口部３２を形成する。以下、図８〜図１１に示す場合と同様の製造工程を経ると、図２３に示す半導体装置が複数個得られる。
【００６４】
このようにして得られた半導体装置では、図２５に示すように、互いに隣接する半導体構成体２２間における封止膜３１の量を埋込材７１の体積の分だけ少なくすることができる。この結果、エポキシ系樹脂などからなる封止膜３１の硬化時の収縮による応力を小さくすることができる。
【００６５】
（その他の実施形態）
ところで、上記各実施形態では、封止膜３１上に設けた絶縁膜３５上に上層再配線３４を設けた場合について説明したが、これに限らず、封止膜３１上に設ける絶縁膜を複数層とし、その層間に、半導体構成体２２の再配線３０と上層再配線３４とを接続する層間再配線を設けるようにしてもよい。
【００６６】
【発明の効果】
以上説明したように、この発明によれば、半導体基板上に再配線を設けてなる複数または複数組の半導体構成体をベース板上に配置し、半導体構成体を含むベース板の上面全体に絶縁膜を形成し、絶縁膜の上面に上層再配線を半導体構成体の再配線に接続させて形成し、絶縁膜を少なくとも切断することにより、半導体構成体を１つまたは１組有し、その周囲に絶縁膜を有するとともに、周囲の絶縁膜上に上層再配線の一部が配置されてなる半導体装置を複数個一括して得ることができ、従来のようなボンディング工程がなく、したがってボンディングによることなく外部接続電極の配置間隔を大きくすることができ、また複数または複数組の半導体構成体に対して絶縁膜および上層再配線の形成を一括して行うことができるので、製造工程を簡略化することができる。
【図面の簡単な説明】
【図１】この発明の第１実施形態としての半導体装置の断面図。
【図２】図１に示す半導体装置の製造方法の一例において、当初用意したものの断面図。
【図３】図２に続く製造工程の断面図。
【図４】図３に続く製造工程の断面図。
【図５】図４に続く製造工程の断面図。
【図６】図５に続く製造工程の断面図。
【図７】図６に続く製造工程の断面図。
【図８】図７に続く製造工程の断面図。
【図９】図８に続く製造工程の断面図。
【図１０】図９に続く製造工程の断面図。
【図１１】図１０に続く製造工程の断面図。
【図１２】図１に示す半導体装置の製造方法の他の例において、当初用意したものの断面図。
【図１３】同他の例において、所定の製造工程の断面図。
【図１４】図１に示す半導体装置の製造方法のさらに他の例において、所定の製造工程の断面図。
【図１５】図１４に続く製造工程の断面図。
【図１６】この発明の第２実施形態としての半導体装置の断面図。
【図１７】この発明の第３実施形態としての半導体装置の断面図。
【図１８】この発明の第４実施形態としての半導体装置の断面図。
【図１９】この発明の第５実施形態としての半導体装置の断面図。
【図２０】この発明の第６実施形態としての半導体装置の断面図。
【図２１】この発明の第７実施形態としての半導体装置の断面図。
【図２２】図２１に示す半導体装置の製造方法の一例において、所定の製造工程の断面図。
【図２３】この発明の第８実施形態としての半導体装置の断面図。
【図２４】図２３に示す半導体装置の製造方法の一例において、所定の製造工程の断面図。
【図２５】図２４に続く製造工程の断面図。
【図２６】従来の半導体装置の一例の断面図。
【符号の説明】
２０　ベース板
２１　接着層
２２　半導体構成体
２３　半導体チップ
２４　シリコン基板
２５　接続パッド
２９　下地金属層
３０　再配線
３１　封止膜
３３　上層下地金属層
３４　上層再配線
３５　絶縁膜
３７　半田ボール[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method for manufacturing the same.
[0002]
[Prior art]
For example, in a semiconductor device called a BGA (ball grid array), a semiconductor chip composed of an LSI or the like is mounted on the center of the upper surface of a relay substrate (interposer) slightly larger than the size of the semiconductor chip, and is mounted on the lower surface of the relay substrate. There is one in which connection terminals using solder balls are arranged in a matrix.
[0003]
FIG. 26 is a sectional view showing an example of such a conventional semiconductor device. The semiconductor chip 1 has a structure in which a plurality of bump electrodes 3 made of copper or the like are provided on a peripheral portion of a silicon substrate 2.
[0004]
The relay substrate 4 includes a base film 5 whose size is slightly larger than the size of the silicon substrate 2 of the semiconductor chip 1. On the upper surface of the base film 5, a rewiring 6 connected to the bump electrode 3 of the semiconductor chip 1 is provided.
[0005]
The rewiring 6 includes a first connection pad 7 provided corresponding to the bump electrode 3 of the semiconductor chip 1, a second connection pad 8 provided in a matrix, and first and second connection pads 7. , 8 are connected. A circular hole 10 is provided in the base film 5 at a portion corresponding to the center of the second connection pad 8.
[0006]
The semiconductor chip 1 is mounted on the center of the upper surface of the relay board 4 via the anisotropic conductive adhesive 11. The anisotropic conductive adhesive 11 is made of a thermosetting resin 12 containing a large number of conductive particles 13.
[0007]
When the semiconductor chip 1 is mounted on the relay substrate 4, first, the semiconductor chip 1 is positioned at the center of the upper surface of the relay substrate 4 via the sheet-like anisotropic conductive adhesive 11 and simply placed. I do.
[0008]
Next, bonding is performed by applying a predetermined pressure at a temperature at which the thermosetting resin 12 is cured. Then, the bump electrode 3 pushes away the thermosetting resin 12 and is conductively connected to the upper surface of the first connection pad 7 through the conductive particles 13, and the lower surface of the semiconductor chip 1 is thermoset to the upper surface of the relay substrate 4. It is bonded via the conductive resin 12.
[0009]
Next, a sealing film 14 made of an epoxy resin is formed on the entire upper surface of the relay substrate 4 including the semiconductor chip 1. Next, a solder ball 15 is formed in and below the circular hole 10 so as to be connected to the second connection pad 8. In this case, since the second connection pads 8 are arranged in a matrix, the solder balls 15 are also arranged in a matrix.
[0010]
Here, the size of the solder balls 15 is larger than the size of the bump electrodes 3 of the semiconductor chip 1, and the interval between the solder balls 15 needs to be larger than the interval between the bump electrodes 3 to avoid contact between the solder balls 15. . Therefore, when the number of the bump electrodes 3 of the semiconductor chip 1 increases, it is necessary to make the arrangement area larger than the size of the semiconductor chip 1 in order to obtain a necessary arrangement interval between the solder balls 15. The size of the substrate 4 is slightly larger than the size of the semiconductor chip 1. Therefore, among the solder balls 15 arranged in a matrix, the peripheral solder balls 15 are arranged around the semiconductor chip 1.
[0011]
[Problems to be solved by the invention]
By the way, in the above-described conventional semiconductor device, the lower surface of the bump electrode 3 of the semiconductor chip 1 is bonded to the first surface of the rewiring 6 of the relay substrate 4 by bonding after alignment using the relay substrate 4 on which the rewiring 6 is formed. Is electrically conductively connected to the upper surface of the connection pad 7, the number of bump electrodes 3 of the semiconductor chip 1 increases, and if the size and arrangement interval of the bump electrodes 3 are reduced, the alignment is extremely difficult. there were. In this case, if the size of the semiconductor chip 1 is increased, it is natural that the size and the arrangement interval of the bump electrodes 3 can be increased. However, in this case, the number of semiconductor chips to be removed from the wafer state is drastically reduced. Would be extremely expensive. In addition, the semiconductor chips 1 must be bonded and mounted one by one on the relay substrate 4, and there is a problem that the manufacturing process is complicated. The same applies to a multi-chip module type semiconductor device including a plurality of semiconductor chips.
[0012]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device and a method of manufacturing the semiconductor device, which can increase the interval between external connection electrodes without using bonding.
Another object of the present invention is to provide a method of manufacturing a semiconductor device, which can manufacture a plurality of semiconductor devices collectively.
[0013]
[Means for Solving the Problems]
The invention according to claim 1, wherein the semiconductor structure includes a plurality of rewirings each having a pad portion on a semiconductor substrate, and the semiconductor structure including the rewiring except for the pad portions. An insulating film provided on the entire upper surface of the semiconductor device and an extension portion outside the peripheral side surface of the semiconductor structure; and at least a connection pad portion provided on the insulating film so as to be connected to the pad portion of the rewiring. One upper layer redistribution, wherein at least a part of the uppermost layer upper redistribution is such that the connection pad portion extends from the insulating film outside the peripheral side surface of the semiconductor structure. It is characterized by being arranged on a part.
According to a second aspect of the present invention, there is provided a semiconductor device, comprising: a semiconductor substrate; and a plurality of semiconductor structures provided on an upper surface of the semiconductor substrate and having a plurality of rewirings each having a pad portion, which are arranged apart from each other. An insulating film provided on the entire upper surface including the rewiring except for the pad portion of each of the semiconductor structures and an extension portion outside the peripheral side surface of each of the semiconductor structures; and the pad on the insulating film. At least one layer of upper-layer rewiring connected to the portion and having a connection pad portion, wherein at least part of the upper-layer upper-layer rewiring in the upper-layer rewiring is such that the connection pad portion is one of the above-described ones. The semiconductor component is disposed on the extension portion outside the peripheral side surface.
According to a third aspect of the present invention, in the first or second aspect of the invention, the insulating film is provided so as to cover a peripheral side surface of the semiconductor structure.
According to a fourth aspect of the present invention, in the first or second aspect of the invention, the plurality of rewirings are formed on a protective film provided on the semiconductor substrate. is there.
According to a fifth aspect of the present invention, in the invention of the fourth aspect, a lower surface of the insulating film covering a peripheral side surface of the semiconductor structure is disposed on substantially the same plane as a lower surface of the semiconductor structure. It is characterized by the following.
According to a sixth aspect of the present invention, in the fourth aspect of the present invention, a heat dissipation layer is provided on a lower surface of the semiconductor structure and the insulating film around the semiconductor structure.
According to a seventh aspect of the present invention, in the first or second aspect, an embedding material is disposed below the extension of the insulating film. According to an eighth aspect of the present invention, in the seventh aspect of the invention, the embedding material has substantially the same thickness as the semiconductor substrate.
According to a ninth aspect of the present invention, in the eighth aspect of the present invention, an insulating film is filled between the burying material and the semiconductor structure.
According to a tenth aspect of the present invention, in the first or second aspect, the semiconductor structure is provided on a base plate.
According to an eleventh aspect of the present invention, in the first or second aspect of the present invention, the insulating film has a plurality of layers, and an interlayer connecting the rewiring of the semiconductor structure and the upper rewiring between the layers. A rewiring is provided.
According to a twelfth aspect of the present invention, in the first or second aspect of the present invention, an uppermost insulating film is provided on a portion of the upper surface of the insulating film including the upper redistribution wiring except a connection pad portion of the upper redistribution wiring. It is characterized by being carried out.
According to a thirteenth aspect, in the twelfth aspect, a protruding connection terminal is provided on the connection pad portion of the upper layer rewiring.
According to a fourteenth aspect, in the fourteenth aspect, the projecting connection terminal is a solder ball.
The invention according to claim 15, wherein a plurality of semiconductor components on which a plurality of rewirings each having a pad portion are formed on a semiconductor substrate are arranged on a base plate at a distance from each other; Forming an insulating film over the entire upper surface of the base plate including the semiconductor structure, and connecting a pad portion on the upper surface of the insulating film and forming a connection pad portion on the corresponding pad portion of any of the semiconductor structures. Forming an upper-layer rewiring to be connected such that at least one of the connection pad portions of the upper-layer rewiring is disposed on the insulating film formed between the semiconductor structures; and At least one of the semiconductor components formed on the insulating film in a region outside the semiconductor component by cutting at least one of the upper layer rewirings by cutting the insulating film between them It is characterized in that a step of obtaining a plurality of conductor device.
According to a sixteenth aspect of the present invention, in the invention according to the fifteenth aspect, in the step of cutting the insulating film, the semiconductor structure is cut so as to include a plurality of the semiconductor structures.
According to a seventeenth aspect of the present invention, in the invention according to the fifteenth aspect, the step of arranging the semiconductor components on the base plate so as to be separated from each other includes the step of arranging an embedding material between the semiconductor components. It is characterized by including.
According to an eighteenth aspect of the present invention, in the semiconductor device according to the fifteenth aspect, the plurality of rewirings are formed on a protective film provided on the semiconductor substrate.
The invention according to claim 19 is the invention according to claim 15, wherein the insulating film has a plurality of layers, and between the layers, the rewiring of each of the semiconductor structures and the upper rewiring of each of the sets corresponding thereto. And a step of forming a plurality of sets of interlayer rewirings for connecting
According to a twentieth aspect of the present invention, in the invention according to the fifteenth aspect, a step of forming an uppermost insulating film on a portion of the upper surface of the insulating film including the upper layer redistribution except for a pad portion of the upper layer redistribution is performed. It is characterized by having.
According to a twenty-first aspect, in the twenty-second aspect, a step of forming a projecting connection terminal on a pad portion of the upper layer rewiring is provided.
According to a twenty-second aspect, in the twenty-first aspect, the projecting connection terminal is a solder ball.
According to a twenty-third aspect of the present invention, the method according to the fifteenth aspect, further comprising the step of cutting the insulating film and cutting the base plate.
According to a twenty-fourth aspect of the present invention, in the invention of the twenty-third aspect, a step of disposing another base plate below the base plate before cutting, and removing the another base plate after cutting the base plate. Which is characterized by having
According to a twenty-fifth aspect of the present invention, in the invention according to the fifteenth aspect, the step of arranging the semiconductor components on a base plate while separating from each other is a step of arranging an embedding material between the semiconductor components. Wherein the step of cutting the insulating film between the semiconductor structures includes the step of cutting the burying material.
The invention according to claim 26 is the invention according to claim 25, wherein the step of cutting the insulating film between the respective semiconductor structures includes a step of cutting the base plate. is there.
According to a twenty-seventh aspect of the present invention, in the invention of the fifteenth aspect, a step of removing the base plate is provided before the step of cutting the insulating film between the semiconductor structures. It is.
The invention according to claim 28 is the invention according to claim 26, characterized by further comprising a step of thinning the semiconductor substrate, following the step of removing the base plate.
According to the present invention, a plurality of or a plurality of sets of semiconductor components provided with rewiring on a semiconductor substrate are arranged on a base plate, and an insulating film is formed on the entire upper surface of the base plate including the semiconductor components. Forming an upper layer rewiring on the upper surface of the insulating film by connecting to the rewiring of the semiconductor structure, and cutting at least the insulating film to have one or a set of the semiconductor structure and surrounding the insulating film with the insulating film. And a plurality of semiconductor devices in which a part of the upper layer rewiring is arranged on the surrounding insulating film can be obtained in a lump. Can be increased, and an insulating film and an upper layer rewiring can be formed collectively on a plurality or a plurality of sets of semiconductor structures, thereby simplifying a manufacturing process. Door can be.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention. The semiconductor device includes a square base plate 20 made of silicon, glass, ceramics, resin, metal, or the like. An adhesive layer 21 made of an adhesive, a pressure-sensitive adhesive sheet, a double-sided adhesive tape, or the like is provided on an upper surface of the base plate 20. At the center of the upper surface of the adhesive layer 21, the lower surface of a planar square semiconductor component 22 slightly smaller than the size of the base plate 20 is bonded.
[0015]
The semiconductor component 22 includes a semiconductor chip 23. In the semiconductor chip 23, a plurality of connection pads 25 made of aluminum or the like are provided around the upper surface of the silicon substrate 24 bonded to the center of the upper surface of the adhesive layer 21, and the upper surface of the silicon substrate 24 excluding the center of the connection pad 25 is provided. Is provided with an insulating film 26 made of silicon oxide or the like and a protective film 27 made of photosensitive polyimide or the like, and a central portion of the connection pad 25 is exposed through an opening 28 formed in the insulating film 26 and the protective film 27. Is made of things.
[0016]
Here, the semiconductor chip 23 is usually obtained when a semiconductor substrate in a wafer state is diced into individual semiconductor chips. However, according to the present invention, in a state where the connection pads 25, the insulating film 26, and the protective film 27 are formed on the semiconductor substrate in a wafer state, dicing is not performed, and as described below, The semiconductor substrate in a wafer state is diced in a state where 22 is obtained.
[0017]
On the protective film 27 of the semiconductor chip 23, a base metal layer 29a is provided from the upper surface of the connection pad 25 exposed through the opening 28 formed in the protective film 27 to a predetermined portion of the upper surface of the protective film 27. ing. An upper metal layer 29b is provided on the upper surface of the base metal layer 29a, and the rewiring 30 is formed by the base metal layer 29a and the upper metal layer 29b.
[0018]
As described above, the semiconductor structure 22 includes the conductor chip 23 having the connection pad 25, the insulating film 26, and the protective film 27, and further includes the sealing film 31 including the base metal layer 29a and the upper metal layer 29b. Have been. In FIG. 1, only the base metal layer 29a is formed in the opening 28 of the protective film 27, but this is for convenience of illustration, and the upper metal layer 29b is actually formed.
[0019]
A sealing film (insulating film) 31 made of an epoxy resin is provided on the upper surface of the protective film 27 including the rewiring 30 of the semiconductor structure 22 and the upper surface of the adhesive layer 21 around the semiconductor structure 22. An opening 32 is provided in a portion of the sealing film 31 corresponding to the pad portion of the rewiring 30. An upper base metal layer 33a is provided from the upper surface of the pad portion of the rewiring 30 exposed through the opening 32 to a predetermined location on the upper surface of the sealing film 31. An upper metal layer 39b is provided on the entire upper surface of the upper base metal layer 33a, and a redistribution line 34 is formed by the upper base metal layer 33a and the upper metal layer 39b.
[0020]
An insulating film 35 made of a solder resist or the like is provided on the entire upper surface of the sealing film 31 including the upper layer rewiring 34. An opening 36 is provided in a portion corresponding to the connection pad portion 34a of the upper layer rewiring 34 of the insulating film 35. Inside and above the opening 36, a solder ball (projection-like connection terminal) 37 is provided so as to be connected to the connection pad 34a of the upper layer rewiring 34. The plurality of solder balls 37 are arranged on the insulating film 35 in a matrix.
[0021]
By the way, the reason why the size of the base plate 20 is made slightly larger than the size of the semiconductor component 22 is that the arrangement area of the solder balls 37 is changed according to the increase in the number of connection pads 25 of the semiconductor chip 23. This is because the size and the arrangement interval of the connection pads 34a are made larger than the size and the arrangement interval of the connection pads 25.
[0022]
For this reason, the connection pad portions 34 a of the upper layer rewirings 34 arranged in a matrix form not only the region corresponding to the semiconductor structure 22 but also the region corresponding to the insulating film 31 provided on the peripheral side surface of the semiconductor structure 22. It is also located above. That is, of the solder balls 47 arranged in a matrix, at least the outermost solder balls 47 are arranged around the outside of the semiconductor structure 22.
[0023]
Next, an example of a method of manufacturing the semiconductor device will be described. First, an example of a method of manufacturing the semiconductor structure 22 will be described. First, as shown in FIG. 2, a connection pad 25 made of aluminum, an insulating film 26 made of silicon oxide, and a protective film 27 made of photosensitive polyimide are provided on a silicon substrate (semiconductor substrate) 24 in a wafer state. 25 is prepared by exposing a central portion of the insulating film 25 through an opening 28 formed in the insulating film 26 and the protective film 27.
[0024]
Next, as shown in FIG. 3, a base metal layer 29a is formed on the entire upper surface of the protective film 27 including the upper surface of the connection pad 25 exposed through the opening 28. In this case, the base metal layer 29a consists of only a copper layer formed by electroless plating, but may be a copper layer formed only by sputtering, or a thin film layer of titanium or the like formed by sputtering. A copper layer may be formed thereon by sputtering. This is the same in the case of an upper base metal layer 33a to be described later.
[0025]
Next, a plating resist film 41 is pattern-formed on the upper surface a of the base metal layer 29. In this case, an opening 42 is formed in the plating resist film 41 in a portion corresponding to the region where the rewiring 30 is formed. Next, an upper metal layer 29b is formed on the upper surface of the base metal layer 29a in the opening 42 of the plating resist film 41 by performing copper electrolytic plating using the base metal layer 29a as a plating current path.
[0026]
Next, the plating resist film 41 is peeled off, and then unnecessary portions of the base metal layer 29a are removed by etching using the upper metal layer 29b as a mask. As shown in FIG. The metal layer 29a remains, and the rewiring 30 is formed. Next, as shown in FIG. 5, through a dancing step, a plurality of semiconductor components 22 each having the rewiring 30 provided on the semiconductor chip 23 are obtained.
[0027]
Next, an example of manufacturing the semiconductor device shown in FIG. 1 using the semiconductor component 22 obtained in this manner will be described. First, as shown in FIG. 6, a base plate 20 from which a plurality of base plates 20 shown in FIG. 1 can be obtained is provided with an adhesive layer 21 provided on the entire upper surface thereof. Then, the lower surface of the silicon substrate 24 of the semiconductor structure 22 is bonded to a plurality of predetermined locations on the upper surface of the adhesive layer 21.
[0028]
Next, as shown in FIG. 7, a sealing film 31 made of an epoxy resin is formed on the entire upper surface of the adhesive layer 21 including the plurality of semiconductor structures 22 by a printing method, a molding method, or the like so that the thickness of the semiconductor film 22 is reduced. It is formed so as to be slightly thicker than the height. Therefore, in this state, the upper surface of the semiconductor structure 22 is covered with the sealing film 31. Next, if necessary, the upper surface of the sealing film 31 is appropriately polished to smooth the upper surface of the sealing film 31. Next, an opening 32 is formed in a portion of the sealing film 31 corresponding to the pad portion of the rewiring 30 by photolithography or irradiation of a CO2 laser.
[0029]
Next, as shown in FIG. 8, an upper base metal layer 33a is formed on the entire upper surface of the sealing film 31 including the pad portion of the rewiring 30 exposed through the opening 32 by electroless plating of copper. Next, a plating resist film 43 is pattern-formed on the upper surface of the upper underlying metal layer 33a. In this case, an opening 44 is formed in the plating resist film 43 in a portion corresponding to the region where the upper layer rewiring 34 is formed. Next, the upper metal layer 33b is formed on the upper surface of the upper metal layer 33a in the opening 44 of the plating resist film 43 by performing copper electrolytic plating using the upper metal layer 33a as a plating current path.
[0030]
Next, the plating resist film 43 is peeled off, and then unnecessary portions of the upper base metal layer 33a are removed by etching using the upper metal layer 33b as a mask. As shown in FIG. 9, only the portion under the upper metal layer 33b is removed. An upper layer rewiring with the upper layer underlying metal layer 33a remaining is formed.
[0031]
Next, as shown in FIG. 10, an insulating film 35 made of a solder resist is pattern-formed on the entire upper surface of the sealing film 31 including the upper layer rewiring 34. In this case, an opening 36 is formed in a portion corresponding to the connection pad portion 34a of the upper layer rewiring 34 of the insulating film 35. Next, a solder ball 37 is formed in and above the opening 36 so as to be connected to the connection pad 34a of the upper layer rewiring 34.
[0032]
Next, as shown in FIG. 11, the insulating film 35, the sealing film 31, the adhesive layer 21, and the base plate 20 are cut between the adjacent semiconductor structures 22 to obtain a plurality of semiconductor devices shown in FIG. Can be
[0033]
In the semiconductor device thus obtained, the upper metal layer 33a and the upper metal layer 33b connected to the rewiring 30 of the semiconductor structure 22 are formed by electroless plating (or sputtering) and electrolytic plating. In addition, the conductive connection between the rewiring 30 of the semiconductor structure 22 and the upper rewiring 34 can be made without using bonding.
[0034]
As described above, since the upper layer redistribution line 34 is directly bonded to the pad portion of the redistribution line 30 of the semiconductor structure 22 by plating, the opening 32 of the upper layer insulation film 31 has a square or the same area of 10 μm × 10 μm. It is sufficient in terms of strength to have a circular area of.
[0035]
On the other hand, in the conventional semiconductor chip shown in FIG. 26, the diameter of the bump electrode 3 is about 100 to 150 μm (the pitch is usually twice this), so that the conventional bump electrode and the rewiring are bonded by bonding. Compared with the joining method, the size and arrangement interval of the connection pad portions 34a can be made far more, and the process is more efficient.
[0036]
As described above, since the size and the arrangement interval of the connection pad portions 34a can be reduced, the size of the semiconductor device of the present invention having the upper layer rewiring can be reduced.
[0037]
Further, in the above-described manufacturing method, the semiconductor structure 22 is bonded and arranged at a plurality of predetermined locations on the adhesive layer 21 on the base plate 20, and the sealing film 31 and the upper layer underlayer are applied to the plurality of semiconductor structures 22. Since the formation of the metal layer 33, the upper layer redistribution wiring 34, the insulating film 35, and the solder balls 37 is collectively performed, and thereafter, a plurality of semiconductor devices are obtained by dividing, the manufacturing process can be simplified.
[0038]
In addition, since the plurality of semiconductor components 22 can be transported together with the base plate 20, the manufacturing process can be simplified. Furthermore, if the external dimensions of the base plate 20 are made constant, the transport system can be shared regardless of the external dimensions of the semiconductor device to be manufactured.
[0039]
Further, in the semiconductor device shown in FIG. 1, a protective film 27 made of photosensitive polyimide or the like, a sealing film 31 made of epoxy resin or the like, and an insulating film 35 made of photosensitive polyimide or the like are stacked on the silicon substrate 24. Therefore, after the semiconductor device is mounted on a circuit board (not shown) via the solder balls 37 by the three resin layers, the stress caused by the difference in thermal expansion coefficient between the silicon substrate 24 and the circuit board is reduced. Can be alleviated to some extent.
[0040]
Next, another example of the method for manufacturing the semiconductor device shown in FIG. 1 will be described. First, as shown in FIG. 12, an adhesive layer 52 made of an ultraviolet-curable pressure-sensitive adhesive sheet or the like is adhered to the entire upper surface of another base plate 51 made of a transparent resin plate or a glass plate that is transparent to ultraviolet light. A base plate having the above-mentioned base plate 20 and adhesive layer 21 adhered to the upper surface thereof is prepared.
[0041]
Then, after passing through the manufacturing steps shown in FIGS. 6 to 10, as shown in FIG. 13, the insulating film 35, the sealing film 31, the adhesive layer 21, the base plate 20 and the adhesive layer 52 are cut, and another base is cut. The plate 51 is not cut. Next, ultraviolet rays are irradiated from the lower surface side of another base plate 51 to cure the adhesive layer 52. Then, the adhesiveness of the adhesive layer 52 to the lower surface of the divided base plate 20 is reduced. Then, when individual pieces existing on the adhesive layer 52 are peeled off one by one and picked up, a plurality of semiconductor devices shown in FIG. 1 are obtained.
[0042]
In this manufacturing method, in the state shown in FIG. 13, the individualized semiconductor devices existing on the adhesive layer 52 do not fall apart, so that a circuit (not shown) is used without using a dedicated semiconductor device mounting tray. At the time of mounting on a substrate, it can be peeled off and picked up one by one. Further, when the adhesive layer 52 remaining on the upper surface of another base plate 51 and having reduced adhesiveness is peeled off, another base plate 51 can be reused. Furthermore, if the external dimensions of another base plate 51 are made constant, the transport system can be shared regardless of the external dimensions of the semiconductor device to be manufactured.
[0043]
It is also possible to use a normal dicing tape or the like for removing the semiconductor device by expanding it as another base plate 55, and in that case, the adhesive layer does not need to be an ultraviolet curing type. Further, another base plate 55 may be removed by polishing or etching.
[0044]
Next, still another example of the method for manufacturing the semiconductor device shown in FIG. 1 will be described. In this manufacturing method, after the manufacturing process shown in FIG. 7, as shown in FIG. 14, the entire upper surface of the sealing film 31 including the upper surface of the rewiring 30 exposed through the opening 32 is formed by electroless plating of copper. An upper base metal layer 33a is formed. Next, the upper metal layer 33c is formed on the entire upper surface of the upper metal layer 33 by performing copper electrolytic plating using the upper metal layer 33a as a plating current path. Next, a resist film 53 is pattern-formed on a portion of the upper surface of the upper metal layer 33c corresponding to the upper layer rewiring formation region.
[0045]
Next, unnecessary portions of the upper metal layer 33c and the upper base metal layer 33a are removed by etching using the resist film 53 as a mask, and as shown in FIG. The metal layer 33a remains, and the upper layer redistribution wiring 34 is formed. After that, the resist film 53 is peeled off. Note that the upper metal layer 29b and the base metal layer 29a of the semiconductor structure 22 may be formed by the same forming method.
[0046]
(2nd Embodiment)
In the manufacturing process shown in FIG. 6, when the adhesive layer 21 is provided on the lower surface of the silicon substrate 24 of the semiconductor structure 22 and the adhesive layer 21 is bonded to each predetermined position on the upper surface of the base plate 20, FIG. A semiconductor device as a second embodiment of the present invention as shown is obtained.
[0047]
In the semiconductor device thus obtained, the lower surface of the silicon substrate 24 is bonded to the upper surface of the base plate 20 via the adhesive layer 21, and the side surface of the silicon substrate 24 is bonded via the sealing film 36. Since the semiconductor structure 22 is connected to the upper surface of the base plate 20, the bonding strength of the semiconductor structure 22 to the base plate 20 can be increased to some extent.
[0048]
(Third and fourth embodiments)
FIG. 17 is a sectional view of a semiconductor device according to a third embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that it does not include a base plate 20 and an adhesive layer 21.
[0049]
In the case of manufacturing the semiconductor device of the third embodiment, for example, as shown in FIG. 10, after the solder balls 37 are formed, the base plate 20 is peeled off from the adhesive layer 21 or the base plate 20 and the adhesive layer 21 are removed. After removal by polishing or etching or the like, the insulating film 35 and the sealing film 31 are cut between the adjacent semiconductor structures 22 to obtain a plurality of semiconductor devices shown in FIG. Since the semiconductor device thus obtained does not include the base plate 20 and the adhesive layer 21, the thickness can be reduced accordingly.
[0050]
After removing the base plate 20 and the adhesive layer 21, the lower surfaces of the silicon substrate 24 and the sealing film 31 are appropriately polished, and then the insulating film 35 and the sealing film 31 are interposed between the adjacent semiconductor structures 22. Is cut, a plurality of semiconductor devices as the fourth embodiment of the present invention shown in FIG. 18 are obtained. The semiconductor device thus obtained can be further reduced in thickness.
[0051]
Before the formation of the solder balls 37, the base plate 20 and the adhesive layer 21 are removed by polishing, etching, or the like (if necessary, the lower surfaces of the silicon substrate 24 and the sealing film 31 are appropriately polished). Next, the solder balls 37 may be formed, and then the insulating film 35 and the sealing film 31 may be cut between the adjacent semiconductor structures 22.
[0052]
(Fifth embodiment)
FIG. 19 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention. This semiconductor device differs from the semiconductor device shown in FIG. 1 in that a metal layer 61 for heat dissipation is adhered to the lower surface of the adhesive layer 21. The metal layer 61 is made of a copper foil having a thickness of several tens of μm or the like.
[0053]
In the case of manufacturing the semiconductor device of the fifth embodiment, for example, as shown in FIG. 10, after the solder balls 37 are formed, the base plate 20 is removed by polishing or etching, and then the entire lower surface of the adhesive layer 21 is formed. 18 is obtained by cutting the insulating film 35, the sealing film 31, the adhesive layer 21, and the metal layer 61 between the adjacent semiconductor structures 22. Thus, a plurality of semiconductor devices shown in FIG. 18 are obtained. .
[0054]
The adhesive layer 21 is also removed by polishing, etching, or the like (if necessary, the lower surfaces of the silicon substrate 24 and the sealing film 31 are appropriately polished), and a new surface is formed on the lower surfaces of the silicon substrate 24 and the sealing film 31. The metal layer 61 may be bonded via an adhesive layer.
[0055]
(Sixth embodiment)
In the case shown in FIG. 11, the cutting is performed between the semiconductor components 22 adjacent to each other. However, the present invention is not limited to this, and two or more semiconductor components 22 are cut as one set. As in the sixth embodiment of the present invention, three semiconductor components 22 may be cut into one set to obtain a multi-chip module type semiconductor device. In this case, the set of three semiconductor components 22 may be the same or different.
[0056]
(Seventh embodiment)
FIG. 21 is a sectional view of a semiconductor device according to a seventh embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that the semiconductor structure 22 is provided with an upper protective film 62 made of photosensitive polyimide or the like on the upper surface of the protective film 27 including the rewiring 30. This is that an opening 63 is provided in a portion of the rewiring 62 corresponding to the pad portion.
[0057]
In the case of manufacturing the semiconductor device of the seventh embodiment, after the manufacturing process shown in FIG. 4, an upper protective film made of photosensitive polyimide or the like is formed on the upper surface of the protective film 27 including the rewiring 30, as shown in FIG. 21. An opening 63 is formed in a portion of the upper protective film 62 corresponding to the pad portion of the rewiring 30. After the same manufacturing steps as those shown in FIGS. A plurality of the semiconductor devices shown are obtained.
[0058]
In the semiconductor device thus obtained, the protective film 27 made of photosensitive polyimide or the like, the upper protective film 62 made of photosensitive polyimide or the like, the sealing film 31 made of epoxy resin or the like, and the photosensitive film 27 are formed on the silicon substrate 24. Since the insulating film 35 made of polyimide or the like is laminated, the semiconductor device is mounted on a circuit board (not shown) via the solder balls 37 by the four resin layers. The stress caused by the difference in the coefficient of thermal expansion from the circuit board can be further reduced. The upper surface of the sealing film 31 may be flush with the upper surface of the upper protective film 62.
[0059]
(Eighth embodiment)
FIG. 23 is a sectional view of a semiconductor device according to an eighth embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that a rectangular frame-shaped embedding material 71 is provided on the upper surface of an adhesive layer 21 around a semiconductor structure 22.
[0060]
In this case, the thickness of the embedding material 71 may be the same as the thickness of the silicon substrate 24, and may be the same as the sum of the thickness of the insulating film 25 and the thickness of the protective film 26. The thickness may be the same as the added thickness, or may be the same as the added thickness of the rewiring 30. Therefore, the upper surface of the embedding material 71 is covered with the sealing film 31. Further, the sealing film 31 is filled between the semiconductor structure 22 and the embedding material 71.
[0061]
In the case of manufacturing the semiconductor device of the eighth embodiment, in the manufacturing process shown in FIG. 6, the silicon substrate of the semiconductor structure 22 is provided at a plurality of predetermined locations on the upper surface of the adhesive layer 21 as shown in FIG. The lower surface of the embedding material 71 is bonded to the upper surface of the adhesive layer 21 between the semiconductor structures 22 adjacent to each other.
[0062]
The material of the embedding material 71 may be the same as that of the base plate 20, or may be different. When the material of the base plate 20 and the embedding material 71 is a thermoplastic resin, the two are thermocompression-bonded without using the adhesive layer 21, and then the adhesive provided on the lower surface of the silicon substrate 24 of the semiconductor structure 22. The layer 21 (see FIG. 16) may be adhered to the upper surface of the base plate 20. Alternatively, the sheet-shaped embedding material 71 may be bonded to the entire upper surface of the adhesive layer 21 (or may be thermocompression-bonded onto the base plate 20), and the grid-shaped embedding material 71 may be formed by spot facing. Good.
[0063]
Next, as shown in FIG. 25, a sealing film 31 made of an epoxy resin or the like is formed on the entire upper surface of the adhesive layer 21 including the plurality of semiconductor structures 22 and the lattice-shaped embedding material 71 by a printing method, a molding method, or the like. Accordingly, the thickness is formed to be slightly thicker than the height of the semiconductor structure 22. Next, if necessary, the upper surface of the sealing film 31 is appropriately polished to smooth the upper surface of the sealing film 31. Next, an opening 32 is formed in a portion of the sealing film 31 corresponding to the pad portion of the rewiring 30 by photolithography or irradiation of a CO2 laser. Thereafter, through the same manufacturing steps as those shown in FIGS. 8 to 11, a plurality of semiconductor devices shown in FIG. 23 are obtained.
[0064]
In the semiconductor device obtained in this manner, as shown in FIG. 25, the amount of the sealing film 31 between the semiconductor structures 22 adjacent to each other can be reduced by the volume of the embedding material 71. As a result, stress due to shrinkage of the sealing film 31 made of an epoxy resin or the like during curing can be reduced.
[0065]
(Other embodiments)
By the way, in each of the above embodiments, the case where the upper layer rewiring 34 is provided on the insulating film 35 provided on the sealing film 31 is described. However, the present invention is not limited to this. Layers may be provided, and interlayer rewiring connecting the rewiring 30 of the semiconductor structure 22 and the upper rewiring 34 may be provided between the layers.
[0066]
【The invention's effect】
As described above, according to the present invention, a plurality or a plurality of sets of semiconductor components formed by providing rewiring on a semiconductor substrate are arranged on a base plate, and the entire upper surface of the base plate including the semiconductor components is insulated. A film is formed, an upper layer rewiring is formed on the upper surface of the insulating film so as to be connected to the rewiring of the semiconductor structure, and at least one of the semiconductor structures is cut by cutting the insulating film. A plurality of semiconductor devices having an insulating film at the same time and a part of the upper layer rewiring disposed on the surrounding insulating film can be obtained in a lump, and there is no bonding process as in the related art. In addition, the arrangement interval of the external connection electrodes can be increased, and the insulating film and the upper layer rewiring can be collectively formed on a plurality or a plurality of sets of the semiconductor structures. It can be simplified.
[Brief description of the drawings]
FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention;
FIG. 2 is a cross-sectional view of an example of a method for manufacturing the semiconductor device shown in FIG. 1 which is initially prepared.
FIG. 3 is a sectional view of the manufacturing process following FIG. 2;
FIG. 4 is a sectional view of the manufacturing process following FIG. 3;
FIG. 5 is a sectional view of the manufacturing process following FIG. 4;
FIG. 6 is a sectional view of the manufacturing process following FIG. 5;
FIG. 7 is a sectional view of the manufacturing process following FIG. 6;
FIG. 8 is a sectional view of the manufacturing process following FIG. 7;
FIG. 9 is a sectional view of the manufacturing process following FIG. 8;
FIG. 10 is a sectional view of the manufacturing process following FIG. 9;
FIG. 11 is a sectional view of the manufacturing process continued from FIG. 10;
FIG. 12 is a cross-sectional view of another example of the method of manufacturing the semiconductor device shown in FIG. 1, which is initially prepared.
FIG. 13 is a sectional view of a predetermined manufacturing process in the other example.
14 is a cross-sectional view of a predetermined manufacturing step in still another example of the method of manufacturing the semiconductor device shown in FIG. 1;
FIG. 15 is a sectional view of the manufacturing process continued from FIG. 14;
FIG. 16 is a sectional view of a semiconductor device as a second embodiment of the present invention.
FIG. 17 is a sectional view of a semiconductor device according to a third embodiment of the present invention;
FIG. 18 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 19 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention.
FIG. 20 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention;
FIG. 21 is a sectional view of a semiconductor device according to a seventh embodiment of the present invention;
FIG. 22 is a sectional view of a predetermined manufacturing step in the example of the method for manufacturing the semiconductor device shown in FIG. 21;
FIG. 23 is a sectional view of a semiconductor device as an eighth embodiment of the present invention.
24 is a cross-sectional view of a predetermined manufacturing process in the example of the method for manufacturing a semiconductor device shown in FIG. 23;
FIG. 25 is a sectional view of the manufacturing process continued from FIG. 24;
FIG. 26 is a cross-sectional view of an example of a conventional semiconductor device.
[Explanation of symbols]
20 Base plate
21 Adhesive layer
22 Semiconductor components
23 Semiconductor Chip
24 Silicon substrate
25 connection pads
29 Base metal layer
30 Rewiring
31 sealing film
33 Upper Underlying Metal Layer
34 Upper layer rewiring
35 Insulating film
37 Solder Ball

Claims (28)

半導体基板上に、それぞれが、パッド部を有する複数の再配線を設けてなる半導体構成体と、前記各パッド部を除いて前記再配線を含む前記半導体構成体の上面全体および前記半導体構成体の周側面より外側の延出部に設けられた絶縁膜と、該絶縁膜上に、前記再配線のパッド部に接続されて設けられ且つ接続パッド部を有する少なくとも一層の上層再配線とを備え、前記上層再配線の中、最上層の上層再配線の少なくとも一部は、前記接続パッド部が、前記半導体構成体の周側面より外側の前記絶縁膜の延出部上に配置されていることを特徴とする半導体装置。On a semiconductor substrate, a semiconductor structure formed by providing a plurality of rewirings each having a pad portion, and the entire top surface of the semiconductor structure including the rewiring except for the pad portions and the semiconductor structure An insulating film provided on the extension portion outside the peripheral side surface, and at least one upper layer rewiring provided on the insulating film and connected to the pad portion of the rewiring and having a connection pad portion; In the upper layer rewiring, at least a part of the upper layer rewiring, the connection pad portion is arranged on an extension of the insulating film outside a peripheral side surface of the semiconductor structure. Characteristic semiconductor device. 各々が、半導体基板と、該半導体基板の上面に設けられ且つパッド部を有する複数の再配線を有し、互いに離間して配置された複数の半導体構成体と、前記各半導体構成体のパッド部を除いて前記再配線を含む上面全体および前記各半導体構成体の周側面より外側の延出部に設けられた絶縁膜と、該絶縁膜上に、前記パッド部に接続されて設けられ且つ接続パッド部を有する少なくとも一層の上層再配線とを備え、前記上層再配線の中、最上層の上層再配線の少なくとも一部は、前記接続パッド部が前記いずれかの半導体構成体の周側面より外側の前記延出部上に配置されていることを特徴とする半導体装置。A plurality of semiconductor components each having a semiconductor substrate, a plurality of rewirings provided on the upper surface of the semiconductor substrate and having a pad portion, and arranged at a distance from each other; and a pad portion of each of the semiconductor components An insulating film provided on the entire upper surface including the rewiring except for the rewiring and an extension portion outside the peripheral side surface of each of the semiconductor structures; and provided on the insulating film and connected to the pad portion and connected At least one upper layer rewiring having a pad portion, wherein at least a part of the uppermost layer upper rewiring in the upper layer rewiring is such that the connection pad portion is located outside the peripheral side surface of any of the semiconductor structures. Wherein the semiconductor device is disposed on the extending portion. 請求項１または２に記載の発明において、前記絶縁膜は前記半導体構成体の周側面を覆って設けられていることを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein the insulating film is provided to cover a peripheral side surface of the semiconductor structure. 4. 請求項１または２に記載の発明において、前記複数の再配線は、前記半導体基板上に設けられた保護膜上に形成されていることを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein the plurality of rewirings are formed on a protective film provided on the semiconductor substrate. 請求項４に記載の発明において、前記半導体構成体の周側面を覆う前記絶縁膜の下面は前記半導体構成体の下面とほぼ同一の平面上に配置されていることを特徴とする半導体装置。5. The semiconductor device according to claim 4, wherein a lower surface of the insulating film covering a peripheral side surface of the semiconductor structure is disposed on substantially the same plane as a lower surface of the semiconductor structure. 請求項４に記載の発明において、前記半導体構成体およびその周囲における前記絶縁膜の下面に放熱層が設けられていることを特徴とする半導体装置。5. The semiconductor device according to claim 4, wherein a heat radiation layer is provided on a lower surface of the semiconductor structure and the insulating film around the semiconductor structure. 請求項１または２に記載の発明において、前記絶縁膜の延出部の下方には、埋込材が配置されていることを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein an embedding material is arranged below the extension of the insulating film. 請求項７に記載の発明において、前記埋込材は前記半導体基板とほぼ同じ厚さを有することを特徴とする半導体装置。8. The semiconductor device according to claim 7, wherein the embedding material has substantially the same thickness as the semiconductor substrate. 請求項８に記載の発明において、前記埋込材と前記半導体構成体との間に絶縁膜が充填されていることを特徴とする半導体装置。9. The semiconductor device according to claim 8, wherein an insulating film is filled between the embedding material and the semiconductor structure. 請求項１または２に記載の発明において、前記半導体構成体はベース板上に設けられていることを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein the semiconductor structure is provided on a base plate. 請求項１または２に記載の発明において、前記絶縁膜は複数層であり、その層間に、前記半導体構成体の再配線と前記上層再配線とを接続する層間再配線が設けられていることを特徴とする半導体装置。3. The invention according to claim 1, wherein the insulating film has a plurality of layers, and an interlayer rewiring connecting the rewiring of the semiconductor structure and the upper rewiring is provided between the layers. 4. Characteristic semiconductor device. 請求項１または２に記載の発明において、前記上層再配線を含む前記絶縁膜の上面において前記上層再配線の接続パッド部を除く部分に最上層絶縁膜が設けられていることを特徴とする半導体装置。3. The semiconductor according to claim 1, wherein an uppermost insulating film is provided on a portion of the upper surface of the insulating film including the upper layer redistribution except for a connection pad portion of the upper layer redistribution. 4. apparatus. 請求項１２に記載の発明において、前記上層再配線の接続パッド部上に突起状の接続端子が設けられていることを特徴とする半導体装置。13. The semiconductor device according to claim 12, wherein a protruding connection terminal is provided on the connection pad portion of the upper layer rewiring. 請求項１４に記載の発明において、前記突起状の接続端子は半田ボールであることを特徴とする半導体装置。15. The semiconductor device according to claim 14, wherein the projecting connection terminals are solder balls. 半導体基板上に、それぞれ、パッド部を有する複数の再配線が形成された複数の半導体構成体を相互に離間してベース板上に配置する工程と、
前記複数の半導体構成体上を含む前記ベース板の上面全体に絶縁膜を形成する工程と、
前記絶縁膜の上面に、接続パッド部を有し且ついずれかの前記半導体構成体の対応する前記パッド部に接続される上層再配線を、少なくともいずれかの前記上層再配線の接続パッド部が前記半導体構成体間に形成された前記絶縁膜上に配置されるように形成する工程と、
前記各半導体構成体間における前記絶縁膜を切断して少なくともいずれかの前記上層再配線の接続パッド部が前記半導体構成体より外側の領域の前記絶縁膜上に形成された前記半導体構成体を少なくとも１つ有する半導体装置を複数個得る工程とを有することを特徴とする半導体装置の製造方法。A step of arranging a plurality of semiconductor structures on which a plurality of rewirings each having a pad portion are formed on a base plate, apart from each other, on a semiconductor substrate,
Forming an insulating film over the entire top surface of the base plate including the plurality of semiconductor structures;
On the upper surface of the insulating film, a connection pad portion, and an upper layer rewiring connected to the corresponding pad portion of any of the semiconductor structures, at least one of the connection pad portions of the upper layer rewiring is the Forming it so as to be disposed on the insulating film formed between the semiconductor components,
By cutting the insulating film between the semiconductor structures, at least one of the connection pads of the upper layer rewiring is formed on the insulating film in a region outside the semiconductor structure at least by the semiconductor structure. Obtaining a plurality of semiconductor devices having one semiconductor device. 請求項１５に記載の発明において、前記絶縁膜を切断する工程は、前記半導体構成体が複数個含まれるように切断することを特徴とする半導体装置の製造方法。16. The method of manufacturing a semiconductor device according to claim 15, wherein the step of cutting the insulating film includes cutting the plurality of semiconductor components. 請求項１５に記載の発明において、前記半導体構成体を相互に離間してベース板上に配置する工程は、前記半導体構成体間に埋込材を配置する工程を含むことを特徴とする半導体装置の製造方法。16. The semiconductor device according to claim 15, wherein the step of arranging the semiconductor components on the base plate so as to be separated from each other includes a step of arranging an embedding material between the semiconductor components. Manufacturing method. 請求項１５に記載の発明において前記複数の再配線は、前記半導体基板上に設けられた保護膜上に形成されていることを特徴とする半導体装置の製造方法。16. The method according to claim 15, wherein the plurality of rewirings are formed on a protective film provided on the semiconductor substrate. 請求項１５に記載の発明において、前記絶縁膜は複数層であり、その層間に、前記各半導体構成体の再配線とそれに対応する前記各組の上層再配線とを接続する複数組の層間再配線を形成する工程を有することを特徴とする半導体装置の製造方法。The invention according to claim 15, wherein the insulating film has a plurality of layers, and between the layers, a plurality of sets of interlayer wirings for connecting the rewiring of each semiconductor structure and the corresponding upper rewiring of each set. A method for manufacturing a semiconductor device, comprising a step of forming a wiring. 請求項１５に記載の発明において、前記上層再配線を含む前記絶縁膜の上面において前記上層再配線のパッド部を除く部分に最上層絶縁膜を形成する工程を有することを特徴とする半導体装置の製造方法。16. The semiconductor device according to claim 15, further comprising a step of forming an uppermost insulating film on a portion of the upper surface of the insulating film including the upper redistribution wiring except for a pad portion of the upper redistribution wiring. Production method. 請求項２０に記載の発明において、前記上層再配線のパッド部上に突起状の接続端子を形成する工程を有することを特徴とする半導体装置の製造方法。21. The method of manufacturing a semiconductor device according to claim 20, further comprising a step of forming a protruding connection terminal on a pad portion of the upper layer rewiring. 請求項２１に記載の発明において、前記突起状の接続端子は半田ボールであることを特徴とする半導体装置の製造方法。22. The method according to claim 21, wherein the projecting connection terminals are solder balls. 請求項１５に記載の発明において、前記絶縁膜を切断するとともに前記ベース板を切断する工程を有することを特徴とする半導体装置の製造方法。16. The method according to claim 15, further comprising a step of cutting the insulating film and cutting the base plate. 請求項２３に記載の発明において、切断前の前記ベース板下に別のベース板を配置し、前記ベース板を切断した後に、前記別のベース板を取り除く工程を有することを特徴とする半導体装置の製造方法。24. The semiconductor device according to claim 23, further comprising a step of disposing another base plate below the base plate before cutting, and removing the another base plate after cutting the base plate. Manufacturing method. 請求項１５に記載の発明において、　前記半導体構成体を相互に離間してベース板上に配置する工程は、前記半導体構成体間に埋込材を配置する工程を含み、前記各半導体構成体間における前記絶縁膜を切断する工程は、前記埋込材を切断する工程を含むことを特徴とする半導体装置の製造方法。16. The semiconductor device according to claim 15, wherein the step of disposing the semiconductor components on the base plate so as to be spaced apart from each other includes the step of disposing an embedding material between the semiconductor components. The method of manufacturing a semiconductor device according to claim 1, wherein the step of cutting the insulating film includes the step of cutting the embedding material. 請求項２５に記載の発明において、前記各半導体構成体間における前記絶縁膜を切断する工程は、前記ベース板を切断する工程を含むことを特徴とする半導体装置の製造方法。26. The method of manufacturing a semiconductor device according to claim 25, wherein the step of cutting the insulating film between the respective semiconductor structures includes a step of cutting the base plate. 請求項１５に記載の発明において、前記各半導体構成体間における前記絶縁膜を切断する工程の前に、前記ベース板を取り除く工程を有することを特徴とする半導体装置の製造方法。16. The method of manufacturing a semiconductor device according to claim 15, further comprising a step of removing the base plate before the step of cutting the insulating film between the semiconductor components. 請求項２７に記載の発明において、前記ベース板を取り除く工程に引き続き、前記半導体基板を薄くする工程を有することを特徴とする半導体装置の製造方法。28. The method according to claim 27, further comprising, after the step of removing the base plate, a step of thinning the semiconductor substrate.
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