JP2018152537A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce warpage of a semiconductor device.SOLUTION: A semiconductor device comprises: a semiconductor element including a first insulation layer arranged on a terminal formation surface on which connection terminals of a semiconductor chip are formed and a first wiring layer which is formed on the first insulation layer and connected with the connection terminals; an encapsulation resin for encapsulating the semiconductor element; a second insulation layer formed on the encapsulation resin; and a second wiring layer which is connected with the first wiring layer and formed on one surface of the second insulation layer and which extends from a region above the terminal formation surface in a vertical direction to a region of the second insulation layer outside the region above the terminal formation surface in the vertical direction.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  A semiconductor device using two rewiring layers has been proposed in order to realize wiring even when the internal wirings connecting the connection terminals of the semiconductor element and the external connection terminals of the semiconductor package need to cross each other. . Patent Document 1 describes a method for manufacturing a semiconductor device in which a semiconductor element on which bumps are formed is molded and then a two-layer rewiring layer is formed.

US Patent Application Publication No. 2004/245608

  However, the semiconductor device of Patent Document 1 requires a plurality of insulating layers with multilayer wiring on the package side, which causes a problem that warpage of the rewiring board is increased.

According to the first aspect of the present invention, the semiconductor device is formed on the first insulating layer disposed on the terminal forming surface on which the connection terminal of the semiconductor chip is formed, and on the first insulating layer. , A semiconductor element including a first wiring layer connected to the connection terminal, a sealing resin for sealing the semiconductor element, a second insulating layer formed on the sealing resin, and the first Connected to the wiring layer, formed on one surface of the second insulating layer, and extending from a region vertically above the terminal forming surface to an outer region vertically above the terminal forming surface of the second insulating layer A second wiring layer.
According to a second aspect of the present invention, a method of manufacturing a semiconductor device includes preparing a semiconductor wafer having a plurality of semiconductor chip forming regions in which connection terminals connected to an internal circuit are formed, and each of the semiconductor chips Forming a first insulating layer on a terminal formation surface on which the connection terminal is formed in a formation region; and forming a first wiring layer connected to the connection terminal on the first insulating layer. Separating the semiconductor wafer on which the first wiring layer is formed, obtaining a semiconductor element, forming a wiring structure including a second insulating layer, and a second wiring layer; Sealing the obtained semiconductor element and forming a sealing body, wherein the second wiring layer is connected to the first wiring layer, and the terminal forming surface on the second insulating layer is formed. In front of the second insulating layer from a vertically upper region It is formed so as to extend to the outer region vertically above the terminal forming surface.

  According to the present invention, since the wiring layer is formed on the semiconductor element side, a semiconductor device with less warpage than when all the wiring layers are arranged on the package side while maintaining a high degree of wiring freedom by two or more wiring layers. Can be provided.

1A and 1B are diagrams illustrating a semiconductor device according to a first embodiment, FIG. 1A schematically illustrating a cross section, and FIG. 1B schematically illustrating a circuit. 1 is a cross-sectional view schematically showing a semiconductor device according to a first embodiment. FIG. 3A is a top view of the semiconductor device of the first embodiment, and FIG. 3B is a top view of a semiconductor chip constituting the semiconductor device. It is a figure which shows typically the circuit of the semiconductor element mounted in the semiconductor device of 1st Embodiment. It is a figure which shows typically the circuit of the semiconductor device of 1st Embodiment. 6A to 6D are cross-sectional views schematically showing each step for explaining the method for manufacturing the semiconductor device of the first embodiment. 7A to 7C are cross-sectional views schematically showing the process following FIG. 8A to 8C are cross-sectional views schematically showing the process following FIG. 9A and 9B are cross-sectional views schematically showing the process following FIG. 10A to 10E are cross-sectional views schematically showing the process following FIG. 11A to 11D are cross-sectional views schematically showing the process following FIG. 12A to 12C are cross-sectional views schematically showing the process following FIG. 13A to 13C are cross-sectional views schematically showing the process following FIG. It is sectional drawing which shows typically the semiconductor device of the modification 1 of 1st Embodiment. It is sectional drawing which shows typically the semiconductor device of the modification 2 of 1st Embodiment. It is a figure which shows typically the circuit of the semiconductor device of the modification 3 of 1st Embodiment. It is sectional drawing which shows typically the semiconductor device of the modification 3 of 1st Embodiment. It is sectional drawing which shows the semiconductor device of 2nd Embodiment typically. 19A to 19C are cross-sectional views schematically showing each step for explaining the method for manufacturing the semiconductor device of the second embodiment. 20A and 20B are cross-sectional views schematically showing the process following FIG. It is sectional drawing which shows typically the semiconductor device of the modification of 2nd Embodiment.

  Hereinafter, the semiconductor device of the first embodiment, the method for manufacturing the semiconductor device, and the like will be described with reference to the drawings as appropriate. In the following embodiments, unless otherwise specified, the surface of the semiconductor device having the external connection terminal is the top surface of the semiconductor device, the vertical direction is the direction perpendicular to the top surface, and the direction from the top surface of the semiconductor device to the outside is upward And Further, in the following embodiments, the term “wiring layer” is used to connect between terminals of two semiconductor elements as described later, in addition to a rewiring layer that rearranges the positions of terminals such as pads of the semiconductor elements. Including the wiring etc. Furthermore, in the following embodiments, the term “connect” includes the meaning that two connected objects can conduct.

  FIG. 1 is a conceptual diagram schematically showing a semiconductor device 1 of the present embodiment. FIG. 1A is a diagram schematically showing a cross-section perpendicular to the top surface of the semiconductor device 1 with a simplified circuit. FIG. 1B is a top view of the semiconductor device 1 and shows the inside of the semiconductor device 1. It is a figure which shows a circuit and is shown typically.

The semiconductor device 1 includes a semiconductor element 100, a package side wiring structure 200, a mold resin 30, and solder balls 25. The semiconductor element 100 includes a semiconductor chip 10, a pad 11, a semiconductor element side insulating layer 12, a pad conducting part 13, a semiconductor element side wiring layer 14, a columnar structure 15, and a solder plating 16. The package side wiring structure 200 includes an input / output terminal 21, a package side insulating layer 22, an input / output terminal conducting portion 23, and a package side wiring layer 24. In FIG. 1B, a portion corresponding to the semiconductor element 100 is indicated by a broken line.
In this embodiment, one wiring layer 14 and 24 is provided on the semiconductor element side and one layer on the package side. However, a plurality of wiring layers may be provided on the semiconductor element side and / or the package side. Further, an insulating layer and a conductor layer are further formed on the input / output terminal 21 for another purpose such as formation of a pad for improving reliability, which is different from wiring routing for connecting the pad 11 and the input / output terminal 21. May be.

A surface on which the pad 11 of the semiconductor element 100 is formed is referred to as a terminal formation surface S. On the terminal forming surface S, as shown in FIG. 1B, a plurality of pads 11 are arranged in two rows. Each pad 11 is connected to the semiconductor element side wiring layer 14 via a pad conduction part 13 formed in the opening of the semiconductor element side insulating layer 12. The semiconductor element side wiring layer 14 is formed on the semiconductor element side insulating layer 12, forms a predetermined pattern of wiring along the semiconductor element side insulating layer 12, and is connected to the columnar structure 15 corresponding to each pad 11. To do.
Although not shown in FIG. 1, a passivation layer or the like may be disposed on the lower surface of the semiconductor element side insulating layer 12 of the semiconductor chip 10, that is, the terminal formation surface S (see FIG. 6 and the like).

The columnar structure 15 of the semiconductor element 100 is connected to the package side wiring layer 24 of the package side wiring structure 200 via the solder plating 16. The package-side wiring layer 24 is formed on one surface of the package-side insulating layer 22 formed on the mold resin 30, forms a predetermined pattern of wiring along the package-side insulating layer 22, and conducts input / output terminal conduction The input / output terminal 21 and the solder ball 25 are connected via the part 23.
The wiring patterns of the semiconductor element side wiring layer 14 and the package side wiring layer 24 are not particularly limited. In addition, the plurality of portions constituting the wiring connecting the pad 11 and the solder ball 25 can be integrally formed as appropriate. Further, the semiconductor element side wiring layer 14 and the package side wiring layer 24 are not limited to those extending in a two-dimensional pattern, and may be formed as a structure having a three-dimensional wiring pattern.

  The semiconductor chip 10 includes an electronic circuit such as an integrated circuit or a large-scale integrated circuit. The material of the semiconductor element side insulating layer 12 includes polyimide or the like. Each of the pad conductive portion 13 and the semiconductor element side wiring layer 14 includes a metal such as copper and can be integrally formed. The columnar structure 15 includes a metal such as copper. The package side wiring layer 24 and the input / output terminal conducting portion 23 are configured to include a metal such as copper and can be formed integrally. The package-side insulating layer 22 includes an epoxy resin or the like. The input / output terminal 21 includes a metal such as copper. The aspect of the solder plating 16 and the solder ball 25 is not particularly limited, and the configuration may be changed as appropriate according to the characteristics of the element to be connected and the connection method.

FIG. 2 is a diagram illustrating a positional relationship between the semiconductor element 100 and the input / output terminal 21. A region vertically above the terminal formation surface S of the semiconductor element 100 is defined as a region V. FIG. 2 schematically shows the range of the region V with a dotted line. In the semiconductor device 1 of this embodiment, the package side wiring layer 24 extends from the region V of the package side insulating layer 22 to a region outside the region V of the package side insulating layer 22. An input / output terminal 21 or a solder ball 25 that functions as an external connection terminal connected to an external printed circuit board or the like of the semiconductor device 1 is a region outside the region V on the upper surface (surface including the external connection terminal) of the semiconductor device 1. Is arranged. Thus, the semiconductor device 1 can be configured as a fan-out type semiconductor package.
Note that some of the external connection terminals may be disposed inside the region V as in the example illustrated in FIG. Similarly, some package-side wiring layers 24 do not need to extend to the outside of the region V.

  The thickness T1 of the semiconductor element side insulating layer 12 can be made smaller than the thickness T2 of the package side insulating layer 22. In particular, the semiconductor element side insulating layer 12 and the package side insulating layer 22 are of different types, such as the semiconductor element side insulating layer 12 including a polyimide material and the package side insulating layer 22 including an epoxy resin. When configured to include a resin, the thickness T1 can be significantly smaller than the thickness T2. The thickness T1 of the semiconductor element side insulating layer 12 is preferably 4 μm or more and 9 μm or less, and more preferably 4 μm or more and 6 μm or less. The thickness T2 of the package-side insulating layer 22 is preferably 20 μm or more and 50 μm or less, and more preferably 30 μm or more and 50 μm or less.

  Since the semiconductor element side insulating layer 12 can be formed thinner than the case where the insulating layer is formed on the package side, the semiconductor device 1 can reduce the overall thickness T. In particular, when the device is mounted on a device such as a mobile phone that requires a thinner part, the thickness T is preferably 500 μm or less, and more preferably 300 μm or less.

FIG. 3A is a top view of the semiconductor device 1. A part of the upper surface of the semiconductor device 1 is covered with the package-side insulating layer 22, and solder balls 25 are discretely arranged.
The arrangement of the solder balls 25 or the input / output terminals 21 of the semiconductor device 1 is not limited to the example shown in FIG. 3A and can be set as appropriate.

FIG. 3B is a diagram showing a top view of the semiconductor chip 10 constituting the semiconductor device 1. A pad 11 is provided on the upper surface of the semiconductor chip 10. As described above, each pad 11 is exposed to the outside from the opening formed in the passivation layer (see FIG. 6 and the like).
Note that the arrangement of the pads 11 on the upper surface of the semiconductor chip 10 is not particularly limited.

FIG. 4 is a diagram schematically showing a circuit of the semiconductor element 100. The upper surface of the semiconductor chip 10 is covered with the semiconductor element side insulating layer 12, and the pad conductive portion 13 is formed in the opening (opening 510, see FIG. 6B) of the semiconductor element side insulating layer 12 formed on the pad 11. Is formed. When it sees about the pad 11a, the pad conduction | electrical_connection part 13a is connected with the columnar structure 15a and the solder plating 16a by the semiconductor element side wiring layer 14a. Here, the distance D2 between the center C of the terminal formation surface S and the columnar structure 15a or the solder plating 16a projected onto the terminal formation surface S rather than the distance D1 between the center C of the terminal formation surface S and the pad 11a. Is short. As described above, the semiconductor element side wiring layer 14 can have a fan-in structure in which rewiring is performed inward from the pad 11.
It should be noted that some or all of the semiconductor element side wiring layers 14 do not necessarily have a fan-in structure.

  FIG. 5 is a diagram schematically showing a circuit of the semiconductor device 1. In FIG. 5, as in FIG. 1B, a portion corresponding to the semiconductor element 100 is indicated by a broken line. The pad 11b is connected to the solder ball 25b through the semiconductor element side wiring layer 14b and the package side wiring layer 24b. The pad 11c is connected to the columnar structure 15c via the semiconductor element side wiring layer 14c, and the columnar structure 15c is connected to the solder ball 25c without passing through the package side wiring layer.

  In the semiconductor device 1 of the present embodiment, when the circuits of the semiconductor element side wiring layer 14c and the package side wiring layer 24b are projected onto a plane including the terminal formation surface S, the projected circuit of the semiconductor element side wiring layer 14c and the package side The projected circuit of the wiring layer 24b intersects at the point P. As described above, the semiconductor device 1 projects the semiconductor element side wiring layer 14 and the package side wiring layer 24 connected to the different pads 11 on at least a part of the pads 11 when projected onto the terminal formation surface S. It is preferable to provide wiring structures that intersect.

Further, when the input / output terminal 21d and the solder ball 25d are projected onto the terminal forming surface S, they overlap the pad 11b. As described above, when the input / output terminal 21 or the solder ball 25 connected to one pad 11 is projected onto the terminal formation surface S for at least a part of the pads 11, the semiconductor device 1 overlaps the other pads 11. It is preferable.
In a configuration in which a certain pad 11 and a solder ball 25 connected to the pad 11 projected onto the terminal formation surface S overlap, the pad 11 is located at a position different from the pad 11 via the semiconductor element side wiring layer 14. After being connected to the columnar structure 15, wiring may be performed so as to return to the position of the solder ball 25 that overlaps the pad 11 again via the package side wiring layer 24. Thereby, the freedom degree of arrangement | positioning of an external connection terminal can be raised further.

(Manufacturing method of the semiconductor device 1)
Below, the flow of the manufacturing method of the semiconductor device 1 is demonstrated. A method for manufacturing the semiconductor element 100 will be described with reference to FIGS. 6 to 9, and a method for molding the semiconductor element 100 to form a semiconductor package will be described with reference to FIGS. 10 to 13.

  6 to 9 are diagrams schematically showing a method of forming the semiconductor element side wiring layer 14 on the semiconductor wafer 100W on which a plurality of circuits included in the semiconductor element 100 are formed. FIGS. 6A to 6D, FIGS. 7A to 7C, FIGS. 8A to 8C, and FIGS. 9A and 9B are shown in chronological order.

  FIG. 6A is a diagram schematically showing the semiconductor wafer 100W as an explanation of the first step of manufacturing the semiconductor element 100. FIG. The semiconductor wafer 100W includes a substrate 50 and a semiconductor chip formation region Vt. On the substrate 50, semiconductor chip forming regions Vt are formed at regular intervals, and each semiconductor chip forming region Vt has a pad 11, a passivation layer 51, and an internal electronic circuit (non-connected) connected to the pad 11. As shown). This electronic circuit functions as a circuit inside the semiconductor element 100 after the semiconductor wafer is separated into pieces. In the first step of manufacturing the semiconductor element 100, the semiconductor wafer 100W is acquired by manufacturing or purchasing, and inspection of foreign matters, scratches, and the like is performed as appropriate.

  FIG. 6B is a diagram for explaining a second step of manufacturing the semiconductor element 100. In the second step, the semiconductor element side insulating layer 12 is formed on the passivation layer 51. First, a photosensitive polyimide resin is applied on the passivation layer 51 with a spin coater or the like. Thereafter, the polyimide resin is exposed with a photomask so that a predetermined pattern including the openings 51 remains, and after development, the polyimide resin is heated and cured.

  FIG. 6C is a diagram for explaining a third step of manufacturing the semiconductor element 100. In this third step, a seed layer 52 for plating is formed. The seed layer 52 functions as an UBM (Under Bump Metallurgy), and one or more thin films containing titanium and / or copper are formed on the pad 11 and the semiconductor element side insulating layer 12 by a sputtering method or the like.

  FIG. 6D is a diagram for explaining a fourth step of manufacturing the semiconductor element 100. In the fourth step, a photoresist 53 is formed on the seed layer 52 with a predetermined pattern. A photosensitive plating resist is applied onto the seed layer 52 by a spin coater or the like, exposed with a photomask in a pattern based on the pattern of the semiconductor element side wiring layer 14, and developed.

  FIG. 7A is a diagram for explaining a fifth step of manufacturing the semiconductor element 100. In the fifth step, the pad conductive portion 13 and the semiconductor element side wiring layer 14 are formed on the seed layer 52 by electrolytic plating. A wiring layer is formed within a range surrounded by the photoresist 53 from the seed layer 52 by electrolytic copper plating.

FIG. 7B is a diagram for explaining a sixth step of manufacturing the semiconductor element 100. In the sixth step, the photoresist 53 formed on the seed layer 52 is removed.
When the columnar structure 15 (FIG. 1) is not formed, the photoresist 53 may be removed in the sixth step, and then the process shown in FIG. 8C may be performed.

FIG. 7C is a view for explaining a seventh step of manufacturing the semiconductor element 100. In the seventh step, the dry film 54 is formed in a predetermined pattern. First, a dry film-like photoresist material is laminated on the semiconductor element side wiring layer 14 and the seed layer 52. Then, it exposes with the photomask with the pattern based on the pattern of the columnar structure 15, and develops.
A liquid resist may be used as the photoresist material 54 in accordance with the diameter and height of the columnar structure 15 and / or the interval at which the columnar structures are arranged.

FIG. 8A is a view for explaining an eighth step of manufacturing the semiconductor element 100. In the eighth step, the columnar structure 15 and the solder plating 16 are formed. By electrolytic copper plating, the columnar conductor layer 15 is formed in a range surrounded by the dry film 54 using the semiconductor element side wiring layer 14 as a seed. Thereafter, solder plating 16 is formed.
When the package-side wiring layer 24 is formed on the columnar conductor layer 15 by electrolytic plating after the semiconductor element 100 is molded, the formation of the solder plating 16 can be omitted.

  FIG. 8B is a view for explaining a ninth step of manufacturing the semiconductor element 100. In the ninth step, the dry film 54 is removed.

  FIG. 8C is a diagram for explaining a tenth process of manufacturing the semiconductor element 100. In the tenth step, a part of the seed layer 52 is removed. The seed layer 52 formed on the semiconductor element side insulating layer 12 and the like is removed by etching, and unnecessary conductor portions are removed.

  FIG. 9A is a view for explaining an eleventh step of manufacturing the semiconductor element 100. In the eleventh step, the substrate 50 is thinned to a predetermined thickness by back grinding.

  FIG. 9B is a view for explaining a twelfth process of manufacturing the semiconductor element 100. In the twelfth step, the substrate 50 is separated into pieces using a dicing blade or the like. Each of the separated elements becomes a semiconductor element 100.

  10 to 13 are diagrams schematically showing a method for manufacturing the semiconductor device 1 by a chip last method in which a semiconductor element is bonded to the package substrate after a package substrate having a redistribution layer is formed. FIGS. 10A to 10E, FIGS. 11A to 11D, FIGS. 12A to 12C, and FIGS. 13A to 13C are shown in chronological order. The semiconductor device 1 can be mass-produced efficiently at low cost by using the following manufacturing method using, for example, a panel having a size of several tens of cm in length and width. 10 to 13, the direction from the support substrate 41 side to the semiconductor element 100 side in the direction perpendicular to the support substrate 41 is upward.

  FIG. 10A is a diagram showing a support substrate 41 as an explanation of the process 1 of manufacturing the semiconductor device 1. A release layer 42 is formed on the support substrate 41 to facilitate the release of the support substrate 41 from the package substrate to be formed. In step 1, the support substrate 41 is acquired.

  FIG. 10B is a diagram for explaining a process 2 of manufacturing the semiconductor device 1. In step 2, a seed layer 43 is formed on the release layer. The method for forming the seed layer 43 is not particularly limited as long as it can be removed by plating and etching.

  FIG. 10C is a diagram for explaining a process 3 of manufacturing the semiconductor device 1. In step 3, a photoresist 44 is formed on the seed layer 43, exposed with a photomask in a pattern based on the pattern of the input / output terminals 21 (FIG. 1), and developed.

  FIG. 10D is a diagram for explaining a process 4 of manufacturing the semiconductor device 1. In step 4, the input / output terminal 21 is formed. A conductor layer corresponding to the input / output terminal 21 is formed from the seed layer 43 within a range surrounded by the photoresist 44 by electrolytic copper plating.

  FIG. 10E is a diagram for explaining a process 5 of manufacturing the semiconductor device 1. In step 5, the photoresist 44 formed on the seed layer 43 excluding the input / output terminal 21 is removed.

  FIG. 11A is a diagram for explaining a process 6 of manufacturing the semiconductor device 1. In step 6, the package side insulating layer 22 is formed with a predetermined pattern. First, an insulating material such as an epoxy resin is laminated on the input / output terminal 21 and the seed layer 43. Thereafter, an opening (via) 230 of the insulating material 22 is formed by a laser at a position corresponding to the input / output terminal conducting portion 23.

  FIG. 11B is a diagram for explaining a process 7 of manufacturing the semiconductor device 1. In step 7, a photoresist 45 is formed on the package-side insulating layer 22 and above the opening 230.

  FIG. 11C is a diagram for explaining a process 8 of manufacturing the semiconductor device 1. In step 8, a photoresist 45 is formed in a predetermined pattern. The photoresist 45 is exposed with a photomask in a pattern based on the pattern of the package side wiring layer 24 (FIG. 1) and developed.

  FIG. 11D is a diagram for explaining a process 9 of manufacturing the semiconductor device 1. In step 9, the input / output terminal conducting portion 23 and the package side wiring layer 24 are formed. Conductive layers corresponding to the input / output terminal conductive portion 23 and the package-side wiring layer 24 within the range surrounded by the photoresist 45 on the semiconductor element side insulating layer 22 with the input / output terminal 21 as a seed layer by electrolytic copper plating. Form. As shown in FIG. 2, some or all of the package-side wiring layers 24 are formed on the terminal-forming surface S of the package-side insulating layer 22 from the region vertically above the terminal-forming surface S in the completed semiconductor device 1. It is formed to extend to a region outside the vertically upper region.

  FIG. 12A is a diagram for explaining a process 10 of manufacturing the semiconductor device 1. In step 10, the photoresist 45 formed on the package side insulating layer 22 and the package side wiring layer 24 is removed. Thus, the package substrate 201 is formed as a whole of the package side wiring structure 200 (FIG. 1) and each layer from the substrate 50 to the package side wiring layer 24.

  FIG. 12B is a diagram for explaining a process 11 of manufacturing the semiconductor device 1. In step 11, the semiconductor element 100 is bonded to the package side wiring layer 24. The semiconductor element 100 is flip-bonded to the semiconductor element-side wiring layer 24 via the solder plating 16 with the terminal formation surface S facing downward.

  FIG. 12C is a diagram for explaining a process 12 of manufacturing the semiconductor device 1. In step 12, the semiconductor element 100 is sealed by transfer molding or compression molding using an epoxy resin 30 or the like.

  FIG. 13A is a diagram for explaining a process 13 of manufacturing the semiconductor device 1. In step 13, the support substrate 41 and the release layer 42 disposed under the input / output terminals 21 and the package-side insulating layer 22 are removed, and the seed layer 43 is removed by etching or the like.

FIG. 13B is a diagram for explaining a process 14 of manufacturing the semiconductor device 1. In step 14, the solder balls 25 are formed in contact with the input / output terminals 21.
Note that a semiconductor device of the following embodiment includes a panel and the like in a state before being singulated as shown in FIG.

  FIG. 13C is a diagram for explaining a process 15 of manufacturing the semiconductor device 1. In step 15, the semiconductor device 1 is obtained by dividing into pieces using a dicing blade or the like.

According to the above-described embodiment, the following operational effects can be obtained.
(1) The semiconductor device 1 of this embodiment is formed on the semiconductor element side insulating layer 12 and the semiconductor element side insulating layer 12 disposed on the terminal formation surface S, and is connected to the pad 11. A semiconductor element including the semiconductor element side wiring layer 14, and a terminal forming surface of the package side insulating layer 22 from a region on the package side insulating layer 22 which is connected to the semiconductor element side wiring layer 14 and is vertically above the terminal forming surface S. A package-side wiring layer 24 extending to an outer region vertically above S. As a result, the wiring of the semiconductor device can be reduced as compared with the case where all the rewiring layers are arranged on the package side, while the wiring can be routed using the multilayer structure.

(2) In the semiconductor device 1 of the present embodiment, the input / output terminal 21 or the solder ball 25 connected to the package side wiring layer 24 and disposed in a region vertically above the terminal formation surface S on the package side insulating layer. Is provided. Thereby, the external connection terminals can be arranged in a wide range, and the interval between the external connection terminals can be widened.

(3) In the semiconductor device 1 of this embodiment, when the input / output terminals 21 or the solder balls 25 are projected onto a plane including the terminal formation surface S, some of the input / output terminals 21 or the solder balls 25 overlap the pads 11. Thereby, arrangement | positioning of the external connection terminal which has a higher freedom degree is realizable.

(4) In the semiconductor device 1 of the present embodiment, when the circuits of the semiconductor element side wiring layer 14 and the package side wiring layer 24 are projected onto a plane including the terminal formation surface S, they are connected to different pads 11 at least in one place. The circuit of the semiconductor element side wiring layer 14 and the circuit of the package side wiring layer 24 intersect. Thereby, arrangement | positioning of the external connection terminal which has a higher freedom is realizable using the three-dimensional intersection of wiring.

(5) In the semiconductor device 1 of this embodiment, the semiconductor element side insulating layer 12 and the package side insulating layer 22 contain different types of resins. As a result, the thickness T of the semiconductor device 1 can be adjusted, and a design that makes it particularly thin is possible.

(6) In the semiconductor device 1 of this embodiment, the thickness of the semiconductor element side insulating layer 12 is smaller than the thickness of the package side insulating layer 22. As a result, the thickness T of the semiconductor device 1 can be reduced by several tens of μm or more than when all the redistribution layers are arranged on the package side.

(7) In the semiconductor device 1 of the present embodiment, at least some of the pads 11 are closer to the center C of the terminal formation surface S and the terminal formation surface S than the distance between the center C of the terminal formation surface S and the pad 11. The distance between the projected semiconductor element side wiring layer 14 connected to the pad 11 and the conductive portions 15 and 16 of the package side wiring layer is shorter. Thereby, the pads 11 arranged on the edge portion or the like of the terminal formation surface S can also be rewired, and the degree of freedom of arrangement of the external connection terminals connected to such pads 11 can be increased.

(8) In the semiconductor device 1 of the present embodiment, the semiconductor element side wiring layer 14 and the package side wiring layer 24 are connected via the columnar structure 15. Thereby, since the distance between the semiconductor element 100 and the package side wiring layer 24 can be increased, the insulation reliability can be improved and the panel warpage can be easily absorbed.

(9) In the manufacturing method of the semiconductor device 1 of the present embodiment, the semiconductor side insulating layer 12 is formed on the terminal formation surface S of the semiconductor wafer 100W, and the pad 11 is connected to the semiconductor element side insulating layer 12. Forming the semiconductor element side wiring layer 14, separating the semiconductor wafer 100W on which the semiconductor element side wiring layer 14 is formed, obtaining the semiconductor element 100, the package side insulating layer 22, and the package Forming a package-side wiring structure 200 including a side wiring layer 24. The package-side wiring layer 24 is connected to the semiconductor element-side wiring layer 14 and has a terminal formation surface on the package-side insulating layer 22 It is formed so as to extend from a region V vertically above S to a region outside vertically above the terminal formation surface S of the semiconductor element 100. Thereby, the wiring of the semiconductor device 1 can be reduced as compared with the case where all of the rewiring layers are arranged on the package side, while the wiring can be routed using the multilayer structure.

(10) In the method for manufacturing a semiconductor device according to this embodiment, the obtained semiconductor element 100 is bonded to a package substrate including the package-side wiring structure 200, and then the semiconductor element 100 is sealed. Thereby, it is not necessary to consider the deviation of the semiconductor element 100 at the time of sealing, the arrangement interval of the semiconductor elements 100 can be narrowed, and the semiconductor device 1 can be manufactured more efficiently.

The following modifications are also within the scope of the present invention, and can be combined with the above-described embodiment. In the following modified examples, portions having the same structure and function as those of the above-described embodiment are referred to by the same reference numerals, and description thereof will be omitted as appropriate.
(Modification 1)
In the semiconductor device 1 of the above-described embodiment, the package side wiring layer 24 and the input / output terminal 21 are connected by the input / output terminal conducting portion 23, but the input / output terminal 21 may be directly connected to the package side wiring layer 24. . Thereby, a part of manufacturing process can be simplified.

  FIG. 14 is a diagram schematically showing a cross section of the semiconductor device 1a of the present modification. The package-side wiring structure 200a of the semiconductor device 1a includes an input / output terminal 21, a package-side insulating layer 22, and a package-side wiring layer 24, and connects the input / output terminal 21 and the package-side wiring layer 24. The terminal conduction part 23 (FIG. 1) is not provided.

(Modification 2)
In the semiconductor device 1 of the above-described embodiment, the solder ball 25 and the package side wiring layer 24 are connected by the input / output terminal 21 and the input / output terminal conducting portion 23. However, the solder ball 25 is directly formed on the package side wiring layer 24. And it is good also as an external connection terminal. As a result, the thickness T of the semiconductor device can be made thinner than that of the semiconductor device 1.

  FIG. 15 is a diagram schematically showing a cross section of the semiconductor device 1b of the present modification. The package side wiring structure 200b of the semiconductor device 1b includes a package side wiring layer 24, solder balls 25, and a solder resist layer 29. Although the thickness of a soldering resist layer is not specifically limited, 20 micrometers or more and 50 micrometers or less are preferable.

(Modification 3)
Although the semiconductor device 1 of the above-described embodiment includes only one semiconductor element 100, the semiconductor device 1 may include a plurality of semiconductor elements 100. Each semiconductor element 100 preferably has at least some of the pads connected to each other.

FIG. 16 is a diagram schematically illustrating a semiconductor device 1c according to the present modification, with the circuit inside the semiconductor device 1c superimposed on the top view. In FIG. 16, portions corresponding to the semiconductor element 100e and the semiconductor element 100f are indicated by broken lines. The semiconductor device 1c includes a semiconductor element 100e and a semiconductor element 100f. The pad 11e of the semiconductor element 100e and the pad 11f of the semiconductor element 100f are connected through the semiconductor element side wiring layer 14e of the semiconductor element 100e, the semiconductor element side wiring layer 14f of the semiconductor element 100f, and the inter-semiconductor element connection wiring layer 240. It is connected.
The semiconductor device 1c shown in FIG. 16 includes the two semiconductor elements 100e and 100f, but may include three or more semiconductor elements.

  In the semiconductor device 1c, the semiconductor element 100e includes a package side wiring layer 24e connected to a solder ball 25e serving as an external connection terminal, and the semiconductor element 100f includes a package side wiring connected to the solder ball 25f serving as an external connection terminal. A layer 24f is provided.

  FIG. 17 is a diagram schematically showing a cross section of the semiconductor device 1c. The semiconductor element 100e is connected to a solder ball 25e, which is an external connection terminal, via an input / output terminal 21e, an input / output terminal conducting portion 23e, and a package side wiring layer 24e. The semiconductor element 100f is connected to a solder ball 25f, which is an external connection terminal, via an input / output terminal 21f, an input / output terminal conducting portion 23f, and a package side wiring layer 24f. The semiconductor element 100 e and the semiconductor element 100 f are formed on one surface of the package-side insulating layer 22, and are connected by an inter-semiconductor-element connection wiring layer 240 that extends along the package-side insulating layer 22. The inter-semiconductor element connection wiring layer 240 extends to a region vertically above the semiconductor elements 100e and 100f and is included in the package-side wiring layer 24.

  The semiconductor device 1c of this modification includes a semiconductor element 100e and a semiconductor element 100f, and the pad 11e of the semiconductor element 100e is connected to the pad 11f of the semiconductor element 100f via the package side wiring layer 24. Accordingly, it is possible to provide the semiconductor device 1 designed with a higher degree of freedom using a plurality of semiconductor elements 100 connected to each other.

(Second Embodiment)
The semiconductor device 2 of the second embodiment has the same configuration as that of the semiconductor device 1 according to the first embodiment, except that the package-side wiring layer 24 is formed after the semiconductor element is molded. This is different from the manufacturing method shown in the first embodiment. The same parts as those of the first embodiment are referred to by the same reference numerals as those of the first embodiment, and description thereof will be omitted depending on the case.

  FIG. 18 is a diagram schematically showing a cross section of the semiconductor device 2 of the second embodiment. The semiconductor device 2 includes a semiconductor element 1100, a package side wiring structure 1200, solder balls 25, and a mold resin 30. The semiconductor device 2 differs from the semiconductor device 1 of the first embodiment in the configuration of the semiconductor element 1100 and the configuration of the package side wiring structure 1200. Compared with the semiconductor element 100 of the first embodiment, the semiconductor element 1100 does not include the solder plating 16 and the surface opposite to the terminal formation surface S of the semiconductor element 1100 is exposed on the surface of the semiconductor device 2. The point is different. The package-side wiring structure 1200 is different from the package-side wiring structure 200 of the first embodiment in that it does not include the input / output terminal conductive portion 23, and includes the package-side insulating layer conductive portion 26 and the solder resist layer 27. Is different.

  The package-side insulating layer conducting portion 26 is configured to include a metal such as copper, and connects the columnar structure 15 and the package-side wiring layer 24. The solder resist layer 27 includes an organic material resin such as polyimide or epoxy. The solder resist layer 27 is preferably formed with a thickness of 20 μm or more and 50 μm or less.

(Manufacturing method of the semiconductor device 2)
Below, the flow of the manufacturing method of the semiconductor device 2 is demonstrated. The semiconductor element 1100 can be manufactured by not forming the solder plating 16 in the eighth step (FIG. 8A) of the method for manufacturing the semiconductor element 100. A method of molding the semiconductor element 1100 to form a semiconductor package will be described with reference to FIGS.

  19 and 20 are diagrams schematically showing a method of manufacturing the semiconductor device 2 by a chip first method in which a rewiring layer is formed after molding a semiconductor element. 19A to 19C and FIGS. 20A to 20D are shown in chronological order. The semiconductor device 2 can be mass-produced efficiently at low cost by using the following manufacturing method using, for example, a panel having a size of several tens of cm in length and width.

  FIG. 19A is a diagram showing a process I for manufacturing the semiconductor device 2. In step I, the semiconductor element 1100 is placed on the fixing layer 62 made of a sheet-like fixing material, which is formed on the support substrate 61, using a mounter or the like.

  FIG. 19B is a diagram illustrating a process II of manufacturing the semiconductor device 2. In step II, the semiconductor element 1100 is sealed with a mold resin 30 containing an epoxy resin or the like.

  FIG. 19C is a diagram showing a process III of manufacturing the semiconductor device 2. In step III, the support substrate 61 and the fixed layer 62 are removed, and the surface of the sealing body 300 where the columnar structures 15 are exposed is appropriately polished.

  FIG. 20A is a diagram showing a process IV of manufacturing the semiconductor device 2. In step IV, the surface of the sealing body 300 opposite to the surface on which the columnar structure 15 is exposed is polished to expose the semiconductor element 1100.

  FIG. 20B is a diagram illustrating a process V of manufacturing the semiconductor device 2. In step V, the package-side insulating layer 22 including an epoxy resin or the like is formed on the sealing body 300, and an opening (via) 220 is formed by a laser or the like.

  FIG. 20C is a diagram illustrating a process VI for manufacturing the semiconductor device 2. In step VI, the package side wiring layer 24 and the package side insulating layer conducting portion 26 are formed by electrolytic copper plating using a photoresist, a seed layer, or the like as appropriate.

  FIG. 20D shows a process VI for manufacturing the semiconductor device 2. In Step VI, the solder resist layer 27, the input / output terminals 21 and the solder balls 25 are formed, and the semiconductor device 2 is obtained.

According to the second embodiment described above, the following functions and effects can be obtained in addition to the functions and effects obtained by the first embodiment.
(1) In the manufacturing method of the semiconductor device 2 of the present embodiment, after forming the sealing body 300, the package-side insulating layer 22 is formed on the sealing body 300, and the package-side insulating layer 22 is formed. Forming a package-side wiring layer 24. As a result, the semiconductor device 2 can be manufactured while saving time and cost as appropriate.

The following modifications are also within the scope of the present invention, and can be combined with the above-described embodiment. In the following modified examples, portions having the same structure and function as those of the above-described embodiment are referred to by the same reference numerals, and description thereof will be omitted as appropriate.
(Modification 1)
In the semiconductor device 2 of the above-described embodiment, the solder ball 25 and the input / output terminal 21 are directly connected, but may be connected via the conductive trapezoidal structure 28.

  FIG. 21 is a diagram schematically showing a cross section of the semiconductor device 2a of the present modification. The semiconductor device 2 a includes a trapezoidal structure 28. The trapezoidal structure 28 includes a metal such as copper, and is preferably formed by using the UBM technique in order to improve the adhesion of the solder balls 25.

  The present invention is not limited to the contents of the above embodiment. Other embodiments conceivable within the scope of the technical idea of the present invention are also included in the scope of the present invention.

DESCRIPTION OF SYMBOLS 1, 2 ... Semiconductor device, 12 ... Semiconductor element side insulating layer, 14 ... Semiconductor element side wiring layer, 15 ... Columnar structure, 22 ... Package side insulating layer, 24 ... Package side wiring layer, 100, 1100 ... Semiconductor element, 200, 1200 ... package-side wiring structure, S ... terminal forming surface.

Claims (13)

A first insulating layer disposed on a terminal formation surface on which a connection terminal of a semiconductor chip is formed; and a first wiring layer formed on the first insulating layer and connected to the connection terminal. A semiconductor element comprising:
A sealing resin for sealing the semiconductor element;
A second insulating layer formed on the sealing resin;
Connected to the first wiring layer, formed on one surface of the second insulating layer, and from a region vertically above the terminal forming surface to an outer region vertically above the terminal forming surface of the second insulating layer. A second wiring layer extending;
A semiconductor device comprising: The semiconductor device according to claim 1,
A semiconductor device comprising an external connection terminal connected to the second wiring layer and disposed in a region outside the terminal formation surface on the second insulating layer and above the terminal formation surface. The semiconductor device according to claim 2,
A semiconductor device in which a part of the external connection terminals overlaps with the connection terminals when the external connection terminals are projected onto a plane including the terminal formation surface. In the semiconductor device according to any one of claims 1 to 3,
When the circuit of the first wiring layer and the second wiring layer is projected onto a plane including the terminal formation surface, the circuit of the first wiring layer connected to the different connection terminals at least in one place and the circuit of the first wiring layer A semiconductor device intersecting with a circuit of the second wiring layer. In the semiconductor device according to any one of claims 1 to 4,
The first insulating layer and the second insulating layer are semiconductor devices containing different types of resins. The semiconductor device according to any one of claims 1 to 5,
A semiconductor device in which the thickness of the first insulating layer is smaller than the thickness of the second insulating layer. In the semiconductor device according to any one of claims 1 to 6,
For at least some of the connection terminals, the center of the terminal formation surface and the connection terminal projected to the terminal formation surface are connected to the connection terminal, rather than the distance between the center of the terminal formation surface and the connection terminal. A semiconductor device in which the distance between the first wiring layer and the conductive portion between the second wiring layer is shorter. In the semiconductor device as described in any one of Claim 1-7,
The semiconductor element includes a first semiconductor element and a second semiconductor element,
The semiconductor device wherein the connection terminal of the first semiconductor element is connected to the connection terminal of the second semiconductor element via the second wiring layer. In the semiconductor device according to any one of claims 1 to 8,
With a conductive columnar structure,
The first wiring layer and the second wiring layer are semiconductor devices connected via the columnar structures. The semiconductor device according to any one of claims 1 to 9,
A semiconductor device comprising a conductive trapezoidal structure connected to the second wiring layer. Preparing a semiconductor wafer having a plurality of semiconductor chip formation regions in which connection terminals connected to an internal circuit are formed;
Forming a first insulating layer on a terminal formation surface on which the connection terminal of each of the semiconductor chip formation regions is formed;
Forming a first wiring layer connected to the connection terminal on the first insulating layer;
Separating the semiconductor wafer on which the first wiring layer is formed to obtain a semiconductor element;
Forming a wiring structure comprising a second insulating layer and a second wiring layer;
Sealing the acquired semiconductor element to form a sealing body;
With
The second wiring layer is connected to the first wiring layer, and is located on the second insulating layer from the region vertically above the terminal forming surface and above the terminal forming surface of the second insulating layer. A method of manufacturing a semiconductor device formed so as to extend to the region. In the manufacturing method of the semiconductor device according to claim 11,
A method of manufacturing a semiconductor device, wherein the obtained semiconductor element is bonded to a package substrate including the wiring structure, and then the semiconductor element is sealed to form the sealing body. In the manufacturing method of the semiconductor device according to claim 11,
After forming the sealing body, forming the second insulating layer on the sealing body;
Forming the second wiring layer on the second insulating layer;
A method for manufacturing a semiconductor device comprising:

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