JP4427874B2 - Multilayer wiring board manufacturing method and multilayer wiring board - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer wiring board on which a semiconductor chip is mounted, and relates to a method for manufacturing a multilayer wiring board that performs electrical connection and adhesion between layers at the same time, and a multilayer wiring board manufactured by the manufacturing method.
[0002]
[Prior art]
In recent years, with the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration and further high-density mounting of electronic components have progressed. Semiconductor packages used in these electronic devices have been In addition, the size and number of pins are increasing.
[0003]
A conventional circuit board is called a printed wiring board, and after patterning a copper foil attached to a glass epoxy board made of a laminated board in which a glass fiber woven fabric is impregnated with an epoxy resin, a plurality of sheets are laminated and adhered. The mainstream is to use a wiring board in which a through hole is made with a drill, and copper is plated on the wall surface of this hole to form a via and make an electrical connection between layers. However, with the progress of downsizing and increasing the density of mounted components, the above wiring board is insufficient in wiring density, causing problems in mounting components.
[0004]
Against this background, in recent years, build-up multilayer wiring boards have been adopted. The build-up multilayer wiring board is molded while stacking an insulating layer made of only resin and a conductor. As a via forming method, a high density can be achieved by freely arranging small-diameter via holes, such as a laser method, a plasma method and a photo method, instead of a conventional drilling process. Examples of the interlayer connection include a buried via and a buried via (Buried Via: a structure in which a via is filled with a conductor), and a buried via hole capable of forming a stacked via on the via is particularly noted. ing. The burred via hole is divided into a method of filling the via hole with plating and a case of filling with a conductive paste or the like. On the other hand, as a method of forming a wiring pattern, there are a method of etching a copper foil (subtractive method), a method of electrolytic copper plating (additive method), etc., and an additive method that can cope with a higher wiring density is particularly noted. Being started.
[0005]
Since a semiconductor package using such a multilayer wiring board has a very large number of pins, the multilayer wiring board is generally larger in size than a semiconductor chip. Therefore, from the viewpoint of handling properties of the multilayer wiring board, it is natural that the multilayer wiring board needs to be rigid. At present, in order to ensure the rigid property of the multilayer wiring board, the rigid property of the printed wiring board (glass epoxy substrate such as FR-4) having an insulating layer in which a reinforcing fiber is impregnated with resin is used on both sides. Build-up layers are stacked. However, a printed wiring board having an insulating layer in which a reinforcing fiber is impregnated with a resin may cause a dielectric breakdown at the interface between the reinforcing fiber and the resin, leaving a problem in the insulating characteristics.
[0006]
On the other hand, “conventional technology” in Japanese Patent Application Laid-Open No. 11-1111887 describes a stiffener (reinforcing frame) of a tape BGA. It is common to affix a stiffener on the tape BGA, and the purpose is to ensure the rigid property of the tape BGA from the viewpoint of the handleability of the tape BGA. As a result, the solder balls can be smoothly mounted. The tape BGA uses polyimide or the like as an insulating layer, that is, the insulating layer is made of a resin not filled with reinforcing fibers, and therefore has good insulating characteristics. However, since tape BGA is difficult to be multi-layered, it cannot be adopted as a super multi-pin semiconductor package. In order to prevent unwanted radiation of noise and improve heat dissipation characteristics, it is preferable to connect the stiffener to the ground wiring pattern. However, since an adhesive having high insulation and thermal conductivity is used for bonding the tape BGA and the stiffener, improvement in heat dissipation characteristics can be expected, but there is a problem that it cannot cope with prevention of unnecessary radiation.
[0007]
[Problems to be solved by the invention]
An object of the present invention is to provide a multilayer wiring board having not only rigid properties but also excellent heat dissipation characteristics and noise characteristics in view of such problems in a multilayer wiring board on which a semiconductor chip is mounted.
[0008]
[Means for Solving the Problems]
The present invention is a method for producing a multilayer wiring board comprising a step of forming a resist metal layer and a wiring pattern by electrolytic plating using a metal plate as a lead for electrolytic plating, and a step of removing the metal plate by etching, A step of forming a metal frame on the outermost layer of the multilayer wiring board by partially etching away the metal plate used when forming the outermost layer on the side of mounting the semiconductor chip of the multilayer wiring board And a step of conductively connecting the metal frame to a ground wiring pattern provided on the multilayer wiring board. It is a manufacturing method of the multilayer wiring board characterized by including.
[0009]
The method for producing a multilayer wiring board of the present invention comprises a step of forming a resist metal layer and a wiring pattern by electrolytic plating using a metal plate as a lead for electrolytic plating, and a step of removing the metal plate by etching. The process is repeated, and the outermost layer of the multilayer wiring board is removed by partially etching and removing the metal plate used when forming the outermost layer on the side of the multilayer wiring board on which the semiconductor chip is mounted. Basically, the method includes a step of forming a metal frame on the top, a step of forming a resist metal layer and a wiring pattern by electrolytic plating, using a metal plate as a lead for electrolytic plating, and forming an insulating film on the wiring pattern Process, forming vias in the insulating film so that part of the wiring pattern is exposed, and electroplating the conductor posts using a metal plate as the lead for electrolytic plating. Forming a bonding metal material layer on at least one of the surface of the conductor post or the connected portion of the connected layer, and bonding to at least one of the surface of the insulating film or the surface of the connected layer A step of forming an agent layer, a step of bonding a conductor post and a portion to be bonded by a bonding metal material layer via an adhesive layer, and bonding an insulating film and a layer to be connected by an adhesive layer, a metal plate And removing the metal plate used for forming the outermost layer on the side of mounting the semiconductor chip of the multilayer wiring board by partially etching and removing the multilayer wiring. It is preferable to include a step of forming a metal frame on the outermost layer of the plate. Furthermore, the insulating film is preferably made of a resin not filled with reinforcing fibers, and the metal frame is formed of a multilayer wiring board. Provided in Ground wiring pattern When Conductive connection Including a process Even more preferred.
[0010]
The multilayer wiring board of the present invention is obtained by the above-described method for manufacturing a multilayer wiring board.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited thereto.
[0012]
FIGS. 1A to 4R are diagrams for explaining an example of a method for manufacturing a multilayer wiring board according to an embodiment of the present invention. FIG. 4R shows the structure of the resulting multilayer wiring board. It is sectional drawing shown.
[0013]
As a method for manufacturing a multilayer wiring board according to the present invention, first, a patterned plating resist 102 is formed on a metal plate 101 (FIG. 1A). The plating resist 102 can be formed, for example, by laminating an ultraviolet-sensitive dry film resist on the metal plate 101, selectively exposing it using a negative film or the like, and then developing it. The material of the metal plate 101 may be any material as long as it is suitable for the manufacturing method of the present invention. In particular, the metal plate 101 is resistant to the chemical used and can be finally removed by etching. It is necessary to be. Examples of the material of the metal plate 101 include copper, copper alloy, 42 alloy, and nickel.
[0014]
Next, the resist metal layer 103 is formed by electrolytic plating using the metal plate 101 as a lead for electrolytic plating (FIG. 1B). By this electrolytic plating, a resist metal layer 103 is formed on a portion of the metal plate 101 where the plating resist 102 is not formed. The material of the resist metal layer 103 may be any material as long as it is suitable for the manufacturing method of the present invention. In particular, the resist metal layer 103 is resistant to a chemical solution used when the metal plate 101 is finally removed by etching. It is necessary to have. Examples of the material of the resist metal layer 103 include nickel, gold, tin, silver, solder, palladium, and the like. The purpose of forming the resist metal layer 103 is to prevent the wiring pattern 104 shown in FIG. 1C from being eroded and corroded by the chemical solution used when the metal plate 101 is etched. Therefore, when the wiring pattern 104 shown in FIG. 1C is resistant to the chemical used when the metal plate 101 is etched, the resist metal layer 103 is unnecessary. The resist metal layer 103 does not have to be the same pattern as the wiring pattern 104, and the resist metal layer 103 may be formed on the entire surface of the metal plate 101 before the plating resist 102 is formed on the metal plate 101. .
[0015]
Next, the wiring pattern 104 is formed by electrolytic plating using the metal plate 101 as a lead for electrolytic plating (FIG. 1C). By this electrolytic plating, a wiring pattern 104 is formed on a portion of the metal plate 101 where the plating resist 102 is not formed. Any material can be used as the material of the wiring pattern 104 as long as it is suitable for the manufacturing method of the present invention. In particular, the wiring pattern 104 is resistant to a chemical solution used when the resist metal layer 103 is finally removed by etching. It is necessary to have Actually, it is best to select a material for the resist metal layer 103 that can be etched with a chemical solution that does not erode or corrode the wiring pattern 104. Examples of the material of the wiring pattern 104 include copper, nickel, gold, tin, silver, palladium, and the like. Furthermore, by using copper, a stable wiring pattern 104 can be obtained with low electrical resistance.
[0016]
Next, the plating resist 102 is removed (FIG. 1D), and an insulating film 105 is formed on the formed wiring pattern 104 (FIG. 1E). Any resin can be used for the insulating film 105 as long as it is suitable for the manufacturing method of the present invention. In particular, it is preferable to form the insulating film 105 made of a resin not filled with reinforcing fibers (for example, glass cloth). The insulating film 105 may be formed by a method suitable for the resin to be used. The resin varnish may be directly applied by printing, curtain coating, bar coating, or the like, or a dry film type resin may be vacuum laminated or vacuum pressed. The method of laminating | stacking by the method of these etc. is mentioned. In particular, a commercially available copper foil with resin is easy to obtain, and if the concave and convex portions of the wiring pattern 104 are embedded by vacuum lamination and finally the copper foil is etched, the surface of the insulating film 105 becomes the wiring pattern 104. It becomes very flat without being affected by unevenness. In addition, since a fine rough shape on the surface of the copper foil is transferred to the surface of the insulating film 105, adhesion with the adhesive layer 109 shown in FIG. 2 (i) can be ensured.
[0017]
Next, a via 106 is formed in the formed insulating film 105 (FIG. 1F). Any method may be used for forming the via 106 as long as it is suitable for the manufacturing method of the present invention, and examples thereof include laser, plasma dry etching, and chemical etching. In the case where the insulating film 105 is made of a photosensitive resin, the via 106 can be formed by selectively exposing and developing the insulating film 105.
[0018]
Next, the conductor post 107 is formed by electrolytic plating using the metal plate 101 as a lead for electrolytic plating (FIG. 2G). By this electrolytic plating, a conductor post 107 is formed in a portion of the insulating film 105 where the via 106 is formed. If the conductor post 107 is formed by electrolytic plating, the shape of the tip of the conductor post 107 can be freely controlled. The material of the conductor post 107 may be any material as long as it is suitable for the manufacturing method of the present invention, and examples thereof include copper, nickel, gold, tin, silver, and palladium. Furthermore, by using copper, a stable conductor post 107 can be obtained with low electrical resistance.
[0019]
Next, the bonding metal material layer 108 is formed on the surface (tip) of the conductor post 107 (FIG. 2H). Examples of the method for forming the bonding metal material layer 108 include a method of forming by electroless plating, a method of forming the metal plate 101 by electrolytic plating using the electroplating lead, and a method of printing a paste containing the bonding metal material. It is done. In the printing method, it is necessary to accurately align the printing mask with respect to the conductor post 107. However, in the method using electroless plating or electrolytic plating, the bonding metal material layer 108 is formed in addition to the surface of the conductor post 107. Therefore, the conductor posts 107 can be easily miniaturized and densified. In particular, the electrolytic plating method is very suitable because the metal that can be plated is more diverse and the chemical solution can be easily managed than the electroless plating method. The material of the bonding metal material layer 108 may be any metal as long as it can be metal-bonded to the bonded portion 112 shown in FIG. 2 (j), for example, solder. Among the solders, it is preferable to use Sn, In, or solder composed of at least two of Sn, Ag, Cu, Zn, Bi, Sb, Pb, In, and Au. More preferably, it is an environmentally friendly Pb-free solder. 2H shows an example in which the bonding metal material layer 108 is formed on the surface of the conductor post 107. The purpose of forming the bonding metal material layer 108 is to form the conductor post 107 and the bonded portion 112. Therefore, the bonding metal material layer 108 may be formed on the bonded portion 112. Of course, it may be formed on both surfaces of the conductor post 107 and the bonded portion 112.
[0020]
Next, an adhesive layer 109 is formed on the surface of the insulating film 105 (FIG. 2I). Formation of the adhesive layer 109 may be performed by a method suitable for the adhesive resin to be used. The resin varnish is directly applied by a method such as printing, curtain coating, or bar coating, or a dry film type resin is vacuum laminated. The method of laminating | stacking by methods, such as a vacuum press, is mentioned. Note that although FIG. 2I shows an example in which the adhesive layer 109 is formed on the surface of the insulating film 105, the adhesive layer 109 may be formed on the surface of the connected layer 111. Needless to say, they may be formed on both surfaces of the insulating film 105 and the connected layer 111.
[0021]
Next, the connection layer 110 and the connection layer 111 obtained by the above-described steps are aligned (FIG. 2 (j)). For alignment, a method of reading and aligning positioning marks formed in advance on the connection layer 110 and the connected layer 111 with an image recognition device, a method of aligning with positioning pins, or the like can be used. Note that the connected layer 111 illustrated in FIG. 2J can be obtained by a process similar to the process illustrated in FIGS.
[0022]
Next, the connection layer 110 and the connection layer 111 are stacked (FIG. 2K). As a laminating method, for example, using a vacuum press, pressure is applied until the conductor post 107 is metal-bonded to the bonded portion 112 by the bonding metal material layer 108 via the adhesive layer 109, and further heated and bonded. The agent layer 109 can be cured to bond the connection layer 110 and the connection target layer 111.
[0023]
Next, the metal plate 101 of the connection layer 110 is removed by etching (FIG. 3L). A resist metal layer 103 is formed between the metal plate 101 and the wiring pattern 104, and the resist metal layer 103 is resistant to a chemical solution used when the metal plate 101 is removed by etching. Therefore, even if the metal plate 101 is etched, the resist metal layer 103 is not eroded / corroded, and as a result, the wiring pattern 104 is not eroded / corroded. When the material of the metal plate 101 is copper and the material of the resist metal layer 103 is nickel, tin, or solder, a commercially available ammonia-based etching solution can be used. When the material of the metal plate 101 is copper and the material of the resist metal layer 103 is gold or silver, most etching solutions including ferric chloride solution and cupric chloride solution can be used.
[0024]
Next, the resist metal layer 103 is removed by etching (FIG. 3M). Since the wiring pattern 104 is resistant to a chemical used when the resist metal layer 103 is removed by etching, the wiring pattern 104 is not eroded or corroded. Therefore, the wiring pattern 104 is exposed by removing the resist metal layer 103. When the material of the wiring pattern 104 is copper and the material of the resist metal layer 103 is nickel, tin, or solder, a commercially available solder / nickel stripper (for example, Mitsubishi Gas Chemical Co., Ltd., Pewtax) can be used. When the material of the wiring pattern 104 is copper and the material of the resist metal layer 103 is gold, it is difficult to etch the resist metal layer 103 without eroding and corroding the wiring pattern 104. In this case, the step of etching the resist metal layer 103 may be omitted and the resist metal layer 103 may be left.
[0025]
Subsequently, by repeating the above-described steps, that is, FIG. 1A to FIG. 3M, another layer is produced for the multilayer wiring board 113 being manufactured (see FIG. 3M). A laminated product can be obtained (FIG. 3 (n)).
[0026]
The processes shown in FIGS. 3O to 4P are diagrams for explaining the process of forming the outermost layer 117a of the multilayer wiring board 113. FIG. Similar to the steps shown in FIGS. 2J to 2K, the steps shown in FIGS. 3O to 4P are performed by aligning the connecting layer and the connected layer (FIG. 3O). ), And a connection layer and a connection layer (FIG. 4 (p)).
[0027]
Next, the metal plate 101a is completely removed by etching, and only the portion on which the semiconductor chip 202 is mounted is removed by etching to form the metal frame 116 (FIG. 4 (q)). Since the multilayer wiring board 113 has the metal frame 116, the multilayer wiring board 113 has a rigid property even when the insulating film 105 is made of a resin not filled with reinforcing fibers (for example, glass cloth). The insulating film 105a can be applied directly to a metal plate by directly applying a resin varnish by printing, curtain coating, bar coating, or by laminating a dry film type resin by vacuum lamination, vacuum pressing, or the like. Since it is formed on 101b, the adhesion between the insulating film 105a and the metal frame 116 is enhanced.
[0028]
Finally, the solder resist 115 is formed on the surface of the outermost layer 117b, and the portion of the pad 114b is opened to obtain the multilayer wiring board 113 (FIG. 4 (r)). When the wiring pattern 104 is not formed on the outermost layer 117b and only the pad 114b is formed, the solder resist 115 need not be formed. The same applies to the other outermost layer 117a. In the case of FIG. 4 (r), since only the pad 114a is formed, it is not necessary to form a solder resist. Further, it is not necessary to remove the resist metal layers 118a and 118b used when forming the outermost layers 117a and 117b. That is, the resist metal layers 118a and 118b are used as plating films applied to the pads 114a and 114b formed on both surfaces of the multilayer wiring board 113. Examples of the material of the resist metal layers 118a and 118b include gold, silver, palladium, nickel, and solder. The resist metal layers 118a and 118b may have a layer structure including any two or more of gold, silver, palladium, and nickel. Further, when the wiring pattern 104 is made of copper, a two-layer structure of gold and nickel is preferable. Thereby, it is possible to prevent the solder of the solder balls mounted on the pads 114 a and 114 b from diffusing into the copper of the wiring pattern 104. Furthermore, by electrically connecting the metal frame 116 to the ground wiring pattern 119 of the multilayer wiring board 113, not only the unnecessary radiation of noise from the semiconductor device 201 can be reduced, but also the heat dissipation characteristics of the semiconductor device 201 can be improved. be able to.
[0029]
Through the above steps, a multilayer wiring board having the metal frame 116 on the side on which the semiconductor chip 202 is mounted of the multilayer wiring board 113 can be manufactured.
[0030]
The manufacturing method of the multilayer wiring board according to the present invention and the characteristics of the manufactured multilayer wiring board are as follows.
(1) The metal frame 116 can be formed by partially etching the metal plate 101b used at the time of manufacture.
(2) Since the multilayer wiring board 113 has the metal frame 116, the multilayer wiring board 113 has a rigid property even when the insulating film 105 is made of a resin not filled with reinforcing fibers (for example, glass cloth).
(3) Conductive connection of the metal frame 116 to the ground wiring pattern 119 of the multilayer wiring board 113 can not only reduce unnecessary radiation of noise from the semiconductor device 201, but also improve the heat dissipation characteristics of the semiconductor device 201. be able to.
[0031]
The semiconductor device 201 can be obtained by mounting the semiconductor chip 202 on the pad 114a side of the multilayer wiring board 113 obtained by the above-described process and mounting the solder ball 205 on the pad 114b side (FIG. 5). .
[0032]
【Example】
Hereinafter, the present invention will be described more specifically with reference to examples, but the present invention is not limited thereto.
[0033]
Example of adhesive formulation
100 g of m, p-cresol novolak resin (Nippon Kayaku Co., Ltd. PAS-1, OH group equivalent 120) and bisphenol F type epoxy resin (Nippon Kayaku Co., Ltd. RE-404S, epoxy group equivalent 165) 140 g Was dissolved in 60 g of cyclohexanone, and 0.2 g of triphenylphosphine (manufactured by Hokuko Chemical Co., Ltd.) was added as a curing catalyst to prepare an adhesive varnish.
[0034]
Example (manufacturing example of multilayer wiring board)
A dry film resist (AQ-2058 manufactured by Asahi Kasei) is roll-laminated to a 150 micron thick rolled copper plate (metal plate 101, EFTEC-64T manufactured by Furukawa Electric Co., Ltd.) whose surface has been roughened, and is exposed to light using a predetermined negative film. Development was performed to form a plating resist (plating resist 102) necessary for forming the wiring pattern 104. Next, using a rolled copper plate as a lead for electrolytic plating, a resist metal layer (resist metal layer 103) made of nickel was formed by electrolytic plating, and a wiring pattern (wiring pattern 104) was further formed by electrolytic copper plating. The wiring pattern was line width / line spacing / thickness = 20 microns / 20 microns / 10 microns. Next, a copper foil with resin (APL manufactured by Sumitomo Bakelite Co., Ltd.) was formed by embedding the wiring pattern irregularities by vacuum lamination, and the copper foil was entirely etched to form an insulating film (insulating film 105) having a thickness of 25 microns. Next, a 50 micron diameter via (via 106) was formed by a UV-YAG laser. Next, the rolled copper plate was used as a lead for electrolytic plating, and the via was filled with copper by electrolytic copper plating to form a copper post (conductor post 107). Next, the Sn-Pb eutectic solder layer (joining metal material layer 108) was formed on the copper post by electrolytic plating using the rolled copper plate as the lead for electrolytic plating. Next, the above-mentioned adhesive varnish is applied to the surface of the insulating film, that is, the surface on which the Sn—Pb eutectic solder is formed by bar coating, followed by drying at 80 ° C. for 20 minutes, and an adhesive layer having a thickness of 10 microns. (Adhesive layer 109) was formed. A build-up layer (connection layer 110) was obtained by the steps so far. On the other hand, in the same manner as described above, a resist metal layer (resist metal layer 118b) is formed on the rolled copper plate by electrolytic nickel / gold plating, a wiring pattern is formed by electrolytic copper plating, and a land (bonded portion 112). A to-be-connected layer (connected layer 111) was obtained. Next, the positioning marks formed in advance in the build-up layer and the connected layer obtained by the above-described steps were read by an image recognition device, both were aligned, and temporarily pressed at a temperature of 100 ° C. This was heated and pressed by a press at a temperature of 220 ° C., the copper post penetrated the adhesive layer and soldered to the land, and the buildup layer was adhered to the connected layer by the adhesive layer. Next, the rolled copper plate of the buildup layer was removed by etching using an ammonia-based etchant, and nickel was removed by etching using a solder / nickel remover (Mitsubishi Gas Chemical Co., Ltd./Petax). Furthermore, the above-described steps were repeated to laminate another buildup layer. However, the resist metal layer (resist metal layers 118a and 118b) when forming the outermost layer (outermost layers 117a and 117b) has a two-layer structure of nickel / gold. Subsequently, a metal frame (metal frame 116) was formed by etching the rolled copper plate on the side where the semiconductor chip is mounted, and the entire surface was removed by etching the rolled copper plate on the connected layer side. Finally, a solder resist (solder resist 115) was formed. Through the above steps, a multilayer wiring board (multilayer wiring board 113) having a metal frame and having an insulating film made of a resin not filled with reinforcing fibers could be obtained.
[0035]
【The invention's effect】
Since the multilayer wiring board obtained by the present invention has a metal frame, even when the insulating film is made of a resin that is not filled with reinforcing fibers, it has a rigid property, so that it can ensure handling properties, and further has an insulating property. Can be greatly improved. In addition, by conducting the ground wiring pattern to the metal frame, the heat dissipation characteristics of the semiconductor device can be greatly improved. Furthermore, unnecessary radiation from the semiconductor device can be prevented and high-speed operation can be supported. A multilayer wiring board can be manufactured.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an example of a method for manufacturing a multilayer wiring board according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing an example of a method for manufacturing a multilayer wiring board according to an embodiment of the present invention (continuation of FIG. 1).
3 is a cross-sectional view showing an example of a method for manufacturing a multilayer wiring board according to an embodiment of the present invention (continuation of FIG. 2).
4 is a cross-sectional view showing an example of a method for manufacturing a multilayer wiring board according to an embodiment of the present invention (continuation of FIG. 3).
FIG. 5 is a cross-sectional view showing an example of a semiconductor device manufactured using the multilayer wiring board according to the embodiment of the present invention.
[Explanation of symbols]
101 metal plate
101a metal plate
101b metal plate
102 Plating resist
103 resist metal layer
104 Wiring pattern
105 Insulating film
106 Via
107 Conductor post
108 Metal material layer for bonding
109 Adhesive layer
110 Connection layer
111 Connected layer
112 Joined part
113 multilayer wiring board
114a pad
114b pad
115 solder resist
116 metal frame
117a outermost layer
117b outermost layer
118a Resist metal layer
118b Resist metal layer
201 Semiconductor device
202 Semiconductor chip
203 Bump
204 Underfill
205 Solder ball

Claims (5)

A method for producing a multilayer wiring board, comprising: a step of forming a resist metal layer and a wiring pattern by electrolytic plating using a metal plate as an electrolytic plating lead; and a step of removing the metal plate by etching, the multilayer wiring board Forming a metal frame on the outermost layer of the multilayer wiring board by partially etching and removing the metal plate used when forming the outermost layer on the side of mounting the semiconductor chip ; and A method of manufacturing a multilayer wiring board, comprising: a step of electrically connecting a frame to a ground wiring pattern provided on the multilayer wiring board.   A step of forming a resist metal layer and a wiring pattern by electrolytic plating using a metal plate as a lead for electrolytic plating, a step of forming an insulating film on the wiring pattern, and the insulating film so that a part of the wiring pattern is exposed Forming a via on the surface, forming a conductive post by electrolytic plating using the metal plate as a lead for electrolytic plating, and bonding to at least one of the surface of the conductive post or the surface of the connected portion of the connected layer A step of forming a metal material layer, a step of forming an adhesive layer on at least one of the surface of the insulating film or the surface of the connected layer, and the conductor post and the bonded portion via the adhesive layer. A method of manufacturing a multilayer wiring board comprising: a step of bonding with the bonding metal material layer, and bonding the insulating film and the connected layer with the adhesive layer; and a step of removing the metal plate by etching. A metal frame is formed on the outermost layer of the multilayer wiring board by partially etching and removing the metal plate used when forming the outermost layer on the side of the multilayer wiring board on which the semiconductor chip is mounted. A process for producing a multilayer wiring board comprising the step of forming   3. The method for manufacturing a multilayer wiring board according to claim 2, wherein the insulating film is made of a resin not filled with reinforcing fibers. Method for manufacturing a multilayer wiring board according to claim 2 or claim 3, further comprising the step of conductively connected with the ground wiring pattern provided with the metal frame to the multilayer wiring board.   A multilayer wiring board obtained by the method for manufacturing a multilayer wiring board according to any one of claims 1 to 4.

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