JP2010034430A - Wiring board and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress occurrence of electro-migration between wirings by reducing the resistivity of a wiring. <P>SOLUTION: The wiring board is manufactured by steps of: forming a resin layer 15 so as to cover the side of a base material 11 on which a wiring layer 13 is formed; forming trenches 15a corresponding to the shape of a wiring pattern on the surface of the resin layer 15, forming a first conductor layer 17 by means of electroless plating on the resin layer 15 including the wall and the bottom of each of the trenches 15a, forming a second conductor layer 18 in the trenches covered with the first conductor layer 17 by filling a conductive paste therein by means of screen printing, which is made of the same metal as that of the first conductor layer 17; and removing an exposed part of the first conductor layer 17. Moreover, when the trenches 15a are formed, a via-hole reaching the wiring layer 13 of the base material 11 is also formed in each of the trenches 15a, and the first conductor layer 17 is also formed on the wall and the bottom of each of the via-holes. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a wiring board (hereinafter also referred to as “semiconductor package” for convenience) used for mounting an electronic component such as a semiconductor element (chip) and a manufacturing method thereof.

  2. Description of the Related Art Recent electronic devices such as mobile terminals and mobile devices are required to have high functionality and downsizing (thinning), and in response to such demands, wiring boards (semiconductor packages) used in such electronic devices are used. ) Is also progressing in miniaturization and high density of wiring. As a technique for forming fine wiring, a process using a semi-additive method has been conventionally used. This is the target base material (resin substrate) after the necessary pretreatment (drilling for double-sided connection, surface roughening, desmear, catalyzed, etc.), then electroless copper (Cu) plating, Next, a plating resist pattern is formed, electrolytic Cu plating is applied to the pattern portion, and then unnecessary Cu portions are etched to form wiring.

  In such a semi-additive method, after electroless Cu plating is performed, only a necessary portion is subjected to electrolytic Cu plating using a plating resist to form a circuit (wiring), which is advantageous for forming fine wiring. It is disadvantageous in terms of processing time. That is, since a considerable amount of time is required for the electroless Cu plating and the electrolytic Cu plating, the time required for wiring formation accordingly increases. Therefore, for the purpose of improving productivity, a wiring forming technique by a screen printing method using a conductive paste has been put into practical use.

As a technique related to such a conventional technique, for example, as described in Patent Document 1, an insulating resin layer from which a portion to be a conductive circuit is removed is provided on one or both surfaces of an insulating plate, and the removed portion is provided on this removed portion. There is a conductive circuit filled with a conductive paste. In addition, as described in Patent Document 2, when electrical connection between printed wiring layers is performed by injecting and curing a conductive paste into a through hole, a conductor film such as copper is previously formed on the wall surface of the through hole. There is something to use.
JP-A-9-331136 JP-A-4-53188

  As described above, in the prior art, wiring formation using a conductive paste has been put to practical use in order to improve productivity, but this wiring formation has the following problems.

  First, since the thickness of the conductive paste printed as the wiring is limited, there is a problem that the conduction resistance value becomes large. That is, since the cross-sectional area of the conductive paste (wiring) (area of the surface orthogonal to the direction of current flow) is relatively small, the resistivity is increased and the resistivity of the entire wiring is increased. There was a problem.

  In addition, when fine wiring is printed in a thick state, electromigration (or ion migration) is likely to occur between adjacent wirings, causing a short circuit between the wirings and impairing insulation reliability. There was also. In relation to this, in the technique described in Patent Document 1 described above, a recess is provided in a portion of the insulating resin layer that becomes a conductive circuit, and the conductive circuit (wiring) is formed by filling the concave portion with a conductive paste. Thus, the occurrence of electromigration between adjacent wirings is suppressed.

  However, if further miniaturization and higher density of the wiring are to be realized, it is necessary to make the width and pitch of the recesses correspondingly, so that the recess is filled with the conductive paste as described above. However, it may not always be possible to effectively suppress the occurrence of electromigration. That is, in the screen printing method using a conductive paste, a method of filling a groove (concave portion) with a paste using a squeegee is generally used, but as the squeegee moves, the surface of the insulating substrate between adjacent concave portions is used. In some cases, a part (residue) of the paste adheres. In particular, when the recesses are provided at a narrow pitch, there is a high possibility that the adjacent wiring is short-circuited through the paste residue.

  The present invention was created in view of the problems in the prior art, and it is an object of the present invention to provide a wiring board that can reduce the resistivity of wiring and suppress the occurrence of electromigration between wirings, and a method for manufacturing the same. And

  In order to solve the above-described problems of the prior art, according to one aspect of the present invention, a step of forming a resin layer on a base substrate and a groove are formed on the surface of the resin layer according to the shape of the wiring pattern. A step of forming a first conductor layer on the resin layer including a wall surface and a bottom surface of the groove by electroless plating, and the groove covered with the first conductor layer, Filling a conductive paste made of the same metal as the first conductor layer by a screen printing method to form a second conductor layer; and removing the exposed portion of the first conductor layer. A method of manufacturing a wiring board is provided.

  According to the method for manufacturing a wiring board according to this embodiment, the first conductor layer and the second conductor formed on the groove are formed on the surface of the resin layer on the base substrate according to the shape of the wiring pattern. A wiring layer made of a conductive layer is embedded. That is, the wiring layer is formed in the groove and has a structure in which the first conductor layer and the second conductor layer are connected in parallel along the direction in which the current flows. With this structure, the first conductive layer and the second conductive layer are compared with the case where the wiring is formed by filling only the conductive paste in the concave portion of the insulating resin layer as seen in the above prior art. The resistivity of the wiring layer configured by parallel connection can be reduced.

  In addition, since the wiring layer embeds the second conductor layer (inner layer) in the groove with the first conductor layer (outer layer) formed so as to cover the wall surface and bottom surface of the groove, Even when grooves are provided at a narrow pitch in order to achieve further miniaturization, the occurrence of electromigration between adjacent wirings can be effectively suppressed. That is, since the outer layer (first conductor layer) of the wiring layer is formed by electroless plating and the inner layer (second conductor layer) of the wiring layer is formed by filling with conductive paste, the movement of the squeegee As a result, even if a part of the paste adheres to the portion between adjacent grooves, the attached portion is separated from the inner layer of the wiring layer in the adjacent groove by the thickness of the outer layer of the wiring layer. . As a result, the possibility of short-circuiting the adjacent wiring through part of the paste can be greatly reduced, which contributes to suppression of the occurrence of electromigration.

  Furthermore, since the first conductor layer and the second conductor layer are formed of the same metal, the outer layer (first conductor layer) and the inner layer (second conductor layer) constituting the wiring layer are in close contact with each other. Thus, the reliability of the wiring layer can be improved.

  Moreover, according to the other form of this invention, the wiring board which can be manufactured with the manufacturing method of the wiring board which concerns on said form is provided. The wiring board includes a base substrate, a resin layer provided on the base substrate and having grooves formed on the surface according to the shape of the wiring pattern, and a wiring layer embedded in the grooves of the resin layer. The wiring layer is formed by electroless plating so as to cover the wall surface and the bottom surface of the groove, and is formed on the first conductor layer by a screen printing method. And a second conductor layer made of the same metal as the conductor layer.

  Other structural features of the wiring board and the manufacturing method thereof according to the present invention and advantageous advantages based thereon will be described with reference to the embodiments of the invention described below.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the accompanying drawings.

  FIG. 1 is a sectional view showing steps of a method for manufacturing a wiring board according to an embodiment of the present invention (steps related to the present invention). FIG. 2 shows an example of a wiring board (semiconductor package) obtained by using the manufacturing method in the form of a sectional view, and FIG. 3 shows a state when a semiconductor element is mounted on the wiring board. (Semiconductor device) is shown in the form of a sectional view.

  First, the configuration of the wiring board (semiconductor package) 10 of this embodiment will be described with reference to FIG.

  In the illustrated wiring substrate (semiconductor package) 10, 11 is a core substrate as a base substrate of the wiring substrate, 12 is a conductor filled in a through hole formed in a required portion of the core substrate 11, and 13 and 14 are cores. A first wiring layer formed in a required pattern shape on both surfaces of the substrate 11 is shown. The wiring layers 13 and 14 are connected to each other through the conductors 12 in the core substrate 11 at required places.

  Reference numerals 15 and 16 denote interlayer insulation layers (resin layers) formed on the core substrate 11 so as to cover the wiring layers 13 and 14, respectively. The resin layers 15 and 16 each have a required wiring pattern on the surface. Grooves 15a and 16a are formed according to the shape, and via holes 15b and 16b reaching the pad portions of the wiring layers 13 and 14 are formed at required locations in the grooves. Reference numerals 17 and 19 denote first conductor layers (outer layers of the wiring layer) formed to cover the wall surfaces and bottom surfaces of the grooves 15a and 16a of the corresponding resin layers 15 and 16, respectively, and to cover the wall surfaces and bottom surfaces of the via holes 15b and 16b. , And 18 and 20 indicate second conductor layers (inner layers of the wiring layer) formed on the corresponding first conductor layers 17 and 19, respectively. The first and second conductor layers constitute a second wiring layer in the package 10. That is, the second wiring layers 17 and 18 (19 and 20) are formed so as to be embedded in the grooves 15a and 16a and the via holes 15b and 16b of the corresponding resin layers 15 and 16 as shown in the drawing, and the direction of current flow. The first conductor layers 17 and 19 and the second conductor layers 18 and 20 are connected in parallel with each other.

  Reference numerals 21 and 22 denote interlayer insulating layers (resin layers) formed so as to cover the corresponding wiring layers 18 and 20 and the resin layers 15 and 16, respectively. Grooves 21a and 22a are formed according to the shape of the required wiring pattern, and via holes 21b and 22b reaching the pad portions of the wiring layers 18 and 20 are formed at required positions in the groove. Reference numerals 23 and 25 respectively denote first conductor layers (outer layers of the wiring layer) formed to cover the wall surfaces and bottom surfaces of the grooves 21a and 22a of the corresponding resin layers 21 and 22, and further to cover the wall surfaces and bottom surfaces of the via holes 21b and 22b. , And 24 and 26 indicate second conductor layers (inner layers of the wiring layer) formed on the corresponding first conductor layers 23 and 25, respectively. The first and second conductor layers constitute a third wiring layer in the package 10. That is, the third wiring layers 23 and 24 (25 and 26) are also formed by being embedded in the grooves 21a and 22a and the via holes 21b and 22b of the corresponding resin layers 21 and 22 as shown in the figure. The first conductor layers 23 and 25 and the second conductor layers 24 and 26 are connected in parallel along the flowing direction.

  Reference numerals 27 and 28 denote solder resist layers as protective films formed so as to cover both surfaces except for the pad portions 24P and 26P defined at required portions of the corresponding wiring layers 24 and 26, respectively. Copper (Cu) is typically used as the material for the conductor 12 and the wiring layers 13, 14, 17 to 20, and 23 to 26, and the epoxy resin is typically used as the material for the resin layers 15, 16, 21, and 22. Is used.

  Further, the pad portions 24P and 26P exposed from the solder resist layers 27 and 28 are respectively connected to external connection terminals (chip terminal terminals of the chip mounted on the package 10, and when the package 10 is mounted on a mounting substrate such as a motherboard. Since the solder balls and pins used in the above are joined, nickel (Ni) plating and gold (Au) plating are applied to the pad portions (Cu) 24P and 26P in this order. This is to improve the contactability when the external connection terminals are joined, to improve the adhesion with Cu constituting the pad portions 24P and 26P, and to prevent Cu from diffusing into the Au layer. .

  Furthermore, for the pad portion 24P on the chip mounting surface side (upper side in the illustrated example), solder 29 is attached so that it can be easily connected to the electrode terminals of the chip at the time of mounting in consideration of the convenience of the customer. . On the other hand, the pad portion 26P on the side opposite to the chip mounting surface side is left exposed so that the external connection terminals can be joined as required by the customer. Alternatively, as indicated by a broken line in the figure, an external connection terminal such as a solder ball may be bonded to the pad portion 26P in advance.

  On the wiring board (semiconductor package) 10 configured as described above, a semiconductor element (chip) 40 can be surface-mounted via its electrode terminals 41 as shown as an example in FIG. The electrical connection between the chip 40 and the wiring board 10 is performed by reflow by bringing the electrode terminal 41 of the chip 40 into contact with the solder 29 attached to the pad portion 24P of the wiring board 10. Further, an underfill resin 42 such as an epoxy resin is filled in the gap between the wiring substrate 10 and the chip 40, and is fixed by thermosetting. In the illustrated semiconductor device 50, a solder ball 30 as an external connection terminal is bonded to the surface opposite to the chip mounting surface.

  Next, a method for manufacturing the wiring board (semiconductor package) 10 of the present embodiment will be described with reference to FIG. 1 showing an example of the manufacturing process (steps related to the present invention). In the illustrated example, only the configuration on one surface side (chip mounting surface side) of the wiring substrate is shown for the sake of simplicity. Further, for each member on the other surface side corresponding to the illustrated configuration, a reference number indicating the member is added in parentheses.

  First, in the first step (see FIG. 1A), a core substrate 11 is prepared as a base material, through holes are formed in the required locations, filled with conductors, and further wired in the required pattern shape on both sides. Layer 13 (14) is formed. For example, a glass cloth base epoxy resin copper-clad laminate widely used for printed wiring boards is prepared, and through holes are formed by drilling or the like at the required locations. Next, the conductor 12 (FIG. 2) is formed in the through hole by electrolytic Cu plating using the copper foils on both sides of the laminate as seed layers (feeding layers), or by screen printing or ink jet using a Cu paste. Filling). Further, the first wiring layer 13 (14) is formed in a required pattern shape on both surfaces of the core substrate 11 so as to be connected to the conductor 12 by a subtractive method, a semi-additive method, an ink jet method or the like. . When the semi-additive method or the ink jet method is used, the wiring layer 13 (14) can be formed simultaneously with the filling of the conductor 12 into the through hole, which contributes to simplification of the process.

  In the next step (see FIG. 1B), a semi-cured resin film made of an epoxy resin or the like is laminated on the wiring layer 13 (14) and the core substrate 11, and thermally cured to obtain an interlayer insulating layer. The resin layer 15 (16) is formed.

  In the next step (see FIG. 1C), an excimer laser, a CO 2 laser, a UV − is applied to a required portion of the resin layer 15 (16) formed on the core substrate 11 so as to cover the wiring layer 13 (14). Using a YAG laser or the like, a groove 15a (16a) corresponding to the shape of the second-layer wiring pattern is formed. Further, although not shown in the figure, via holes 15b (16b) reaching the pad portions of the lower wiring layer 13 (14) are formed at required locations in the groove by the same laser processing.

  When the laser processing is performed on the resin layer 15 (16) in this manner, a resin residue (resin smear) may remain on the bottom surface (on the lower wiring layer 13 (14)) of each via hole 15b (16b). If the resin smear remains, it becomes a cause of poor conduction between each via hole and the lower wiring layer 13 (14) when the conductive paste is filled in the subsequent process, so that smear removal (desmear) is performed. I do. Desmearing is performed by the potassium permanganate method or the like.

  In the next step (see FIG. 1 (d)), each via hole 15b (16b) formed in the groove includes the wall surface and bottom surface of each groove 15a (16a) formed in the resin layer 15 (16). The first conductor layer 17 (19) is formed on the resin layer including the wall surface and the bottom surface by performing electroless copper (Cu) plating. The first conductor layer 17 (19) is formed thicker than usual, for example, with a thickness of about 20% with respect to the width of the groove 15a (16a).

  In the next step (see FIG. 1E), copper (Cu) is formed in the groove 15a (16a) and the via hole 15b (16b) covered with the electroless Cu plating film (first conductor layer 17 (19)). ) A conductive paste such as paste or silver (Ag) paste is filled by screen printing to form the second conductor layer 18 (20).

  In the next step (see FIG. 1 (f)), the exposed portion of the electroless Cu plating film (first conductor layer 17 (19)) is removed by flash etching. As a result, the resin layer 15 (16) just under the removed electroless Cu plating film 17 (19) is exposed, and the adjacent wiring layers 17, 18 (19, 20) are insulated from each other as shown. It becomes a state.

  In addition, although flash etching is performed in this process, it is needless to say that the method of removing the unnecessary electroless Cu plating film is not limited to this. For example, a machine such as buffing (a method in which a cylindrical buff embedded with an abrasive is rotated and the buff and the object to be processed (copper surface) are wetted with cooling water and the buff is pressed against the copper surface for polishing) A typical method may be used.

  At this stage, the first wiring layer 13 (14), the resin layer 15 (16), and the second wiring layers 17, 18 (19, 20) are formed on both surfaces of the core substrate 11 as shown in the figure. A structure is produced.

  Further, although not specifically shown, the resin layer and the wiring layer are repeatedly processed on the structure body in the same manner as the processing performed in the steps (b) to (f) until the required number of layers is obtained. Are stacked alternately. In the configuration example shown in FIG. 2, two wiring layers (build-up layers) are formed on both sides of the core substrate 11 (including the wiring layers 13 and 14 on both sides). Further, the solder resist layers 27 and 28 are formed so as to cover both surfaces except for the pad portions 24P and 26P of the outermost wiring layers 24 and 26, and the solder resist layers 27 and 28 are exposed. Ni / Au plating is applied to the pad portions 24P and 26P. Then, a pre-solder is applied to the pad portion 24P on the chip mounting surface side (attachment of solder 29).

  The wiring board (semiconductor package) 10 of the present embodiment is manufactured through the above steps.

  As described above, according to the wiring substrate (semiconductor package) 10 and the manufacturing method thereof according to the present embodiment, the resin layer 15 on the core substrate 11 (and the lower resin layers 15 and 16) as the base substrate. Grooves 15a and 16a (and grooves 21a and 22a) are formed on the surface of 16 (and resin layers 21 and 22) according to the shape of the second-layer wiring pattern (and third-layer wiring pattern). Via holes 15b and 16b (and via holes 21b and 22b) are formed in the groove. Then, the first conductor layers 17 and 19 (and the first conductor layers 23 and 25) are formed so as to cover the wall surfaces and the bottom surfaces of the grooves and the corresponding via holes, and the first conductor layers are formed on the first conductor layers. Two conductor layers 18 and 20 (and second conductor layers 24 and 26) are formed, and the first and second conductor layers constitute the second wiring layer (and the third wiring layer). Has been. That is, each wiring layer is embedded in the trench and the via hole, and the first conductor layers 17 and 19 (and 23 and 25) and the second conductor layers 18 and 20 (and 24 and 26 are arranged along the direction in which the current flows. ) And are connected in parallel.

  With such a structure, the first conductor layer and the second conductor layer are compared with the case where the wiring is formed by filling only the conductive paste in the recesses of the insulating resin layer as seen in the above-described prior art. The resistivity of the wiring layer configured by parallel connection can be reduced.

  In particular, in the present embodiment, the first conductor layers 17, 19, 23, and 25 constituting the outer layer of the wiring layer are formed thicker than usual, so that the cross-sectional area (current current) of the first conductor layer is formed. The area of the surface perpendicular to the flowing direction) is relatively large and the resistivity is lowered, so that the resistivity of the entire wiring layer can be further reduced.

  The second layer (third layer) wiring layer is formed to cover the grooves 15a, 16a (21a, 22a) and the corresponding via holes 15b, 16b (21b, 22b) and the wall surfaces and bottom surfaces thereof. Since the second conductor layers 18 and 20 (24 and 26) are embedded in the grooves with the conductor layers 17 and 19 (23 and 25) interposed therebetween, the wiring can be further miniaturized. Therefore, even when the grooves are provided at a narrow pitch, it is possible to effectively suppress the occurrence of electromigration between adjacent wirings. That is, the first conductor layers 17 and 19 (23 and 25) constituting the outer layer of the wiring layer are formed by electroless Cu plating, and the second conductor layers 18 and 20 (24 constituting the inner layer of the wiring layer are formed. , 26) is formed by filling with a conductive paste (Cu paste or the like), so even if a portion of the paste temporarily adheres to the portion between adjacent grooves as the squeegee moves, The wiring layer is separated from the inner layer of the wiring layer in the adjacent groove by the thickness of the outer layer of the wiring layer. As a result, the possibility of short-circuiting the adjacent wiring through a part of the paste can be greatly reduced, and it can contribute to the suppression of the occurrence of electromigration.

  In addition, since the second conductor layers 18, 20, 24, and 26 constituting the inner layer of the wiring layer are formed by filling with a conductive paste, wiring formation by electrolytic Cu plating used in the semi-additive method is performed. Compared to the case, the time required for wiring formation can be shortened.

  In particular, in the present embodiment, the first conductor layers 17, 19, 23, and 25 constituting the outer layer of the wiring layer are formed thicker than usual, so that the groove covered with the “thick” conductor layer and In forming the second conductor layer by filling the corresponding via hole with the conductive paste, the amount of the conductive paste used is relatively small, so the time required for the filling is relatively shortened. be able to. This contributes to shortening the time required for wiring formation.

  When the second conductor layers 18, 20, 24, and 26 are formed by filling with a copper (Cu) paste, the second conductor layer (Cu paste) is the first conductor layer (electroless Cu plating film). Since it is formed of the same metal as 17, 19, 23, 25, the adhesion between the outer layer (first conductor layer) and the inner layer (second conductor layer) of the wiring layer is improved, and the wiring The reliability as a layer can be improved. Furthermore, since copper (Cu) has high adhesion to the resin, the adhesion between the wiring layer and the resin layers 15, 16, 21, and 22 in contact with the wiring layer is also improved, contributing to further improvement in wiring reliability. can do.

  Further, the first and second conductor layers 17, 19, 23, 25 and the second conductor layers 18, 20, 24, 26 are formed of the same metal (Cu), so that the first and second conductor layers can be simultaneously formed. Etching can be removed. Thereby, even when a part of the second conductor layer is formed on the first conductor layer by the screen printing method using the conductive paste (that is, when there is a residue), the residue (second conductor) Part of the layer) and the first conductor layer can be removed simultaneously in the same process, and the process can be simplified.

  Further, since the first conductor layers 17, 19, 23, and 25 are formed by electroless Cu plating, a conductor layer (electroless Cu plating film) is formed with a uniform film quality even on a so-called large-sized substrate. Can do. For example, when a conductor layer is uniformly formed by sputtering on the same large substrate, it is necessary to newly manufacture a sputtering apparatus corresponding to the large substrate, which is disadvantageous in terms of cost. By forming it, such disadvantages can be eliminated.

  Furthermore, since the first conductor layers 17, 19, 23, and 25 are formed by electroless Cu plating, it is possible to form the conductor layers thicker than when formed using a sputtering process. .

  In the above-described embodiment, Cu paste is formed in the grooves 15a, 16a, 21a, 22a and the via holes 15b, 16b, 21b, 22b covered with the electroless Cu plating film (first conductor layers 17, 19, 23, 25). The case where the second conductor layers 18, 20, 24, and 26 are formed by filling a conductive paste such as (see FIG. 1 (e)) has been described as an example. However, the groove and the corresponding via hole are filled. Of course, the form or filling method of the conductive material is not limited to this. For example, the second conductor layers 18, 20, 24, and 26 may be formed by electrolytic plating. Although not shown in particular, the process in this case will be described as follows.

  First, a plating resist is formed using a patterning material on the electroless Cu plating film (first conductor layer 17) for the structure obtained in the step of FIG. Opening (formation of a resist layer having an opening). The opening of the resist layer is formed by patterning according to the shape of the wiring pattern (the shape of the groove 15a). A photosensitive dry film is used as the patterning material. The resist patterning method is performed as follows, for example. First, after cleaning both surfaces, a dry film having a required thickness is attached to the surface of the electroless Cu plating film by thermocompression bonding (lamination), and then a mask (not shown) patterned to the required shape for the dry film. And using a predetermined developer (a developer containing an organic solvent in the case of a negative type, an alkali developer in the case of a positive type). The portion is etched (formation of an opening), and a resist layer corresponding to a required pattern shape is formed.

  Next, on the electroless Cu plating film (first conductor layer 17) exposed from the opening of the plating resist, the second electroplating is performed by using the electroless Cu plating film as a power feeding layer. The conductor layer 18 is formed. Then, the plating resist (dry film) is removed using an alkaline chemical such as sodium hydroxide or monoethanolamine. Thereby, a structure equivalent to the structure obtained in the step of FIG. The subsequent steps are the same as the steps shown in FIG.

  In the above-described embodiment, the case where a resin substrate used in a plastic package is used as an example of the form of the base substrate of the wiring board has been described. However, as is apparent from the gist of the present invention, the base Of course, the form of the substrate is not limited to this. For example, a ceramic substrate used in a ceramic package may be used, or a silicon substrate used in a CSP (chip size package) may be used.

It is sectional drawing which shows the process (process of the part relevant to this invention) of the manufacturing method of the wiring board which concerns on one Embodiment of this invention. It is sectional drawing which shows an example of the wiring board (semiconductor package) obtained using the manufacturing method of FIG. FIG. 3 is a cross-sectional view showing a state (semiconductor device) when a semiconductor element is mounted on the wiring board of FIG. 2.

Explanation of symbols

10: Wiring board (semiconductor package),
11 ... Core substrate (base material),
13, 14 ... wiring layer,
15, 16, 21, 22 ... resin layer,
15a, 16a, 21a, 22a ... grooves (wiring patterns),
15b, 16b, 21b, 22b ... via holes,
17, 19, 23, 25 ... outer layer of the wiring layer (seed layer / first conductor layer),
18, 20, 24, 26... Inner layer of the wiring layer (second conductor layer).

Claims (4)

Forming a resin layer on the base substrate;
Forming a groove on the surface of the resin layer according to the shape of the wiring pattern;
Forming a first conductor layer by electroless plating on the resin layer including the wall surface and bottom surface of the groove;
Filling the groove covered with the first conductor layer with a conductive paste made of the same metal as the first conductor layer by screen printing to form a second conductor layer;
And a step of removing the exposed portion of the first conductor layer. In the step of forming the resin layer on the base substrate, a base substrate having a wiring layer formed on at least one surface is prepared, and the surface of the base substrate on which the wiring layer is formed is covered. Forming the resin layer,
In the step of forming a groove on the surface of the resin layer, further forming a via hole reaching the wiring layer of the base substrate in the groove,
2. The method of manufacturing a wiring board according to claim 1, wherein in the step of forming the first conductor layer, the first conductor layer is further formed on the wall surface and bottom surface of the via hole. A base substrate;
A resin layer provided on the base substrate and having grooves formed on the surface according to the shape of the wiring pattern;
A wiring layer embedded in the groove of the resin layer,
The wiring layer is formed by electroless plating so as to cover a wall surface and a bottom surface of the groove, and is formed on the first conductor layer by a screen printing method, and the first conductor layer And a second conductor layer made of the same metal as the wiring board. The base substrate has a wiring layer formed on at least one surface,
The resin layer is formed so as to cover a surface of the base substrate on which the wiring layer is formed, and a via hole reaching the wiring layer of the base substrate is formed in the groove of the resin layer,
The wiring board according to claim 3, wherein the first conductor layer is further formed to cover a wall surface and a bottom surface of the via hole.

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