JP5062533B2 - Wiring board manufacturing method - Google Patents

Description

The present invention relates to a method of manufacturing a wiring board (hereinafter also referred to as “semiconductor package” for convenience) used for mounting an electronic component such as a semiconductor element (chip).

  2. Description of the Related Art Recent electronic devices such as mobile terminals and mobile devices are required to have high functionality and downsizing (thinning), and in response to such demands, wiring boards (semiconductor packages) used in such electronic devices are used. ) Is also progressing in miniaturization and high density of wiring. As a technique for forming fine wiring, a process using a semi-additive method has been conventionally used. This is the target base material (resin substrate) after the necessary pretreatment (drilling for double-sided connection, surface roughening, desmear, catalyzed, etc.), then electroless copper (Cu) plating, Next, a plating resist pattern is formed, and the pattern portion is subjected to electrolytic Cu plating to form a wiring. Then, the plating resist is removed, and the electroless Cu plating film immediately below is etched.

As a technique related to such a conventional technique, for example, there are a printed circuit board manufacturing method described in Patent Document 1 and a circuit board manufacturing method described in Patent Document 2. In addition, there is a method of manufacturing a wiring board using a damascene process described in Patent Document 3.
JP-A-1-99281 Japanese Patent Laid-Open No. 11-68288 JP 2006-49804 A

  As described above, the semi-additive method is used as a fine wiring formation technique. However, this method has a problem that the wiring adhesion strength is reduced as compared with the process using the subtractive method.

  That is, in this semi-additive method, since it is necessary to finally etch the electroless Cu plating film used as a seed layer in the electrolytic Cu plating, the electrolytic Cu plating that has already been formed is used in the etching. The upper end surface of the wiring (rectangular when viewed in cross section) and its corner are also etched at the same time. As a result, the cross-sectional shape of the wiring changes from the original rectangular shape to a shape with rounded corners on the upper end surface, and the adhesion strength with the resin (wiring adhesion strength) decreases. Depending on the case, there is a problem that the wiring is peeled off.

  Further, in the current process, it is becoming difficult to make the wiring pattern finer. That is, in the semi-additive method, a photosensitive dry film is often used as a plating resist. From the viewpoint of handling and cost, the thickness of the dry film resist used depends on the wiring to be formed (Cu plating film). In general, a thickness larger than () is selected. Therefore, if necessary patterning (exposure / development) is performed on this “thick” dry film resist to form fine wiring, a part of the dry film resist may fall down after exposure / development, or an undeveloped part may appear. Inconveniences such as formation may occur. As a result, there has been a problem that the intended fine wiring cannot be reliably formed.

The present invention was created in view of the problems in the prior art, and an object of the present invention is to provide a method of manufacturing a wiring board that can improve wiring adhesion strength and realize the reliable formation of fine wiring.

  In order to solve the above-described problems of the prior art, according to one aspect of the present invention, a step of forming a resin layer on a base substrate, a step of forming a sacrificial conductor layer on the resin layer, and the sacrificial conductor Forming a dry film resist layer having an opening patterned according to the shape of a required wiring pattern on the layer, and removing the portion of the sacrificial conductor layer exposed from the opening, Forming a groove in an exposed portion of the layer, forming a first conductor layer on the resin layer including the wall surface and bottom surface of the groove by electroless plating, and the first conductor Forming a second conductor layer by electrolytic plating in the groove covered with a layer; removing the dry film resist layer; and removing the remaining portion where the sacrificial conductor layer is exposed. It is characterized by including Preparation method for one-substrate.

  According to the method for manufacturing a wiring board according to this embodiment, after forming the sacrificial conductor layer on the resin layer on the base substrate, a dry film resist layer having openings patterned according to the shape of the wiring pattern is formed. After removing the portion of the sacrificial conductor layer exposed from the opening, a groove is formed in the exposed portion of the resin layer, and the first layer is formed by electroless plating on the resin layer including the inside of the groove. The conductor layer 17 is formed, and the second conductor layer is formed by electrolytic plating. Finally, the remaining portion where the dry film resist layer and the sacrificial conductor layer are exposed is removed. That is, the wiring layer composed of the first and second conductor layers has a structure embedded in the groove.

  With this structure, when the electroless Cu plating film used as a seed layer for electrolytic Cu plating as seen in the prior art is finally etched, the upper end surface of the wiring already formed and its corners are formed. The inconvenience that the portion is also etched to change its cross-sectional shape and the adhesion strength with the resin is reduced can be solved. That is, the wiring adhesion strength can be improved.

  Further, since the first and second conductor layers constituting the wiring layer are formed only in the groove portion dug in the surface of the resin layer, the thickness of the dry film resist layer used as a plating resist is reduced. The thickness of the dry film used in the current process can be made thinner. As a result, even if the required exposure / development is performed on this “thin” dry film resist layer, a part of the dry film resist may fall down after exposure / development as in the prior art, or may be undeveloped. The inconvenience of forming a part can be solved. That is, according to the present invention, the intended fine wiring can be reliably formed.

Other structural features of the method for manufacturing a wiring board according to the present invention and advantageous advantages based thereon will be described with reference to embodiments of the invention described below.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the accompanying drawings.

1 and 2 are cross-sectional views showing steps of a method of manufacturing a wiring board according to an embodiment of the present invention (steps related to the present invention). FIG. 5 shows an example of a wiring board (semiconductor package) obtained by using the manufacturing method in the form of a sectional view, and FIG. 6 shows a state when a semiconductor element is mounted on the wiring board . (Semiconductor device) is shown in the form of a sectional view.

First, the configuration of the wiring board (semiconductor package) 10 of the present embodiment will be described with reference to FIG .

  In the illustrated wiring substrate (semiconductor package) 10, 11 is a core substrate as a base substrate of the wiring substrate, 12 is a conductor filled in a through hole formed in a required portion of the core substrate 11, and 13 and 14 are cores. A first wiring layer formed in a required pattern shape on both surfaces of the substrate 11 is shown. The wiring layers 13 and 14 are connected to each other through the conductors 12 in the core substrate 11 at required places.

  Reference numerals 15 and 16 denote interlayer insulation layers (resin layers) formed on the core substrate 11 so as to cover the wiring layers 13 and 14, respectively. The resin layers 15 and 16 each have a required wiring pattern on the surface. Grooves 15a and 16a are formed according to the shape, and via holes 15b and 16b reaching the pad portions of the wiring layers 13 and 14 are formed at required locations in the grooves. Reference numerals 17 and 19 denote first conductor layers (outer layers of the wiring layer) formed to cover the wall surfaces and bottom surfaces of the grooves 15a and 16a of the corresponding resin layers 15 and 16, respectively, and to cover the wall surfaces and bottom surfaces of the via holes 15b and 16b. , And 18 and 20 indicate second conductor layers (inner layers of the wiring layer) formed on the corresponding first conductor layers 17 and 19, respectively. The first and second conductor layers constitute a second wiring layer in the package 10. That is, the second wiring layers 17 and 18 (19 and 20) are formed so as to be embedded in the grooves 15a and 16a and the via holes 15b and 16b of the corresponding resin layers 15 and 16 as shown in the drawing, and the direction of current flow. The first conductor layers 17 and 19 and the second conductor layers 18 and 20 are connected in parallel with each other.

  Reference numerals 21 and 22 denote interlayer insulating layers (resin layers) formed so as to cover the corresponding wiring layers 18 and 20 and the resin layers 15 and 16, respectively. Grooves 21a and 22a are formed according to the shape of the required wiring pattern, and via holes 21b and 22b reaching the pad portions of the wiring layers 18 and 20 are formed at required positions in the groove. Reference numerals 23 and 25 respectively denote first conductor layers (outer layers of the wiring layer) formed to cover the wall surfaces and bottom surfaces of the grooves 21a and 22a of the corresponding resin layers 21 and 22, and further to cover the wall surfaces and bottom surfaces of the via holes 21b and 22b. , And 24 and 26 indicate second conductor layers (inner layers of the wiring layer) formed on the corresponding first conductor layers 23 and 25, respectively. The first and second conductor layers constitute a third wiring layer in the package 10. That is, the third wiring layers 23 and 24 (25 and 26) are also formed by being embedded in the grooves 21a and 22a and the via holes 21b and 22b of the corresponding resin layers 21 and 22 as shown in the figure. The first conductor layers 23 and 25 and the second conductor layers 24 and 26 are connected in parallel along the flowing direction.

  Reference numerals 27 and 28 denote solder resist layers as protective films formed so as to cover both surfaces except for the pad portions 24P and 26P defined at required portions of the corresponding wiring layers 24 and 26, respectively. Copper (Cu) is typically used as the material for the conductor 12 and the wiring layers 13, 14, 17 to 20, and 23 to 26, and the epoxy resin is typically used as the material for the resin layers 15, 16, 21, and 22. Is used.

  Further, the pad portions 24P and 26P exposed from the solder resist layers 27 and 28 are respectively connected to external connection terminals (chip terminal terminals of the chip mounted on the package 10, and when the package 10 is mounted on a mounting substrate such as a motherboard. Since the solder balls and pins used in the above are joined, nickel (Ni) plating and gold (Au) plating are applied to the pad portions (Cu) 24P and 26P in this order. This is to improve the contactability when the external connection terminals are joined, to improve the adhesion with Cu constituting the pad portions 24P and 26P, and to prevent Cu from diffusing into the Au layer. .

  Furthermore, for the pad portion 24P on the chip mounting surface side (upper side in the illustrated example), solder 29 is attached so that it can be easily connected to the electrode terminals of the chip at the time of mounting in consideration of the convenience of the customer. . On the other hand, the pad portion 26P on the side opposite to the chip mounting surface side is left exposed so that the external connection terminals can be joined as required by the customer. Alternatively, as indicated by a broken line in the figure, an external connection terminal such as a solder ball may be bonded to the pad portion 26P in advance.

The configured wiring board (semiconductor package) 10 as described above, as shown in FIG. 6 as an example, the semiconductor element (chip) 40 can be surface mounted via the electrode terminals 41. The electrical connection between the chip 40 and the wiring board 10 is performed by reflow by bringing the electrode terminal 41 of the chip 40 into contact with the solder 29 attached to the pad portion 24P of the wiring board 10. Further, an underfill resin 42 such as an epoxy resin is filled in the gap between the wiring substrate 10 and the chip 40, and is fixed by thermosetting. In the illustrated semiconductor device 50, a solder ball 30 as an external connection terminal is bonded to the surface opposite to the chip mounting surface.

  Next, with respect to a method of manufacturing the wiring substrate (semiconductor package) 10 of the present embodiment, refer to FIG. 1 and FIG. 2 (further FIG. 3) showing an example of the manufacturing process (parts related to the present invention). While explaining. In the illustrated example, only the configuration on one surface side (chip mounting surface side) of the wiring substrate is shown for the sake of simplicity. Further, for each member on the other surface side corresponding to the illustrated configuration, a reference number indicating the member is added in parentheses.

First, in the first step (see FIG. 1A), a core substrate 11 is prepared as a base material, through holes are formed in the required locations, filled with conductors, and further wired in the required pattern shape on both sides. Layer 13 (14) is formed. For example, a glass cloth base epoxy resin copper-clad laminate widely used for printed wiring boards is prepared, and through holes are formed by drilling or the like at the required locations. Next, electroless copper (Cu) plating is performed on both surfaces of the laminate, and this electroless Cu plating film is used as a seed layer (feeding layer) by electrolytic Cu plating, or by screen printing using a Cu paste, The through hole is filled with the conductor 12 (see FIG. 5 ) by an inkjet method or the like. Further, the first wiring layer 13 (14) is formed in a required pattern shape on both surfaces of the core substrate 11 so as to be connected to the conductor 12 by a subtractive method, a semi-additive method, an ink jet method or the like. . When the semi-additive method or the ink jet method is used, the wiring layer 13 (14) can be formed simultaneously with the filling of the conductor 12 into the through hole, which contributes to simplification of the process.

  In the next step (see FIG. 1B), a semi-cured resin film made of an epoxy resin or the like is laminated on the wiring layer 13 (14) and the core substrate 11, and thermally cured to obtain an interlayer insulating layer. The resin layer 15 (16) is formed.

  In the next step (see FIG. 1C), electroless copper (Cu) plating is performed on the resin layer 15 (16) to form the sacrificial conductor layer CP. A part of the sacrificial conductor layer (electroless Cu plating film) CP is used as a seed layer as will be described later, and finally all is removed.

  In this step, the sacrificial conductor layer CP can be formed by using other methods such as sputtering, although it is formed by electroless Cu plating. Moreover, as a form of the material constituting the sacrificial conductor layer CP, a film-like material may be used in addition to the liquid material. For example, the sacrificial conductor layer CP may be formed by laminating copper foil.

  In the next step (see FIG. 1D), a plating resist is formed on the sacrificial conductor layer (electroless Cu plating film) CP by using a patterning material, and the required portions are opened (opening OP is formed). Formation of the provided resist layer R1). The opening OP of the resist layer R1 is formed by patterning according to the required wiring pattern shape (the shape of the groove 15a (16a) formed in a later step). At this time, patterning is performed slightly larger than the size (pattern width) of the groove 15a (16a) to be formed.

  As the patterning material, a photosensitive dry film is preferably used. The resist patterning is performed, for example, as follows. First, both surfaces are cleaned, and a dry film having a required thickness is attached to the surface of the sacrificial conductor layer CP by thermocompression bonding (lamination), and then a mask (not shown) patterned to a required shape is applied to the dry film. ) To be cured by exposure to ultraviolet (UV) irradiation, and further using a predetermined developer (developer containing an organic solvent in the case of negative type, alkaline developer in the case of positive type). The portion is etched (formation of the opening OP), and a resist layer R1 corresponding to the required pattern shape is formed.

  In this step, the patterning portion of the dry film (opening OP of the resist layer R1) is formed slightly larger than the groove. The reason is that it is easy to ensure conduction by electroless Cu plating as will be described later. This is because the dry film resist is prevented from being damaged at the same time when the groove is patterned by the laser.

  In the next step (see FIG. 1E), the exposed portion of the sacrificial conductor layer CP is removed by flash etching. As a result, the resin layer 15 (16) immediately below the removed sacrificial conductor layer CP is exposed.

  In the next step (see FIG. 2A), the resin layer 15 (16) is exposed at a position corresponding to the openings of the sacrificial conductor layer CP and the resist layer R1 (that is, the resin layer 15 (16) is exposed). A groove 15a (16a) corresponding to the shape of the second-layer wiring pattern is formed in the portion) using an excimer laser, a CO2 laser, a UV-YAG laser, or the like. Further, although not shown in the figure, via holes 15b (16b) reaching the pad portions of the lower wiring layer 13 (14) are formed at required positions in the groove by the same laser drilling process. To do.

  When the groove 15a (16a) corresponding to the shape of the wiring pattern is formed, the groove 15a (16a) is formed slightly smaller than the opening OP (see FIG. 1D) of the resist layer R1. That is, in the example of FIG. 2A, the edge of the resist layer R1 coincides with the edge of the groove 15a (16a), but actually, the resist layer R1 with respect to the edge of the completed groove 15a (16a). The edge of has a slightly receding shape. As described above, since the groove is patterned by the laser in the area smaller than the opening OP of the resist layer R1, it is possible to avoid damage to the edge of the resist layer R1 due to the laser irradiation. it can.

  When laser processing is performed on the resin layer 15 (16) in this way, a resin residue (resin smear) may remain on the bottom surface (on the lower wiring layer 13 (14)) of each via hole 15b (16b). If the resin smear remains, it causes a conduction failure between each via hole and the lower wiring layer 13 (14) when plating is performed in the subsequent process, so that smear removal (desmear) is performed. Desmearing is performed by the potassium permanganate method or the like.

  In the next step (see FIG. 2B), each via hole 15b (16b) formed in the groove includes the wall surface and bottom surface of each groove 15a (16a) formed in the resin layer 15 (16). The first conductor layer 17 (19) is formed on the resin layer including the wall surface and the bottom surface by performing electroless copper (Cu) plating. The electroless Cu plating is preferably performed under conditions such that about 50% to 150% of Ra (arithmetic mean roughness) is achieved.

  At this time, since the edge of the resist layer R1 slightly recedes from the edge of the groove 15a (16a) as described above, the completed first conductor layer 17 (19) is not shown in the example of FIG. Although it remains in the groove 15a (16a), it actually extends on the upper end surface of the resin layer 15 (16) as illustrated in FIG. Thereby, the first conductor layer 17 (19) is connected to the sacrificial conductor layer CP, and electrical conduction on the surface of the resin layer 15 (16) is ensured. That is, the first conductor layer 17 (19) can be used as a seed layer in cooperation with the sacrificial conductor layer CP.

  In the next step (see FIG. 2C), on the electroless Cu plating film (the first conductor layer 17 (19)) formed from the groove 15a (16a) to the upper end surface of the resin layer 15 (16). Then, the second conductor layer 18 (20) is formed by electrolytic Cu plating using the first conductor layer 17 (19) and the sacrificial conductor layer CP as seed layers.

  In the next step (see FIG. 2D), the dry film used as the plating resist (resist layer R1) is removed using an alkaline chemical such as sodium hydroxide or monoethanolamine. Further, the exposed seed layer (sacrificial conductor layer CP) is removed by wet etching. As a result, the resin layer 15 (16) immediately under the removed sacrificial conductor layer CP is exposed, and the adjacent wiring layers 17, 18 (19, 20) are insulated from each other as shown.

  In this step, unnecessary sacrificial conductor layer (Cu layer) CP is removed by wet etching, but it is needless to say that the removal method is not limited to this. For example, buff polishing (a method of rotating a cylindrical buff embedded with an abrasive and pressing the buff against the copper surface while wetting the buff and the surface to be processed (copper surface) with cooling water) A mechanical method may be used.

  At this stage, the first wiring layer 13 (14), the resin layer 15 (16), and the second wiring layers 17, 18 (19, 20) are formed on both surfaces of the core substrate 11 as shown in the figure. A structure is produced.

  Thereafter, although not particularly shown, the same process as that performed in the steps of FIGS. 1B to 2D is repeated for this structure until the required number of layers is obtained. Layers and wiring layers are stacked alternately. In the configuration example shown in FIG. 4, two wiring layers (build-up layers) are formed on both sides of the core substrate 11 (including the wiring layers 13 and 14 on both sides thereof). Further, the solder resist layers 27 and 28 are formed so as to cover both surfaces except for the pad portions 24P and 26P of the outermost wiring layers 24 and 26, and the solder resist layers 27 and 28 are exposed. Ni / Au plating is applied to the pad portions 24P and 26P. Then, a pre-solder is applied to the pad portion 24P on the chip mounting surface side (attachment of solder 29).

  The wiring board (semiconductor package) 10 of the present embodiment is manufactured through the above steps.

  As described above, according to the wiring substrate (semiconductor package) 10 and the manufacturing method thereof according to the present embodiment, the resin layer 15 on the core substrate 11 (and the lower resin layers 15 and 16) as the base substrate. Grooves 15a and 16a (and grooves 21a and 22a) are formed on the surface of 16 (and resin layers 21 and 22) according to the shape of the second-layer wiring pattern (and third-layer wiring pattern). Via holes 15b and 16b (and via holes 21b and 22b) are formed in the groove. Then, the first conductor layers 17 and 19 (and the first conductor layers 23 and 25) are formed so as to cover the wall surfaces and the bottom surfaces of the grooves and the corresponding via holes, and the first conductor layers are formed on the first conductor layers. Two conductor layers 18 and 20 (and second conductor layers 24 and 26) are formed, and the first and second conductor layers constitute the second wiring layer (and the third wiring layer). Has been. That is, each wiring layer has a structure embedded in the trench and the via hole.

  With this structure, when the electroless Cu plating film used as a seed layer for electrolytic Cu plating as seen in the prior art is finally etched, the upper end surface of the wiring already formed and its corners are formed. The inconvenience that the portion is also etched to change its cross-sectional shape and the adhesion strength with the resin is reduced can be solved. That is, the wiring adhesion strength can be improved.

  Further, since the patterning portion (opening OP) of the dry film resist (resist layer R1) is formed larger than the groove (see FIG. 1D), the first conductor layer 17 is exemplified as shown in FIG. The contact portion between (19) and the sacrificial conductor layer CP is not a corner portion of the resin layer 15 (16) but a flat surface. As a result, the adhesion between the electroless Cu plating film (first conductor layer 17 (19) and sacrificial conductor layer CP) and the resin layer 15 (16) is enhanced, and the connection reliability is improved.

  Further, in the step of FIG. 1E, even if a part of the sacrificial conductor layer CP immediately below the dry film resist (resist layer R1) is excessively etched by over-etching, the subsequent step (FIG. 2B) )) To reliably deposit metal (Cu) in the gap between the resin layer 15 (16) and the resist layer R1 (a space where a part of the sacrificial conductor layer CP is etched). it can. Thereby, electrical conduction between the first conductor layer 17 (19) and the sacrificial conductor layer CP on the surface of the resin layer 15 (16) is ensured.

  Further, the Cu plating layers (the first conductor layers 17, 19, 23, and 25 and the second conductor layers 18, 20, 24, and 26) constituting the wiring layer are the resin layers 15, 16, 21, and 22. Since it is formed only in the part dug in the surface (groove and via hole), the thickness of the dry film used as the plating resist can be made thinner than the thickness of the dry film used in the current process it can. Therefore, even if necessary patterning (exposure / development) is performed on this “thin” dry film resist, a part of the dry film resist may fall down after exposure / development as in the prior art, It is possible to eliminate the inconvenience that a development portion is formed. That is, according to the process according to the present embodiment, the intended fine wiring can be reliably formed.

  In the above-described embodiment, the plating resist (dry film resist) R1 patterned according to the shape of the required groove 15a (16a) is provided on the sacrificial conductor layer CP formed on the resin layer 15 (16) (FIG. 1 (d)), after removing the unnecessary sacrificial conductor layer CP (FIG. 1 (e)), grooves 15a (16a) are formed in the exposed portions of the resin layer 15 (16), and further if necessary. A via hole 15b (16b) is formed in the groove (FIG. 2A). That is, although the case where the process of patterning the dry film resist R1 according to the shape of the groove 15a (16a) and the process of forming the groove 15a (16a) in the resin layer 15 (16) are performed separately has been described as an example. Of course, it is not always necessary to perform the process in a separate step.

  FIG. 4 is a cross-sectional view showing a process (a process related to the present invention) of a method for manufacturing a wiring board according to another embodiment of the present invention.

  First, after passing through the same steps as those in FIGS. 1A to 1C in the above-described embodiment, in the first step (see FIG. 4A), the sacrificial conductor layer CP is used as a plating resist. A resist layer R2 is formed. As a material for the resist layer R2, a material to which the plating material (Cu) does not adhere when electroless Cu plating is applied in a later step is appropriately selected. For example, an acrylic or epoxy liquid resin or resin film can be used.

  In the next step (see FIG. 4B), the structure covered with the resist layer R2 is passed through the sacrificial conductor layer CP from above the resist layer R2 using an excimer laser, a CO2 laser, or the like. A groove 15a (16a) corresponding to the shape of the second-layer wiring pattern is formed in the resin layer 15 (16). Further, although not shown in the figure, via holes 15b (16b) reaching the pad portions of the lower wiring layer 13 (14) are formed at required locations in the groove by the same laser processing.

  As a result, a structure equivalent to the structure obtained in the step of FIG. The subsequent steps are the same as the above-described steps shown in FIGS.

  The process according to the present embodiment has the following merits in addition to the effects obtained in the above-described embodiment. That is, the process of patterning the dry film resist R2 according to the shape of the groove 15a (16a) and the process of forming the groove 15a (16a) in the resin layer 15 (16) are performed at the same time. Compared with the process which concerns, simplification of a process can be aimed at.

  Further, when patterning the copper foil (sacrificial conductor layer CP) and the insulating layer (resin layer 15 (16)) at the same time, by using a very thin copper foil (for example, electrolytic copper foil), the groove 15a by laser is used. (16a) can be formed more easily. Furthermore, since the etching amount when the sacrificial conductor layer CP is removed by etching is small, the risk of overetching can be reduced. The electrolytic copper foil is also called a copper foil with a carrier, and an ultrathin electrolytic copper foil is bonded to one side of the metal carrier foil, and this ultrathin electrolytic copper foil can be handled with good handling properties. The metal carrier foil and the ultrathin electrolytic copper foil can be peeled off. In use, the metal carrier foil is peeled off and only the ultrathin electrolytic copper foil is used.

  In each of the above-described embodiments, the case where a resin substrate used in a plastic package is used as the base substrate of the wiring board has been described as an example. However, as is apparent from the gist of the present invention, the base substrate Of course, the form is not limited to this. For example, a ceramic substrate used in a ceramic package may be used.

It is sectional drawing which shows the process (process of the part relevant to this invention) of the manufacturing method of the wiring board which concerns on one Embodiment of this invention. It is sectional drawing which shows the manufacturing process following the manufacturing process of FIG. It is a supplementary explanatory drawing of the process performed at the process of FIG.2 (b). It is sectional drawing which shows the process (process of the part relevant to this invention) of the manufacturing method of the wiring board which concerns on other embodiment of this invention. It is sectional drawing which shows an example of the wiring board (semiconductor package) obtained using the manufacturing method of FIG.1 and FIG.2, or FIG. FIG. 6 is a cross-sectional view showing a state (semiconductor device) when a semiconductor element is mounted on the wiring board of FIG. 5.

Explanation of symbols

10: Wiring board (semiconductor package),
11 ... Core substrate (base material),
13, 14 ... wiring layer,
15, 16, 21, 22 ... resin layer,
15a, 16a, 21a, 22a ... grooves (wiring patterns),
15b, 16b, 21b, 22b ... via holes,
17, 19, 23, 25 ... outer layer of the wiring layer (seed layer / first conductor layer),
18, 20, 24, 26 ... inner layer of the wiring layer (second conductor layer),
CP: sacrificial conductor layer,
R1, R2 ... Plating resist (resist layer).

Claims (7)

Forming a resin layer on the base substrate;
Forming a sacrificial conductor layer on the resin layer;
Forming a dry film resist layer having an opening patterned on the sacrificial conductor layer according to the shape of a required wiring pattern;
Forming a groove in the exposed portion of the resin layer after removing the portion of the sacrificial conductor layer exposed from the opening;
Forming a first conductor layer by electroless plating on the resin layer including the wall surface and bottom surface of the groove;
Forming a second conductor layer by electrolytic plating in the groove covered with the first conductor layer;
And a step of removing the dry film resist layer and further removing the remaining portion where the sacrificial conductor layer is exposed. 2. The sacrificial conductor layer and the first conductor layer are electrically connected, and the electrolytic plating is performed using the sacrificial conductor layer and the first conductor layer as a power feeding layer. The manufacturing method of the wiring board as described in 2 ..   2. The method of manufacturing a wiring board according to claim 1, wherein in the step of forming the dry film resist layer, the opening is patterned to be larger than a pattern width of the groove to be formed. In the step of forming a resin layer on the base substrate, a base substrate having a wiring layer formed on at least one surface is prepared, and the surface of the base substrate on which the wiring layer is formed is covered. Forming the resin layer,
In the step of forming a groove in the exposed portion of the resin layer, further forming a via hole reaching the wiring layer of the base substrate in the groove,
2. The method of manufacturing a wiring board according to claim 1, wherein in the step of forming the first conductor layer, the first conductor layer is further formed on a wall surface and a bottom surface of the via hole. Forming a resin layer on the base substrate;
Forming a sacrificial conductor layer on the resin layer;
Forming a dry film resist layer on the sacrificial conductor layer;
Forming a groove corresponding to the shape of the wiring pattern in the resin layer through the sacrificial conductor layer from above the dry film resist layer according to the shape of the required wiring pattern;
Forming a first conductor layer by electroless plating on the resin layer including the wall surface and bottom surface of the groove;
Forming a second conductor layer by electrolytic plating in the groove covered with the first conductor layer;
And a step of removing the dry film resist layer and further removing the remaining portion where the sacrificial conductor layer is exposed. 6. The sacrificial conductor layer and the first conductor layer are electrically connected, and the electrolytic plating is performed using the sacrificial conductor layer and the first conductor layer as a power feeding layer. The manufacturing method of the wiring board as described in 2 .. In the step of forming a resin layer on the base substrate, a base substrate having a wiring layer formed on at least one surface is prepared, and the surface of the base substrate on which the wiring layer is formed is covered. Forming the resin layer,
In the step of forming the groove, a via hole reaching the wiring layer of the base substrate is further formed in the groove,
6. The method of manufacturing a wiring board according to claim 5, wherein in the step of forming the first conductor layer, the first conductor layer is further formed on the wall surface and bottom surface of the via hole.

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