JP2005236067A - Wiring substrate, its manufacturing method and semiconductor package - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring substrate for a package which can be adapted to high density mounting which can particularly reduce the total thickness of a substrate thinner than 0.30 mm, has excellent productivity, and can further solve the problem of the power loss of the input and output of a high-frequency signal. <P>SOLUTION: A three-layer wiring substrate includes three-layer wiring layers having only one of wiring layers 191, 192 formed by a semi-additive method on the roughed surfaces of both front and back surfaces of a core wiring substrate 110 having a one-layer wiring layer 122A in an insulating resin substrate layer. The wiring substrate includes a through hole 115a and a blind via 116a formed by providing conductive parts 193, 194 formed by plating the hole of the resin substrate layer formed by a laser. Further, the through hole 115a and the blind via 116a are filled up with the conductive parts formed by plating the hole of the resin substrate layer 110 formed by the laser. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention provides a three-layer wiring board having a three-layer wiring layer in which one internal wiring layer is provided inside an insulating organic resin layer, and one wiring layer is provided on each of the front and back surfaces, and a method for manufacturing the same. The present invention also relates to a wiring board in which wiring layers are further arranged on the front and back of the three-layer wiring board.

In recent years, a multilayer printed circuit board (hereinafter also referred to as a multilayer wiring board) has a finer wiring pattern than a conventional bonded printed circuit board in order to cope with the increasingly smaller and lighter electronic devices. Using a core substrate in which wiring layers are arranged on both sides of a core base material, and a build-up layer composed of an insulating layer and a wiring layer in that order on each side of the core substrate. Various build-up-type multilayer wiring boards (hereinafter also referred to as build-up boards) have been developed, and there are various production methods.
In addition, in order to cope with the downsizing of electronic equipment, it is required to mount semiconductor components mounted on the electronic equipment with high density. As a demand accompanying improvement in performance of semiconductor devices, semiconductor chips are faced. A flip chip system that is mounted on a printed circuit board such as a mother board with a down structure has attracted attention.

Under such circumstances, a build-up type multilayer wiring board (build-up board) is used as an interposer, and a semiconductor chip is mounted on the double-sided wiring board by a flip chip method or a wire bonding method.
For example, as shown in FIG. 10, the semiconductor chip 20 is mounted on the solder resist 12 of the multilayer wiring board 10 by face-down bonding with solder bumps 21 by a flip chip method, and the semiconductor chip 20 and the multilayer wiring board 10 are mounted. The gap between the solder resists 12 is filled with an underfill resin 30, and the connecting portion between the semiconductor chip 20, the solder bump 21 and the wiring member 11 is sealed with a sealing resin 40.
Note that flip chip is a bare chip with connection bumps such as Au or solder bumps. Due to the demand for higher pin count, improved high frequency characteristics, and smaller size, the terminals are usually in an area array or peripheral shape. A narrow pitch is also used for the terminals.
The flip chip method was put into practical use by IBM in 1963. It is connected to the wiring electrode of the circuit board through the bumps of the flip chip. Since the chip mount and the electrical connection are performed at a time, Even if the number of pins increases, the time required for assembly does not increase and it can be said that this is an excellent connection method for multi-pin support.

Here, as an example, a method for manufacturing a core substrate in a conventional build-up substrate will be briefly described with reference to FIG.
First, a through-hole 715 is mechanically formed on a copper-clad laminate 710 in which copper foils 712 are disposed on both surfaces of a core material 711 using a drill machine. (Fig. 8 (a))
Next, the inside of the through hole 715 is washed, a copper plating layer 720 is formed on the entire surface by electroless plating, and the inside of the through hole (715 in FIG. 8A) is made conductive. A copper plating copper plating layer 730 is formed on the entire surface by plating to have a predetermined thickness, and the inside of the through hole is electrically connected. (Fig. 8 (b))
Next, a filling material 740 made of a conductive metal material or a non-conductive paste is filled in the through hole, and a surface smoothing process is performed by physical polishing. (Fig. 8 (c))
Thereafter, a film formation process is performed using a dry film resist or a liquid resist, and a predetermined pattern exposure and development are performed to form a resist pattern. Using this resist pattern as a mask, a copper plating layer 730, electroless copper 720, and copper foil 712 are formed. By performing pattern etching, a plated through hole portion 750 and desired circuit wiring (not shown) are formed, and the core substrate 760 is formed. (Fig. 8 (d))

Thereafter, high-density wiring is formed on both surfaces of the thus manufactured core substrate (760 in FIG. 8 (d)) by a build-up method, and the build-up multilayer wiring substrate is used as an interposer for semiconductor packages. For example, it is used as shown in FIG.
The multilayer wiring board 810 shown in FIG. 9 can be manufactured as follows.
That is, glass cloth epoxy resin (prepreg) or resin insulating layers 851 and 851a are formed on both surfaces of a core substrate (corresponding to 760 in FIG. 8D), and a core is formed using a carbon dioxide gas laser or a UV-YAG laser. A small-diameter hole is formed at a predetermined position of each insulating layer 851 and 851a so that a plated through hole (corresponding to 750 in FIG. 8D) on the substrate and a desired portion of the circuit wiring are exposed.
After cleaning, a conductive layer is formed in the hole by electroless plating, a dry film resist is laminated, a predetermined pattern is used as a mask, and a via 871 is formed in the exposed part including the hole by electrolytic plating. A first buildup layer is formed.
By repeating this operation, a plurality of build-up layers (two layers on each side in the illustrated example of FIG. 9) are formed, and the multilayer wiring board 810 is manufactured.
In the buildup layer on the semiconductor chip mounting side, connection pads 865 for mounting a semiconductor chip are formed along with necessary wiring.
Next, the connection pad portions 865 and 855 are opened, and the solid resist 885 is disposed.
In such a multilayer wiring substrate 810, the semiconductor chip 890 can be mounted on the connection pads 865 for mounting a semiconductor chip via metal bumps 891 such as solder.
In addition, a back surface side external connection terminal 880 of the multilayer wiring board 810 is provided and can be mounted on a printed wiring board (motherboard or the like).
FIG. 9 shows a part of the multilayer wiring board in a simplified manner.
Of course, a semiconductor chip can be wire-bonded to the build-up multilayer wiring board shown in FIG. 9, and the multilayer wiring board can be used as an interposer for a semiconductor package.

Since the core substrate formed by the conventional method shown in FIG. 8 has through holes formed by a mechanical drill and wiring by a subtractive method, the through hole diameter / land diameter is from 150 μm / 350 μm level. It is difficult to reduce the size, and because of the line formation by the subtractive method, it is difficult to manufacture a line / space of 50 μm / 50 μm or less.
Since such a core substrate alone cannot increase the wiring density, in reality, a build-up multilayer wiring substrate provided with two or one build-up layer as shown in FIG. Although it is used as an interposer, it corresponds to the high-density wiring and wiring routing limits. However, the production of such a build-up multilayer wiring board has a large number of processes, which directly leads to an increase in cost.
In addition, the wiring board as shown in FIG. 9 has a large power loss in the through hole, and is not suitable for an application requiring a high frequency.
Japanese Patent Application No. 2002-299665

In addition, when a two-layer wiring board having wiring layers on both sides of the core material is used as a core wiring board and a build-up layer is provided on both sides, it is easy to form fine wiring on the outermost layer, but the inner layer wiring is always A total of two layers, including the build-up layer, is a wiring substrate having at least four wiring layers. For example, an unnecessary wiring layer is increased as a wiring substrate for a semiconductor package.
Further, in this case, it is difficult to produce a very thin core wiring board due to a problem of mechanical strength during handling in manufacturing, and it is difficult to reduce the total thickness of the board to less than 0.30 mm.
Specifically, the core layer of a conventional build-up board usually has a thickness of 0.4 mm to 0.8 mm, and the build-up layer also has a thickness of 40 μm to 60 μm, so that the wiring layer has four layers. The build-up substrate had a total thickness of 0.48 mm or more.

On the other hand, a two-layer wiring board in which a wiring layer is provided on both surfaces of a core material with a prepreg, two sets are bonded together, and a through hole for forming a through hole with a mechanical drill is known. However, it is difficult to make the hole diameter 200 μm or less in addition to the poor position accuracy of the mechanical drill of ± 50 μm.
In the case of this method, it is difficult to miniaturize wiring in order to form each wiring layer by etching, which is also a problem.
This method has a disadvantage in that when forming a through hole for connecting the central part of the two-layer board, it is necessary to drill from the front surface to the back surface, and that part cannot be wired on the front and back. Become.

As described above, using a core wiring board formed by a conventional subtractive method as it is as a wiring board for a semiconductor package has problems in terms of wiring density and wiring and is not practical. In this case, a build-up multilayer wiring board in which built-up layers are formed on both sides of a core wiring board formed by a subtractive method is used as a wiring board for a semiconductor package. The process is long, cumbersome and costly. Also, the power loss in the through-hole is large, making it unsuitable for applications that require high-frequency input / output. When combined with the up-wiring layer, the wiring board has at least four wiring layers, and is often used as a wiring board for semiconductor packages. The number of unnecessary wiring layers is increased, and it is difficult to produce an extremely thin core wiring board due to the problem of mechanical strength during manufacturing handling, and it is difficult to reduce the total thickness of the board to less than 0.30 mm. It was.
Also known is a method of bonding two sets of two-layer wiring boards with wiring layers provided on both sides of a core material with a prepreg, and providing a through hole for forming a through hole with a mechanical drill. In this case, the wiring substrate for a semiconductor package has problems in terms of positional accuracy of a mechanical drill and in miniaturization of wiring when forming a wiring layer by etching.
The present invention is compatible with these, and can be used for high-density mounting. In particular, the total thickness of the substrate can be made thinner than 0.30 mm, and the conventional build-up wiring layer has two layers and the wiring layer has a total of four. It is an object of the present invention to provide a wiring board having a three-layered wiring layer for a package, which is superior in productivity from the build-up multilayer wiring board of layers and can solve the problem of high-frequency input / output power loss.
Furthermore, it is difficult to skid during wire bonding and flip chip bonding in semiconductor chip assembly, and there is no dent (also referred to as dent) on the through hole or blind via. Furthermore, uniform wiring thickness variation is required. The present invention is intended to reliably provide a wiring board having three wiring layers for a package that can be used.
Another object of the present invention is to provide a highly integrated and thin semiconductor package using the substrate.
At the same time, an object of the present invention is to provide a wiring board manufacturing method for manufacturing such a wiring board.

The double-sided wiring board of the present invention is formed by a semi-additive method on the roughened surfaces on both the front and back sides of a core wiring base material having one wiring layer inside the insulating resin base material layer. A three-layer wiring board having a three-layer wiring layer in which only one wiring layer is provided, and a conductive portion plated by a hole is formed in a resin base layer formed by a laser. A blind via for electrically connecting the wiring of each wiring layer on the front and back of the material and the wiring of the internal wiring layer, respectively, or the blind via and the through-hole portion of the resin base layer formed by laser And a through hole for electrically connecting the wirings of the wiring layers on the front and back sides of the core wiring substrate.
In the above wiring board, one wiring layer inside the insulating resin base material layer of the core wiring base material is disposed substantially at the center in the thickness direction of the insulating resin base material layer. It is characterized by being.
Further, in any one of the wiring boards described above, the blind via, or the blind via and the through hole, each having a hole formed in a resin base layer formed by laser plating is formed. Including the outer surface of the blind via, or including the outer surface of the blind via and the through hole, the outer surface side of the wiring portion of each wiring layer on the front and back sides Is characterized in that a planarization treatment is performed by mechanical polishing or chemical mechanical polishing.
Further, in any of the above wiring boards, the roughness of the roughened surfaces on both sides of the core wiring substrate is characterized in that the ten-point average roughness RzJIS is in the range of 2 μm to 10 μm. To do.
Also, in any one of the above wiring boards, an insulating resin layer (solder resist) covering the front and back surfaces of the predetermined terminal portion is exposed. . Also, any one of the above wiring boards, characterized in that it is a wiring board for a semiconductor package, one surface for connecting to a semiconductor chip by a flip chip method or a wire bonding method It has a connection pad, and has an external connection terminal for connecting to an external circuit on the other surface.
Further, in any of the above wiring boards, the terminal portion is provided with a Ni plating layer and an Au plating layer in order.
In the wiring board having three wiring layers according to the present invention, in order to prevent warping and distortion of the wiring board, the internal wiring layer should be positioned at the center of the insulating resin base layer in the thickness direction. It is arranged. Further, in the wiring board of the present invention, even in a form in which no through-hole is formed, blind vias for electrically connecting the wiring of each wiring layer on the front and back of the core wiring substrate and the wiring of the internal wiring layer are respectively provided. By providing, the wiring of the wiring layers on the front and back sides can be conducted without forming a through hole.
In addition, the planarization process here includes the outer surface of the blind via, or includes the outer surface of the blind via and the through hole, and the outer surface side of the wiring portion of each wiring layer on the front and back is all on the same plane. In the case of a package wiring board by mechanical polishing or chemical mechanical polishing, each surface within the substrate has a variation range within ± 5 μm from the same plane. It is easy to suppress the position.
As described above, the present invention includes the outer surface of the blind via, or includes the outer surface of the blind via and the through hole, and the outer surface side of the wiring portion of each wiring layer on the front and back surfaces is mechanically polished or chemically machined. It is characterized in that a planarization process is performed by automatic polishing.
Here, the ten-point average roughness RzJIS is defined or displayed according to JIS B0601-2001.
According to this, only the reference length was extracted from the roughness curve in the direction of the average line, and the height of the peak from the highest peak to the fifth peak was measured from the average line of the extracted part in the direction of the vertical magnification. Calculate the sum of the absolute value and the average value of the absolute values of the bottom of the valley from the lowest valley floor to the fifth, and express this value in micrometer (μm) as the 10-point average roughness RzJIS In other words, here, the reference length is 0.25 mm.
In addition, in the above, “a wiring board on which a solder resist that covers the front and back surfaces in a state where a predetermined terminal portion is exposed” means an opening in the solder resist so that only a predetermined terminal portion region is exposed. It is not limited to that.
For example, the thing of the form which exposes a predetermined | prescribed terminal part area | region and opens the whole semiconductor chip mounting area | region of a wiring board is also contained.

  Further, a wiring layer is further formed on both outer surfaces or one surface of the wiring substrate according to any one of claims 1 to 6.

The manufacturing method of the double-sided wiring board of the present invention is applied to the semi-additive method on the roughened surfaces on both the front and back sides of the core wiring base material having one wiring layer inside the insulating resin base material layer. A method of manufacturing a three-layer wiring board having a three-layer wiring layer in which only one wiring layer is provided, and in order (A) the internal wiring layer inside an insulating resin substrate layer And a core wiring base material forming step for forming a core wiring base material provided with a through hole for forming a through hole and a hole for forming a blind via, and (B) a core wiring base material forming step. Electroless plating is performed on the entire surface including the surface of through holes for forming through holes and holes for forming blind vias to form an electroless plated layer as a current-carrying layer. Plating process and resist pattern on both sides, Electrolytic Cu plating is performed using the electroplating layer as a current-carrying layer, and the wiring part including the terminal part and the conduction part of the through hole for forming the through hole and the hole for forming the blind via are selectively selected by the electrolytic Cu plating layer. A selective plating process for forming a plating layer, an etching process for removing unnecessary exposed electroless plating layers by flash etching after removing the resist pattern, and conducting through holes and blind vias in order. And a semi-additive process step of forming wiring portions on both sides, and the core wiring base material forming step is performed in the order of (a) the first insulating resin base material layer. Resist that corresponds to the wiring layer to be formed by placing a photosensitive resist on the copper foil on one side of the laminated base material, which is laminated with copper foil on both sides, and performing predetermined selective exposure and development. Forming a turn, etching the copper foil using the resist pattern as an anti-etching mask, removing the resist pattern, and leaving the copper foil on the other surface of the insulating resin base layer; A first wiring base material forming step of obtaining a first wiring base material in which an internal wiring layer serving as a wiring layer inside the material is formed on one surface of the insulating resin base material layer; ) A copper foil is laminated and pressure-bonded to the inner wiring layer forming side of the first wiring substrate through a second insulating resin substrate layer made of the same material as the first insulating resin substrate layer. Alternatively, on the inner wiring layer forming side of the first wiring substrate, a copper foil is placed on one surface of the second insulating resin substrate layer made of the same material as the first insulating resin substrate layer. The laminated base material that has been pressure-bonded is laminated and pressure-bonded with the second insulating resin base material layer side facing the internal wiring layer side, An internal wiring layer is disposed at the boundary between the first insulating resin substrate layer and the second insulating resin substrate layer, and a copper foil is provided on the outer surface of each insulating resin substrate layer. (C) Furthermore, the copper foil on the outer surface of each insulating resin substrate layer of the second wiring substrate is removed by etching to obtain an insulating material. A third wiring base material forming step for obtaining a third wiring base material in which the internal wiring layer is disposed inside the resin base material layer; and (d) a third wiring by a CO ₂ laser or a UV laser. A through hole for forming a through hole and a hole for forming a blind via are formed on the base material, and further, a desmear treatment is performed as necessary to obtain a core wiring base material, The copper foil on the outer surface of the second wiring substrate has a rough surface formed by electrolytic plating facing the resin substrate layer side. Was an electrolytic copper foil, by these copper foils etched away, is characterized in that in which the shape of the rough surface of the copper foil is transferred and formed on the corresponding resin base layer side.
In the step (a), the internal wiring layer is formed by etching. However, if the wiring is formed by plating using a semi-additive method, formation of the internal wiring layer having a high degree of freedom in routing is possible at a higher density. Can do.

And it is a manufacturing method of said wiring board, Comprising: Electrolytic Cu plating in a selective-plating process fills the through-hole for through-hole formation, and the hole for blind via formation with an electrolytic Cu plating layer. It is a characteristic, before removing the resist pattern after the selective plating process, before removing the unnecessary electroless plating layer after the resist pattern is removed by flash etching, or unnecessary electroless plating layer. Is removed by flash etching, and then mechanical polishing or chemical mechanical polishing is performed to planarize an electrolytic Cu plating layer selectively formed by selective plating.
Further, in any one of the above wiring board manufacturing methods, the insulating resin base material layer is perforated by a laser in the perforating process by placing a contact plate that does not excessively reflect the laser on one surface. The laser irradiation is performed from the other surface.
Further, in any one of the above-described wiring board manufacturing methods, after the flash etching step, (E) a photosensitive insulating resin layer (solder resist) is applied and formed on both surfaces in order, and the insulating resin The masking exposure of the layer (solder resist), development, and the patterning step of the insulating resin layer (solder resist) exposing the terminal portion are performed. The insulating resin layer (solder resist) ), After the patterning step, Ni plating and Au plating are sequentially performed on the surface of the terminal portion.
Also, in any one of the above-described wiring board manufacturing methods, the resist pattern is formed when the selective plating step is performed by disposing a dry film resist, performing masking exposure, and developing. It is characterized by this.
Here, “to flatten the electrolytic Cu plating layer” means that the surface side of the electrolytic Cu plating layer is on the same plane and is a flat surface, so that mechanical polishing or By chemical mechanical polishing, in the case of a package wiring board, it is possible to easily suppress the position of each surface within a variation range within ± 5 μm from the same plane.

(Function)
The wiring board having three wiring layers according to claims 1 to 9 of the present invention can cope with high-density mounting by using such a configuration, and in particular, the total thickness of the board can be made thinner than 0.30 mm. In addition, the package wiring is superior in terms of productivity and can solve the problem of high-frequency input / output power loss, compared to the conventional build-up multilayer wiring board with two build-up wiring layers and a total of four wiring layers. It is possible to provide a wiring board having three layers.
In addition, when forming a hole in the resin base layer with a laser, the hole diameter on the laser irradiation side is large, the hole diameter on the opposite side to the laser irradiation side is small, and the cross section can be formed in a trapezoidal shape. When filling the through hole of the insulating resin base layer for forming the through hole and the hole of the insulating resin base layer for forming the blind via with the conductive portion formed by plating, the filling is easy. Since the hole region becomes flat, the solder resist can be disposed flat on both sides of the hole on the hole region.
In this case, since the plating of the hole region is flat, the terminal portion (also referred to as a pad) can be provided in the through hole region or the blind via region, and a pad on through hole design or a pad on via design is possible. As the degree increases, the wiring density can be improved.
For this reason, when a wiring board having three wiring layers according to claims 1 to 9 of the present invention is used as a wiring board for a semiconductor package, a core board as shown in FIG. 8D is used as an interposer for a semiconductor package. In this case, wiring that cannot be obtained is made possible, and it is possible to replace a package wiring board by a build-up four-layer wiring board in which one build-up layer is arranged on both surfaces of the core board.
In addition, since the hole area becomes flat, when a multilayer wiring layer is applied without applying a solder resist, vias (via holes) are placed on flat through holes or blind vias by the build-up method. In addition, the copper foil is bumped through the insulating layer and bumps are stacked on the core wiring board side, the copper foil is processed by a photo-etching method to form a wiring layer, and the bumps are It is possible to reliably perform a multilayering method as a connection means between wiring layers.
In the wiring board having three wiring layers according to the first to ninth aspects of the present invention, the holes in the insulating resin base layer for forming the blind vias, or the insulating layers for forming the blind vias and the through holes are used. The holes of the resin base material layer are formed by laser, but the diameter thereof can be 150 μm or less, and of course, a hole larger than 150 μm can be formed.
In the conventional core substrate, a mechanical drill is used for producing a through hole, and the diameter thereof cannot be made 150 μm or less.

In addition, by roughening both surfaces of the core base material and forming the wiring by a semi-additive method, it is possible to manufacture a fine, high-density wiring.
Further, the ten-point average roughness RzJIS of the surface of the roughened resin substrate layer on both sides of the core wiring substrate is preferably in the range of 2 μm to 10 μm from the practical level.
If RzJIS is less than 2 μm, the adhesion strength with the wiring will not be sufficient, and if RzJIS is greater than 10 μm, the unevenness of the surface of the resin base layer will affect the shape of the wiring, which may hinder miniaturization of the wiring. At the same time, the load in the production of the electrolytic Cu foil increases.

In particular, include the outer surface of the blind via, or include the outer surface of the blind via and the through-hole, and the outer surface side of the wiring portion of each wiring layer on the front and back surfaces is precisely polished by mechanical polishing or chemical mechanical polishing. Due to the flattening process, it is difficult for skidding to occur during wire bonding and flip chip bonding in semiconductor chip assembly, and there is no dent on the filling type through hole or blind via, and Therefore, the provision of a wiring board for a package capable of making the variation in wiring thickness uniform is ensured. Since the wiring layer of the present invention is a three-layer wiring board, one surface has a connection pad for mounting a semiconductor chip by a flip chip method or a wire bonding method, and the other surface is connected to an external circuit. The form which has the following external connection terminal is mentioned.
In this case, there is a configuration in which an opening is provided in the solder resist so as to expose only the predetermined terminal portion region, or a configuration in which the predetermined terminal portion region is exposed and the entire semiconductor chip mounting region of the wiring board is opened. Can be mentioned.
In particular, when the wiring layer of the present invention is a three-layer wiring board and the through-hole region and the blind via region are flat, it is possible to directly mount a chip without providing a solder resist.
When the chip is directly mounted, there is no restriction on the bump on the chip side, which is advantageous for flip chip connection. Of course, when the underfill resin is filled at the time of chip mounting, bubbles are not caught on the through hole side.
Usually, the terminal part is provided with a Ni plating layer and an Au plating layer in this order.
In addition, the wiring layer of the present invention is a three-layer wiring board in which a solder resist is not provided on both sides thereof, and if a build-up layer is formed on both sides, the wiring of the core board has a high density, Since wiring is possible on the through-holes and the blind vias of the three-layer wiring board, a high-density wiring board can be configured with a smaller number of layers than in the past.

  The wiring board having three wiring layers according to claims 1 to 9 of the present invention has a through hole portion for forming a through hole and a hole portion for forming a blind via formed in a core wiring substrate by a laser. Since the laser processing machine has high positional accuracy, the land diameter margin to cover the misalignment between the land and the through hole or blind via can be reduced, and the land diameter should be reduced to 250 μm or less along with the reduction of the through hole diameter. Is possible.

The manufacturing method of the wiring board according to the present invention has the above-described configuration. Specifically, the wiring substrate is roughly roughened on both the front and back sides of the core wiring substrate having one wiring layer inside the insulating resin substrate layer. A three-layer wiring board having a three-layer wiring layer in which only one wiring layer formed by a semi-additive method is provided on each surface, and can be used for high-density mounting. Can be made thinner than 0.30 mm, and the conventional build-up wiring layer has two layers, the core wiring layer has two wiring layers, and the wiring layer has a total of four layers in terms of productivity. It is possible to provide a method for manufacturing a wiring board, which is excellent in manufacturing a wiring board that can solve the problem of high-frequency input / output power loss for a package.
The method for producing a wiring board according to the present invention includes a step of laminating and pressing the second insulating resin base material layer with the copper foil remaining on one surface of the first insulating resin base material layer ((a ) And (b) process), even if the insulating resin base layer is thin, the copper thin film remains on one side, so that the mechanical strength can be maintained and the handling in manufacturing is possible. Become.
As a result, it can be used for high-density mounting, and it has a higher productivity and quality than conventional build-up multilayer wiring boards with two build-up wiring layers and a total of four wiring layers. It is possible to provide a method for manufacturing a wiring board having three wiring layers.
Specifically, by transferring and forming the rough shape of the electrolytic copper foil on both surfaces of the insulating resin base material layer of the core wiring base material, a desired rough surface can be formed, and the wiring is semi-finished. The additive method can be formed with sufficient adhesion strength with the core substrate.
In particular, after forming holes for forming through holes and holes for forming blind vias with a laser, a conductive layer for through holes and a conductive layer for blind vias are formed together with wiring portions on both sides, so that productivity is high. It is supposed to be.
In the case of a conventional build-up multilayer wiring board with two build-up wiring layers and a total of four wiring layers, the hole forming process for through-hole formation and the hole forming process for blind via formation are performed separately. The through hole conductive layer and the blind via conductive layer are also formed in separate steps.
In addition, the method for forming a rough surface of the core substrate has few restrictions on applicable materials, and widens the selection range of the insulating resin substrate layer of the core wiring substrate.
In addition, through holes for through holes and holes for forming blind vias are formed in the insulating resin base layer of the core wiring base with a laser. When filling, the surface of the hole forming region can be formed to be sufficiently flat.

In particular, after removing the resist pattern after the selective plating process, or after removing the unnecessary electroless plating layer after removing the resist pattern, or after removing the unnecessary electroless plating layer by flash etching, Wiring parts, pads, and through holes plated by the selective plating process by performing mechanical polishing or chemical mechanical polishing to planarize the electrolytic Cu plating layer that is selectively plated by the selective plating process The cross-sectional shape of the part has a good flatness, specifically, the outer surface of the wiring part, the pad part, and the through-hole part has a variation of ± 5 μm from the same plane in the case of the wiring board for packaging. It can also be suppressed within.
The wiring part and the pad part formed by plating by the selective plating process have a semi-cylindrical cross-sectional shape on the outside. However, by performing mechanical polishing or chemical mechanical polishing, this can be made into a substantially rectangular shape. The filling-type through-hole portion formed by plating by the selective plating step has a cross-sectional shape that dents toward the substrate at the central portion, and can be flattened.
In this way, mechanical polishing or chemical mechanical polishing makes it difficult for skidding to occur during wire bonding and flip chip bonding in conductor chip assembly, and there is no dent on the filling type through hole. In addition, it is possible to provide a method for reliably manufacturing a wiring board for a package capable of making the variation in wiring thickness uniform.
When mechanical polishing or chemical mechanical polishing is not performed, as shown in FIGS. 10 (a), 10 (b), and 10 (c), connection wiring 910 and terminal portions (also referred to as pads) 920 are provided. The cross-sectional shape of the through-hole portion 930 including the land portion may be recessed toward the substrate side, but the central portion may be recessed toward the substrate side. By mechanical polishing, as shown in FIG. 10 (a1), FIG. 10 (b1), and FIG. 10 (c1), the connection wiring 910, the terminal portion (also referred to as a pad) 920, and the through-hole portion 930 are removed. The surface side is precisely flattened.
Here, the terminal portion, the land portion, the connection wiring, and the like are collectively referred to as a wiring portion. When the wiring is referred to, the terminal portion and the land portion may be included in addition to the connection wiring.
Further, in the method of manufacturing a wiring board according to the present invention, when filling through holes and blind vias with plating, there are few dents in the through hole regions and blind via regions, especially when mechanical polishing or chemical mechanical polishing is applied. The solder resist can be arranged flat on both sides without generating a dent in the through-hole region, and the wiring layer produced by such a manufacturing method uses a three-layer wiring board, on which a semiconductor chip is mounted. When filling the underfill resin layer, it is possible to reduce the addition of the process at the customer, assuming that bubbles do not enter the chip and impair the reliability of the semiconductor device. It was.

The present invention can cope with high-density mounting as described above, and is superior in productivity from the conventional build-up multilayer wiring board having two layers of build-up wiring layers and a total of four wiring layers, It is possible to provide a wiring board having three wiring layers for a package that can solve the problem of high-frequency input / output power loss.
In particular, it is difficult for skidding to occur during wire bonding and flip chip bonding in semiconductor chip assembly, and there is no dent on the through hole or blind via, and furthermore, the variation in wiring thickness can be made uniform. It is possible to reliably provide a wiring board having three wiring layers for a package.
At the same time, it is possible to provide a method for manufacturing a wiring board for manufacturing such a wiring board.
Conventionally, by reducing the land diameter and line miniaturization, the core substrate is provided with one wiring layer formed by the subtractive method on both sides of the core base material, and the wiring layer is plated on each wiring layer. A single wiring layer is formed by the additive method to be formed, and the double-sided wiring board having the four-layer structure is used for the CSP and the stack package, and the wiring layer of the present invention is placed on the three-layer wiring board. It became possible to replace it.
The wiring board having a three-layer structure according to the present invention has a simpler structure and fewer manufacturing steps than a conventional build-up multilayer wiring board having two layers of build-up wiring layers and a total of four wiring layers. Excellent in terms of productivity and power loss of high frequency input / output.

Embodiments of the present invention will be described with reference to the drawings.
FIG. 1A is a partial cross-sectional view of the first example of the embodiment of the wiring board of the present invention, and FIG. 1B is a partial cross-sectional view of the second example of the embodiment of the present invention. 1C is a partial cross-sectional view of a third example of the embodiment of the present invention, and FIG. 2A is a partial cross-sectional view of the fourth example of the embodiment of the wiring board of the present invention. FIG. 2B is a partial cross-sectional view of the fifth example of the embodiment of the present invention, and FIG. 2C is a partial cross-sectional view of the sixth example of the embodiment of the present invention. FIG. 3A is a partial sectional view of a seventh example of the embodiment of the wiring board of the present invention, and FIG. 3B is a partial sectional view of the eighth example of the embodiment of the present invention. FIG. 3C is a partial cross-sectional view of the ninth example of the embodiment of the present invention, and FIG. 4 is a process cross-sectional view showing a partial process of one example of the method of manufacturing the wiring board of the first example. FIG. 5 is a process diagram showing the process following FIG. 4, and FIG. 6 is a second example, a third process. FIG. 7 is a process cross-sectional view for explaining the plating filling process and the planarization process. FIG. 11 (a), FIG. 11 (b), FIG. c) shows a cross-sectional shape before mechanical polishing, and FIGS. 11 (a1), 11 (b1), and 11 (c1) respectively show cross-sectional shapes after corresponding mechanical polishing. FIG. 12 is a diagram of a wiring board in which the wiring layer of the present invention is further formed on one outer surface of a three-layer wiring board. FIG. 13 is a diagram of the wiring layer of the present invention on both outer surfaces of a three-layer wiring board. Furthermore, it is the figure of the wiring board in which the wiring layer was formed.
1 to 7 and FIGS. 11 to 13, reference numerals 100 and 101 denote wiring boards, 110 and 111 denote resin base layers, 115 denotes a through hole portion (for forming a through hole), and 115a, 115b, and 115c denote through holes. 116, 116a, 116b and 116c are blind vias, 121, 122 and 123 are copper foils, 122A is a wiring of an internal wiring layer, 130 is an electroless plating layer, and 150 is a resist. Pattern, 160 is an electrolytic plating layer, 165 is a dent (also called dent), 170 is a solder resist, 181 is a Ni plating layer, 182 is an Au plating layer, 185 is a terminal portion, 191, 191A, 191B, 192, 192A, 192B Is a wiring, 193 and 193A are conduction parts (through holes), 194 and 194A are conduction parts (blind vias), 200 Wiring substrate, 210 is a core base material (insulating base material), 220 is a wiring layer, 221 is a copper layer (copper foil layer), 225 is a plated Cu layer, 250 is a bump, and 260 is a filling (made of an insulating resin) 270 is a solder resist, 285 is a terminal part, 290 is an insulating resin layer, 301 and 302 are additional layers, 320 and 321 are wiring layers, 325 and 326 are conduction parts, 370 is a solder resist, 385 is a terminal part, 390 and 391 are insulating resin layers, 910 and 910a are connection wirings, 920 and 920a are terminal portions (also referred to as pads), 930 and 930a are through-hole portions, 931 is a recess (also referred to as a dent), and 932 and 932a are Land 935 is a conducting part (through hole), and 950 is an insulating base part.

First, a first example of an embodiment of a wiring board according to the present invention will be described with reference to FIG.
The wiring board of the first example is roughened on both the front and back sides of a core wiring base material having one wiring layer (a wiring layer with wiring 122A) inside the insulating resin base material layer 110. A three-layer wiring board having a three-layer wiring layer in which only one wiring layer formed by a semi-additive method is provided on the surface, and is formed in the through-hole portion of the resin base material layer 110 formed by a laser. A through hole 115a for providing a conductive portion 193 formed by plating and electrically connecting wirings on the front and back wiring layers of the core wiring substrate, and a hole portion of the resin substrate layer 110 formed by laser. Conductive portions 194 plated are provided, and blind vias 11aA are provided to electrically connect the wiring 192 of each wiring layer on the front and back of the core wiring substrate and the wiring 122A of the internal wiring layer, respectively. It will be described later It is manufactured by the manufacturing process shown in 4 to FIG. 5.
The wiring board of the first example has the wiring portions 191 and 192 exposed on both surfaces, and is shipped as a product as it is, or as a wiring substrate for forming a wiring layer on both sides, or It is used to form wiring boards of second and third examples described later.
The wiring board of the first example is arranged so that the internal wiring layer is located at the center of the insulating resin base material layer 110 in the thickness direction, and thus the wiring board is not easily warped or distorted. It is supposed to be.
The wiring board of this example is thinner than the build-up multilayer wiring board having four wiring layers, is excellent in productivity, and can be replaced for a semiconductor package.

As the resin base material layer 110 of the core wiring base material, a glass cloth, an aramid non-woven fabric, a liquid crystal polymer non-woven fabric, porous polytetrafluoroethylene (for example, trade name Gore-Tech) is appropriately added to a heat-resistant thermosetting insulating resin layer. And the like are used.
Examples of the resin layer include cyanate resins, BT resins (resins composed of bismaleimide and triazine), epoxy resins, PPE (polyphenylene ether), and the like.
For example, if the thickness of the resin 110 is 0.06 mm above and below the internal wiring layer located at the center and the total thickness is 0.12 mm, the thickness of the wiring portions 191 and 192 is usually as described later. , 0.03 mm or less, the total thickness of the wiring board having three wiring layers in this example is 0.18 mm, and terminal plating and solder resist are further provided on such a wiring board. The total thickness of the wiring boards of the second example and the third example, which will be described later, is 0.3 mm or less even when the thickness of the plating of the terminal portion and the thickness of the solder resist are taken into consideration.
As will be described later, the surface of the resin base material layer is cured by thermocompression-bonding the plating surface side of the electrolytic Cu foil (115 in FIG. 2) to the resin base material layer of the core wiring base material. 115) is obtained by transferring the rough shape of the plated surface (see the steps of FIGS. 4 to 5 described later), and the wirings 191 and 192 have good adhesion.
In the wiring board of the first example, the roughness of the roughened surfaces on both sides of the core wiring substrate is controlled so that the ten-point average roughness RzJIS is in the range of 2 μm to 10 μm.
As a result, both surfaces of the core base material are roughened, and the wiring is formed by a semi-additive method, thereby making it possible to manufacture a fine, high-density wiring.
When RzJIS is smaller than 2 μm, the adhesion strength with the wiring is not sufficient, and when RzJIS is larger than 10 μm, the unevenness of the surface of the resin substrate layer affects the shape of the wiring and inhibits the miniaturization of the wiring. It becomes a factor and the load in the production of the electrolytic Cu foil is also increased.
According to the test, when Hitachi 679F series (cyanate resin) was used as the resin layer, Rz was 5 μm and peel strength was 800 g / cm (JIS C5012-19878.1).

The through holes for forming the through holes 115a and the holes for forming the blind vias 116a are formed by a CO ₂ laser or a UV laser, and the conductive portions 193 and 194 together with the wiring portions 191 and 192 form the electroless plating layer 130. The base layer is formed by electrolytic plating.
In addition, since the through hole for forming the through hole is formed, the diameter can be made 150 μm or less.
The wiring portions 191 and 192 preferably have a thickness of about 5 μm to 30 μm from the viewpoint of conductivity. In this example, the conductive portions 193 and 194 have the same thickness as the wiring portions 191 and 192.
The electroless plating layer 130 is formed by a known method such as electroless Ni plating, electroless Cu plating, and the like when performing electrolytic Cu plating to form the wirings 191 and 192 and the through hole conductive portion 193. The thickness of the conductive layer is sufficient as long as it can be easily removed by flash etching without damaging the others.

Next, a second example of the embodiment of the wiring board according to the present invention will be described with reference to FIG.
The wiring board of the second example is provided with a solder resist 170 so as to cover both surfaces of the wiring board of the first example so that only the terminal portion 185 is exposed. In the semiconductor package as shown in FIG. 10, it is used instead of the multilayer wiring board 10 as an interposer.
The wiring board of the second example has a terminal portion on one surface as a connection pad for connecting to a semiconductor chip, and a terminal portion on the other surface as an external connection terminal for connecting to an external circuit.
A description of each part is omitted here.
In the second example, the blind via 116 a and the through hole 115 a are filled with the solder resist 170.

Next, a third example of the embodiment of the wiring board according to the present invention will be described with reference to FIG.
The wiring board of the third example is the wiring board of the second example in which the solder resist 170 is disposed so as to cover both surfaces of the wiring board of the first example so that only the terminal portion 185 is exposed. 10 is a wiring board for a semiconductor package in which a Ni plating layer 181 and an Au plating layer 182 are arranged in this order on the surface of the terminal portion 185. As in the second example, in the semiconductor package as shown in FIG. It is used in place of the multilayer wiring board 10.
The wiring board of the third example also has a terminal portion on one side as a connection pad for connecting to a semiconductor chip, and a terminal portion on the other side as an external connection terminal for connecting to an external circuit.
A description of each part is omitted here.

Next, a fourth example of the embodiment of the wiring board according to the present invention will be described with reference to FIG.
As in the first to third examples, the wiring board of the fourth example was roughened on both the front and back sides of the core wiring substrate having one wiring layer inside the insulating resin substrate layer 110. A three-layer wiring board having three wiring layers each provided with only one wiring layer formed by a semi-additive method on the surface, but unlike the first to third examples, is formed by a laser. Through hole 193A plated so as to fill the through-hole portion of the resin base material layer 110 formed is provided, and the conductive layer 193A electrically connects the wiring of the wiring layers on the front and back of the core wiring base material 115b and a conductive portion 194A plated so as to fill the hole of the resin base material layer 110 formed by a laser, and wiring 192 of each wiring layer on the front and back of the core wiring base The wiring 122A of the internal wiring layer is electrically connected In which it is provided with a blind via 116b to be connected to.
In the fourth example, as in the first to third examples, the through hole for forming the through hole 115b and the hole for forming the blind via 116b are formed by a CO ₂ laser or a UV laser, and their conduction parts are formed. 193A and 194A are formed by electrolytic plating using the electroless plating layer 130 together with the wiring portions 191A and 192A. The wiring board of the fourth example is the same as the wiring board of the first example. On the other hand, through holes 115b and blind vias 116b are formed by electrolytic plating and conductive layers 193A and 194A are formed as they are, respectively.
Some dents (also called dents) 165 remain in the through hole 115b and blind via 116b regions.
Similarly to the wiring substrate of the first example, the wiring substrate of the fourth example is shipped as a product as it is, or as a wiring substrate for forming a wiring layer on both surfaces thereof, or a fifth example described later. , Used to form the wiring board of the sixth example.
The wiring portions 191A and 192A preferably have a thickness of about 5 μm to 30 μm from the viewpoint of conductivity. However, in order to reliably perform plating filling in the production, for example, the hole diameter on the laser irradiation side with a thickness of 100 μm is used. In the case of 100 μm and the opposite pore diameter of 70 μm, the thickness is usually about 10 μm to 30 μm.
Each part is basically the same as in the first example, and the description thereof is omitted here.

Next, a fifth example of the embodiment of the wiring board according to the present invention will be described with reference to FIG.
The wiring board of the fifth example is provided with the solder resist 170 so as to cover both surfaces of the wiring board of the fourth example so that only the terminal portion 185 is exposed. In the semiconductor package as shown in FIG. 10, it is used instead of the multilayer wiring board 10 as an interposer.
The wiring board of the fifth example has a terminal portion on one surface as a connection pad for connecting to a semiconductor chip, and a terminal portion on the other surface as an external connection terminal for connecting to an external circuit.
A description of each part is omitted here.

Next, a sixth example of the embodiment of the wiring board according to the present invention will be described with reference to FIG.
The wiring board of the sixth example is the wiring board of the fifth example in which the solder resist 170 is disposed so as to cover both surfaces of the wiring board of the fourth example so that only the terminal portion 185 is exposed. 10 is a wiring board for a semiconductor package in which a Ni plating layer 181 and an Au plating layer 182 are arranged in this order on the surface of the terminal portion 185. As in the fifth example, in the semiconductor package as shown in FIG. It is used in place of the multilayer wiring board 10.
The wiring board of the sixth example also has a terminal portion on one surface as a connection pad for connecting to a semiconductor chip, and a terminal portion on the other surface as an external connection terminal for connecting to an external circuit.
A description of each part is omitted here.

Next, a seventh example of the embodiment of the wiring board according to the present invention will be described with reference to FIG.
As in the first to sixth examples, the wiring board of the seventh example was roughened on both sides of the core wiring substrate having one wiring layer inside the insulating resin substrate layer 110. A three-layer wiring board having three wiring layers each provided with only one wiring layer formed by a semi-additive method, and formed by laser as in the fourth to sixth examples. A conductive portion 193A plated so as to fill the through hole portion of the resin base material layer 110 is provided, and a through hole 115b for electrically connecting the wiring of the wiring layer on the front and back of the core wiring base material is provided. And a conductive portion 194A plated so as to fill the hole of the resin base material layer 110 formed by a laser, and wiring 192 and internal wiring of each wiring layer on the front and back of the core wiring base material The wiring 122A of the layer is electrically connected to each other. The wiring board of the seventh example further includes the outer surfaces of the through holes 115c and the blind vias 116c, and the outer surfaces of the wiring portions 191B and 192B of the respective wiring layers on the front and back sides. The side is subjected to precise planarization by mechanical polishing or chemical mechanical polishing.
The wiring board of the seventh example has a form in which the wiring board of the fourth example is further subjected to a precise planarization process by mechanical polishing or chemical mechanical polishing.
Due to flattening by mechanical polishing or chemical mechanical polishing, side slip hardly occurs at the time of wire bonding or flip chip bonding in conductor chip assembly, and dents on filling type through holes (dents) Thus, it is possible to reliably provide a wiring board for a package that has a structure with no gaps and can make the variation in wiring thickness uniform.
Similarly to the wiring boards of the first and fourth examples, the wiring board of the seventh example is shipped as a product as it is, or as a wiring substrate for forming wiring layers on both sides thereof, or described later. This is used to form the wiring substrate of the eighth example and the ninth example.
Each part is basically the same as in the first example, and the description thereof is omitted here.

Next, an eighth example of the embodiment of the wiring board according to the present invention will be described with reference to FIG.
The wiring board of the eighth example is provided with a solder resist 170 so as to cover both surfaces of the wiring board of the seventh example so that only the terminal portion 185 is exposed. In the semiconductor package as shown in FIG. 10, it is used instead of the multilayer wiring board 10 as an interposer.
In the wiring board of the eighth example, the terminal portion on one surface is used as a connection pad for connecting to a semiconductor chip, and the terminal portion on the other surface is used as an external connection terminal for connecting to an external circuit.
A description of each part is omitted here.

Next, a ninth example of the embodiment of the wiring board according to the present invention will be described with reference to FIG.
The wiring board of the ninth example is the wiring board of the eighth example in which the solder resist 170 is disposed so as to cover both surfaces of the wiring board of the seventh example so that only the terminal portion 185 is exposed. 10 is a wiring board for a semiconductor package in which a Ni plating layer 181 and an Au plating layer 182 are arranged in this order on the surface of the terminal portion 185. As in the eighth example, in the semiconductor package as shown in FIG. It is used in place of the multilayer wiring board 10.
The wiring board of the ninth example also has a terminal portion on one surface as a connection pad for connecting to a semiconductor chip, and a terminal portion on the other surface as an external connection terminal for connecting to an external circuit.
A description of each part is omitted here.

As a modified example of the first to ninth examples, there is a form in which no through hole is provided in each example.
In these forms, the wiring of each wiring layer on the front and back of the core wiring substrate and the wiring of the internal wiring layer are respectively provided with blind vias to electrically connect the front and back surfaces without forming through holes. Conduct the wiring of the wiring layer.

Next, an example of the manufacturing method of the wiring board of the first example shown in FIG. 1A will be described with reference to FIGS.
In addition, it replaces with description of one example of embodiment of the manufacturing method of a wiring board in this invention by this. In this example, simply, first, the internal wiring layer is disposed inside an insulating resin base material layer, and a through hole for forming a through hole and a hole for forming a blind via are disposed. Conduct core wiring base material forming step to form core wiring base material, then form through hole and blind via conductive layer on core wiring base material obtained by core wiring base material forming step and wire on both sides And a semi-additive process for forming the part.
First, the core wiring substrate forming process will be described.
First, a photosensitive resist is arranged on the copper foil 122 on one side of the laminated base material (FIG. 4A) in which the copper foils 121 and 122 are pressure-bonded and laminated on both surfaces of the first insulating resin base material layer 110. The resist pattern corresponding to the wiring layer to be formed is formed, the copper foil 122 is etched using the resist pattern as an anti-etching mask, the resist pattern is removed, and the insulating pattern is formed. The wiring part 122A used as the internal wiring layer of a core wiring base material was formed in the one surface of the insulating resin base material layer 110 in the state which left the copper foil 121 on the other surface of the resin base material layer 110. The 1st wiring base material shown to 4 (b) is obtained.
Next, the second insulating resin base material layer 111 made of the same material as the first insulating resin base material layer 110 is formed on the internal wiring layer forming side of the first wiring base material shown in FIG. The copper foil 123 is laminated and pressure-bonded via the first wiring base, or the second insulating resin base made of the same material as the first insulating resin base layer is formed on the inner wiring layer forming side of the first wiring base. A laminated base material obtained by pressure-bonding and laminating a copper foil 123 on one surface of the material layer 111 is laminated and pressure-bonded with the second insulating resin base material layer 111 side directed to the internal wiring layer side, and an internal wiring layer The defeated part 122A is disposed at the boundary between the first insulating resin base layer 110 and the second insulating resin base layer 111, and the outer surface of each insulating resin base layer A second wiring substrate shown in FIG. 4C in which copper foils 121 and 122 are respectively laminated is obtained.
Next, the copper foil on the outer surface of each insulating resin substrate layer 110, 111 of the second wiring substrate shown in FIG. 4C is removed by etching, so that the insulating resin substrate layer 110 and the insulating resin substrate 110 are insulated. A third wiring substrate shown in FIG. 4D is obtained in which the wiring portion 122A serving as an internal wiring layer is disposed at the boundary with the resin substrate layer 111.
The insulating resin base material layer 110 and the insulating resin base material layer 111 are made of the same material, and the third wiring base material shown in FIG. A wiring portion 122A serving as a wiring layer for use is disposed.
As the resin base layers 110 and 111, those obtained by appropriately mixing glass cloth, aramid nonwoven fabric, liquid crystal polymer nonwoven fabric, porous polytetrafluoroethylene (for example, trade name Gore-Tex) or the like with an insulating resin are used. Here, a thermosetting type is used.
As the insulating resin, cyanate resin, BT resin (resin composed of bismaleimide and triazine), epoxy resin, PPE (polyphenylene ether) and the like are used.
Next, a through hole for forming a through hole and a hole for forming a blind via are formed by a CO ₂ laser or a UV laser with respect to the obtained third wiring substrate shown in FIG. The core wiring base material shown in FIG. 4 (e) is formed to form a core wiring base material in which through holes for forming through holes and holes for forming blind vias are disposed by performing a desmear treatment as necessary. Is done.
Here, the copper foils 121 and 123 on the outer surface of the second wiring substrate shown in FIG. 4 (c) described above are resin-based rough surfaces formed by electrolytic plating, respectively. Electrolytic copper foils directed to the layers 110 and 111 side. By etching away these copper foils, the rough shapes of the copper foils 121 and 123 are transferred and formed on the corresponding resin base material layers 110 and 111 side. .
Etching of the copper foils 121 and 123 is performed using a ferric chloride solution, a cupric chloride solution, or an alkaline etching solution.
In the third wiring substrate shown in FIG. 4D, laser drilling is performed by placing a black plate or the like that does not excessively reflect laser light on one surface of the substrate, and laser light from the other surface. When the through-hole portion 115 is formed in the base material by laser irradiation, the hole diameter on the laser beam irradiation side is large and the hole diameter on the side opposite to the laser beam irradiation side is small. The cross section can be formed in a trapezoidal shape.
For example, when a CO ₂ laser is used, a core base material using a cyanate resin having a thickness of 100 μm can have a hole diameter on the irradiation side of 100 μm and a hole diameter on the opposite side to the laser light irradiation side of 70 μm.
As a result, when filling the through holes of the core base material by plating, which can be performed later, the filling can be facilitated. Further, when the solder resist is disposed on both sides, the through hole region is also made flat. The solder resist can be disposed on both sides.
Further, in the conventional core substrate, a mechanical drill is used for producing a through hole, and the diameter thereof cannot be reduced to 150 μm or less, but it is possible to form a through hole having a hole diameter of 150 μm or less.
The minimum hole diameter can be up to 80 μm with a carbon dioxide laser and about 25 μm with a UV-YAG laser.

Next, the semi-additive process steps for forming through holes and blind via conductive layers and forming wiring portions on both sides of the core wiring substrate shown in FIG. 4E will be described.
First, electroless plating is performed on the entire surface including the through hole for forming the through hole and the surface of the hole for forming the blind via on the obtained core wiring substrate shown in FIG. An electroless plating layer 130 is formed. (Fig. 4 (f))
Next, a resist pattern 150 is formed on both surfaces (FIG. 4G), electrolytic Cu plating is performed using the electroless plating layer as an energization layer, wiring portions including terminal portions, through holes for forming through holes, and The conductive part of the hole for forming the blind via is selectively plated with an electrolytic Cu plating layer. (Fig. 5 (h))
The electroless plating layer 130 is formed by a known method such as electroless Ni plating, electroless Cu plating, etc., and has a thickness that serves as an energization layer when performing electrolytic Cu plating for forming the wirings 191 and 192. The thickness may be any thickness that can be easily removed by subsequent flash etching without damaging the others.
The resist is not particularly limited as long as it has desired resolution, plating resistance, and good processability.
Usually, dry film resists are used because they are easy to handle.
Next, after removing the resist pattern 150 (FIG. 5 (i)), the exposed unnecessary electroless plating layer is removed by flash etching to form a conductive layer of through-holes and blind vias on both sides. A wiring part is formed. (Fig. 5 (j))
Examples of the etchant include perhydrosulfuric acid, persulfuric acid, hydrochloric acid, nitric acid, cyanine, and organic etchants.
In this way, the wiring board of the first example shown in FIG.

Furthermore, a photosensitive solder resist is applied to both surfaces of the wiring board of the first example shown in FIG. 1A, and then the solder resist is subjected to mask masking exposure using a predetermined photomask or the like, developed, and a terminal. Expose the part. (Fig. 6 (k))
Thus, with the predetermined terminal portion exposed, the solder resist covering the front and back surfaces is disposed, and the wiring board of the second example shown in FIG. 1B is manufactured.

  Furthermore, Ni plating and Au plating are applied to the terminal portion in order to form a Ni plating layer 181 and an Au plating layer 182 (FIG. 6 (l)), and the wiring board of the third example shown in FIG. 1 (c). Is made.

Next, a method of manufacturing a wiring board according to the fourth example, the fifth example, and the sixth example will be described.
Similar to the first example, the steps of FIGS. 4 to 5 are performed, and further, electrolytic copper plating is performed, and through holes and blind vias are filled with the plated conductive layer 160 (FIG. 7A). Then, the resist pattern 150 is removed. (Fig. 7 (b))
Thereby, the wiring board of the fourth example shown in FIG. 2A is formed.
In addition, by applying a photosensitive solder resist on both surfaces of the wiring board of the fourth example, and then exposing the solder resist to mask masking exposure using a predetermined photomask and the like, exposing the terminal portion, With the predetermined terminal portion exposed, the wiring board of the fifth example shown in FIG. 2B in which the solder resist that covers the front and back surfaces is disposed is manufactured.
Furthermore, in the sixth example shown in FIG. 2C, Ni plating and Au plating are applied in order to the terminal portion of the wiring board of the fifth example to form a Ni plating layer 181 and an Au plating layer 182. This wiring board is manufactured.

Next, a method for manufacturing the wiring board of the seventh example, the eighth example, and the ninth example will be described.
As in the first example, the steps of FIGS. 4 to 5 are performed, and further, electrolytic copper plating is performed, and through holes and blind vias are filled with a conductive layer formed by plating, as shown in FIG. (Same as FIG. 2A) After forming the wiring substrate of the fourth example, mechanical polishing or chemical treatment is performed on the outer surface side of the wiring portion of each wiring layer on the front and back surfaces including the outer surface of the through hole and the blind via. A flattening process is performed by mechanical polishing. (Fig. 7 (c))
Thereby, the wiring board of the seventh example shown in FIG. 3A is formed.
As the mechanical polishing, buffing or the like is used, and recently, chemical mechanical polishing (also referred to as CMP) has been used for each treatment.
In the flattening of the electrolytic Cu plating layer, the flatness can usually be suppressed within a variation range of ± (0.05 to 0.5 μm).
The polishing end point detection method includes a determination method based on rotational torque and a determination method based on electrostatic capacity.
In addition, by applying a photosensitive solder resist on both surfaces of the wiring board of the seventh example, and then exposing the solder resist to mask masking exposure using a predetermined photomask and the like, exposing the terminal portion, With the predetermined terminal portion exposed, the wiring substrate of the eighth example shown in FIG. 3B, in which the solder resist that covers the front and back surfaces is provided, is manufactured.
Furthermore, Ni plating and Au plating are sequentially applied to the terminal portions of the wiring board of the eighth example to form a Ni plating layer and an Au plating layer, and the wiring of the ninth example shown in FIG. A substrate is produced.

Next, as a wiring board in which a wiring layer of the present invention is further formed on one side of a three-layer wiring board, for example, bumps 250 as shown in FIG. A wiring board for a semiconductor package having a total of five wiring layers, in which a two-layer wiring board provided with a wiring layer 220 is arranged and installed.
The wiring board shown in FIG. 12 has a form in which a wiring layer is further formed on the wiring board corresponding to the wiring board of the seventh example shown in FIG. 3A, but is not limited to this.
The wiring board of the first example shown in FIG. 1A, the wiring board of the second example shown in FIG. 1B, the wiring board of the fourth example shown in FIG. 2A, and FIG. The wiring board of the fifth example shown in FIG. 3 and the wiring board of the eighth example shown in FIG. 3B may have a configuration in which a wiring layer is similarly provided on one outer surface thereof.
Moreover, as a wiring board in which the wiring layers of the present invention are further formed on both outer surfaces of a three-layer wiring board, for example, the one shown in FIG.
The wiring board shown in FIG. 13 has a configuration in which a wiring layer is further formed on the wiring board corresponding to the wiring board of the seventh example shown in FIG. 3A, but is not limited to this.
The wiring board of the first example shown in FIG. 1A, the wiring board of the second example shown in FIG. 1B, the wiring board of the fourth example shown in FIG. 2A, and FIG. The wiring board of the fifth example shown in FIG. 5 and the wiring board of the eighth example shown in FIG. 3B may have a configuration in which wiring layers are similarly provided on both outer surfaces.
The formation of the wiring layers 320 and 321 on both sides can be performed in the same manner as the method of forming the wiring layers 191 and 192 together with the blind via 116c (through hole 115c) in the steps shown in FIGS. .

FIG. 1A is a partial cross-sectional view of the first example of the embodiment of the wiring board of the present invention, and FIG. 1B is a partial cross-sectional view of the second example of the embodiment of the present invention. FIG. 1C is a partial sectional view of a third example of the embodiment of the present invention. FIG. 2A is a partial sectional view of a fourth example of the embodiment of the wiring board of the present invention, and FIG. 2B is a partial sectional view of the fifth example of the embodiment of the present invention. FIG. 2C is a partial sectional view of a sixth example of the embodiment of the present invention. FIG. 3A is a partial sectional view of a seventh example of the embodiment of the wiring board of the present invention, and FIG. 3B is a partial sectional view of the eighth example of the embodiment of the present invention. FIG. 3C is a partial sectional view of a ninth example of the embodiment of the present invention. It is process sectional drawing which showed the one part process of one example of the manufacturing method of the wiring board of a 1st example. It is process drawing which showed the process following FIG. It is a figure for demonstrating the manufacturing method of the wiring board of a 2nd example and a 3rd example. It is process sectional drawing for demonstrating the process of plating filling, and a planarization process. It is process sectional drawing of the manufacturing method of the conventional core board | substrate. It is a schematic sectional drawing of the conventional multilayer wiring board. It is the schematic sectional drawing which showed the semiconductor package using a multilayer wiring board. FIG. 10 is a diagram showing the cross-sectional shape of each part for explaining the mechanical polishing process, and FIGS. 10 (a), 10 (b), and 10 (c) show the cross-sectional shapes before mechanical polishing. 10 (a1), FIG. 10 (b1), and FIG. 10 (c1) each show a corresponding cross-sectional shape after mechanical polishing. FIG. 3 is a view of a wiring board in which a wiring layer is further formed on one outer surface of a wiring board having three wiring layers according to the present invention. FIG. 3 is a view of a wiring board in which wiring layers of the present invention are further formed on both outer sides of a three-layer wiring board.

Explanation of symbols

10 multilayer wiring board 11 wiring member 12 solder resist 15 external connection terminal (solder ball)
20 Semiconductor chip 21 Solder bump 30 Underfill resin 40 Sealing resin 100, 101 Wiring substrate 110, 111 Resin base layer 115 Through holes 115a, 115b, 115c (for through hole formation) Through hole 116 (blind via formation) Holes 116a, 116b, 116c Blind vias 121, 122, 123 Copper foil 122A Internal wiring layer wiring 130 Electroless plating layer 150 Resist pattern 160 Electrolytic plating layer 165 Dented (also referred to as dent)
170 Solder resist 181 Ni plating layer 182 Au plating layer 185 Terminal portion 191, 191 A, 191 B, 192, 192 A, 192 B Wiring 193, 193 A (through hole) conducting portion 194, 194 A (blind via) conducting portion 200 Wiring substrate 210 Core substrate (insulating substrate)
220 Wiring layer 221 Copper layer (copper foil layer)
225 Plating Cu layer 250 Bump 260 Filler 270 Solder resist 285 Terminal portion 290 Insulating resin layer 301, 302 Additional layer 320, 321 Wiring layer 325, 326 Conductive portion 370 Solder resist 385 Terminal portion 390, 391 Insulating resin layer 710 Copper clad laminate 711 Core material 712 Copper foil 715 Through hole 720 Electroless copper (copper plating layer)
730 Copper plating layer 740 Filling material 750 Through hole 760 Core substrate 760
810 Multilayer wiring board 811 Core substrate 820 Electroless plating layer 830 Electrolytic plating layer 840 Filler 851, 851a Insulating layer 852, 852a Insulating layer 855 Connection pad 861, 862 Wiring part 865 Connection pad 871, 872 Via 880 External connection Terminal 885 Solder resist 890 Semiconductor chip 891 Metal bump 910, 910a Connection wiring 920, 920a Terminal (also referred to as pad)
930, 930a Through hole 931 Recessed (also called dent)
932, 932a Land 935 Conducting portion 950 (through hole) Insulating base material portion

Claims (18)

  Only one wiring layer formed by the semi-additive method is provided on each of the roughened surfaces on both sides of the core wiring substrate having one wiring layer inside the insulating resin substrate layer. A three-layer wiring board having three wiring layers, provided with conductive portions plated in the holes of the resin base layer formed by laser, and for each wiring layer on the front and back of the core wiring base. Provided with blind vias that electrically connect the wiring and the wiring of the internal wiring layer, respectively, or the blind via and a conductive portion formed by plating in a through-hole portion of a resin base material layer formed by a laser A wiring board comprising: a through hole that is provided and electrically connects wirings on the wiring layers on the front and back sides of the core wiring base.   The wiring board according to claim 1, wherein the one wiring layer inside the insulating resin base layer of the core wiring base is disposed substantially at the center in the thickness direction of the insulating resin base layer. A wiring board characterized by being made.   3. The wiring board according to claim 1, wherein each of the blind via or the blind via and the through hole has a hole portion of a resin base layer formed by a laser. 4. A three-layer wiring board, which is filled with a conductive part formed by plating.   The wiring board according to claim 3, comprising an outer surface of a blind via, or an outer surface of a blind via and a through hole, wherein the outer surface side of the wiring portion of each wiring layer on the front and back surfaces is mechanically polished. Alternatively, a planarization process is performed by chemical mechanical polishing.   5. The wiring board according to claim 1, wherein the roughness of the roughened surfaces on both sides of the core wiring base material is a range of 10-point average roughness RzJIS of 2 μm to 10 μm. A wiring board characterized by the above.   6. The wiring board according to claim 1, wherein an insulating resin layer (solder resist) covering the front and back surfaces of the wiring board is disposed in a state where a predetermined terminal portion is exposed. Wiring board.   7. The wiring board according to claim 1, wherein the wiring board is a wiring board for a semiconductor package.   8. The wiring board according to claim 7, wherein one surface has a connection pad for connecting to a semiconductor chip by a flip chip method or a wire bonding method, and the other surface is for connecting to an external circuit. A wiring board having an external connection terminal.   The wiring board according to any one of claims 1 to 8, wherein the terminal part is provided with a Ni plating layer and an Au plating layer in order.   7. A wiring board, further comprising a wiring layer formed on both sides or one side of the wiring board according to claim 1.   A semiconductor package using the wiring board according to claim 1. Only one wiring layer formed by the semi-additive method is provided on each of the roughened surfaces on both sides of the core wiring substrate having one wiring layer inside the insulating resin substrate layer. A method of manufacturing a three-layer wiring board having three wiring layers, wherein, in order, (A) the internal wiring layer is disposed inside an insulating resin base material layer, and a through hole is formed. A core wiring base material forming step for forming a core wiring base material provided with a through hole and a blind via forming hole; and (B) a core wiring base material obtained by the core wiring base material forming step. Electroless plating is performed on the entire surface including the surface of the hole for forming the hole and the hole for forming the blind via to form an electroless plating layer as a conductive layer, and a resist pattern is formed on both sides. The electroless plating layer is used as a current-carrying layer. a selective plating step in which u plating is performed and the wiring part including the terminal part and the conductive part of the through hole for forming the through hole and the hole for forming the blind via are selectively formed by the electrolytic Cu plating layer; After removing the resist pattern, the exposed unnecessary electroless plating layer is removed by flash etching, and an etching process is sequentially performed to form conductive layers of through holes and blind vias, and wiring portions on both sides The core wiring substrate forming step is, in order, (a) a laminate in which a copper foil is pressure-bonded and laminated on both surfaces of the first insulating resin substrate layer. A photosensitive resist is disposed on the copper foil on one side of the base material, subjected to predetermined selective exposure and development, and a resist pattern corresponding to the wiring layer to be formed is formed. Etching the copper foil using as an etching resistant mask, removing the resist pattern, leaving the copper foil on the other surface of the insulating resin base layer to be a wiring layer inside the core wiring base A first wiring base material forming step of obtaining a first wiring base material in which an internal wiring layer is formed on one surface of the insulating resin base material layer; and (b) the first wiring base material. A copper foil is laminated and pressure-bonded to the internal wiring layer forming side through a second insulating resin base material layer made of the same material as the first insulating resin base material layer, or the first On the inner wiring layer forming side of the wiring substrate, a laminated substrate in which a copper foil is pressure-bonded and laminated on one surface of the second insulating resin substrate layer made of the same material as the first insulating resin substrate layer, The second insulating resin base material layer side is directed to the internal wiring layer side and laminated and pressure-bonded, and the internal wiring layer is bonded to the first insulating resin base. The process of obtaining the 2nd wiring base material which is arrange | positioned in the boundary part of a material layer and a 2nd insulating resin base material layer, and laminated | stacked copper foil on the outer surface of each insulating resin base material layer, respectively (C) Furthermore, the copper foil on the outer surface of each insulating resin substrate layer of the second wiring substrate is removed by etching, and the internal wiring layer is placed inside the insulating resin substrate layer. A third wiring substrate forming step for obtaining a third wiring substrate disposed; and (d) a through hole and a blind via for forming a through hole in the third wiring substrate by a CO ₂ laser or a UV laser. A hole for forming is formed, and further, a desmear treatment is performed as necessary, and a drilling step is performed to obtain a core wiring substrate, and on the outer surface of the second wiring substrate Each of the copper foils is an electrolytic copper foil having a rough surface formed by the electrolytic plating directed toward the resin base material layer side. By quenching removal method for manufacturing a wiring substrate, characterized in that in which the shape of the rough surface of the copper foil is transferred and formed on the corresponding resin base layer side.   13. The method of manufacturing a wiring board according to claim 12, wherein the electrolytic Cu plating in the selective plating step is to fill a through hole for forming a through hole and a hole for forming a blind via with an electrolytic Cu plating layer. A method of manufacturing a wiring board.   14. The method of manufacturing a wiring board according to claim 13, wherein the resist pattern is removed after the selective plating step or before the unnecessary electroless plating layer is removed by flash etching after the resist pattern is removed. Alternatively, after removing unnecessary electroless plating layer by flash etching, mechanical polishing or chemical mechanical polishing is performed to planarize the electrolytic Cu plating layer selectively formed by selective plating. A method for manufacturing a wiring board.   15. The method of manufacturing a wiring board according to claim 12, wherein the drilling of the insulating resin base layer by the laser in the drilling step does not excessively reflect the laser on one surface. A method of manufacturing a wiring board, comprising: placing a contact plate and performing laser irradiation from the other surface.   16. The method for manufacturing a wiring board according to claim 12, further comprising: (E) a photosensitive insulating resin layer (solder resist) formed on both sides in sequence after the flash etching step. And a patterning step of the insulating resin layer (solder resist), in which the insulating resin layer (solder resist) is subjected to masking exposure, developed, and the terminal portion is exposed.   17. The method for manufacturing a wiring board according to claim 16, wherein the surface of the terminal portion is successively subjected to Ni plating and Au plating after the patterning step of the insulating resin layer (solder resist). Manufacturing method. 18. The method of manufacturing a wiring board according to claim 12, wherein the resist pattern is formed when the selective plating step is performed by providing a dry film resist, performing masking exposure, and developing. A method of manufacturing a wiring board, wherein the wiring board is formed.

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