JP2008108904A - Four-layer substrate for semiconductor package, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a four-layer substrate for a semiconductor package which is of high performance, with a simple structure, at a reduced manufacturing cost. <P>SOLUTION: The substrate comprises a first insulating base material (1) where a copper foil (2) is pasted on both surfaces, and a second insulating base material (7) which is provided on both sides of the first insulating base material (1), with a copper foil (8) pasted on one outside surface. A first blind via hole (11) is formed which extends from an opening (10) for a blind via hole of the outer layer copper foil (8) on the outside of the second insulating base material (7) and reaches the outer layer copper foil (8) on the opposite side by penetrating openings (6 and 6) for blind via hole formed on the inner layer copper foil (2) on both surfaces of the first insulating base material (1). A second blind via hole (12) is formed which extends from the opening (10) for the blind via hole of the outer layer copper foil (8) and reaches the inner layer copper foil (2) on the opposite side by penetrating the opening (6) for the blind via hole of the inner layer copper foil (2) of the first insulating base material (1) on the side of the opening (10) for the blind via hole. Conduction is established between layers via the first and second blind via holes (11 and 12) by copper plating (14). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a four-layer substrate for a semiconductor package for mounting a semiconductor chip and a method for manufacturing the same.

  In recent years, with the high integration of semiconductor devices, it is necessary to increase the density of semiconductor package substrates. In particular, not only multilayering of substrates and thinning of wiring but also miniaturization and high density of through-holes are progressing (see, for example, Patent Documents 1 to 3).

  3A, 3B, and 3C are process diagrams showing an example of a conventional method for manufacturing a four-layer substrate for a semiconductor package. (A)-(aa) in a figure is a figure which shows the cross section of the 4-layer board | substrate for semiconductor packages in each manufacturing process.

  First, as shown in FIG. 3A (a), an insulating base material 21 having a copper foil 22 attached on both sides is prepared. Next, a photosensitive film 23 is attached on the copper foil 22 attached to both surfaces of the insulating substrate 21 (FIG. 3A (b)), and a photosensitive film is formed to form a blind via hole opening 25 described later. The opening 23 is exposed to form an opening forming resist pattern 24 (FIG. 3A (c)). Portions other than the opening forming resist pattern 24 are removed with a developing solution to form openings 25 in the photosensitive film 23 (FIG. 3A (d)).

  Further, the portion of the copper foil 22 from which the photosensitive film 23 has been removed is removed with an etching solution (FIG. 3A (e)), and the photosensitive film 23 is peeled off with an alkaline solution (FIG. 3A (f)). Next, the portion of the insulating base material 21 from which the copper foil 22 has been removed is removed by laser irradiation to form a blind via hole 26 (FIG. 3A (g)). Then, after the blind via hole 26 is formed, desmear treatment and conductive treatment in the blind via hole 26 are performed, and then copper plating 27 is applied to ensure conduction between the copper foils 22 on both sides (FIG. 3A (h)).

  Next, the photosensitive film 23 is affixed on the copper foils 22 on both sides (FIG. 3A (i)), and the photosensitive film 23 on both sides is exposed to form a wiring pattern to form a wiring pattern. (FIG. 3A (j)). Thereafter, portions other than the wiring forming resist pattern 28 are removed with a developer (FIG. 3A (k)). Further, the photosensitive film 23 is removed, and the exposed copper foil 22 is removed with an etching solution to form a wiring pattern 29 (FIG. 3A (l)), and the wiring forming resist pattern 28 is stripped with an alkaline aqueous solution. (FIG. 3A (m)).

  Next, the thermoplastic resin 31 with the copper foil 32 attached on one side is attached to both sides of the insulating substrate 21 on which the wiring pattern 29 is formed (FIG. 3B (n)), and the photosensitive film 23 is further attached. It affixes on the copper foil 32 of an outer layer (FIG. 3B (o)). Next, in order to form an opening 34 for a blind via hole described later, the photosensitive film 23 is exposed to form an opening forming resist pattern 33 (FIG. 3B (p)). Portions other than the opening forming resist pattern 33 are removed with a developer (FIG. 3B (q)). Further, the photosensitive film 23 is removed, and the exposed copper foil 32 is removed with an etching solution (FIG. 3B (r)), and the opening forming resist pattern 33 is peeled off with an alkaline aqueous solution (FIG. 3B (s)). .

Next, laser irradiation is performed to remove the portion of the thermoplastic resin 31 from which the copper foil 32 has been removed, thereby forming a blind via hole 35 (FIG. 3B (t)). After the formation of the blind via hole 35, desmear treatment, conductive treatment in the blind via hole 35, and copper plating treatment are performed, and the copper plating 36 ensures electrical conduction between the outer copper foil 32 and the inner copper foil 22 (FIG. 3B (u)).

  Subsequently, the photosensitive film 23 is stuck on the outer copper foil 32 (FIG. 3B (v)). Then, exposure is performed on the bonded photosensitive films 23 on both sides to form a wiring formation resist pattern 37 for forming a wiring pattern 38 to be described later (FIG. 3C (w)). Thereafter, portions other than the wiring formation resist pattern 37 are removed with a developer (FIG. 3C (x)). Further, the photosensitive film 23 is removed, the exposed copper foil 32 is removed with an etching solution (FIG. 3C (y)), and the wiring formation resist pattern 37 is peeled off with an alkaline aqueous solution (FIG. 3C (z) )). Finally, a circuit protection solder resist 39 is formed on a predetermined portion of the outer layer, and Au / Ni plating 40 is applied to the predetermined electrode portion (FIG. 3C (aa)).

JP-A-7-297551 JP 2001-217543 A JP 2003-7777 A

In the conventional method for manufacturing a four-layer substrate for a semiconductor package shown in FIGS. 3A, 3B, and 3C, as described above, the inner copper foil 22 is blinded with respect to the insulating base material 21 and the inner copper foil 22. After forming the opening 25 for the via hole, forming the blind via hole 26 by laser, ensuring conduction of the blind via hole 26, forming the wiring pattern 29, and forming the wiring on the inner layer copper foil 22, the insulating base material is formed in the same manner as the inner layer. 31 and outer layer copper foil 32, formation of blind via hole opening 34 in outer layer copper foil 32, formation of blind via hole 35 by laser, ensuring conduction of blind via hole 35, formation of wiring pattern 38, outer layer copper foil 32 Repeat wiring formation.
Thus, the conventional method has a problem that the number of manufacturing steps is large and the manufacturing cost is high. In addition, along with the miniaturization of wiring and the like, misalignment of the inner layer and outer layer blind via holes is likely to occur due to errors during exposure and pasting, which hinders conduction between the outer layer and the inner layer, which reduces the yield. It was a cause.

  The present invention provides a four-layer substrate for a semiconductor package that eliminates the above-described problems of the prior art, can reduce the number of steps, and can reduce the manufacturing cost, and a method for manufacturing the same.

  The four-layer substrate for a semiconductor package according to the invention of claim 1 includes a first insulating base material having copper foil attached to both sides, and a copper foil attached to one side of the first insulating base material provided on both sides of the first insulating base material. An opening for blind via holes formed in the inner layer copper foil on both sides of the first insulating base material from the opening for blind via hole in the outer layer copper foil outside the second insulating base material. A first blind via hole penetrating to reach the outer copper foil on the opposite side, and an opening for the blind via hole in the inner copper foil of the first insulating base on the blind via hole opening side from the blind via hole opening in the outer copper foil. At least one blind via hole penetrating to the inner copper foil on the opposite side is formed, and the blind via hole is formed between each layer by copper plating. Wherein the passage has been made.

  A four-layer substrate for a semiconductor package according to a second aspect of the invention is the first aspect of the invention according to the first aspect, wherein a blind via hole opening formed in the outer layer copper foil has a blind diameter formed in the inner layer copper foil. It is characterized by being larger than the diameter of the via hole opening.

According to a third aspect of the invention, there is provided the four-layer substrate for a semiconductor package according to the first or second aspect, wherein the first insulating base and the second insulating base are formed of a flexible material. It is characterized by that.

  According to a fourth aspect of the present invention, there is provided a method for manufacturing a four-layer substrate for a semiconductor package, wherein openings for wiring and blind via holes are provided in the inner-layer copper foil on both sides of the first insulating base material having copper foil attached on both sides. A step of forming, and a second insulating base material having a copper foil attached on one side is attached to both surfaces of the first insulating base material, and the outer layer copper foil is positioned outside the second insulating base material. The step of forming the opening for the blind via hole and the opening for the blind via hole of the outer layer copper foil by irradiating the blind via hole formed in the outer layer copper foil of the second insulating base with laser. A first blind via hole penetrating through an opening for a blind via hole formed in the inner layer copper foil on both surfaces of the first insulating substrate and reaching the outer layer copper foil on the opposite side; and a blind via in the outer layer copper foil A second blind via hole that passes through the blind via hole opening of the inner layer copper foil of the first insulating base on the opening side for the blind via hole and reaches the opposite inner layer copper foil from the opening for the blind via hole Including a step of forming a via hole, a step of performing copper plating on the first blind via hole to conduct between the layers, and a step of forming a wiring on the outer layer copper foil of the second insulating substrate. And

  According to a fifth aspect of the present invention, there is provided the method for manufacturing a four-layer substrate for a semiconductor package according to the fourth aspect of the present invention, wherein the aperture of the blind via hole opening formed in the outer copper foil is formed in the inner copper foil. It is characterized by being larger than the diameter of the blind via hole opening.

  According to a sixth aspect of the present invention, in the method for manufacturing a four-layer substrate for a semiconductor package according to the fourth or fifth aspect, the first insulating base and the second insulating base are formed of a flexible material. It is characterized by being.

  According to the present invention, a four-layer substrate for a semiconductor package can be manufactured with a small number of processes, and the four-layer substrate for a semiconductor package can be obtained at a low cost.

  Exemplary embodiments of a four-layer substrate for a semiconductor package and a method for manufacturing the same according to the present invention will be explained below in detail with reference to the accompanying drawings.

  1A and 1B are process diagrams showing a method for manufacturing a four-layer substrate for a semiconductor package according to an embodiment of the present invention. The manufacturing method will be described in accordance with steps (a) to (t).

(A) First, as shown to FIG. 1A (a), the insulating base material 1 (1st insulating base material) by which the copper foil 2 was affixed on both surfaces is prepared.
(B) Next, the photosensitive film 3 is affixed on the copper foil 2 affixed on both surfaces of the insulating base material 1.
(C) In order to form the wiring 5 and the blind via hole opening 6 which will be described later, the photosensitive film 3 is exposed to form a resist pattern 4.
(D) Then, the photosensitive film 3 in a portion (a portion other than the resist pattern 4) not exposed with the developer is removed.
(E) Further, the portion of the copper foil 2 from which the photosensitive film 3 has been removed is removed with an etching solution. (F) The resist pattern 4 is stripped with an alkaline solution. In this way, the wiring 5 and the blind via hole opening 6 are formed on both surfaces of the insulating base material 1.

(G) Next, the thermoplastic resin 7 (second insulating base material) having the copper foil 8 attached on one side is connected to the wiring 5
And it affixes on both surfaces of the insulating base material 1 in which the opening 6 for blind via holes was formed.
(H) Furthermore, the photosensitive film 3 is affixed on the copper foil 8 in both outer sides.
(I) Next, in order to form a blind via hole opening 10 to be described later, the photosensitive film 3 is exposed to form an opening forming resist pattern 9.
(J) Then, the photosensitive film 3 in a portion not exposed to the developing solution (a portion other than the opening forming resist pattern 9) is removed.
(K) The portion of the copper foil 8 from which the photosensitive film 3 has been removed is removed with an etching solution. (L) As shown in FIG. 1B (l), the resist pattern 9 for opening formation is stripped with an alkaline aqueous solution. By doing so, blind via hole openings 10 are formed outside the thermoplastic resin 7 attached to both surfaces of the insulating substrate 1.

(M) Next, laser irradiation is performed from the opening 10 for the blind via hole to remove the portion of the thermoplastic resin 7 and the insulating substrate 1 from which the copper foils 2 and 8 have been removed, and to remove the copper foil 8 and the inner layer of the outer layer. Blind via holes that connect the copper foil 2 are formed. There are three types of blind via holes formed here: A, B, and C. The A type blind via hole penetrates from the copper foil 8 affixed to the outer layer thermoplastic resin 7 to the copper foil 2 affixed to both surfaces of the inner insulating base material 1 to the opposite outer layer thermoplastic resin 7. This is a blind via hole 11 (first blind via hole) reaching the copper foil 8 affixed to. The B type blind via hole is a blind via hole 12 (second blind via hole) that passes through one surface of the inner copper foil 2 from the outer layer copper foil 8 and reaches two surfaces of the inner copper foil 2. Further, the C type blind via hole is pasted on the outer layer thermoplastic resin 7 opposite to the blind via hole extending from the outer layer copper foil 8 through one surface of the inner layer copper foil 2 to the second surface of the inner layer copper foil 2. The blind via hole 13 (third blind via hole) is a combination of the attached copper foil 8 and the blind via hole reaching the copper foil 2 on the two surfaces.

(N) After forming each blind via hole, after the desmear process and the conductive process in the blind via hole, the copper plating 14 is applied to ensure the conduction between the outer layer copper foil 2 and the inner layer copper foil 8.
(O) Next, the photosensitive film 3 is affixed on the copper foil 8 of the outer layer of both surfaces.
(P) In order to form the wiring 16 to be described later, the photosensitive film 3 is exposed to form a wiring forming resist pattern 15.
(Q) Then, the photosensitive film 3 in a portion not exposed to the developer (portion other than the wiring pattern resist pattern 15) is removed.
(R) The portion of the copper foil 8 from which the photosensitive film 3 has been removed is removed with an etching solution.
(S) Further, the resist pattern 15 for wiring formation is stripped with an alkaline aqueous solution. In this way, the wiring 16 on the outer layer side is formed.
(T) Finally, a solder resist 17 for circuit protection is formed on a necessary part of the outer layer, and Au / Ni plating 18 is applied to the electrode part of the necessary part.

  The four-layer substrate for a semiconductor package according to this embodiment is manufactured through the processes as described above. The structure of this four-layer substrate for a semiconductor package is as follows.

Insulating base material 1 (first insulating base material) having copper foil 2 attached to both surfaces, and thermoplastic resin 7 (second material) provided on both sides of insulating base material 1 and having copper foil 8 attached to one outer surface. Insulating base), and
The outer via-hole copper foil 8 on the opposite side passes through the blind via-hole openings 6 and 6 formed in the inner-layer copper foil 2 on both sides of the insulating substrate 1 from the blind via-hole opening 10 of the outer-layer copper foil 8 outside the thermoplastic resin 7. The first blind via hole 11 reaching
A second blind that reaches from the blind via hole opening 10 of the outer layer copper foil 8 to the opposite inner layer copper foil 2 through the blind via hole opening 6 of the inner layer copper foil 2 of the insulating base 1 on the blind via hole opening 10 side. Via hole 12,
The blind via hole opening 1 from the blind via hole opening 10 of the outer layer copper foil 8
Blind via hole reaching the inner copper foil 2 on the opposite side through the blind via hole opening 6 on the inner layer copper foil 2 of the insulating substrate 1 on the 0 side and the opening for the blind via hole on the outer layer copper foil 8 on the opposite side of the blind via hole A third blind via hole 13 consisting of a blind via hole reaching the inner layer copper foil 2 reaching the blind via hole 10 from 10;
The first to third blind via holes 11, 12 and 13 are electrically connected to each other by copper plating 14.

  In the four-layer substrate for a semiconductor package of this embodiment, the insulating base material 1 and the thermoplastic resin 7 can be formed of a flexible material, which is suitable as a flexible wiring board.

  By the way, as described above, the four-layer substrate for a semiconductor package of the embodiment has three patterns of blind via holes formed in the manufacturing process, but all of them are formed in the outer layer than those formed in the inner layer. The thing has a larger opening diameter. This is due to the following reason.

  FIG. 2 is a diagram for explaining the opening diameter of the blind via hole. As shown in FIG. 2A, when the apertures for the blind via holes formed in the outer layer copper foil and the inner layer copper foil have the same size (conventional example), they are formed in the outer layer copper foil and the inner layer copper foil. If the position of the opening for the blind via hole is shifted, conduction between the outer layer and the inner layer becomes poor.

  On the other hand, as shown in FIG. 2B, the diameter of the blind via hole opening formed in the outer layer copper foil is larger than the diameter of the blind via hole opening formed in the inner layer copper foil (this embodiment). Even if the position of the opening for the blind via hole formed in the outer layer copper foil and the inner layer copper foil is shifted, the outer layer and the inner layer are electrically connected. In the four-layer substrate for a semiconductor package of the present embodiment having such a configuration, the yield of the product can be remarkably improved and the manufacturing cost can be reduced even if the work accuracy of forming the blind via hole is not so high.

  As described above, in the structure and the manufacturing method of the four-layer substrate for a semiconductor package according to the present embodiment, the blinds conventionally performed on the inner-layer substrate and the outer-layer substrate for conducting the inner-layer substrate and the outer-layer substrate, respectively. In the via formation process, the blind via formation of the inner layer substrate and the outer layer substrate is collectively performed, and the number of the blind via hole formation steps can be greatly reduced as compared with the conventional method. As a result, the manufacturing cost can be reduced and an inexpensive four-layer substrate for a semiconductor package can be provided.

Next, specific examples of manufacturing a four-layer substrate for a semiconductor package according to the steps described in the above embodiment will be described.

As the type of the four-layer wiring board, an FCBGA board in which an IC chip and a wiring board are joined with solder balls was used. Espanex M (copper foil thickness = 12 μm, polyimide (PI) thickness = 25 μm) manufactured by Nippon Steel Chemical Co., Ltd. was used for the insulating base material 1 having the inner layer copper foil 2 attached on both sides.
Espanex L (copper foil thickness = 9 μm, liquid crystal polymer (LCP) thickness = 25 μm) manufactured by Nippon Steel Chemical Co., Ltd. was used as the thermoplastic resin 7 with the outer layer copper foil 8 attached on one side.

For the A type blind via hole 11 (first blind via hole), the diameter of the blind via hole opening of each copper foil layer from the outer layer toward the inner layer was set to 160 μm, 100 μm, and 40 μm in order. For the B type blind via hole 12 (second blind via hole), the diameters of the blind via hole openings of the copper foil layers from the outer layer toward the inner layer were set to 100 μm and 40 μm in order. Further, for the C type blind via hole 13 (third blind via hole), the diameter of the blind via hole opening of each copper foil layer from the outer layer on one side to the inner layer is sequentially 160 μm, 100 μm, and the outer layer copper foil on the opposite side. The diameter of the blind via hole opening formed in 8 was set to 40 μm.

  Moreover, LAVIA1000 manufactured by Sumitomo Heavy Industries, Ltd. was used as a laser processing machine that performs laser irradiation for forming blind via holes. A chemical solution manufactured by Ebara Eugleite was used for the desmear treatment and the conductive treatment for removing the debris after the laser irradiation. As the photosensitive film 3, a dry film made of Asahi Kasei with a thickness of 15 μm was used, and the thickness of the electrolytic copper plating was 12 μm.

  As a result of comparing the four-layer substrate for a semiconductor package of this example manufactured under the above conditions and structure with the four-layer substrate for a semiconductor package manufactured by the conventional structure and manufacturing method described above, the quality is equivalent. Was confirmed. In addition, it was also confirmed that the manufacturing cost can be reduced by using the four-layer substrate for a semiconductor package of this example.

It is process drawing which shows the manufacturing method of the 4-layer board | substrate for semiconductor packages concerning one Embodiment of this invention. It is process drawing which shows the manufacturing method of the 4-layer board | substrate for semiconductor packages concerning one Embodiment of this invention. It is a figure for demonstrating the opening diameter of a blind via hole. It is process drawing which shows the manufacturing method of the conventional 4 layer board | substrate for semiconductor packages. It is process drawing which shows the manufacturing method of the conventional 4 layer board | substrate for semiconductor packages. It is process drawing which shows the manufacturing method of the conventional 4 layer board | substrate for semiconductor packages.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Insulating base material 2,8 Copper foil 3 Photosensitive film 4 Resist pattern 5,16 Wiring 6,10 Blind via hole opening 7 Thermoplastic resin 9 Opening resist pattern 11, 12, 13 Blind via hole 14 Copper plating 15 Wiring formation Resist pattern 17 Solder resist 18 for circuit protection Au / Ni plating

Claims (6)

A first insulating base material having a copper foil attached on both sides thereof, and a second insulating base material provided on both sides of the first insulating base material and having a copper foil attached on one side of the outer side,
A blind via hole opening formed in the inner layer copper foil on both sides of the first insulating base material reaches the outer layer copper foil on the opposite side from the blind via hole opening of the outer layer copper foil outside the second insulating base material. 1 blind via hole,
A second blind via hole reaching from the opening for blind via hole of the outer layer copper foil to the inner layer copper foil on the opposite side through the opening for blind via hole of the inner layer copper foil of the first insulating base on the opening side of the blind via hole;
At least one blind via hole is formed,
The four-layer substrate for a semiconductor package, wherein the blind via hole is conductive between the layers by copper plating.   2. The four-layer substrate for a semiconductor package according to claim 1, wherein the aperture of the blind via hole opening formed in the outer layer copper foil is larger than the aperture of the blind via hole opening formed in the inner layer copper foil.   3. The four-layer substrate for a semiconductor package according to claim 1, wherein the first insulating base and the second insulating base are formed of a flexible material. Forming an opening for a wiring and a blind via hole in the inner layer copper foil on both sides of the first insulating base material on which the copper foil is pasted on both sides;
A second insulating base material having a copper foil attached on one side is attached to both surfaces of the first insulating base material, and an opening for blind via holes is formed in the outer layer copper foil located outside the second insulating base material. Forming a step;
By irradiating the blind via hole opening formed in the outer layer copper foil of the second insulating base with laser, the inner layer copper foil on both sides of the first insulating base from the blind via hole opening of the outer layer copper foil. A first blind via hole penetrating the blind via hole opening formed on the outer layer and reaching the outer copper foil on the opposite side, and the first insulating base material on the blind via hole opening side from the blind via hole opening of the outer copper foil. A step of forming at least one blind via hole through a blind via hole opening in the inner layer copper foil and reaching the inner layer copper foil on the opposite side;
Applying copper plating to the blind via hole and conducting between the layers;
Forming a wiring on the outer layer copper foil of the second insulating substrate;
The manufacturing method of the 4-layer board | substrate for semiconductor packages characterized by the above-mentioned.   5. The four-layer substrate for a semiconductor package according to claim 4, wherein a diameter of the opening for the blind via hole formed in the outer layer copper foil is larger than a diameter of the opening for the blind via hole formed in the inner layer copper foil. Production method.   6. The method for manufacturing a four-layer substrate for a semiconductor package according to claim 4, wherein the first insulating base and the second insulating base are formed of a flexible material.

Images