JP5176643B2 - Multilayer circuit board manufacturing method - Google Patents

Description

  The present invention relates to a method for manufacturing a multilayer circuit board by a build-up method, and more particularly to a method for manufacturing a long wiring board that is a semi-finished product for manufacturing a multilayer circuit board.

  In recent years, with the demand for higher functionality, smaller size, and thinner electronic devices, higher density integration of semiconductors and faster operation clocks have been progressing. On the other hand, high density, high speed, miniaturization, etc. are also desired for semiconductor packages and printed wiring boards on which semiconductors are mounted. Miniaturization of wiring circuit patterns, thinning of core substrates, and low dielectric constant of insulating layers Development such as rate improvement is progressing. For example, in a wiring circuit, a wiring width of 20 μm or less is possible by shifting from a subtractive method to a semi-additive method. In addition, a copper-clad laminate has been developed from a core substrate having a thickness of about 800 μm to a thin core substrate having a thickness of about 200 μm and a coreless substrate having a thickness of about 20 μm. Thus, with the advancement of semiconductors, circuit boards are being developed for higher density, multilayers, and higher transmission.

  In addition, as a multilayer technology for such a circuit board, a so-called build-up method is generally known, in which an insulating resin layer and a conductor layer are alternately laminated as outer layers on the inner layer core substrate one by one, and blind vias are used. This is a technique for electrically connecting an inner layer circuit pattern and an outer layer circuit pattern. In this case, the method for forming the via hole can be broadly divided into two methods: a method of forming a via hole using a laser in a non-photosensitive insulating resin and a photo via using a photosensitive insulating resin. In the former case, an excimer laser, a carbon dioxide gas laser, a UV laser, etc. can be cited as the laser light source, and the application speed of the carbon dioxide gas laser is widespread because the device development speed is high and the drilling speed is high. Development of hole processing using a UV laser is also progressing as the density of the laser beam increases.

  In such a build-up method, it is necessary to accurately align the via hole in the outer layer with respect to the land portion of the circuit pattern in the inner layer. In particular, as the density increases, the alignment accuracy becomes increasingly severe. In particular, when the positional accuracy of the land portion and the via hole is poor, even if the land portion and the via hole are electrically connected, the connection portion between the land portion and the via hole is broken in a reliability test in which evaluation is performed under severe conditions. One cause of this breakage is that the center position of the land portion and the via hole is greatly displaced, and the fracture occurs without being able to withstand the stress generated at the connection portion between the land portion and the via hole. Therefore, some inventions and devices have been disclosed in order to improve the above alignment accuracy.

For example, as an example, the outer layer is laminated in the order of the insulating layer and the conductor layer so that the alignment mark formed on the inner layer circuit board is not covered, and the via hole and the outer layer circuit pattern are formed based on the alignment mark formed on the inner layer circuit board. A manufacturing method of a build-up multilayer circuit board that is easy to form is disclosed (see, for example, Patent Document 1, “Manufacturing Method of Multilayer Circuit Wiring Board”).
According to this disclosure, a through hole punched out by a die is formed at an end of an inner layer circuit board, via holes and conductor circuit patterns produced on the inner layer board, and stacked layers sequentially stacked on the front and back of the inner layer circuit board A through hole is used as an alignment mark for forming a via hole and a conductor circuit pattern formed on the body. By the above method, the density of the circuit can be increased, accumulation of position errors does not occur, the alignment accuracy of the inner layer circuit wiring and the outer layer circuit wiring is improved, and good interlayer connection is possible.

In addition, as another method, a multilayer printed wiring board by a build-up method capable of highly accurately aligning an outer layer blind via hole and an inner layer bottom land under the name of “manufacturing method of multilayer printed wiring board”. Has been proposed (for example, see Patent Document 2).
According to Patent Document 2, an alignment mark is covered with a film-like member in advance before laminating an insulating layer on an inner circuit board, and a cut groove penetrating from the outer surface to the film-like member is laminated by laser processing after the conductor layer is laminated. The insulating layer and the conductor layer are removed together with the film-like member, and the alignment mark formed before the lamination is exposed. With the above method, the insulating layer is not excavated when the alignment mark is exposed, and the film-like member only needs to be peeled off. Therefore, the visibility of the alignment mark is not lowered, and unnecessary portions of the insulating layer and the conductor layer are easily removed. Therefore, the alignment mark can be accurately exposed, so that highly accurate alignment can be performed.

Furthermore, as another method, a build-up method capable of accurately forming the position of the circuit pattern to be laminated with respect to the inner-layer circuit board under the name of “multilayer wiring board manufacturing method and semiconductor package and long wiring board”. Has been proposed (see, for example, Patent Document 3).
According to Patent Document 3, after forming a first alignment mark together with a circuit pattern on the first laminate, and laminating the second laminate so that the first alignment is exposed on the first laminate, A second via alignment and a via hole are formed on the second stacked body using the first alignment, and a circuit pattern is formed on the second stacked body using the second alignment. . By using the alignment mark formed in the lower layer by the above method, an upper layer via hole is formed, and the upper layer circuit pattern is formed using the via hole as an alignment mark. The position of the circuit pattern of the layer can be formed with high accuracy.
JP 2004-71749 A JP 2006-237088 A JP 2007-299842 A

  However, in the invention disclosed in Patent Document 1 described above, since the through holes prepared in advance in the inner layer base material serve as alignment marks for forming circuit patterns and via holes every time they are stacked, etching during circuit pattern formation is performed. Increased number of exposures. Therefore, the copper foil at the edge portion of the through hole is excessively etched, and erroneous recognition occurs at the time of alignment recognition in the processing apparatus, resulting in a problem that the position accuracy is lowered.

  Further, in the invention disclosed in Patent Document 2, in the process of coating the alignment mark with a masking material, and forming the outer layer of the via via hole, the masking material and the insulating layer and the conductor layer laminated thereon are removed to align the alignment mark. There is a problem that the manufacturing process is complicated by adding the step of exposing the substrate.

  Furthermore, in the invention disclosed in Patent Document 3, in order to carry out the lamination so as to expose the alignment mark produced in the lower layer, the width of the laminated body (in the direction perpendicular to the conveying direction) increases as the number of laminations increases. Since the effective area that can be used as a multilayer circuit board is reduced, there is a problem in that the number of stacked layers is limited and productivity is lowered.

  The present invention has been made in view of the above points, and in a multilayer circuit board that has been increased in the number of layers, it is a laminate that is stacked on an inner circuit board using alignment marks that are produced on the inner circuit board. The upper via hole and the lower layer can be aligned with a laminated body having the same width even when the body (upper layer) via hole and the inner layer (lower layer) circuit pattern land portion can be aligned with high accuracy. An object of the present invention is to provide a method for manufacturing a multilayer circuit board capable of maintaining a high alignment accuracy with the bottom land.

To solve the above problems, the present onset Ming, the inner layer substrate having a conductive layer for the inner layer board side conductor wiring circuit on both surfaces of the insulating layer, the first and second composed of an insulating layer and the conductor layer through an adhesive was Awa bonding laminate to this order, the form the inner substrate side conductor wiring circuit on the inner layer board, the inner layer substrate, by forming a via hole and laminated body side conductor wiring circuit to the first, second laminate In the manufacturing method of a multilayer circuit board, a through-hole for forming a conductor wiring circuit at an edge in the width direction of the inner-layer board, and orthogonal to the width direction of the inner-layer board with the through-hole for forming a conductor wiring circuit as a center Forming a pair of via-hole forming through holes arranged in the direction of the point, forming the via hole in the inner layer substrate using the via-hole forming through-hole as an alignment mark, and forming the conductor wiring circuit forming through-hole A hole Used as Lee placement mark to the first alignment mark and the second laminate for forming a via hole to said to form an inner layer substrate side conductor wiring circuit at the same time the first stack to the conductor layer of the inner layer board the second alignment marks for forming a via hole adjacent the via holes for forming through-holes are formed on the inner layer substrate, using said first alignment mark in the first laminate to be bonded together in the inner layer board Forming a conductor wiring circuit forming alignment mark on the edge of the first laminated body in the width direction at the same time as forming the via hole, and using the conductive wiring circuit forming alignment mark, the laminated body side conductor wiring circuit is formed by using the second alignment mark in the second laminate are bonded together in the first laminate At the same time as forming the via hole, an alignment mark for forming a conductor wiring circuit is formed on the edge in the width direction of the second stacked body, and the alignment mark for forming the conductor wiring circuit is used to form the alignment mark on the second stacked body. A laminated body-side conductor wiring circuit is formed, the first laminated body is affixed on the inner layer substrate so that the first alignment mark is exposed, and the second laminated body has the second alignment mark The insulating layer is affixed on the first laminated body so as to be exposed, and when the inner-layer substrate-side conductor wiring circuit is formed, the conductor layer in the region where the second alignment mark is disposed is removed in advance. The layer is exposed .

Te present invention odor also to expose the first alignment pattern marks on the inner layer substrate when bonding the first laminate to the inner layer base material, a via hole is formed on the first laminate It is possible to be done.

Te present invention odor also to expose the second alignment marks on the inner layer base material when bonded to the second laminate to the first laminate, via holes on the second stack forming It is possible to be done. In addition, the second laminate can be a laminate having a width equal to or greater than that of the first laminate.

Te present invention smell also because the conductor layer of the region where the second Alignment Tomah over click is disposed Ru removed in advance, it is possible to the second alignment mark is formed on the inner layer substrate, and The shape of the mark is prevented from being deformed, and when the via hole processing is performed on the second stacked body, the second alignment mark can be recognized with high accuracy.

Te present invention odor also uses the first alignment mark, a via hole is formed on the first stack, alignment marks for forming a wiring circuit pattern on the first laminate the first Therefore, it is possible to form a wiring circuit pattern in accordance with the position of the via hole formed on the first stacked body.

Te present invention odor also uses the second alignment mark, a via hole is formed on the second laminate, the alignment marks for forming a wiring circuit pattern on the second laminate second Therefore, it is possible to form a wiring circuit pattern in accordance with the position of the via hole formed on the second stacked body.

  In the present invention, the inner layer substrate, the laminate and the adhesive are supplied by a tape-like long substrate, and the laminate is sequentially bonded to the inner layer substrate via the adhesive by a reel-to-reel method. The method of manufacturing a multilayer circuit board according to claim 1, characterized in that:

  According to the present invention, in the process of manufacturing a multilayer circuit board, the alignment marks formed on the inner layer substrate are used for positioning of via holes on the stacked body that is sequentially bonded to the inner layer substrate, and therefore, the layers having the same width are used. It becomes possible to produce a multilayer circuit board by laminating the base materials sequentially. In addition, since the alignment mark is formed for each layer, the position of the via hole and the wiring circuit pattern formed in each layer and the position of the upper layer via hole with respect to the lower wiring circuit pattern can be accurately formed.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to FIGS.
FIG. 1 is a plan view showing a state in which a sheet-like second laminate is bonded to a sheet-like inner layer base material in a long wiring board. Note that the X direction and the Y direction perpendicular to each other indicated by arrows in the figure are the length direction of the long wiring board (lateral direction in the figure) and the width direction of the long wiring board (up and down direction in the figure), respectively. To do. FIG. 2 is a cross-sectional view (cross-sectional view taken along line YY in FIG. 1) when the long wiring substrate in FIG. 1 is cut in the width direction.

First, as shown in FIG. 2, the inner layer base material A is formed by forming conductor layers 2a and 2b on the front and back sides of the insulating layer 3 having flexibility, and the conductor wiring circuit patterns 2a and 2b are formed. Has been. The circuit patterns 2 a and 2 b are electrically connected by the via hole 4. At both ends in the Y direction of the inner layer base material A, holes 1a and 1b penetrating from the front surface to the back surface are formed, and at least formed of the through holes 1a on a line passing through the center of the multilayer circuit board 19 in the X direction, For example, in FIG. 1, on the line passing through the center of the multilayer circuit board 19 in the X direction, the through hole 1a and the center of the multilayer circuit board 19 are formed at point symmetrical positions.
The alignment mark 6a is formed at a point-symmetrical position with respect to the center of the multilayer circuit board 19 when the circuit pattern of the inner layer base material A is formed. Further, the alignment mark 12a is formed at a point-symmetrical position with respect to the center of the multilayer circuit board 19 when the circuit pattern is formed on the first stacked body Ba . The lower layer surface side alignment marks 6b and 12b are formed in the same manner as the upper layer surface side described above.

Laminates Ba and Bb bonded to the front and back of the inner layer base material A are composed of flexible insulating layers 8 a and 8 b and conductor layers 9 a and 9 b through adhesives 7 a and 7 b. A circuit pattern is formed on the conductor layer. In addition, via holes 10a and 10b are respectively formed in the stacked bodies Ba and Bb, and the holes are filled with metal. The circuit patterns 9a and 9b and the circuit patterns 2a and 2b of the inner layer base material A are electrically connected to each other. Is made. The alignment marks 11a and 11b of the front and back laminated bodies Ba and Bb are formed by penetrating the adhesives 7a and 7b and the laminated bodies Ba and Bb at the same time as forming the via holes 10a and 10b. It is formed on a line passing through the center of. In addition, the alignment marks 12a and 12b are formed by etching the conductor layers 2a and 2b of the inner layer base material A in advance at a point-symmetrical position with respect to the center of the multilayer circuit board 19 when the circuit patterns of the stacked bodies Ba and Bb are formed. It is formed on the regions 5a and 5b where the insulating layer 3 is removed and exposed.

Laminated bodies Ca and Cb respectively bonded to the laminated bodies Ba and Bb are composed of flexible insulating layers 14a and 14b and conductor layers 15a and 15b via adhesives 13a and 13b. Is formed with a circuit pattern. In addition, via holes 16a and 16b are formed in the stacked bodies Ca and Cb, and the holes are filled with metal. The circuit patterns 15a and 15b and the circuit patterns 9a and 9b of the stacked bodies Ba and Bb are electrically connected. Has been. The alignment marks 17a and 17b on the front and back laminates Ca and Cb are formed by penetrating the adhesives 13a and 13b and the laminates Ca and Cb at the same time as forming the via holes 16a and 16b. It is formed on a line passing through the center of.
In FIG. 2, the circuit patterns 2a and 2b of the inner layer substrate, the circuit patterns 9a and 9b of the stacked bodies Ba and Bb, and the circuit patterns 15a and 15b of the stacked bodies Ca and Cb may be formed in different patterns.

The multilayer circuit board 19 is a rectangular area inside the alignment marks 17a and 17b formed on the innermost side in the Y direction, and is used by being separated from a long wiring board.

Next, a method for manufacturing the multilayer circuit board 19 will be described.
First, the inner layer substrate A is processed. As shown in FIG. 3, alignment marks for forming circuit patterns 2a and 2b on the front and back of the inner substrate A are prepared. A through hole 1a penetrating the inner substrate A is formed by punching using a mold, and this is used as an alignment mark. At the same time, the through-hole 1b is formed and used as an alignment mark for forming the via hole 4 that conducts the wiring circuit pattern on the front and back of the inner substrate A.

  Via holes 4 are formed in the inner layer substrate A using the through holes 1b, metal is filled in the via holes 4 by plating to make the front and back conductive, and circuit patterns 2a and 2b are formed using the through holes 1a. At the same time, the conductor layers 2a and 2b are removed so that the insulating layer 3 is exposed in the regions 5a and 5b where the alignment marks 12a and 12b used for processing the laminated bodies Ca and Cb are formed on the front and back of the inner layer substrate A. . This is performed in order to prevent the alignment marks 12a and 12b formed later from being deformed.

  After the via hole processing and pattern circuit formation of the inner layer substrate A are completed, the laminates Ba and Bb made of the insulating layer 8 and the conductor layer 9 are bonded via the adhesive 7 to the alignment mark 6a formed on the inner layer base material A. Adhere to the front and back so that 6b is exposed. Via holes 10a and 10b are formed in the stacked bodies Ba and Bb by the alignment marks 6a and 6b, and at the same time, alignment marks 11a and 11b for forming circuit patterns of the stacked bodies Ba and Bb are formed. After processing the via holes, the via holes 10a and 10b are filled with metal by plating to establish electrical connection between the laminate B and the inner layer base material A. At this time, the regions 5a and 5b where the insulating layer 3 is exposed are also plated, so that the conductor thickness is the same as that of the stacked bodies Ba and Bb.

The circuit patterns on the stacked body Ba and Bb are formed using the alignment marks 11a and 11b. Since the alignment marks 11a and 11b are formed by via hole processing of the stacked bodies Ba and Bb, respectively, the positional accuracy of the circuit patterns 9a and 9b and the via holes 10a and 10b is good. Further, the processing of the via holes 10a and 10b uses alignment marks 6a and 6b, and the alignment marks 6a and 6b are formed simultaneously with the formation of the circuit pattern of the inner layer base material A. Therefore, the positional accuracy of the via holes 10a and 10b and the circuit pattern 2 of the inner layer base material A formed in the stacked bodies Ba and Bb, respectively, is also good.
On the other hand, at the same time as forming the circuit patterns 9a and 9b, the alignment marks 12a and 12b are formed in the regions 5a and 5b so as not to overlap the alignment marks 6a and 6b. The alignment marks 12a and 12b may be formed anywhere within the regions 5a and 5b, respectively, but are preferably formed next to the alignment marks 6a and 6b with respect to the X direction.

  After the processing of the via holes of the multilayer bodies Ba and Bb and the formation of the wiring circuit pattern are completed, the multilayer bodies Ca and Cb composed of the insulating layers 14a and 14b and the conductor layers 15a and 15b are connected to the inner layer via the adhesives 13a and 13b. The alignment marks 12a and 12b formed on the substrate A are bonded to the front and back surfaces so that they are exposed. Via holes 16a and 16b are formed in the stacked bodies Ca and Cb from the alignment marks 12a and 12b. After processing the via hole, plating is performed on both sides, and the via holes 16a and 16b are filled with metal to establish electrical connection between the stacked bodies Ca and Cb and the stacked bodies Ba and Bb. Here, since the alignment marks 12a and 12b are formed next to the alignment marks 6a and 6b, those having the same width as the stacked bodies Ba and Bb can be used.

  The circuit patterns of the stacked bodies Ca and Cb are formed using the alignment marks 17a and 17b, respectively. Since the alignment marks 17a and 17b are formed by processing the via holes of the stacked bodies Ba and Bb, the positional accuracy of the circuit patterns 15a and 15b and the via holes 16a and 16b is good. Further, the processing of the via holes 16a and 16b uses the alignment marks 12a and 12b, and the alignment marks 12a and 12b are formed simultaneously with the formation of the circuit patterns of the stacked bodies Ba and Bb. Therefore, the positional accuracy of the via holes 16a and 16b formed in the stacked bodies Ca and Cb and the circuit patterns 9a and 9b of the stacked bodies Ba and Bb is also good.

The regions 5a and 5 of the inner layer substrate for forming alignment marks for processing the via holes of each stacked body are prepared by previously preparing regions where the insulating layer 3 is exposed, whereby the conductor thicknesses of the stacked bodies Ba and Bb. The following conductor layers can be obtained. Therefore, the alignment marks 12a and 12b can be formed simultaneously with the formation of the circuit patterns Ba and Bb on the laminate. On the other hand, when the regions 5a and 5b in which the insulating layer 3 is exposed in the present invention are not formed, since the conductor layers thicker than the conductor thicknesses of the stacked bodies Ba and Bb are formed in the regions 5a and 5b, the stacked bodies Ba and Bb are formed. When the circuit pattern is formed, it becomes difficult to form the alignment marks 12a and 12b at the same time.
Therefore, in the present invention, the alignment mark can be formed on the inner layer base material without causing the alignment mark shape to collapse. Furthermore, since it becomes possible to laminate | stack without reducing the width | variety of a laminated body and the effective area | region which can be used as a product part can be maintained, even when it increases the number of lamination | stacking, as shown in FIG. Can be produced efficiently. In addition, the upper and lower layer circuit patterns can be accurately connected because the upper layer via holes are always processed using the alignment marks formed in the lower layer circuit pattern.

The vertical width of the laminate composed of the insulating layer films 8a and 8b and the conductor layer films 9a and 9b laminated on the inner layer substrate A is not particularly limited, and both end portions of the inner layer base material A in the vertical width. The alignment marks formed on the substrate may be stacked so as not to be covered.
Arbitrary shapes of alignment marks can be used when forming circuit patterns or processing via holes. For example, circular, donut-shaped, square-shaped, well-shaped, etc., can be checked at the center or at a specific position. Any shape can be used. In particular, a circular shape and a donut shape are preferable.
As a method for forming the alignment mark, a photolithography method, a drilling method, or the like can be used. Examples of the photolithography method include formation of an alignment mark by a photoresist, and an alignment mark formation method by an additive method, a semi-additive method, and a subtractive method. In this method, the shape of the alignment mark can be arbitrarily designed. Further, depending on the process, the circuit pattern and the alignment mark can be formed at the same time. In this case, the number of processes can be reduced. Examples of the drilling process include a drilling process, a laser process, or a punching process using a mold, but the shape of the hole serving as the alignment mark is limited to a circle.
The manufacturing method of the multilayer circuit board 19 is not limited to a single-wafer inner layer board, but can also be applied to a roll-to-roll continuous production method using a tape-like flexible board.
The multilayer circuit board 19 is a case where the circuit pattern has three upper and lower layers. However, the multilayer circuit board 19 can be widely applied to more multilayer circuit boards such as upper and lower four layers and five layers.

Next, with reference to FIGS. 5 and 6, an embodiment of a method for manufacturing a multilayer circuit board according to the present invention will be described.
As shown in FIG. 5A, a tape-shaped double-sided copper foil base material having a width of 105 mm (inner layer base material A in which copper foils of conductor layers 2a and 2b are bonded to both surfaces as polyimide as the insulating layer 3) Then, a punching process was performed with a mold to form a through hole 1 as a through hole, which was used as an alignment mark for via hole processing and circuit pattern formation.

Alignment was performed using the through-hole alignment 1 as a reference, and laser irradiation was performed from the copper foil to the boundary between the polyimide and the lower copper foil to form a via hole 4. Then, after desmear treatment for removing the resin smear generated when the via hole 4 is formed, electroless plating and electrolytic plating are performed to form a filled via that fills the via hole with plating, and the conductive layers 2a and 2b are electrically connected. Connection was made. At this time, the thickness of the conductor layers 2a and 2b is 25 μm. In this case, the electroless plating is performed in order to provide conductivity on the surface of the insulator so that the electrolytic plating can be performed. Through chemical polishing with a mixed solution of sulfuric acid and hydrogen peroxide solution to make the conductor layers 2a and 2b as thin as 15 μm, a positive resist for forming a circuit pattern is applied to the surface of the inner layer substrate A, and through-hole alignment 1 And alignment of the photomask. After that, the exposed portion of the photosensitive resin is removed by batch development, the etching solution is sprayed up and down, the etching resist is removed, the exposed copper foil is chemically etched, and unnecessary etching resist is removed. It peeled and the circuit pattern was formed in the conductor layers 2a and 2b as shown in FIG.5 (b). At the same time, the alignment marks 6a and 6b used for via hole processing of the stacked bodies Ba and Bb are manufactured, and further, the regions 5a and 5b for forming alignment marks used for alignment in via hole processing on the subsequent stacked body are The copper foil was etched to leave the insulating layer 3 exposed.

After forming the circuit pattern of the inner layer base material A, the polyimide-like base materials Ba and Bb with tape-like single-sided copper foil, which are laminates, were laminated and bonded together through an adhesive. At that time, the alignment marks 6a and 6b prepared on both surfaces of the inner layer base material A were not covered. Next, alignment is performed with reference to the alignment marks 6a and 6b, and laser irradiation is performed from the copper foil of the laminated bodies Ba and Bb to the boundary between the polyimide and the copper foil of the inner layer base material, as shown in FIG. Via holes 10a and 10b were formed. Thereafter, desmear treatment for removing resin smear generated when the via holes 10a and 10b were formed was performed. At the same time, to form a luer Raimento marks 11a and 11b be used to form a resist circuit pattern in the laminate Ba and Bb.

  As shown in FIG. 5D, electroless plating and electrolytic plating were performed, and the via holes 10a and 10b were filled vias that fill the via holes with plating, and were electrically connected to the inner layer base material A. In addition, the conductor layers 9a and 9b at this time were set to 25 μm, and the conductor thickness of the regions 5a and 5b formed on the inner layer substrate A was set to 25 μm. In this case, the electroless plating is performed in order to provide conductivity on the surface of the insulator so that the electrolytic plating can be performed. Chemical polishing was performed with a mixed solution of sulfuric acid and hydrogen peroxide solution to reduce the thickness of the conductor layers 9a and 9b to 15 μm. Further, the conductor thickness of the regions 5a and 5b formed on the inner substrate A at this time is also 15 μm. And the positive resist for circuit pattern formation was apply | coated to the surface of laminated body Ba and Bb, and alignment alignment of the via alignment 11a and a photomask was performed. After that, the exposed portion of the photosensitive resin is removed by batch development, the etching solution is sprayed up and down, the etching resist is removed, the exposed copper foil is chemically etched, and unnecessary etching resist is removed. It peeled and the circuit pattern was formed in the conductor layers 9a and 9b as shown in FIG.5 (e). At the same time, alignment marks 12a and 12b used for via-hole processing of the stacked bodies Ca and Cb were produced.

Further, after the circuit patterns of the laminated bodies Ba and Bb were formed, the tape-like single-sided copper foil-attached copper bases Ca and Cb, which were laminated bodies, were laminated together by an adhesive. At that time, a single-sided copper foil-attached polyimide base material having the same width as the laminated bodies Ba and Bb was used so that the alignment marks 12a and 12b produced on both surfaces of the inner layer base material A were not covered. Next, alignment is performed with reference to the alignment marks 12a and 12b, and laser irradiation is performed from the copper foil of the laminated bodies Ca and Cb to the boundary between the polyimide and the copper foils of the laminated bodies Ba and Bb, as shown in FIG. Thus, the via holes 16a and 16b were formed. Thereafter, a desmear process for removing resin smear generated when the via holes 16a and 16b were formed was performed. At the same time, via alignments 17a and 17b used to form resist circuit patterns on the stacked bodies Ca and Cb were formed.
Electroless plating and electrolytic plating are performed, and the via holes 16a and 16b are filled vias that fill the via holes with plating, and are electrically connected to the stacked bodies Ba and Bb. In addition, the conductor layers 15a and 15b at this time were set to 25 μm. In this case, the electroless plating is performed in order to provide conductivity on the surface of the insulator so that the electrolytic plating can be performed. Chemical polishing is performed with a mixed solution of sulfuric acid and hydrogen peroxide solution to reduce the thickness of the conductor layers 15a and 15b to 15 μm, and then a positive resist for forming a circuit pattern is applied to the surfaces of the stacked bodies Ca and Cb. In each of the stacked bodies Ca and Cb, alignment of the via alignments 17a and 17b and the alignment of the photomask was performed. After that, the exposed portion of the photosensitive resin is removed by batch development, the etching solution is sprayed up and down, the etching resist is removed, the exposed copper foil is chemically etched, and unnecessary etching resist is removed. It peeled and the circuit pattern was formed in the conductor layers 15a and 15b as shown in FIG.6 (g).

  As shown in FIG. 6H, since the outermost layer Ca is connected to the semiconductor chip and the outermost layer Cb is connected to the printed wiring board, an opening pad is formed on the circuit patterns of the outermost layers Ca and Cb. Thus, solder resist patterns 18a and 18b were formed. From the above, a long wiring board having a total of six wiring structures, three layers vertically in the stacking direction, was completed. When this value was separated into pieces at a predetermined position, a semiconductor package 19 having a multilayer circuit was obtained.

Industrial applicability

As described above, according to the first and second aspects of the present invention, as a multilayer circuit board manufacturing method by build-up, a wiring pattern is formed on at least the front and back of an insulating layer such as a multilayer printed wiring board or a semiconductor package. The present invention is also applicable when manufacturing a long wiring board having a multilayer circuit having two or more layers.

It is a top view which shows the elongate wiring board which concerns on embodiment of this invention. FIG. 2 is a cross-sectional view taken along line YY of FIG. 1 showing the configuration of the long wiring board and multilayer circuit board shown in FIG. 1. (A)-(c) is a figure which shows the manufacturing method of a multilayer circuit board, and is a top view explaining the process of forming an alignment mark in an inner layer board | substrate. It is a top view of a elongate wiring board, and is a top view which shows an example of the manufacturing method considered when utilizing this invention. (A) to (e) are cross-sectional views for explaining a method of manufacturing a multilayer circuit board. (F) to (h) are cross-sectional views illustrating a method for manufacturing a multilayer circuit board.

Explanation of symbols

    1a, 1b... Through-hole (through-hole alignment), 2a, 2b... Conductor layer or conductor wiring circuit (on inner layer base material) 3, 8a, 8b, 14a, 14b ... Insulating layer 4, 10a, 10b , 16a, 16b... Via hole, 5a, 5b... Region where the insulating layer is exposed, 6a, 6b... Alignment mark (alignment mark for via hole processing on the first laminate), 7a, 7b, 13a, 13b ... Adhesive, 9a, 9b ... Conductor layer or conductor wiring circuit (on the first laminate), 11a, 11b ... Via hole (alignment mark for circuit pattern formation on the first laminate), 12a, 12b ...... Alignment mark (alignment mark for via hole processing on the second laminate), 15a, 15b... Conductor layer or conductor wiring circuit (on the second laminate), 1 a, 17b... via hole (alignment mark for circuit pattern formation on the second laminated body), 18a, 18b... solder resist, 19... multilayer circuit board, A ... inner layer board, Ba, Bb. Laminate body, Ca, Cc... Second laminate body.

Claims (2)

The inner layer substrate having a conductive layer for the inner layer board side conductor wiring circuit on both surfaces of the insulating layer, the first and second stack of insulating layers and the conductor layer via the adhesive was Awa bonded in this order, wherein the inner layer In the method of manufacturing a multilayer circuit board, an inner layer substrate side conductor wiring circuit is formed on a substrate, and via holes and a multilayer body side conductor wiring circuit are formed in the inner layer substrate and the first and second laminates .
A pair of conductor wiring circuit forming through holes and a pair of points arranged in a direction perpendicular to the width direction of the inner layer substrate around the conductor wiring circuit forming through holes at the edge in the width direction of the inner layer substrate Through hole for forming a via hole of
The via hole is formed in the inner layer substrate using the via hole forming through hole as an alignment mark, and the inner layer substrate side conductor is formed in the conductor layer of the inner layer substrate using the conductive wiring circuit forming through hole as an alignment mark. At the same time when the wiring circuit is formed, a first alignment mark for forming a via hole in the first stacked body and a second alignment mark for forming a via hole in the second stacked body are provided in each through-hole for forming the via hole. Formed adjacent to the inner layer substrate,
The conductor wiring circuit forming alignment marks in the width direction of the edge of time the first stack to form the via hole using the first alignment mark in the first laminate is bonded to the inner layer board Forming the laminate-side conductor wiring circuit in the first laminate using the conductor wiring circuit-forming alignment mark,
The via hole is formed in the second laminated body bonded to the first laminated body using the second alignment mark, and at the same time, a conductor wiring circuit is formed at an edge in the width direction of the second laminated body. Forming an alignment mark, and forming the laminate-side conductor wiring circuit in the second laminate using the conductor wiring circuit-forming alignment mark;
The first laminate is affixed on the inner layer substrate so that the first alignment mark is exposed,
The second laminate is affixed on the first laminate so that the second alignment mark is exposed,
At the time of forming the inner-layer substrate-side conductor wiring circuit, the conductor layer in a region where the second alignment mark is disposed is removed in advance to expose the insulating layer ,
A method for manufacturing a multilayer circuit board. The inner layer substrate, the first, second laminate and the adhesive is supplied as a tape-like sheet material, respectively, by the reel-to-reel method, the inner layer substrate, the first, the second laminate 2. The method of manufacturing a multilayer circuit board according to claim 1, wherein each of the sheets is bonded with an adhesive made of the sheet material .

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