JP2010232585A - Multilayer wiring board and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer wiring board which is advantageous in laminating and forming an odd number of conductive layers by a method with high productivity while preventing curving, and to provide a method of manufacturing the same. <P>SOLUTION: A first base material is prepared which has a first insulating layer 101a and a first conductor layer 100a formed on one surface in a thickness direction of the first insulating layer 101a. A second base material is prepared which has a second insulating layer 101b and a second conductor layer 100b formed on one surface in a thickness-direction of the first insulating layer 101b. A third base material is prepared which has a third insulating layer 101c and a third conductor layer 100c formed on one surface in a thickness direction of the third insulating layer 101c. The second base material is laminated by bonding the second insulating layer 101b on the top of the first conductor layer 100a of the first base material with a thin-film adhesion layer 103 interposed. The third base material is laminated by bonding the third insulating layer 101c under the first conductor layer 100a of the first base material with a thin-film adhesion layer 103 interposed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a thin multilayer wiring board having a multilayer structure in which insulating layers made of resin such as polyimide and conductor wiring layers are alternately laminated, and a method for manufacturing the same, and in particular, an odd number using an insulating resin film with a single-sided metal foil This is suitable for manufacturing a multi-wiring board having a conductor layer.

In recent years, due to advancement of electronic technology, electronic information devices such as mobile phones and information communication terminals have been remarkably advanced in function, size and speed.
Along with this, circuit boards such as printed wiring boards and semiconductor packages are also required to have higher density and thinner wiring patterns, and wiring boards tend to be multilayered.

Such a multilayer wiring board is formed by alternately stacking insulating resin layers and conductor wiring layers on a copper-clad substrate or a ceramic substrate (see, for example, Patent Document 1).
The insulating layer of the multilayer wiring board manufactured by this method can be formed and thinned by applying a resin such as polyimide. Further, the conductor wiring layer can be formed by plating, and fine wiring is possible.
On the other hand, the via hole connecting the upper and lower conductor wiring layers can be formed by forming a hole by laser processing or the like and filling the inside with plating.
For this reason, it is possible to achieve a higher wiring density, a thinner film, and a smaller size compared to a conventional multilayer printed wiring board in which copper-clad substrates are laminated at once or a ceramic multilayer wiring board in which green sheets are laminated and fired at once. .

In addition, there is a configuration in which a polyimide film with copper foil is bonded to a conventional multilayer printed wiring board with an adhesive, and even in this configuration, fine wiring can be formed from the thinness of the copper foil. Similarly, high wiring density, thin film, and miniaturization can be achieved (see, for example, Patent Document 2).
Furthermore, since it is a tape-like film, reel-to-reel processing is possible and, unlike conventional single wafer processing, production efficiency can be improved.

Here, the conventional printed wiring board manufacturing method can efficiently stack even-numbered conductive layers, but is not suitable for stacking odd-numbered conductive layers.
This is because in multilayer board manufacturing, a double-sided two-layer base material having conductor layers on both sides of an insulating layer is used as a starting base material, and the build-up method of laminating the base material on the upper and lower conductor layers is widely supported. is there.
The reason why such a manufacturing method is used is that when the base material is laminated only on one side of the upper and lower conductor layers, the warpage of the entire substrate tends to become so large that it cannot be ignored.
In multilayer boards, it is preferable to keep the warpage to a minimum, and if the warpage of the board is large, it may become impossible to mount the board and the chip, and there may be serious problems such as the occurrence of cracks in terms of reliability. Will increase.

Patent Document 3 can be cited as a method for laminating and forming an odd number of conductive layers while preventing warpage. Multi-layering in the above-mentioned patent document is performed by thermocompression bonding of a prepreg containing glass cloth.
In this method, since the glass cloth becomes the core layer, it is difficult to reduce the thickness of the substrate, and the influence of power transmission loss can be considered. Further, since the substrate is hard, mass production by reel-to-reel is difficult, and there is a problem that production efficiency is not good.

Japanese Patent Laid-Open No. 4-148590 JP 2001-53115 A Japanese Patent Laid-Open No. 2006-237637

  SUMMARY OF THE INVENTION The present invention has been made in view of the above-described conventional problems, and an object thereof is to provide a multilayer wiring board having a thin core layer and a method for manufacturing the same. It is intended to be laminated and formed.

In order to solve the above-mentioned problem, the invention of claim 1 is a first comprising: a first insulating layer; and a first conductor layer formed on one surface of the first insulating layer in the thickness direction. A second insulating layer, a second insulating layer, and a second insulating layer formed on one surface in the thickness direction of the second insulating layer, and a third insulating layer And a third substrate having a third conductor layer formed on one surface in the thickness direction of the third insulating layer, and the first conductor layer of the first substrate. The second insulating layer is bonded onto the first base material by laminating the second base material, and the first base material under the first insulating layer is adhesively bonded to the second base material. The third insulating layer is adhered and the third base material is laminated, and thus the base material having the insulating layer and the conductor layer is laminated on the upper and lower sides of the first base material, and the number of the conductor layers is determined. Many characterized by odd numbers Is a wiring board.
That is, by using an insulating resin base material with a single-sided metal foil having a conductor layer only on one side of the insulating layer as a starting material, and laminating the base material on the upper and lower sides, both sides having a conductor layer on the upper and lower sides of the conventional insulating layer It is a multilayer wiring board having a low warpage and an odd number of conductor layers, compared to a board prepared by laminating a base material only on one side of a two-layer base material.

The invention of claim 2 is characterized in that a difference between the sum of the thickness of the first insulating layer and the thickness of the third insulating layer and the thickness of the second insulating layer is within 3 μm. The multilayer wiring board according to Item 1.
That is, since the sum of the thicknesses of the first insulating layer and the third insulating layer is substantially equal to the thickness of the second insulating layer, the structure of the entire substrate is highly symmetrical, and the first to third insulating layers This is a multilayer wiring board with less warping than when the thicknesses are all equal.

The invention of claim 3 includes a first base material having a first insulating layer and a first conductor layer formed on one surface in the thickness direction of the first insulating layer; A second substrate having an insulating layer and a second conductor layer formed on one surface in the thickness direction of the second insulating layer; a third insulating layer; and the third insulating layer. A third substrate having a third conductor layer formed on one surface in the thickness direction of the first substrate, and an adhesive agent on the first conductor layer of the first substrate. The second insulating layer is bonded to the second base material, and the third insulating layer is bonded to the first base material under the first insulating layer via an adhesive. The third base material is laminated, and thus the base material having the insulating layer and the conductor layer is laminated on the upper and lower sides of the first base material so that the number of the conductor layers is an odd number. A method for manufacturing a multilayer wiring board .
That is, by using an insulating resin base material with a single-sided metal foil having a conductor layer only on one side of the insulating layer as a starting material, and laminating the base material on the upper and lower sides, both sides having a conductor layer on the upper and lower sides of the conventional insulating layer This is a method for producing a multilayer wiring board having a lower warpage and an odd number of conductor layers than a board prepared by laminating a base material only on one side of a two-layer base material.

The invention according to claim 4 is characterized in that a difference between the sum of the thickness of the first insulating layer and the thickness of the third insulating layer and the thickness of the second insulating layer is within 3 μm. Item 4. A method for producing a multilayer wiring board according to Item 3.
That is, since the sum of the thicknesses of the first insulating layer and the third insulating layer is substantially equal to the thickness of the second insulating layer, the structure of the entire substrate is highly symmetrical, and the first to third insulating layers This is a method of manufacturing a multilayer wiring board with less warping than when the thicknesses are all equal.

  In the inventions of claims 2 and 4, the difference between the sum of the thicknesses of the first insulating layer and the third insulating layer and the thickness of the second insulating layer is set to 3 μm or less. It is preferable from the viewpoint of the symmetry of the substrate, and if it exceeds 3 μm, the structural symmetry is lost, and the magnitude of the warp cannot be ignored.

  The multilayer wiring board and the manufacturing method can be processed on a reel-to-reel with high productivity. Furthermore, since the core layer is formed of a polymer such as an adhesive and polyimide, the power transmission loss due to the core layer can be minimized, and the substrate can be thinned.

  According to the multilayer wiring board and the manufacturing method thereof of the present invention, a single-sided base material with a metal foil having a conductor layer only on one side of the insulating layer is used as a starting material, and a base material with an insulating layer thickness adjusted is laminated on both sides. As a result, an odd number of conductive layers can be stacked and formed, and a multi-layer wiring board having a higher productivity and lower warpage than the conventional manufacturing method and having a thin core layer and a manufacturing method thereof can be provided. .

(A) thru | or (e) is explanatory drawing which shows an example which concerns on the manufacturing method of the multilayer wiring board of this invention. (F) thru | or (i) are explanatory drawings following FIG. (J) thru | or (m) are explanatory drawings following FIG.

The multilayer wiring board and the manufacturing method thereof according to the present invention will be described in more detail.
A polyimide 1000 with a single-sided copper foil having a first insulating layer 101a made of an organic insulating material and a first conductive layer 100a made of a conductive material shown in FIG.
That is, a first base material having a first insulating layer 101a and a first conductor layer 100a formed on one surface in the thickness direction of the first insulating layer 101a is prepared.
Next, as shown in FIG. 1B, a photoresist 102 is coated on polyimide 1000 with a single-sided copper foil.
Various materials can be used for the base material used for the printed wiring board. However, in the production process, it is preferable to use a reel-to-reel for improving production efficiency.
As the material, polyimide film with copper foil using polyimide as insulating material and copper foil as conductor material is more preferable.
The reason why the polyimide film with copper foil is recommended here is that the insulating layer capable of reel-to-reel processing includes liquid crystal polymer, polyimide resin, polyolefin resin, etc., heat resistance, flexibility, smoothness, low water absorption Polyimide resin is recommended as satisfying
The conductor layer may be made of metal and has good conductivity. However, copper is generally preferable from the viewpoint of cost and conductivity, and copper foil having good smoothness such as electrolytic copper foil and rolled copper foil is more preferable. preferable.

Next, as shown in FIG. 1C, exposure and development are performed.
Subsequently, etching is performed as shown in FIG. 1D, and a circuit is formed using a known photolithography technique in which resist is removed as shown in FIG.

On the substrate thus formed, as shown in FIG. 2 (f), polyimide 1000 with a single-sided copper foil is roll-laminated on both sides of the conductor layer and the insulating layer of the first base material via the thin film adhesive layer 103. Is laminated.
More specifically, a second base material having a second insulating layer 101b and a second conductor layer 100b formed on one surface in the thickness direction of the second insulating layer 101b is prepared. A third base material having three insulating layers 101c and a third conductor layer 100c formed on one surface in the thickness direction of the third insulating layer 101c is prepared.
The second insulating layer 101b is bonded to the first conductor layer 100a of the first base material via an adhesive (thin film adhesive layer 103) to laminate the second base material.
Further, the third insulating layer 101c is adhered to the first insulating layer 101a of the first substrate via an adhesive (thin film adhesive layer 103), and the third substrate is laminated.
The thickness of the single-sided polyimide used here is desirably such that the sum of the thicknesses of the first insulating layer 101a and the third insulating layer 101c is substantially equal to the thickness of the third insulating layer 101b. . This is because the symmetry of the entire substrate is maintained.

As shown in FIG. 2G, via holes 104 for connecting the conductor wiring layers are formed in the laminated first base material, second base material, and third base material.
More specifically, a via hole 104 that connects the first and second conductor layers 100a and 100b and a via hole 104 that connects the first and third conductor layers 100a and 100c are formed.
As a method for forming the via hole 104, laser processing is preferable. There are carbon dioxide laser, YAG laser (fundamental wave, second harmonic, third harmonic, or fourth harmonic), or excimer laser, etc., but both conductor layer and insulating layer are processed. A YAG laser (third harmonic or fourth harmonic), which is a short wavelength laser of 400 nm or less that can be processed simultaneously, or an excimer laser is more preferable.
Next, the residue of the organic insulating material deposited in the lower layer of the via hole is immersed in a liquid such as a mixed liquid of potassium permanganate and sodium hydroxide, and desmear treatment is performed.

Next, as shown in FIG. 2H, filled via copper plating for connecting the upper and lower wiring layers (first, second, and third conductor layers 100a, 100b, and 100c) is performed, and the via hole 104 is made of plated copper. Filled vias 105 to be filled are formed.
The plating process includes an electroless copper plating or direct plating process for forming an electroplating seed layer on the resin surface, and an electroplating process for plating using the seed layer as a power supply pattern.
The plating bath for performing filled via copper plating is a so-called general bath having a high copper concentration and a low sulfuric acid concentration.
As shown in FIG. 2 (i), the cross section after filled via plating is as follows. Conductor layers 100b and 100c (copper foil) on the second and third insulating layers 101b and 101c of the second and third substrates. In this state, electrolytic plating copper 106 is deposited.

After the filled via plating, since the plating is thick on the surface of the conductor layer, in order to perform the subsequent pattern plating, it is necessary to reduce the film thickness of the electrolytically plated copper 106 as shown in FIG.
The polishing performed to reduce the film thickness of the electrolytically plated copper 106 includes physical polishing and chemical polishing. However, when physical polishing is performed, in the case of a tape-shaped substrate, the substrate is expanded and contracted. Chemical polishing is preferred because it causes problems such as poor alignment.
Chemical polishing can be performed using a known etching solution.

Next, as shown in FIG. 3J, a photoresist 102 is coated on the surface of the copper 106 formed on the second conductor layer 100b and the third conductor layer 100c.
Next, as shown in FIG. 3 (k), exposure, development, etching, and peeling are performed to form an outermost layer circuit.
Furthermore, when producing a multilayer substrate, as with the base material before lamination, via hole hole laser processing, via hole filled via plating treatment, copper foil chemical polishing, resist coating, exposure, development, etching, resist stripping process By repeating the above, a circuit of the laminated portion is formed.
In other words, similarly to the second and third substrates, a substrate having an insulating layer and a conductor layer is laminated on the top and bottom of the first substrate, and the number of conductor layers is an odd number.

  After the circuit formation is completed, as shown in FIG. 3L, the solder resist 107 is processed on the circuits formed on the second and third substrates, and the filled via 105 is subjected to a surface treatment such as nickel gold plating 108. These may be processed by appropriately adopting known methods.

  Thereafter, as shown in FIG. 3 (m), by performing solder printing, the solder bumps 109 were printed on the filled vias 105 (nickel gold plating 108) to obtain a target multilayer substrate.

Hereinafter, the present invention will be described by way of specific examples.
A polyimide tape with a single-sided copper foil (Cu / PI = 12 μm / 12.5 μm) was used for the substrate.
First, in order to form a wiring pattern on one side, a dry film resist for wiring formation was heated and pressed with a laminator to form a laminated resist layer.
Next, using a photomask having a predetermined pattern, exposure was performed with parallel light using an ultrahigh pressure mercury lamp as a light source, and development was performed with a 1% aqueous sodium carbonate solution to obtain a desired resist shape.
Copper was etched by ferric chloride having a specific gravity of 1.40. Thereafter, the resist was stripped with a 3% aqueous sodium hydroxide solution to obtain a circuit pattern.

Next, a polyimide tape with a single-sided copper foil was attached to both sides with a roll laminator via an adhesive.
Here, the polyimide tape with single-sided copper foil laminated on the conductor layer side is Cu / PI = 12 μm / 25 μm, and the one laminated on the insulating layer side is Cu / PI = 12 μm / 12.5 μm.
This is for adjusting the thickness of the insulating layer so that the entire substrate has a structural contrast.

After that, in order to process the hole for the via hole, an ultraviolet laser with a wavelength of 355 nm was used to process the hole for the via hole.
The processed hole diameter for via holes was 60 μm.
Further, in order to remove the resin residue deposited at the bottom of the via hole hole, potassium permanganate and sodium hydroxide were dissolved in ion exchange water at a ratio of 3 to 2, and heated to about 50 ° C.
The substrate was immersed in this mixed solution to remove the resin residue.

Thereafter, an electroless copper plating process was performed in order to form an electroplating seed layer. Thereafter, an electrolytic plating treatment was performed with a copper sulfate plating solution.
Next, chemical polishing was performed to reduce the copper thickness. The chemical polishing liquid used was a sulfuric acid / hydrogen peroxide type chemical polishing liquid, and both surfaces of the conductor layer were polished from a plated copper thickness of about 20 μm to about 11 μm.

  Thereafter, resist coating, exposure, development, etching, and peeling are performed in the same manner, and circuit formation of the outermost layer can cope with shrinkage of the opening portion of the solder resist process later on the land of the semiconductor element mounting portion in advance in the circuit formation mask. As a result, correction was made to make it larger.

  Then, a pattern was formed on the outermost layer portion with a solder resist, and SnPb eutectic solder bumps were formed on the openings of the solder resist by a solder printing method to obtain a target multilayer substrate.

The warpage of the multilayer substrate obtained here was measured.
As a measuring method, the height of any 25 points of the solder resist coating portion on the BGA surface side of the substrate is measured, and the difference between the largest and smallest absolute values is taken.
As a result, the warpage of the substrate in this measurement method is 90 μm, which can sufficiently withstand the actual printed wiring board and the semiconductor chip, and is considered to have high reliability.

(Comparative example)
As a comparative example, a three-layer substrate was prepared by a general method from a double-sided two-layer substrate having copper foil on both sides of polyimide as a starting substrate, and the warpage of this substrate was measured by the same method as described above.

  When the warpage of the three-layer substrate produced from the double-sided two-layer substrate was measured, it was found to be 150 μm, which was a severe result for mounting on a printed wiring board and a semiconductor chip.

100a... First conductor layer, 100b... Second conductor layer, 100c... Third conductor layer, 101a... First insulation layer, 101b. Insulating layer, 1000 ... first substrate, 102 ... photosensitive resin, 103 ... laminated adhesive layer, 104 ... via hole, 105 ... electrolytic plating metal (filled via), 106 ... electrolytic plating layer, 107 ... Solder resist, 108 ... Nickel gold plating layer, 109 ... Solder bump.

Claims (4)

A first substrate having a first insulating layer and a first conductor layer formed on one surface in the thickness direction of the first insulating layer;
A second substrate having a second insulating layer and a second conductor layer formed on one surface in the thickness direction of the second insulating layer;
A third substrate having a third insulating layer and a third conductor layer formed on one surface in the thickness direction of the third insulating layer;
Adhering the second insulating layer via an adhesive on the first conductor layer of the first substrate to laminate the second substrate,
Adhering the third insulating layer via an adhesive under the first insulating layer of the first substrate to laminate the third substrate,
Thus, the base material which has an insulating layer and a conductor layer is laminated on the upper and lower sides of the first base material, and the number of the conductor layers is an odd number.
A multilayer wiring board characterized by that. The difference between the sum of the thickness of the first insulating layer and the thickness of the third insulating layer and the thickness of the second insulating layer is within 3 μm.
The multilayer wiring board according to claim 1, wherein: A first substrate having a first insulating layer and a first conductor layer formed on one surface in the thickness direction of the first insulating layer;
A second substrate having a second insulating layer and a second conductor layer formed on one surface in the thickness direction of the second insulating layer;
Preparing a third base material having a third insulating layer and a third conductor layer formed on one surface in the thickness direction of the third insulating layer;
Adhering the second insulating layer via an adhesive on the first conductor layer of the first substrate to laminate the second substrate,
Adhering the third insulating layer via an adhesive under the first insulating layer of the first substrate to laminate the third substrate,
Thus, the base material which has an insulating layer and a conductor layer is laminated on the upper and lower sides of the first base material, and the number of the conductor layers is an odd number.
A method for manufacturing a multilayer wiring board. The difference between the sum of the thickness of the first insulating layer and the thickness of the third insulating layer and the thickness of the second insulating layer is within 3 μm.
The method for producing a multilayer wiring board according to claim 3.

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