JP2004071749A - Method of manufacturing multilayer circuit wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase the density of the circuits and to facilitate the confirmation of alignment marks of an inner layer circuit wiring board without accumulating positional errors in alignment, in a method of manufacturing a build-up multilayer circuit wiring board wherein an insulation layer and a conductor layer are stacked in this order via an adhesive on the inner layer circuit wiring board having the alignment marks and conductor wiring patterns to form an outer layer, and then the conductor wiring circuit is formed in the conductor layer of the outer layer. <P>SOLUTION: The outer layer is stacked on the inner layer circuit wiring board so as not to cover the alignment marks formed in the inner layer circuit wiring board. With the alignment marks formed in the inner layer circuit wiring board as a reference, the conductor wiring patterns of an outer layer circuit and vias for electrically connecting the outer layer and the inner layer are formed. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a build-up multilayer circuit wiring board on which a semiconductor element is mounted and a method for manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art In recent years, as electronic and electric devices have become smaller and lighter, there has been a demand for thinner and higher density multilayer circuit wiring boards. In order to satisfy this demand, attention has been paid to a build-up multilayer circuit wiring board formed by sequentially stacking conductive circuits on an inner-layer circuit wiring board.
[0003]
In a method of forming a build-up multilayer circuit wiring plate, an additive method, a semi-additive method, or a subtractive method is often used as a method of forming a conductor layer.
[0004]
In the additive method and the semi-additive method, after laminating a translucent insulating resin on the inner circuit wiring board and then forming a conductor layer on the entire surface by electroless / electrolytic plating, the conductive hole processing step before forming the plating layer However, the alignment mark can be recognized through the insulating resin, but the adhesion between the conductor layer and the insulating layer is low and the reliability is poor. In addition, since the alignment mark formed on the conductive circuit wiring board immediately below the laminated insulating layer is used as a reference for the processing position, when the multi-layering process is repeated for three or more layers, positional accuracy errors are accumulated for each lamination. Problem.
[0005]
On the other hand, in the subtractive method, after laminating an insulating layer and a conductor layer on an inner circuit wiring board, an unnecessary portion of the laminated conductor layer is removed by etching to form a conductor wiring circuit. In addition, since the inner layer circuit cannot be visually recognized from the surface, it is difficult to align the inner layer circuit and the outer circuit. In the conventional method, the alignment marks formed at the same time as the formation of the inner layer circuit are formed by exposing the outer conductor layer and the insulating layer from the surface by using an end mill drill or the like, and the via holes and the outer hole of the outer circuit wiring board are used as a reference. The formation of the outer layer circuit was performed. However, in this method, it is very difficult to perform a drilling process while controlling the depth in micron units while leaving the alignment mark on the inner circuit wiring board. Also in this method, since the alignment mark formed on the conductor circuit wiring board immediately below the laminated insulating layer is used as a reference for the processing position, when the multi-layering process is repeated for three or more layers, the positional accuracy error for each lamination. There was a problem that was accumulated.
[0006]
[Problems to be solved by the invention]
In the conventional build-up multilayer circuit wiring board, the positioning method is based on the alignment mark formed on the immediately preceding conductor wiring pattern, and in order to secure conduction between the inner layer pattern and the outer layer pattern by via holes, the position between each layer is required. In consideration of the deviation, it is necessary to form a large portion, such as a land portion, which is a connection portion between the outer layer pattern and the inner layer pattern, so that the circuit density cannot be increased. Further, when the build-up is repeatedly performed due to the positional deviation, alignment positional errors are accumulated.
[0007]
In addition, an insulating resin having a conductor layer on one side in advance is laminated on the inner layer circuit wiring board via an adhesive, with the conductor layer being on the outside, and a conductor wiring pattern is formed on the outer conductor layer. In order to manufacture a multi-layer circuit wiring board, when copper, which is a metal layer, is used as the outer conductor layer, the alignment mark of the inner circuit wiring board is hidden because it is not transparent, and it is difficult to confirm. there were.
[0008]
[Means for Solving the Problems]
In order to solve the above-mentioned problem in the present invention, in the invention of claim 1, an insulating layer and a conductive layer are laminated in this order on an inner circuit wiring board having an alignment mark and a conductive wiring pattern via an adhesive. In the method of manufacturing a build-up multilayer circuit wiring board, in which a conductor wiring circuit is formed on an outer conductor layer after forming an outer layer, an outer layer is laminated so as not to cover the alignment mark formed on the inner circuit wiring board, A method for manufacturing a build-up multilayer circuit wiring board, characterized by forming a conductor wiring pattern of an outer layer circuit and a via for electrically connecting an outer layer and an inner layer with reference to an alignment mark formed on the circuit wiring board. is there.
[0009]
According to a second aspect of the present invention, in the method for manufacturing a build-up multilayer circuit wiring board according to the first aspect,
(A) a step in which the insulating resin of the inner circuit wiring board is made of a polyimide resin and reference holes serving as two or more alignment marks are simultaneously formed in the inner circuit wiring board by punching using a mold; ,
(B) an insulating resin made of a polyimide resin having a conductor layer on one side in advance through an adhesive, and a conductor on the outside, so as not to cover the alignment marks as the plurality of exposed reference holes of the inner circuit wiring board; A process of laminating layers to form an outer layer,
(C) forming an outer layer wiring pattern and a via for electrically connecting the outer layer and the inner layer with reference to the alignment mark of the inner layer circuit wiring board;
And a method for manufacturing a build-up multilayer wiring circuit wiring board.
[0010]
Further, in the invention according to claim 3, the inner layer circuit wiring board and the insulating resin having the conductor layer on one side are supplied by a tape-shaped long base material. This is a method for manufacturing an up multilayer circuit wiring board.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a method for manufacturing a multilayer circuit wiring board according to the present invention will be described in detail.
[0012]
In the method for manufacturing a multilayer circuit wiring board according to the present invention, first, an alignment mark and an internal circuit wiring are formed on a core substrate composed of an insulating layer and a conductor layer forming the internal circuit wiring board. At this time, after forming the alignment mark, there are a case where the inner layer circuit wiring is formed by positioning with reference to the alignment mark, and a case where the alignment mark and the inner layer circuit wiring are formed simultaneously. Next, an insulating layer and a conductor layer are laminated on the inner layer circuit wiring board in this order via an adhesive. At this time, the insulating layer and the conductor layer are not covered on the alignment mark provided on the inner circuit wiring board, and the alignment mark is exposed. Next, an outer layer circuit wiring is formed by performing via hole forming processing and conductor wiring processing for the outer layer with reference to the exposed alignment marks on the inner circuit wiring board. Further, if necessary, the build-up of the outer layer circuit wiring is repeated in the same process.
[0013]
The shape of the alignment mark used as a reference for the positioning of the conductor wiring pattern formation and the via hole formation processing is not particularly limited, and a shape such as a circular shape, a donut shape, a square shape, a well shape or the like at which a central portion or a specific position portion can be confirmed. Is preferred. Particularly, a circular type and a donut type are preferable.
[0014]
In addition, the number of alignment marks is not particularly limited. By forming the alignment marks with two or more points, not only the deviation of the position coordinates on a plane but also the amount of expansion and contraction of the substrate during the process can be confirmed. It is also possible to perform correction. The number of alignment marks is particularly preferably four.
[0015]
The method for forming the alignment mark is not particularly limited, and a photolithography method, a drilling method, or the like can be used.
[0016]
In the photolithography method, formation of an alignment mark by a photoresist and formation of an alignment mark by an additive method, a semi-additive method, or a subtractive method are considered. In this method, the shape of the alignment mark can be arbitrarily designed. Further, depending on the process, it is also possible to form the inner layer circuit wiring and the alignment mark at the same time, and there is an advantage that the positional accuracy is good and the number of processes can be further reduced.
[0017]
In the drilling method, drilling, laser processing, punching with a die, or the like is conceivable. In this method, since the processed hole is used as an alignment mark, the shape is limited to a substantially circular shape. At this time, if a through hole is formed as an alignment mark, the same alignment mark can be confirmed from both sides of the inner layer circuit wiring board. Therefore, when forming a build-up multilayer circuit wiring board on both sides, alignment of both sides is required. It will be easier. In particular, judging from the accuracy of forming the alignment mark, punching with a die is optimal. At this time, it is desirable that a plurality of alignment marks necessary for one exposure and positioning of the via hole be simultaneously processed by punching using the same die. Therefore, the through holes formed in the inner layer circuit wiring board are formed as alignment marks. In addition, the shape and positional accuracy between alignment marks formed by simultaneous processing can be confirmed in advance by the accuracy of a mold, and it is possible to form with high repetitive processing accuracy.
[0018]
The position of the alignment mark is formed outside the conductor wiring forming surface of the core base material, for example, at both ends in the width direction of the core base material, and the width of the outer layer base material to be laminated is smaller than the interval between the alignment marks of the core base material. Then, the outer layer base material to be stacked is stacked at a position inside the alignment marks provided at both ends of the core base material, and the core material is exposed at the alignment mark portion. The same applies to the case where the multilayering process is repeated for three or more layers.
[0019]
In addition, an opening larger than the alignment mark of the core base material is provided in advance in the outer layer base material to be laminated, and the opening is laminated so as to match the position of the alignment mark of the core base material. It is also possible to use a method that allows confirmation in the opening of the outer layer base material on which is laminated. The same applies to the case where the multilayering process is repeated for three or more layers. With this method, the size of the outer layer substrate to be laminated with the core substrate can be made uniform, but some alignment is required during lamination so that the alignment mark of the core substrate enters the opening of the outer layer substrate during lamination. It becomes. At this time, the position of the alignment mark is not particularly limited, but is preferably outside the conductive wiring forming surface of the core base material.
[0020]
The method of manufacturing a multilayer circuit wiring board according to the present invention is not limited to a single-wafer substrate, but is also applicable to a roll-to-roll continuous production method using a tape-shaped flexible substrate.
[0021]
In forming the laminated upper layer circuit wiring, exposure and via hole processing are positioned based on the alignment marks on the core substrate.
[0022]
The range of the alignment mark can be changed according to the accuracy of the circuit wiring board to be manufactured. In the case of high-definition circuit wiring, it can be dealt with by narrowing the processing pitch of the alignment mark.
[0023]
Use the same alignment marks formed on the inner layer circuit board in forming the conductor wiring pattern of the outer layer circuit and the vias that electrically connect the outer layer and the inner layer, which are sequentially stacked on the front and back of the inner layer circuit board. It is possible to do. Therefore, accumulation of position errors does not occur as compared with the method of performing positioning based on the alignment mark formed on the immediately preceding conductor wiring pattern.
[0024]
Next, the laminating step will be described.
To form a laminated film by laminating a film having a conductor layer on one side with the conductor layer outside on a film having a wiring pattern on at least one side, it is not particularly limited, but a normal press or a laminator It is more preferable to use a vacuum press or a vacuum laminator in order to prevent the generation of bubbles and voids. In addition, it is desirable to produce in a roll-to-roll process because of excellent productivity.
[0025]
The roll-to-roll process refers to a process in which a film is provided with a film unwinding unit and a winding unit, and a processing unit is provided between the unwinding and winding units.
[0026]
Lamination is performed through an adhesive layer made of an adhesive, and if the thermoplastic film is a thermoplastic film such as a thermoplastic polyimide or a liquid crystal polymer, the film itself has an adhesive property, so that a new adhesive should be provided. However, when using a thermoplastic film with excellent heat resistance, the processing temperature generally becomes very high. It is desirable to do it through. Of course, even in the case of a thermoplastic film, it may be laminated via an adhesive layer in order to further improve the adhesive strength.
[0027]
When not laminated via an adhesive, the present invention is not limited to this.For example, if a thermoplastic film is used, the film itself has adhesiveness, so that at least one surface has a wiring pattern on a film, and one surface has a conductor. The laminated film can be formed by laminating a film having a layer with the conductor layer facing outward.
[0028]
When laminating via an adhesive, the form of the adhesive used in the present invention may be a varnish type, a film type, etc., and is not particularly limited, but the film type is excellent in productivity. It is desirable that
[0029]
The method of lamination in the case of using a varnish adhesive is not limited to this, for example, a conductor on one side after forming an adhesive layer by applying an adhesive on a film having wiring on at least one side A method of laminating a film having a layer, a method of laminating the adhesive layer side of a film with an adhesive in which an adhesive has been applied to the film side of a film having a conductor layer on one side in advance, on a film having a wiring pattern on at least one side Can be illustrated.
[0030]
The laminating method when using a film adhesive is not limited thereto, for example, a film having wiring on at least one side, an adhesive film, a method of simultaneously laminating a film having a conductor layer on one side, After laminating the adhesive film to the film having wiring on at least one side, a method of laminating a film having a conductor layer on one side, previously laminating the adhesive film on the film side of the film having the conductor layer on one side, at least A method of laminating on a film having wiring on one side can be exemplified.
[0031]
In addition, when laminating on a film having wiring on both sides, there is a case where lamination is performed on one side at a time and a case where both sides are laminated at the same time. It is desirable to do.
[0032]
Next, a mechanical drill, a carbon dioxide laser beam, an ultraviolet laser beam, an excimer laser beam, or the like can be used to process the via hole. While mechanical drills can form only through holes, drilling using laser light can form both through holes (through holes) and non-through holes (blind vias).
[0033]
The types of the laser light include a carbon dioxide laser (wavelength 9.3 to 10.6 μm), a YAG laser (wavelength of a fundamental wave 1.06 μm), a YAG, YLF, YAP, and YVO4 laser (third harmonic) in an ultraviolet region. 355 nm, the fourth harmonic wavelength 266 nm) and excimer laser (XeCl wavelength 308 nm, KrF wavelength 248 nm, ArF wavelength 193 nm) are currently used as laser beams for processing machines. The carbon dioxide gas laser has the highest energy density per pulse, and the processing speed for forming holes is high, but the formation of a small diameter is limited, and it is said that the diameter is about 50 μm. Further, since the wavelength band is different from the absorption wavelength of the metal, it is necessary to perform a special process such as a blackening process to enhance light energy absorption in order to directly process the conductor layer. The excimer laser is a gas laser, and can process even a small diameter such as φ20 μm, but is not suitable for mass production because expendable supplies such as a highly reflective metal oxide film mask and maintenance of laser medium gas are expensive.
[0034]
Ultraviolet laser light obtained by exciting a solid crystal, such as YAG, YLF, YAP, or YVO4, and converting the wavelength of the extracted laser light overlaps with the absorption wavelength of a metal, and can be directly processed into a conductor layer. Further, since the focal point of the processing point can be narrowed down to a minute diameter as compared with the carbon dioxide laser, a hole having a minute diameter of φ30 μm or less can be formed. Although the speed of hole formation is regarded as a problem, it is being solved by increasing the oscillation frequency of the laser beam and increasing the number of processing heads.
[0035]
In either system, the position of the alignment mark provided on the substrate placed on the processing work table is visually recognized with a CCD camera or the like, the position is corrected based on the position, and the hole is processed to the desired position. Is used.
[0036]
Next, as a wiring processing means, a subtractive method using an etching process and a semi-additive method using electrolytic plating are considered.
[0037]
Comparing the subtractive method and the semi-additive method, the subtractive method is characterized by a small number of steps and is easy, and the semi-additive method has a finer wiring pattern than the subtractive method, which is largely affected by side etching. Is advantageous for the formation of
[0038]
According to the above features, when manufacturing a multilayer circuit wiring board, a multilayer circuit wiring board having finer line, and, and space wiring patterns can be easily obtained by changing the wiring pattern forming means for each layer. . That is, it is desirable that a layer having a fine wiring pattern be processed by a semi-additive method and the other layers be processed by a subtractive method.
[0039]
The degree to which the processing means is switched depends on the required film thickness of the wiring circuit, but when the wiring pitch is 15 to 30 μm or less, processing by the subtractive method is very difficult. Therefore, it is desirable to adopt the semi-additive method.
[0040]
In the case of the subtractive method, it is desirable to form a desired wiring pattern by a photolithographic method using a photosensitive resin as an etching resist.
[0041]
Further, in the case of the semi-additive method, it is desirable to form a desired wiring pattern by a photolithographic method using a photosensitive resin as a plating resist.
[0042]
At this time, an exposure apparatus having a mechanism capable of visually adjusting the position of the alignment mark provided on the substrate with a CCD camera or the like and finely adjusting the relative position between the photomask having a light-shielding portion of a desired pattern and the substrate to a predetermined position. use.
[0043]
By performing the above steps, a four-layered multilayer circuit wiring board can be manufactured. However, by repeating this process once more, a six-layered multilayer circuit wiring board can be manufactured.
[0044]
【Example】
Hereinafter, an embodiment of a method for manufacturing a multilayer circuit wiring board according to the present invention will be described. The method for manufacturing a multilayer circuit wiring board according to the present invention is not limited to the following embodiments.
[0045]
A polyimide substrate 2 with double-sided copper foil (copper / polyimide / copper → 12/25/12 μm configuration) was used as the inner layer circuit wiring board (core substrate). First, as shown in FIG. 1, a through-hole 1 having a diameter of 100 μmφ is formed in a tape-shaped polyimide substrate 2 with a double-sided copper foil having a width W = 105 mm by punching using a mold. The through-hole 1 is a set of two points formed at both ends of the tape-shaped polyimide substrate 2 with a double-sided copper foil at intervals of a width w1 = 95 mm. They are formed at regular intervals at a pitch of 90 mm.
[0046]
Next, after performing the degreasing treatment on the polyimide substrate 2 with the double-sided copper foil, as shown in FIG. 3A, the laser processing device equipped with the CCD camera 7 cuts the through hole 1 at the end of the substrate 2. As an alignment mark, a laser beam is applied to the position where the position is recognized after being recognized by the CCD camera, and the hole is penetrated from the upper surface of the substrate through the copper foil layer 2b and the polyimide layer 2a. This was performed up to the boundary surface of the copper foil layer 2b on the side to form a via hole 6a. For the hole processing, an ultraviolet laser beam having a wavelength of 355 nm was used, and copper and polyimide were irradiated with 5 pulses and 5 pulses of a laser beam having an energy density of 10 J / m ² and ² J / m ² , respectively. The opening diameter was φ30 μm, the bottom diameter was φ18 μm, and the aspect ratio was 0.6. After laser processing, dross removal was performed by chemical polishing using a 30% sodium peroxodisulfate aqueous solution at 30 ° C. In addition, a 10% aqueous solution of potassium permanganate was used at 70 ° C. for desmear treatment.
[0047]
After DPS with a tin-palladium colloid, electrolytic plating was performed containing 225 g / L of copper sulfate, 55 g / L of sulfuric acid, 60 mg / L of chloride ions, and 20 mL of an additive while maintaining the bath temperature at 25 ° C. The bath was stirred using a spray nozzle for every 5 L. A current density of 1 A / dm ² was applied, and electrolytic plating was performed for 20 minutes until the aspect ratio of the via hole became 0.3. Next, a current density of 2.5 A / dm ² was applied for 10 minutes until the aspect ratio became 0, and a via hole (filled via) 6b was formed as shown in FIG. 3B.
[0048]
Next, the copper plating extra deposited on the conductor in the plating step is spray-sprayed for about 60 seconds using a 20% aqueous solution of ammonium peroxodisulfate at 30 ° C. to perform a soft etching treatment until the film thickness of the copper foil layer 2b becomes about 9 μm. Polished.
[0049]
Next, a positive type liquid resist was applied on the surface of the copper foil layer 2b by a roll coater, and post-baked at about 90 ° C. for about 5 minutes in a hot air and IR drying furnace to form a resist layer 5 having a thickness of 4 μm. .
[0050]
Next, as shown in FIG. 3C, the position of the through-hole 1 at the end of the polyimide substrate 2 with copper foil on both sides is recognized as an alignment mark by the CCD camera 7 by the alignment exposure device, The resist layer 5 was exposed after the correction position was aligned with the mark 8a. The exposure process was performed separately on the resist layers 5 on both surfaces of the polyimide substrate 2 with double-sided copper foil using photomasks 8 corresponding to each.
[0051]
Thereafter, as shown in FIG. 3 (d), the exposed portions of the resist layer 5 were removed by spray-development with an organic alkali-based developer for about 90 seconds on both sides at a time to form an etching resist.
[0052]
Next, as shown in FIG. 3E, a ferric chloride solution having a specific gravity of 1.36 and a liquid temperature of 50 ° C. is sprayed on the copper foil layers 2b on both surfaces of the polyimide substrate 2 with double-sided copper foil for about 30 seconds. It was sprayed and processed by etching.
[0053]
Next, as shown in FIG. 3 (f), a 4% aqueous solution of sodium hydroxide is spray-sprayed on the polyimide substrate 2 with double-sided copper foil for about 15 seconds to peel off the resist layer 5 and remove the resist layer 5 to a predetermined thickness of 9 μm. The inner circuit wiring board having the above circuit pattern was obtained.
[0054]
Next, in order to improve the adhesion between the conductor layer and the adhesive layer of the inner circuit wiring board, a hydrogen peroxide solution / sulfuric acid solution is spray-sprayed on both surfaces of the inner circuit board, thereby shaving the surface of the conductor layer by about 1 μm. Was done.
[0055]
Next, as shown in FIG. 3 (g), a polyimide substrate 3 with a single-sided copper foil (copper / polyimide → 12/13 μm configuration) was laminated on both sides of the internal circuit wiring substrate with an adhesive film 4 interposed therebetween. For this purpose, first, a rubber / epoxy adhesive film laminated on a release film of polyethylene terephthalate is used on one side of the interior circuit wiring board, and the adhesive (film) layer faces the inside of the wiring board at 180 ° C. Temporary pressure bonding with a laminator was performed at 3 kg / cm. Further, after the release film was peeled off, the polyimide tape substrate 3 with single-sided copper foil was arranged on the adhesive layer in such a manner that the copper foil face was directed to the outside of the wiring board, and was thermocompressed at 180 ° C. and 3 kg / cm using a laminator. After this laminating step was similarly performed on the opposite surface of the interior circuit wiring board, the obtained laminated board was cured by heating at 150 ° C. for 1 hour. The thickness of the adhesive film is 5 μm. At this time, as shown in FIG. 2, the polyimide substrate 3 with copper foil on one side and the adhesive film as the outer layer base material to be laminated have a width w2 = 90 mm, and the width of the internal circuit wiring board (polyimide substrate 2 with copper foil on both sides). They were bonded with a positional accuracy of ± 2 mm from the center in the direction so as not to cover the through holes 1 which are alignment marks formed at the ends of the inner layer circuit wiring plate.
[0056]
Thereafter, as shown in FIGS. 3H to 3M, a four-layer wiring circuit board was manufactured. As in the case of forming the internal circuit wiring board, first, a hole is formed in the polyimide substrate 3 with a single-sided copper foil laminated on both sides using the through hole 1 formed at the end of the internal circuit wiring board as an alignment mark (h), and a via hole is formed. Formed (i). Thereafter, the steps of resist exposure (j), etching resist formation (k), etching treatment (l), and resist stripping (m) were performed in the same manner as described above, and circuit formation was performed in the upper and lower parts, respectively, to produce a four-layer wiring circuit board. . Further, similarly, by repeating the steps from lamination of the single-sided copper foil polyimide substrate to circuit formation, a six-layer wiring circuit board can be prepared. In addition, the above-mentioned processes all used the roll-to-roll process.
[0057]
【The invention's effect】
In the method for manufacturing a multilayer circuit wiring board according to the present invention, in order to use a through hole formed at an end of the internal circuit wiring board as an alignment mark, an outer layer circuit formed by successively stacking on the front and back of the inner circuit wiring board is used. It is possible to use the same alignment marks formed on the inner circuit wiring board in forming the conductor wiring patterns and vias that electrically connect the outer and inner layers. Therefore, compared to the method of performing positioning based on the alignment mark formed on the immediately preceding conductor wiring pattern, it is not necessary to increase the size of a land portion or the like, thereby increasing the circuit density, and accumulating position errors. In addition, the alignment between the interior circuit wiring and the outer layer circuit wiring is good, the interlayer is hardly disconnected, and it is possible to manufacture a multilayer wiring circuit board corresponding to a fine wiring circuit pattern.
[Brief description of the drawings]
FIG. 1 is an explanatory view showing a substrate in a plane in an embodiment of a method for manufacturing a multilayer circuit wiring board of the present invention.
FIG. 2 is an explanatory diagram showing a plan view of a substrate on which a polyimide substrate with a single-sided copper foil is laminated in the embodiment of the method for manufacturing a multilayer circuit wiring board of the present invention.
FIG. 3 is an explanatory view showing a cross section of an embodiment of the method for manufacturing a multilayer circuit wiring board of the present invention.
[Explanation of symbols]
1: Through hole 2: Polyimide substrate with double-sided copper foil (core substrate)
3: Outer layer base material, polyimide substrate 2a with copper foil on one side 2a, 3a: Polyimide layer 2b, 3b: Copper foil layer 4: Adhesive film 5: Resist layer 6a: Via hole 6b: Filled via 7: CCD camera 8: Photo Mask 8a: fiducial mark of photomask

Claims (3)

An insulating layer and a conductor layer are laminated in that order on an inner circuit wiring board having an alignment mark and a conductor wiring pattern via an adhesive to form an outer layer, and then a conductor wiring circuit is formed on the outer conductor layer. In a method for manufacturing a build-up multilayer circuit wiring board, an outer layer is laminated so as not to cover an alignment mark formed on an inner circuit wiring board, and a conductor wiring pattern of an outer circuit is formed based on the alignment mark formed on the inner circuit wiring board. And forming a via for electrically connecting an outer layer and an inner layer. The method for manufacturing a build-up multilayer circuit wiring board according to claim 1,
(A) a step in which the insulating resin of the inner circuit wiring board is made of a polyimide resin and reference holes serving as two or more alignment marks are simultaneously formed in the inner circuit wiring board by punching using a mold; ,
(B) an insulating resin made of a polyimide resin having a conductor layer on one side in advance through an adhesive, and a conductor on the outside, so as not to cover the alignment marks as the plurality of exposed reference holes of the inner circuit wiring board; A process of laminating layers to form an outer layer,
(C) forming an outer layer wiring pattern and a via for electrically connecting the outer layer and the inner layer with reference to the alignment mark of the inner layer circuit wiring board;
A method for manufacturing a build-up multilayer wiring circuit wiring board, comprising: 3. The method for manufacturing a build-up multilayer circuit wiring board according to claim 1, wherein the inner circuit wiring board and the insulating resin having a conductor layer on one surface are supplied by a tape-shaped long base material.

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