JP4792673B2 - Manufacturing method of high-density multilayer build-up wiring board - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a high-density multilayer build-up wiring board in which wiring layers formed on both surfaces of a core substrate on which through holes are formed via insulating layers are electrically connected by filled vias.
[0002]
[Prior art]
In recent years, as represented by personal computers and the like, downsizing and thinning of electronic devices are required, and in printed wiring boards used there, as well as increasing the density of wiring, downsizing, thinning and High reliability is required. For this reason, there is an increasing need for a substrate for a semiconductor device having a filled via structure in which wiring layers are electrically connected by filled vias. These semiconductor device substrates have semiconductor chips and other components mounted thereon, and are mounted on the semiconductor device substrate as a parent substrate in the form of BGA (ball grid array) or PGA (pin grid array). In many cases, it is used as a parent substrate.
[0003]
In order to achieve miniaturization and thinning, the wiring layer width is narrow, the interval is small, the wiring layers are multilayered, and the via holes connecting the wiring layers are required to have a high density wiring. However, there is a demand for a highly reliable semiconductor device that does not cause connection failure or insulation failure.
[0004]
A multilayer build-up wiring board using a build-up method is known as a substrate for a semiconductor device that meets these requirements. In this method, a multilayer build-up wiring board is produced by repeating the process of forming an insulating layer and a wiring layer on a core substrate.
[0005]
An example of a method of forming a multilayer build-up wiring board having a filled via structure will be described.
4A to 4E are partial schematic cross-sectional views of a manufacturing process in which a filled via and a wiring layer are formed on a core substrate to produce a multilayer build-up wiring board.
First, the first alignment layer 52a and the exposure alignment mark 52d having a circular pattern are formed in the alignment mark area around the core substrate 51 on the core substrate 51 that is imposed, and the insulating layer 53 having a predetermined thickness is formed (FIG. 4 (a)).
[0006]
Next, laser processing is performed by aligning the laser beam with the alignment mark 52d for exposure formed in the alignment mark area of the core substrate 51, and laser processing is performed, and a via is formed in the insulating layer 53 on the land portion 52c of the first wiring layer 52. An alignment mark round hole 55 is formed on the hole 54 and the conductor layer 52e in the alignment region around the substrate (see FIG. 4B).
[0007]
Next, a desmear process is performed, a thin film conductor layer is formed by electroless copper plating on the via hole 54, the alignment mark round hole 55, and the insulating layer 53, and electrolytic copper panel plating is performed using the thin film conductor layer as a cathode. The filled via 61, the second conductor layer 62, and the alignment mark 63 for exposure are formed (see FIG. 4C).
[0008]
Next, a photoresist layer is formed on the second conductor layer 62, the exposure pattern is aligned using the exposure alignment mark 63 formed in the alignment region around the substrate, and a series of pattern exposure, development, and the like are performed. Patterning processing is performed to form a resist pattern 56 (see FIG. 4D).
[0009]
Next, the second conductor layer 62 is etched using the resist pattern 56 as an etching mask, and the resist pattern 56 is removed with a special stripping solution to form a second wiring layer 62a. The land 52c and the second wiring layer A multilayer build-up wiring board having a filled via structure in which 62a is electrically connected by a filled via 61 is manufactured (see FIG. 4E).
Furthermore, the above-described insulating layer, filled via, wiring layer, and exposure alignment mark forming step can be repeated as many times as necessary to obtain a multilayer build-up wiring board having a predetermined number of filled via structures.
[0010]
[Problems to be solved by the invention]
In the manufacturing process of the multi-layered build-up wiring board having the above filled via structure, the alignment mark for exposure used in the next process is simultaneously formed when the filled via and the conductor layer are formed in the insulating layer. Since a processing process is not required, it is a process generally used. When the filled via and the exposure alignment mark are simultaneously formed on this insulating layer, a problem occurs in the surface shape of the exposure alignment mark.
[0011]
As described above, the mark shape of the alignment mark for exposure is generally a circular pattern with a large aperture.
When electrolytic copper panel plating for filled vias is performed in alignment mark round holes formed in the insulating layer, via holes 54 and alignment mark round holes 55 are filled with a copper conductor layer, as shown in FIG. An exposure alignment mark 63 is formed.
As shown in FIG. 4C, the surface shape of the alignment mark 63 for exposure has a smooth edge around the circular hole 55 for the alignment mark, and the recognition rate of the alignment mark for exposure decreases in the alignment process. , Which causes alignment failure.
[0012]
This misalignment causes a misalignment between the filled via and the land when forming a via-via-filled multilayer via board, and with the recent increase in the density of the multilayer wiring board, the diameter of the filled via has become smaller. An electrical connection failure occurs, and as a result, there is a problem that the reliability of a multilayer wiring board having a filled via structure is lowered.
[0013]
The present invention has been devised in view of the above problems, and is a high-density multilayer build-up wiring excellent in reliability that does not cause a connection failure in a multilayer printed wiring board having a filled via structure in which wiring layers are connected by filled vias. It aims at providing the manufacturing method of a board.
[0014]
[Means for Solving the Problems]
In order to solve the above-described problems in the present invention, first, in claim 1, a plurality of wiring layers are formed on both surfaces of a core substrate on which through holes are formed via insulating layers, and the wiring layers Is a method for producing a high-density multilayer build-up wiring board, characterized by comprising at least the following steps in a multilayer printed wiring board electrically connected by filled vias.
(A) A step of forming insulating layers on both surfaces of the core substrate on which through holes and wiring layers are formed.
(B) A step of forming via holes and ring-shaped alignment mark holes in the insulating layer by laser processing.
(C) A process of forming a thin film conductor layer by conducting the via holes, the alignment mark holes, and the insulating layer.
(D) A step of performing electrolytic copper panel plating using the thin film conductor layer as a cathode to form a filled via, an alignment mark for exposure, and a conductor layer.
(E) forming a resist pattern by forming a photosensitive layer on the conductor layer, performing pattern alignment using the alignment mark for exposure, and performing a series of patterning processes such as pattern exposure and development.
(F) Using the resist pattern as a mask, etching the conductor layer and the thin film conductor layer, and peeling the resist pattern to form a wiring layer.
(G) A step of producing a high-density multilayer build-up wiring board having a predetermined number of layers by repeating the steps of forming the insulating layer, filled via, and wiring layer as many times as necessary.
[0015]
In the claim 2, wherein an exposure for the alignment mark gully ring shape formed on the insulating layer, when the outer shape of the-ring and R _D, the ring width and _{R w, R D ≧ 200μmφ,} R _{2. The} method for producing a high-density multilayer build-up wiring board according to claim 1, wherein a condition of _w ≧ 50 μm is satisfied.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described.
As shown in FIGS. 2A to 2F and FIGS. 3B to 3F, the manufacturing method of the high-density multilayer build-up wiring board of the present invention includes the first wiring layer 12a and the first wiring layer 12b. The shape of the alignment mark formed on the insulating layer when the insulating layer 14 is formed on the core substrate 11 in which the through holes 13 are formed and the alignment mark for exposure is formed on the alignment region around the substrate by electrolytic copper plating is shown in FIG. a pattern of-ring shape as shown in (c), when the outer shape of the-ring and _{R D,} the ring width and _{R W,} as _{R D} ≧ _200μmφ, conditions of _{R w} ≧ 50 [mu] m is satisfied, further The alignment mark for pattern exposure of the imposition substrate by projection exposure so that the peripheral edge Re of the exposure alignment mark (see FIG. 3D) obtained by electrolytic copper plating is emphasized. Recognition The recognition rate is improved, and the alignment accuracy of the wiring pattern and the like is improved.
An example of a high-density multilayer build-up wiring board obtained by using the method for manufacturing a high-density multilayer build-up wiring board of the present invention is shown in FIGS.
[0017]
The manufacturing method of the high-density multilayer buildup wiring board of this invention is demonstrated.
2A to 2F are schematic partial configuration sectional views showing an embodiment of a method for manufacturing a high-density multilayer build-up wiring board according to the present invention.
FIGS. 3B to 3F are schematic partial enlarged configuration sectional views of the A region in FIGS. 2B to 2F and schematic partial enlarged configuration sectional views of the alignment mark for exposure in the alignment mark region.
First, the core substrate 11 in which the first wiring layer 12a, the first wiring layer 12b, and the through hole 13 are formed is manufactured (see FIG. 2A).
As the core substrate 11, a printed wiring board produced by laminating an inner layer board on a double-sided wiring board, a printed wiring board produced by a building-up method on an insulating substrate, and the like are used.
[0018]
Next, a resin solution is formed on both surfaces of the core substrate 11 on which the first wiring layer 12a, the first wiring layer 12b, and the through hole 13 are formed by screen printing or the like, or a resin film is laminated and insulated. The layer 14 is formed (see FIGS. 2B and 3B).
[0019]
Next, alignment of the laser beam of the laser processing machine is performed using the exposure alignment mark 12d formed in the alignment mark region of the core substrate 11, and the land portions of the first wiring layer 12a and the first wiring layer 12b are aligned. the via hole 15 in the insulating layer 14 on 12c, forming an alignment mark for re Nguana 16 in the insulating layer 14 on the conductor layer 12e of the alignment mark region (FIGS. 2 (c) and 3 (c) refer) .
Here, the alignment mark Li Nguana 16, when the outer shape of the-ring and _{R D,} the ring width and _{R W, R D} ≧ _200μmφ, have become satisfy the condition of _{R w} ≧ _50μm. For example, with respect to the hole diameter 50μm vias, external _{R D} of the-ring is 200 to 500 [mu] m, preferably preferred is 400 [mu] m, ring width _{R W} has 50～70Myuemu.
[0020]
Then, the via hole 15, perform desmearing of Li Nguana 16 and the insulating layer 14 surface for the alignment mark, on the insulating layer 14, the electroless copper plating in the via hole 15 and the alignment mark Li Nguana 16 Then, electrolytic copper panel plating is performed using the thin film conductor layer as a cathode to form filled via 21, second conductor layer 22, and alignment mark 23 for exposure in the alignment mark region (FIG. 2 ( d) and FIG. 3 (d)).
[0021]
Next, a photoresist layer for forming a wiring layer or the like by a subtractive method is formed on the filled via 21 and the second conductor layer 22, and the exposure apparatus uses the exposure alignment mark 23 formed in the alignment region. The resist mask 17 is formed by aligning the exposure mask and performing a series of patterning processes such as exposure and development (see FIGS. 2E and 3E).
[0022]
Next, using the resist pattern 17 as an etching mask, the second conductor layer 22 and the thin film conductor layer are etched, the resist pattern 17 is removed with a special stripping solution, and the second wiring layer 22a, the second wiring layer 22b, The land portion 22c is formed, and the high-density multilayer build-up wiring board 100 in which the land portion 12c, the second wiring layer 18a, the second wiring layer 18b, and the land portion 22c are electrically connected by the filled via 21 can be obtained. (See FIG. 2 (f) and FIG. 3 (f)).
Furthermore, a high-density multilayer build-up wiring board having a desired number of layers can be obtained by repeating the steps of forming insulating layers, filled vias, and wiring layers as many times as necessary.
[0023]
【Example】
Hereinafter, the present invention will be described in detail by way of examples.
<Example 1>
First, the core substrate 11 having the first wiring layer 12a, the first wiring layer 12b, the land portion 12c, and the through holes 13 having a conductor layer thickness of 15 μm formed on both surfaces was manufactured (see FIG. 2A).
[0024]
Next, an epoxy resin was screen printed on both surfaces of the core substrate 11 on which the first wiring layer 12a and the first wiring layer 12b were formed, and dried to form an insulating layer 14 having a thickness of 45 μm (FIG. 2B). And FIG. 3 (b)).
[0025]
Next, alignment of the laser beam of the laser processing machine is performed using the alignment mark 12d formed in the alignment mark region of the core substrate 11, and the frequency of 5 KHz is applied to the insulating layer 14 on the land portion 12c of the first wiring layer. The via hole 15 having an upper diameter of 50 μm by irradiating with 30 pulses of ultraviolet laser is subjected to a trepanning process on the insulating layer 14 on the conductor layer 12e in the alignment mark region with a frequency of 5 kHz and 4 pulses of ultraviolet laser to obtain a ring width. R _W is a contour _{R D} is 200, 300, 400 and 500μmφ alignment marks for re Nguana 16-ring with 50 [mu] m, you were formed (see FIG. 2 (c) and Figure 3 (c)).
[0026]
Next, potassium permanganate (58 g / L) via hole 15 with a solution, subjected to desmear treatment of Li Nguana 16 and the insulating layer 14 surface for the alignment mark, on the insulating layer 14, holes 15 and alignment via a thin film conductor layer is formed by electroless copper plating or the like to mark re Nguana 16, further a thin film conductor layer and the cathode performs electrolytic copper panel plating, the filled via 21,15μm second conductive layer 22 and the alignment of the thickness external _{R D} of-ring to mark region formed the exposed alignment mark 23 of the 200, 300, 400 and 500Myuemufai (see FIG. 2 (d) and FIG. 3 (d)).
[0027]
Next, a photoresist layer is formed on the filled via 21 and the second conductor layer 22, and the exposure mask is aligned by an exposure apparatus using the exposure alignment mark 23 formed in the alignment mark region, and exposure and development are performed. The resist pattern 17 was formed by performing a series of patterning processes such as (see FIGS. 2E and 3E).
Viewing Here, any result of ring width _{R W} is external _{R D} in-ring at 50μm has performed a confirmation of alignment visibility of the exposure apparatus for each exposure for the alignment mark 23 of the 200, 300, 400 and 500μmφ The property was good.
[0028]
Next, using the resist pattern 17 as an etching mask, the second conductor layer 22 and the thin film conductor layer are etched, the resist pattern 17 is removed with a special stripping solution, and the second wiring layer 22a, the second wiring layer 22b, A land portion 22c of 140 μmφ is formed, and the high-density multilayer build-up wiring board 100 in which the land portion 12c, the second wiring layer 18a, the second wiring layer 18b, and the land portion 22c are electrically connected by the filled via 21 is obtained. (See FIG. 2 (f) and FIG. 3 (f)).
As a result of confirming the alignment accuracy between the filled via 21 and the land portion 22c of the obtained high-density multilayer build-up wiring board 100, the positional deviations were all within 15 μm.
[0029]
<Example 2>
The insulating layer 14 is formed on both surfaces of the core substrate 11 in which the first wiring layer 12a, the first wiring layer 12b, the land portion 12c, and the through hole 13 having a conductor layer thickness of 15 μm are formed on both surfaces in the same process as in the first embodiment. (See FIGS. 2 (a), 2 (b) and 3 (b)).
[0030]
Next, alignment of the laser beam of the laser processing machine is performed using the alignment mark 12d formed in the alignment mark region of the core substrate 11, and the frequency of 5 KHz is applied to the insulating layer 14 on the land portion 12c of the first wiring layer. The via hole 15 having an upper diameter of 50 μm by irradiating with 30 pulses of ultraviolet laser is subjected to a trepanning process on the insulating layer 14 on the conductor layer 12e in the alignment mark region with a frequency of 5 kHz and 4 pulses of ultraviolet laser to obtain a ring width. R _W is a contour _{R D} is 200, 300, 400 and 500μmφ alignment marks for re Nguana 16-ring with 70 [mu] m, it was formed (see FIG. 2 (c) and Figure 3 (c)).
[0031]
In the same steps as in Example 1, desmear treatment, by performing electroless copper plating and electrolytic copper plating, the second conductor layer 22 and the alignment mark region of the filled via 21,15μm thickness profile _{R D} of-ring is 200,300 , 400 and 500 μmφ exposure alignment marks 23 were formed (see FIGS. 2D and 3D).
[0032]
Next, a photoresist layer is formed on the filled via 21 and the second conductor layer 22, and the exposure mask is aligned by an exposure apparatus using the exposure alignment mark 23 formed in the alignment mark region, and exposure and development are performed. The resist pattern 17 was formed by performing a series of patterning processes such as (see FIGS. 2E and 3E).
Viewing Here, any result of ring width _{R W} is external _{R D} in-ring at 70μm has performed a confirmation of alignment visibility of the exposure apparatus for each exposure for the alignment mark 23 of the 200, 300, 400 and 500μmφ The property was good.
[0033]
Next, using the resist pattern 17 as an etching mask, the second conductor layer 22 and the thin film conductor layer are etched, the resist pattern 17 is removed with a special stripping solution, and the second wiring layer 22a, the second wiring layer 22b, A land portion 22c of 140 μmφ is formed, and a high-density multilayer build-up wiring board 100 ′ in which the land portion 12c, the second wiring layer 18a, the second wiring layer 18b, and the land portion 22c are electrically connected by the filled via 21 is formed. It obtained (refer FIG.2 (f) and FIG.3 (f)).
As a result of checking the alignment accuracy between the filled via 21 and the land portion 22c of the obtained high-density multilayer build-up wiring board 100 ′, the positional deviations were all within 15 μm.
[0034]
<Comparative example>
The insulating layer 14 is formed on both surfaces of the core substrate 11 in which the first wiring layer 12a, the first wiring layer 12b, the land portion 12c, and the through hole 13 having a conductor layer thickness of 15 μm are formed on both surfaces in the same process as in the first embodiment. (See FIGS. 2 (a), 2 (b) and 3 (b)).
[0035]
Next, alignment of the laser beam of the laser processing machine is performed using the alignment mark 12d formed in the alignment mark region of the core substrate 11, and the frequency of 5 KHz is applied to the insulating layer 14 on the land portion 12c of the first wiring layer. The via hole 15 having an upper diameter of 50 μm is irradiated by irradiating 30 pulses of ultraviolet laser, and the hole diameter is 70 by irradiating the insulating layer 14 on the conductor layer 12e in the alignment mark region with 30 pulses of ultraviolet laser. , 100, 110, and 120 μmφ alignment mark round holes 55 were respectively formed (see FIG. 2C and FIG. 4B).
[0036]
In the same process as in Example 1, desmear treatment, electroless copper plating and electrolytic copper plating are performed, and the hole diameter is 70, 100, 110 and 120 μmφ in the filled via 21, the 15 μm thick second conductor layer 22 and the alignment mark region. The alignment mark 63 for exposure was formed (see FIG. 2D and FIG. 4C).
[0037]
Next, a photoresist layer is formed on the filled via 21 and the second conductor layer 22, and the exposure mask is aligned by an exposure apparatus using the alignment mark 63 for exposure formed in the alignment mark region, and exposure and development are performed. The resist pattern 17 was formed by performing a series of patterning processes such as (see FIGS. 2E and 3E).
Here, as a result of checking the alignment visibility of the exposure apparatus with respect to the alignment mark 63 for exposure having hole diameters of 70, 100, 110 and 120 μmφ, all of them were poor in visibility and the alignment operation was unstable.
[0038]
Next, using the resist pattern 17 as an etching mask, the second conductor layer 22 and the thin film conductor layer are etched, the resist pattern 17 is removed with a special stripping solution, and the second wiring layer 22a, the second wiring layer 22b, A high-density multilayer build-up wiring board of a comparative example in which a land portion 22c of 140 μmφ is formed and the land portion 12c, the second wiring layer 18a, the second wiring layer 18b, and the land portion 22c are electrically connected by the filled via 21 Got.
As a result of confirming the alignment accuracy between the filled via 21 and the land portion 22c of the high density multilayer buildup wiring board of the comparative example, a positional deviation of 15 μm or more was confirmed.
[0039]
【The invention's effect】
In the production method of a high-density multilayer build-up wiring board of the present invention, by using a-ring-shaped exposure alignment mark formed on the insulating layer, for aligning the exposure mask, a filled via with excellent alignment accuracy You can get a land.
Furthermore, the outer shape R _D ≧ 200μmφ the-rings of exposure for the alignment mark, because it is set in a range of ring width R _w ≧ 50 [mu] m, to obtain a high-density multilayer build-up wiring board having excellent Biaonbia structure alignment accuracy Can do.
Therefore, the present invention exhibits excellent practical effects in the high-density multilayer build-up wiring board field.
[Brief description of the drawings]
FIG. 1A is a schematic partial cross-sectional view showing an example of a high-density multilayer buildup wiring board obtained by the method for producing a high-density multilayer buildup wiring board of the present invention.
FIG. 4B is a schematic partial enlarged configuration sectional view of an A region.
FIGS. 2A to 2F are schematic partial cross-sectional views showing an embodiment of a method for manufacturing a high-density multilayer build-up wiring board according to the present invention.
FIGS. 3B to 3F are a schematic partial enlarged configuration sectional view of an area A in FIGS. 2B to 2F and a schematic partial enlarged configuration sectional view showing alignment marks in an alignment mark area.
4A to 4E are a schematic partial configuration sectional view showing an example of a manufacturing process of a conventional multilayer build-up wiring board and a schematic partial enlarged configuration sectional view showing alignment marks in an alignment mark region.
[Explanation of symbols]
11, 51... Core substrates 12a, 12b, 52... First wiring layers 12c, 22c, 52c... Land portions 12d, 23... Exposure alignment marks 12e, 52e. 53 ...... insulating layer 15,54 ...... via hole 16 ...... Li alignment mark Nguana 17,56A ...... resist pattern 21, 61 ...... filled via 22 and 62 ...... second conductive layer 22a, 22b, 62a ... ... second wiring layers 23, 63 ... exposure alignment mark 100 ... high-density multilayer build-up wiring board

Claims (2)

In a multilayer printed wiring board in which a plurality of wiring layers are formed on both surfaces of a core substrate in which through holes are formed via insulating layers, and the wiring layers are electrically connected by filled vias, the following steps are performed. A method for producing a high-density multilayer build-up wiring board, comprising:
(A) A step of forming insulating layers on both surfaces of the core substrate on which through holes and wiring layers are formed.
(B) A step of forming via holes and ring-shaped alignment mark holes in the insulating layer by laser processing.
(C) A process of forming a thin film conductor layer by conducting the via holes, the alignment mark holes, and the insulating layer.
(D) A step of performing electrolytic copper panel plating using the thin film conductor layer as a cathode to form a filled via, an alignment mark for exposure, and a conductor layer.
(E) forming a resist pattern by forming a photosensitive layer on the conductor layer, performing pattern alignment using the alignment mark for exposure, and performing a series of patterning processes such as pattern exposure and development.
(F) Using the resist pattern as a mask, etching the conductor layer and the thin film conductor layer, and peeling the resist pattern to form a wiring layer.
(G) A step of producing a high-density multilayer build-up wiring board having a predetermined number of layers by repeating the steps of forming the insulating layer, filled via, and wiring layer as many times as necessary. Wherein there is provided an exposure for the alignment mark gully ring shape formed on the insulating layer, when the outer shape of the-ring and _{R D,} the ring width and _{R w, R D} ≧ _200μmφ, conditions of _{R w} ≧ 50 [mu] m is satisfied The manufacturing method of the high-density multilayer buildup wiring board of Claim 1 characterized by the above-mentioned.

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