WO2004064150A1 - Method for manufacturing electronic component mount board and electronic mount board manufactured by this method - Google Patents
Method for manufacturing electronic component mount board and electronic mount board manufactured by this method Download PDFInfo
- Publication number
- WO2004064150A1 WO2004064150A1 PCT/JP2003/000326 JP0300326W WO2004064150A1 WO 2004064150 A1 WO2004064150 A1 WO 2004064150A1 JP 0300326 W JP0300326 W JP 0300326W WO 2004064150 A1 WO2004064150 A1 WO 2004064150A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- build
- electronic component
- support substrate
- hole
- chip
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 title claims description 27
- 239000000758 substrate Substances 0.000 claims abstract description 120
- 238000003475 lamination Methods 0.000 claims abstract description 10
- 238000007747 plating Methods 0.000 claims description 74
- 229910052751 metal Inorganic materials 0.000 claims description 34
- 239000002184 metal Substances 0.000 claims description 34
- 229920005989 resin Polymers 0.000 claims description 34
- 239000011347 resin Substances 0.000 claims description 34
- 239000003990 capacitor Substances 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 17
- 238000010030 laminating Methods 0.000 claims description 12
- 238000007789 sealing Methods 0.000 claims description 6
- 238000005304 joining Methods 0.000 claims description 5
- 230000001681 protective effect Effects 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 46
- 239000010949 copper Substances 0.000 description 46
- 229910052802 copper Inorganic materials 0.000 description 46
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 40
- 239000010408 film Substances 0.000 description 39
- 229910052759 nickel Inorganic materials 0.000 description 20
- 238000005530 etching Methods 0.000 description 14
- 239000003822 epoxy resin Substances 0.000 description 11
- 229920000647 polyepoxide Polymers 0.000 description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 9
- 239000010931 gold Substances 0.000 description 9
- 229910052737 gold Inorganic materials 0.000 description 9
- 239000010935 stainless steel Substances 0.000 description 9
- 229910001220 stainless steel Inorganic materials 0.000 description 9
- 229910000679 solder Inorganic materials 0.000 description 7
- 239000000243 solution Substances 0.000 description 7
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 6
- 229910001374 Invar Inorganic materials 0.000 description 6
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- 239000007864 aqueous solution Substances 0.000 description 6
- 239000000470 constituent Substances 0.000 description 6
- 238000005520 cutting process Methods 0.000 description 6
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 4
- 238000007772 electroless plating Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 239000001569 carbon dioxide Substances 0.000 description 3
- 229910002092 carbon dioxide Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000003351 stiffener Substances 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 239000002699 waste material Substances 0.000 description 3
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 150000001412 amines Chemical class 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 229960003280 cupric chloride Drugs 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- -1 polytetrafluoroethylene Polymers 0.000 description 2
- 238000007788 roughening Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 239000004925 Acrylic resin Substances 0.000 description 1
- 239000004859 Copal Substances 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 241000782205 Guibourtia conjugata Species 0.000 description 1
- 229920000106 Liquid crystal polymer Polymers 0.000 description 1
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 1
- PEEHTFAAVSWFBL-UHFFFAOYSA-N Maleimide Chemical compound O=C1NC(=O)C=C1 PEEHTFAAVSWFBL-UHFFFAOYSA-N 0.000 description 1
- 239000004721 Polyphenylene oxide Substances 0.000 description 1
- 239000004743 Polypropylene Substances 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000010306 acid treatment Methods 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 125000003118 aryl group Chemical group 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- XLJMAIOERFSOGZ-UHFFFAOYSA-M cyanate Chemical compound [O-]C#N XLJMAIOERFSOGZ-UHFFFAOYSA-M 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000012948 isocyanate Substances 0.000 description 1
- 150000002513 isocyanates Chemical class 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 229920001955 polyphenylene ether Polymers 0.000 description 1
- 229920006380 polyphenylene oxide Polymers 0.000 description 1
- 229920001155 polypropylene Polymers 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- KCTAWXVAICEBSD-UHFFFAOYSA-N prop-2-enoyloxy prop-2-eneperoxoate Chemical compound C=CC(=O)OOOC(=O)C=C KCTAWXVAICEBSD-UHFFFAOYSA-N 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000000930 thermomechanical effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
- H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0147—Carriers and holders
- H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0376—Etching temporary metallic carrier substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1536—Temporarily stacked PCBs
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
Definitions
- the present invention relates to a method of manufacturing an electronic component mounting board used in a circuit system of an electric / electronic device, and an electronic component mounting board manufactured by the method.
- a method for forming a multilayer wiring structure in a multilayer wiring board there is a build-up method.
- the formation of an insulating layer and the formation of a wiring pattern on the insulating layer are sequentially repeated on the core substrate, and the wiring is multilayered. Specifically, first, a build-up insulating layer made of an epoxy resin is laminated on a glass epoxy substrate or a BT substrate serving as a core substrate. Next, a via hole is formed in the insulating layer.
- a method of forming a via hole there is a method of forming a hole in the insulating layer by photolithography using a photosensitive resin as a material of the insulating layer, or a method of forming a hole in the insulating layer by irradiating a laser. Adopted. After forming a via hole in the insulating layer, a conductive material is formed on the insulating layer by electroless plating or electric plating. At this time, a via is formed in the via hole by the conductive material. Next, a wiring pattern is formed by etching the conductive material formed on the insulating layer.
- transmission characteristics in a high-frequency band are a problem in a multilayer wiring board having a multilayer wiring structure formed by a build-up method.
- the wiring resistance that is, inductance
- signal noise is more likely to occur.
- the IC chip is built into the core substrate so that the electrodes of the IC chip are exposed on the front side of the core substrate.
- Techniques for forming a multilayer wiring structure on the surface of a core substrate are known (for example, see the following references 1 and 2).
- Another technique for reducing the wiring resistance by shortening the distance between the IC chip and the capacitor is to form a multilayer wiring structure on the surface of a metal support substrate by a build-up method. After mounting the IC chip on the surface of the outermost layer of the structure and subjecting the reinforcing plate to processing, the entire support substrate is removed, thereby forming solder bumps on the back surface of the exposed insulating layer.
- Multi-Layer Thin -Film (MLTF) Packaging Technology is known. (For example, see Reference 3 below.)
- Literature 1 Japanese Unexamined Patent Application Publication No. 2000-3502 174.
- Literature 2 R. Emery, S. Towle, H. Braunisch, C. Hu, G. Raiser, and G. J.
- the technologies disclosed in the above-mentioned references 1 and 2 form a multilayer wiring structure by a build-up method after the IC chip is fixed to a supporting substrate in advance, so that it is difficult to align the IC chip with the multilayer wiring structure. It is.
- the multilayer wiring structure is formed after the IC chip is fixed to the supporting substrate in advance, it is very difficult to reuse the IC chip if a defect occurs in the multilayer wiring structure. In other words, the yield of the multilayer wiring structure is 1
- an object of the present invention is to provide a method of manufacturing an electronic component mounting board which is excellent in alignment, practicality, and work efficiency while reducing the inductance of the electronic component mounting board. It is in.
- Another object of the present invention is to provide a chip component mounting board manufactured by such a method.
- the method for manufacturing an electronic component mounting board includes: a build-up laminating step of alternately forming a build-up insulating layer and a build-up wiring pattern on a surface of a metal support board; A hole forming step of forming a through hole at a position where the electronic component is mounted on the support substrate to expose a build-up insulating layer of the innermost layer; and a build-up of the innermost layer via the through hole of the support substrate. And mounting the electronic component on the up-insulating layer.
- the electronic components can be mounted after the build-up laminate is formed on the surface of the support substrate. Therefore, build-up laminates Positioning when mounting electronic components can be performed relatively easily. Also, since the electronic components can be mounted after the build-up laminate is formed, the electronic components can be mounted after confirming that the build-up laminate has been properly formed. It is practical without waste. Further, since the support substrate removes only the mounting area for electronic components, the remaining portion of the support substrate plays a role similar to that of the stiffener. Therefore, it has sufficient rigidity for mounting and other handling. Therefore, there is no need to provide a separate step for imparting rigidity, and work efficiency is excellent.
- the method further includes a sealing step of sealing a gap generated around the electronic component in the through hole after the mounting step with an insulating resin.
- the method further includes a temporary bonding step of temporarily bonding the back surfaces of the two support substrates before the build-up lamination step, and separating the two support substrates after the build-up lamination step and before the hole forming step.
- the build-up laminating step is performed on the surface of each support substrate.
- the temporary bonding step is performed by sandwiching the two support substrates between two resin sheets having a size protruding from the outer peripheral portion of each support substrate, and vacuum laminating the two resin sheets under heating.
- the two supporting substrates can maintain the joined state without using an adhesive or the like, and for example, only by cutting the resin sheet protruding from the outer peripheral portion, the two supporting substrates are cut. Support substrate Can be easily separated. Also, a part of the resin sheet can be used as the innermost layer of the build-up insulating layer, which is excellent in work efficiency.
- the method further includes a plating step of forming a metal plating film on at least the protruding portions of the resin sheets after the temporary joining step.
- a plating step of forming a metal plating film on at least the protruding portions of the resin sheets after the temporary joining step even when a surface roughening process is performed when forming a build-up wiring pattern on a build-up insulating layer in a build-up laminating step, the resin sheet of the protruding portion is surfaced by the metal plating film. Unaffected by coarse treatment. Therefore, even when a multilayer is formed in the build-up lamination process, the resin sheet at the protruding portion is not damaged, and the temporary bonding state of the two support substrates can be more stably maintained.
- the metal plating film is formed simultaneously with a wiring pattern for the innermost build-up insulating layer. According to such a manufacturing method, the metal plating film can be formed with higher working efficiency.
- the method further includes a film forming step of forming a protective film of a material different from the metal plating film on the metal plating film after the plating step.
- a film forming step of forming a protective film of a material different from the metal plating film on the metal plating film after the plating step it is possible to prevent the metal plating film from being removed by, for example, etching performed when forming a wiring pattern using a subtractive method. This can prevent the judging sheet at the protruding portion from being damaged, and can more stably maintain the temporary joining state of the two support substrates.
- the electronic component further includes a polishing step of polishing a back surface of the innermost build-up insulating layer on which the build-up wiring pattern is not formed and / or a back surface of the support substrate.
- a polishing step of polishing a back surface of the innermost build-up insulating layer on which the build-up wiring pattern is not formed and / or a back surface of the support substrate According to such a manufacturing method, it is possible to reduce the thickness and size of the entire electronic component mounting machine plate.
- the electronic component mounting board provided by the second aspect of the present invention is a build-up laminate formed by alternately forming a metal support board and a build-up insulating layer and a build-up wiring pattern on the surface of the support board.
- An electronic component mounting board comprising: a body; and an electronic component mounted on the build-up laminate, wherein the support substrate has a through hole at a position where the electronic component is mounted;
- the electronic component is connected to a build-up wiring path in the innermost build-up insulating layer through the through hole of the support substrate. It is characterized in that it is mounted on the back side where turns are not formed.
- a gap generated around the electronic component in the through hole is sealed with an insulating resin.
- the electronic component is an IC chip, and a capacitor is mounted on a surface of the outermost build-up insulating layer on which the build-up wiring pattern is formed.
- the wiring distance between the IC chip and the capacitor can be reduced. Therefore, the inductance can be reduced, and the generation of noise can be suppressed.
- the metal constituting the supporting substrate has a coefficient of thermal expansion of 1 ppm / K to 20 ppmZK in a temperature range of 165 ° C to 280 ° C.
- the metal is preferably selected from the group consisting of 42 alloy, molybdenum, kovar, invar, 42 invar, titanium, copper / invar z copper clad material, stainless steel, copper, iron, nickel, and aluminum.
- FIG. 1 is a sectional view of a chip mounting board according to the present invention.
- 2a to 2n are cross-sectional views showing a series of steps of a method for manufacturing the chip mounting board.
- FIG. 3 is a cross-sectional view illustrating a modification of one step of the manufacturing method.
- FIG. 4 is a cross-sectional view illustrating another modified example of one step of the above manufacturing method.
- FIG. 1 is a cross-sectional view of a chip mounting board XI according to an embodiment of the present invention.
- the chip mounting substrate XI includes a support substrate 1 having a front surface 1a and a back surface 1b, a build-up laminate 2 formed on a front surface la, an IC chip 3, and a capacitor 4.
- the support substrate 1 has a through hole 11 for accommodating the IC chip 3.
- the through hole 11 is formed from the rear surface 1 b to the front surface 1 a of the support substrate 1 according to the shape of the IC chip 3 to be mounted.
- the overall shape of the support substrate 1 is, for example, plate-like, and its thickness is preferably approximately the same as the thickness of the IC chip 3. However, the shape and thickness are limited to these. I can't.
- the support substrate 1 is made of metal.
- the metal preferably has a coefficient of thermal expansion in the temperature range from 16 ° C. to 280 ° C. from 1 ppm / K to 20 ppm / K.
- Materials constituting this metal include 42 alloy, molybdenum, copal, Invar, 42 invar, titanium, copper / invar Z copper clad material, stainless steel, copper, iron, nickel, aluminum and the like.
- the build-up laminate 2 includes insulating layers 21a to 21f, wiring patterns 22a to 22f, vias 23, and overcoat layers 24.
- the insulating layer 21a is laminated and formed so as to be joined to the surface 1a of the support substrate 1 at the back surface 21a, and the wiring pattern is formed on the surface 21a of the insulating layer 21a.
- 2 2a is formed.
- the insulating layer 2 1b is formed so as to be bonded to the surface 2 12a of the insulating layer 21a at the back surface 2 lib, and is formed on the surface 2 1 2b of the insulating layer 2 1b.
- insulating layers 21c to 21f are sequentially formed.
- the number of layers of the build-up laminate 2 is not limited to the above, and may be arbitrarily determined as needed.
- thermosetting resin examples include a polyimide resin, an epoxy resin, a bismaleimide resin, a maleimide resin, a cyanate resin, a thermosetting polyphenylene ether resin, a polyphenylene oxide resin, a fluorine-containing resin, and a wholly aromatic type.
- thermosetting resin examples include polyester-based liquid crystal polymer resins. Note that the constituent materials of the insulating layers 21a to 21f are not limited to those described above.
- the wiring patterns 22a to 22f are formed on the insulating layers 21a to 21f, respectively.
- the wiring patterns between the layers (for example, wiring pattern 22 a and wiring pattern 22 b) are electrically connected by vias 23.
- the vias 23 are the same as the wiring patterns 22 a to 22 f by the method described later. Sometimes formed.
- Overcoat layer 2 4 is provided to protect the outermost insulating layer 2 1 f on the patterned wiring pattern 2 2 f, opening a part of the wiring pattern 2 2 f is provided in the Hare by faces It has 24 a.
- the resin listed above as a constituent material of the insulating layers 21a to 21f, or an epoxy acrylate resin used for a general solder resist is used. Can be used.
- the IC chip 3 has a plurality of ball electrodes 31, and the innermost insulating layer 21 a from the back surface 1 b side of the support substrate 1 through the through hole 11. Mounted on the back 2 1 1a.
- the main part of the IC chip 3 is made of a general semiconductor element material such as silicon, and has a coefficient of thermal expansion of 3.0 to 3.5 ppm / K.
- the plurality of ball electrodes 31 are arranged in a grid array on the surface 3a of the IC chip 3 to form a ball grid array.
- the ball electrode 31 is made of gold or solder having a predetermined composition.
- a gap formed around the IC chip 3 in the through hole 11 is resin-sealed with an insulating resin to form a resin-sealed portion 32.
- the insulating resin used for the resin sealing include an epoxy resin, a polyimide resin, and an isocyanate resin.
- the capacitor 4 has a plurality of electrode portions 41, and the outermost layer of the outermost layer is formed from the surface 24 side of the overcoat layer 24 through the opening portion 24a. It is mounted on the surface 2 1 2 f of the insulating layer 2 1 f.
- the number and capacity of the capacitors 4 may be arbitrarily determined as necessary.
- the surfaces 1a and 1a 'of the two supporting substrates 1 and 1 are degreased and acid-treated and surface-roughened. (For example, in the case of a support substrate made of copper, CZ treatment is performed), and the two support substrates 1 and 1 are stacked so that the back surfaces 1 b and 1 b ′ face each other. Is composed.
- each support substrate 1, 1 is made of insulating resin.
- the laminated supporting substrate 10 is sandwiched between two insulating sheets 20 and 20 having a size protruding from the portions lc and 1c ', and vacuum lamination is performed at a predetermined temperature and a predetermined time.
- the two support substrates 1 and 1 ′ can maintain a stacked state.
- the insulating resin constituting the insulating sheets 20 and 20 ' include the same materials as those of the insulating layers 21a to 21f described above. Therefore, the portion of the insulating sheets 20 and 20 'that covers the support substrates 1 and 1 functions as the innermost insulating layers 21a and 21a'.
- FIG. 2B shows a state in which the support substrates 1 and 1 ′ corresponding to one chip mounting substrate XI are vacuum-laminated.
- a support substrate having a size corresponding to the substrate may be subjected to vacuum lamination, and then divided into a plurality of chip mounting substrates after performing the steps described below.
- FIG. 2C is an enlarged view of a main part of the laminated support substrate 10 on which the insulating layers 21a and 21a 'are formed.
- a via hole 23a is formed at a predetermined portion of the insulating layer 21a, and then the resin residue inside the via hole 23a is removed, and the inner wall surface of the via hole 23a and the insulation are removed. Desmearing is performed to roughen the surface 211b of the layer 21a.
- a carbon dioxide laser, an excimer laser, a UV-YAG laser, or the like can be used as a means for forming the via hole 23a. Note that the steps shown in FIGS. 2c to 2h are the same for both support substrates 1, 1, so that only one support substrate 1 is shown.
- an electroless nickel plating layer 22a having a thickness of 0.5 to 2 / im is formed at the bottom of the via hole 23a by an electroless nickel plating method. Then, the thickness of 0.1 to 0 is applied to the surface 21b of the insulating layer 21a, the inner wall surface of the via hole 23a, and the upper surface of the electroless nickel plating layer 21a by the electroless copper plating method. .5 Electroless copper plating layer 2 2 2a is formed.
- the electroless copper plating layer 222 a serves as a seed layer that functions as a current-carrying layer in an electric plating process in a later step.
- a known method can be adopted as a series of processes in each electroless plating method.
- a resist pattern 25 is formed on the electroless copper plating layer 222a.
- dry film layer on electroless copper plating layer 22a A resist pattern 25 is formed by laminating a distant and patterning the dry film resist by an exposure process and a development process corresponding to a desired wiring pattern.
- an electroless copper plating process is performed using the electroless copper plating layer 222a as a current-carrying layer.
- an electromechanical layer 223a having a thickness of 10 to 30 ⁇ is deposited and grown on the non-mask region of the resist pattern 25.
- the electrolytic copper plating method for example, a known method using an acidic copper sulfate plating solution can be employed.
- the resist pattern 25 is peeled off.
- a sodium hydroxide aqueous solution or an organic amine-based aqueous solution can be used as the stripping solution.
- the electroless copper plating layer 222a that is not covered with the electrolytic copper plating layer 222a is removed. Specifically, the electroless copper plating layer 222a is etched away using, for example, a mixed aqueous solution of hydrogen peroxide and sulfuric acid, or an aqueous cupric chloride solution.
- the etchant acts in the same manner on the exposed portion of the electroless copper plating layer 222 a and the electroless copper plating layer 222 a, but as described above, the electroless copper plating layer 222 a Is thinner than that of the electroplated copper plating layer 2 23 a, only the exposed portions of the electroless copper plating layer 22 2 a disappear first. As a result, a wiring pattern 2 2 a having an electroless copper plating layer 2 2 2 a and an electric copper plating layer 2 2 3 a is formed on the surface 2 1 1 b of the insulating layer 2 1 a. .
- the series of steps shown in FIGS. 2c to 2h is repeated a predetermined number of times (for example, six times).
- a predetermined number of times for example, six times.
- the six-layer wiring patterns 22a to 22f electrically connected to each other via the vias 23 and the six insulating layers 21 a to 21 f are formed.
- the surfaces thereof are also electrically connected to each other through vias 23 '.
- Six wiring patterns 22a and six insulating layers 21a are formed.
- the electroless nickel plating layer may be formed only on the innermost insulating layers 21a and 21a '.
- a solder resist is printed on the outermost insulating layers 2lf and 21f, and is exposed, developed, and heat-cured.
- the overcoat layers 24, 24 having the openings 24a, 24a are formed.
- the portions of the wiring patterns 22 f and 22 f ′ exposed by the openings 24 a and 24 a ′ are formed on the wiring patterns 22 f and 22 f by electroless nickel plating.
- An electroless nickel plating layer (not shown) having a thickness of 0.5 to 2 m is formed.
- the portions protruding from the supporting substrate 1, 1 that are not used as the insulating layers 21a, 21a 'in the insulating sheets 20, 20' that is, the edge 20a). , 20 a ').
- the laminated state of the laminated supporting substrate 10 is released, and the multilayer wiring substrate Y1, as two intermediate products, is obtained.
- the removal of the edges 20a, 20a 'by cutting may be accompanied by cutting of a part of the supporting substrates 1, 1'.
- an etching pattern 26 is formed on the back surface 1b of the support substrate 1, as shown in FIG. 2k. Specifically, by laminating a dry film resist on the back surface 1b and performing exposure processing and development processing corresponding to a desired etching pattern, the dry film resist is patterned by etching. A pattern 26 is formed.
- a through hole 11 is formed in the support substrate 1 by etching. Specifically, the support substrate 1 is removed using an etchant that does not dissolve an epoxy resin such as an aqueous cupric chloride solution or a mixed aqueous solution of hydrogen peroxide and sulfuric acid. As a result, a through hole 11 is formed in the support substrate 1.
- the via 23 is an electroless nickel plating layer 22 1 a (see FIG. 2 h) provided at the bottom of the via hole 23 a (see FIG. 2 h). The via 23 is not etched.
- the etching pattern 26 is peeled off.
- an aqueous solution of sodium hydroxide or an aqueous solution of an organic amine can be used.
- an electroless gold plating layer having a thickness of 1 to 5 ⁇ is formed on the electroless nickel plating layer 22 a exposed through the through hole 11 by an electroless gold plating method. I do.
- a known method is used as a series of processes in the electroless gold plating method. Can be adopted.
- the back surface S 1 of the support substrate 1 is connected to the ball electrode 31 of the IC chip 3 and the via 23 via an electroless gold plating layer (not shown).
- the IC chip 3 is mounted on the back surface 211 a of the innermost insulating layer 21 a via the through hole 11 from the b side.
- an insulating resin is injected into a gap formed between the through hole 11 and the IC chip 3 to form an insulating sealing portion 32. Seal.
- the capacitor 4 is mounted on the overcoat layer 24, as also shown in FIG. At this time, the electrode portion 41 of the capacitor 4 is electrically connected to the outermost wiring pattern 22 f via the opening 24 a of the overcoat layer 24.
- the chip mounting substrate XI shown in FIG. 1 is manufactured.
- the laminated support substrate 10 is subjected to vacuum lamination using insulating sheets 20 and 20 ′, and then, as shown in FIG.
- the steps from Fig. 2c to 2h may be performed.
- the metal plating film 50 enables the edge portion 20 to be formed by the metal plating film 50 even when the number of build-up laminates 2 is large and the desmearing process performed when forming the via 23 is repeated many times. Since a and 20a are protected, it is possible to more effectively prevent the occurrence of broken holes or the like at the edges 20a and 20a.
- a copper rack or the like can be used as a constituent material of the metal plating film 50.
- the metal plating film 50 is subjected to the same processing for the edges 20 a and 20 a ′. It may be formed. By doing so, it is not necessary to provide a separate step for forming the metal plating film 50, and the working efficiency is improved.
- a protective film 51 is further formed on the metal plating film 50, and then, as shown in FIGS. Each step up to h may be performed.
- the number of build-up laminates 2 is large, and the seed layer (non- Even if the etching removal of the electrolytic copper plating film) is repeated many times, the metal plating film 50 can be prevented from being removed by etching, and as a result, tears or holes at the edges 20a and 20a 'can be prevented. Can be more effectively prevented.
- a constituent material of the protective film 51 polytetrafluoroethylene, polypropylene, or the like can be used as a constituent material of the protective film 51.
- the above-mentioned chip mounting substrate X1 is composed of a force S produced using a laminated supporting substrate 10 in which two supporting substrates 1 and 1 are laminated, a build-up laminate 2 formed on one supporting substrate 1, and an IC It may be manufactured by mounting the chip 3 and the capacitor 4. Also, the mounting positions of the IC chip 3 and the capacitor 4 may be interchanged. Further, after mounting the IC chip 3 or the capacitor 4 on the build-up laminate 2 through the through-hole 11, a step of further polishing the back surface 1 b of the support substrate 1 and the IC chip 3 or the capacitor 4 is performed. It may be provided.
- the distance between the IC chip 3 and the capacitor 4 can be reduced. Thereby, inductance can be reduced and generation of noise can be suppressed.
- the IC chip 3 can be mounted after the build-up laminate 2 is formed on the surface 1 a of the support substrate 1, the electrical continuity between the build-up laminate 2 and the IC chip 3 is achieved. Alignment for achieving alignment can be performed relatively easily. Also, since the IC chip 3 can be mounted after the build-up laminate 2 is formed, the IC chip 3 can be mounted after confirming that the build-up laminate 2 has been properly formed. It is excellent in practicality without wasting 3. Further, the support substrate 1 forms a through hole 11 by removing only the mounting area of the IC chip 3. Therefore, the remaining portion of the support substrate 1 plays a role similar to that of the stiffener, and has sufficient rigidity for mounting and other handling. Therefore, there is no need to provide a separate process for imparting rigidity. And work efficiency is excellent.
- the build-up laminates 2 and 2 ′ and the support substrates 1 and ⁇ ′ are formed.
- the warpage caused by the difference between the two coefficients of thermal expansion can be reduced. That is, by temporarily joining the back surfaces of the two support substrates 1 and 1 ′, the difference in the coefficient of thermal expansion between one support substrate 1 and the build-up laminate 2 formed on the surface of the support substrate is determined. Even if the warpage caused by the above occurs, the warpage is opposite to the warpage due to the difference in thermal expansion coefficient between the other support substrate 1 ′ and the build-up laminate 2 ′ formed on the surface of the other support substrate. Warping occurs and offset each other. Thereby, mounting reliability is improved.
- the gap between the IC chip 3 mounted through the through-hole 11 and the through-hole 11 and the build-up laminate 2 is sealed with insulating resin to improve the insulation between wirings.
- the stability of the mounted state of the IC chip 3 is increased. Therefore, higher reliability of the electrical connection between the IC chip 3 and the build-up laminate 2 can be achieved.
- the back surface 1 b of the support substrate 1 and the IC chip 3 or the capacitor 4 are further polished, The thickness of the entire chip mounting substrate X1 can be reduced.
- Two copper plates of 0.5 mm thick and 150 x 150 mm were prepared as a supporting base material, and the surfaces forming the build-up laminate were subjected to degreasing, acid treatment and CZ treatment, respectively. did. Then, the two copper plates were stacked so that their back surfaces face each other.
- An epoxy resin sheet with a thickness of 50 ⁇ and a size of 200 ⁇ 200 mm (Product name: SH-9) , Made of Ajinomoto) and pressed at 130 ° C for 2 minutes using a vacuum laminator. Furthermore, an insulating layer was formed on the surface of each copper plate by laminating at 170 ° C. for 30 minutes.
- via holes (diameter 50 / zm) were formed in predetermined positions in each insulating layer using a carbon dioxide laser, and desmearing was performed.
- an electroless nickel layer having a thickness of 1 ⁇ was formed at the bottom of each via hole.
- an electroless copper plating layer having a thickness of 0.3 ⁇ m was formed on each insulating layer and each electroless nickel layer.
- a dry film resist (trade name: RY-340, manufactured by Hitachi Chemical) is formed on each electroless copper plating layer with a predetermined pattern. The electroless copper plating layer was formed using the electroless plating layer as a current-carrying layer.
- the electroless copper plating film that had been covered with the dry film resist was removed by etching. Thereafter, the wiring pattern and the via were formed by heating at 170 ° C. for 6 ° minutes. Thereafter, the above-described series of steps from the step of forming the insulating layer to the step of forming the wiring pattern and the via was repeated four times to form a five-layer wiring structure.
- an overcoat layer was laminated on the five-layer wiring structure by screen printing and photolithography.
- An opening was provided at a predetermined position of the overcoat layer so that a part of the wiring pattern formed last could be seen.
- a 1-m-thick electroless nickel layer is formed on the wiring pattern facing the opening, followed by a 3-m-thick gold plating layer to establish connection with external terminals.
- a land electrode was formed. The land electrodes formed here are arranged corresponding to the arrangement of the conductive connecting portions of the capacitor to be mounted later.
- the laminated state of the two copper plates was released by cutting and removing the epoxy resin sheet protruding from the build-up laminate formed on the surface of the copper plate without forming an insulating layer.
- a dry film resist (trade name: NIT-50, manufactured by Nichigo Moton Co., Ltd.) is formed in a predetermined pattern on the back surface of the copper plate. (Kanto Kagaku) was used to etch the copper plate to form through holes. At this time, the via was not etched because the electroless nickel layer formed at the bottom of the via hole became a barrier metal.
- a land electrode for connection with external terminals was formed by forming a 3 im thick gold plating layer on the electroless nickel layer of the via facing the through hole. .
- the land electrodes formed here are arranged corresponding to the electrode arrangement of the IC chip to be mounted later.
- the IC chip having a thickness of 0.5 mm was mounted on the build-up laminate by solder bonding via land electrodes in such a manner as to be housed in the through hole.
- the gap created between the IC chip and the through-hole was sealed with epoxy resin (trade name: U84434-6, manufactured by Namics).
- the capacitor was mounted on the build-up laminate by solder bonding via the land electrode.
- via holes (diameter: 50 ⁇ ) were formed in predetermined positions in each insulating layer using a carbon dioxide laser, and desmearing was performed.
- an electroless nickel layer having a thickness of 1 ⁇ was formed at the bottom of each via hole.
- an electroless copper plating layer having a thickness of 0.3 ⁇ was formed on each insulating layer and each electroless nickel layer.
- electroless plating was also performed on the edge (the portion other than the insulating layer) of each epoxy resin sheet to form a metal plating film having a thickness of 3 ⁇ m.
- a dry film resist (trade name: RY-3240, manufactured by Hitachi Chemical) was formed in a predetermined pattern on each electroless copper plating layer.
- the electroless copper plating layer was formed using the electroless copper plating layer as a current-carrying layer. After peeling off the dry film resist, the electroless copper plating film that had been covered with the dry film resist was removed by etching. Thereafter, by heating at 170 ° C. for 60 minutes, a wiring pattern and a via were formed. Thereafter, a wiring pattern and a via are formed from the step of forming the insulating layer described above. By repeating the series of steps up to the four steps four times, a five-layer wiring structure was formed.
- an overcoat layer was laminated on the five-layer wiring structure by screen printing and photolithography.
- An opening was provided at a predetermined position of the overcoat layer so that a part of the wiring pattern formed last could be seen.
- an electroless nickel layer having a thickness of 1 ⁇ is formed on the wiring pattern facing the opening, and then a gold plating layer having a thickness is formed.
- a land electrode was formed. The land electrodes formed here are arranged corresponding to the arrangement of the conductive connecting portions of the capacitor to be mounted later.
- the laminated state of the two stainless steel plates was released by cutting and removing the epoxy resin sheet protruding from the build-up laminate formed on the surface of the stainless steel plate without forming an insulating layer.
- a dry film resist (trade name: NI 4-40, manufactured by Nichigo Morton) is formed on the back surface of the stainless steel plate in a predetermined pattern, and using the mask as a mask, the stainless steel plate is etched using an etching solution. Etching was performed to form through holes.
- a land electrode for connection with external terminals is formed by forming a gold plating layer with a thickness of 3 ⁇ on the electroless nickel layer of the via facing the through hole. did.
- the land electrodes formed here are arranged corresponding to the electrode arrangement of an IC chip to be mounted later.
- the IC chip having a thickness of 0.3 mm was mounted on the build-up laminate by soldering via land electrodes in such a manner as to be housed in the through hole.
- the gap created between the IC chip and the through-hole was sealed with epoxy resin (trade name: U84434-6, manufactured by Namics).
- the capacitor was mounted on the build-up laminate by solder bonding via the land electrode.
- the IC chip and the build-up A chip that is relatively easy to align, suppresses waste of Ic chips due to the yield of the build-up laminate, and is efficient and has excellent mountability without additional rigidity.
- the mounting substrate can be manufactured.
- the manufactured chip mounting board has a small inductance due to a small distance between the IC chip and the capacitor, thereby reducing noise.
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Abstract
An electronic component mount board is manufactured by the following method. Firstly, build-up insulation layers (21a-21f) and build-up wiring patterns (22a-22f) are alternately formed on the surface (1a) of a metallic support substrate (1) (Build-up lamination step). Next, a through-hole (11) from the back face (1b) of the support substrate (1) to the front face (1a) is formed to expose the back face (211a) of the innermost build-up insulation layer (21a) (Perforation step). Further, an electronic component (3) is mounted on the back face (211a) of the innermost build-up insulation layer (21a) via the through hole (11) of the support substrate (1) (Mounting step).
Description
明細 電子部品搭載基板の製造方法およびその方法により製造された電子部品搭載基 板 技術分野 Description Method of manufacturing electronic component mounting board and electronic component mounting board manufactured by the method
本発明は、電気 ·電子機器の回路系に使用される電子部品搭載基板の製造方法、 およびその方法により製造される電子部品搭載基板に関する。 背景技術 The present invention relates to a method of manufacturing an electronic component mounting board used in a circuit system of an electric / electronic device, and an electronic component mounting board manufactured by the method. Background art
近年、 電子機器に対する高性能化および小型化などの要求に伴い、 電子機器に 組み込まれる電子部品の高密度実装化が急速に進んでいる。 そのような高密度実 装化に対応すべく、 I Cチップについては、 ベアチップの状態で配線基板に面実 装される即ちフリップチップ実装される場合が多い。 I Cチップを搭載するため の配線基板については、 I Cチップの多ピン化に伴って、 配線の高密度化を達成 するうえで好適な多層配線基板が採用される傾向にある。 In recent years, with the demand for higher performance and smaller size of electronic devices, high-density mounting of electronic components incorporated in electronic devices is rapidly progressing. In order to cope with such high-density mounting, IC chips are often mounted on a wiring board in a bare chip state, that is, flip-chip mounted. With regard to the wiring board for mounting the IC chip, a multilayer wiring board suitable for achieving high-density wiring tends to be adopted as the number of pins of the IC chip increases.
多層配線基板における多層配線構造を形成するための工法として、 ビルドアッ プ法がある。 ビルドアップ法においては、 コア基板上で、 絶縁層の形成と当該絶 縁層上での配線パターンの形成とが順次繰り返されて、 配線が多層化される。 具 体的には、 まず、 コア基板となるガラスエポキシ基板や B T基板上にエポキシ系 樹脂からなるビルドアップ絶縁層を積層形成する。 次いで、 当該絶縁層に対して ビアホールを形成する。 ビアホールの形成手法としては、 絶縁層材料として感光 性樹脂を用いてフォトリソグラフィ技術により絶縁層に穴を形成する方法や、 レ 一ザ一を照射することによって絶縁層に穴を形成する方法などが採用される。 絶 縁層にビアホールを形成した後、 無電解メツキや電気メツキによって、 絶縁層上 に導体材料を成膜する。 このとき、 導体材料によりビアホールにはビアが形成さ れる。 次に、 絶縁層上に成膜された導体材料をエッチングすることによって配線 パターンを形成する。 このようにして絶縁層上において配線パターンを形成した 後、 絶縁層の積層形成から配線パターン形成まで一連の工程を所定回数繰り返す
ことによって、 配線の多層化を図ることができ、 その結果、 回路の集積度を高め ることができる。 As a method for forming a multilayer wiring structure in a multilayer wiring board, there is a build-up method. In the build-up method, the formation of an insulating layer and the formation of a wiring pattern on the insulating layer are sequentially repeated on the core substrate, and the wiring is multilayered. Specifically, first, a build-up insulating layer made of an epoxy resin is laminated on a glass epoxy substrate or a BT substrate serving as a core substrate. Next, a via hole is formed in the insulating layer. As a method of forming a via hole, there is a method of forming a hole in the insulating layer by photolithography using a photosensitive resin as a material of the insulating layer, or a method of forming a hole in the insulating layer by irradiating a laser. Adopted. After forming a via hole in the insulating layer, a conductive material is formed on the insulating layer by electroless plating or electric plating. At this time, a via is formed in the via hole by the conductive material. Next, a wiring pattern is formed by etching the conductive material formed on the insulating layer. After the wiring pattern is formed on the insulating layer in this manner, a series of steps from the formation of the insulating layer to the formation of the wiring pattern is repeated a predetermined number of times. This makes it possible to increase the number of wiring layers, thereby increasing the degree of circuit integration.
し力 し、ビルドアップ法によつて多層配線構造が形成された多層配線基板では、 高周波帯域における伝送特性が問題となっている。 特に、 I Cチップとキャパシ タとの間の距離が長くなると配線抵抗 （つまり、 インダクタンス） が増大し、 そ れに伴レ、信号ノィズがより発生し易くなる。 However, transmission characteristics in a high-frequency band are a problem in a multilayer wiring board having a multilayer wiring structure formed by a build-up method. In particular, when the distance between the IC chip and the capacitor increases, the wiring resistance (that is, inductance) increases, and as a result, signal noise is more likely to occur.
そこで、 I Cチップとキャパシタとの間の距離を短くして配線抵抗を抑制する 技術として、 コア基板の表面側に I Cチップの電極部が露出するようにしてコア 基板に I Cチップを内蔵し、 その後、 コア基板の表面に多層配線構造を形成する 技術が公知となっている （たとえば、 下記文献 1および 2参照。 ） 。 また、 I C チップとキャパシタとの間の距離を短くして配線抵抗を抑制するための他の技術 として、 金属からなる支持基板の表面にビルドアップ法により多層配線構造を形 成し、 この多層配線構造の最外層の表面に対して I Cチップを搭載するとともに 補強板加工を施した後、 前記支持基板の全体を除去し、 それにより露出した絶縁 層の裏面にハンダバンプを开成する Multi - Layer Thin-Fi lm (MLTF) Packaging Technologyが公知となっている。 （たとえば、 下記文献 3参照。 ） 。 In order to reduce the wiring resistance by shortening the distance between the IC chip and the capacitor, the IC chip is built into the core substrate so that the electrodes of the IC chip are exposed on the front side of the core substrate. Techniques for forming a multilayer wiring structure on the surface of a core substrate are known (for example, see the following references 1 and 2). Another technique for reducing the wiring resistance by shortening the distance between the IC chip and the capacitor is to form a multilayer wiring structure on the surface of a metal support substrate by a build-up method. After mounting the IC chip on the surface of the outermost layer of the structure and subjecting the reinforcing plate to processing, the entire support substrate is removed, thereby forming solder bumps on the back surface of the exposed insulating layer. Multi-Layer Thin -Film (MLTF) Packaging Technology is known. (For example, see Reference 3 below.)
' 文献 1 ：特開 2 0 0 1— 3 5 2 1 7 4号公報 文献 2 ： R. Emery, S. Towle, H. Braunisch, C. Hu， G. Raiser, and G. J.'' Literature 1: Japanese Unexamined Patent Application Publication No. 2000-3502 174. Literature 2: R. Emery, S. Towle, H. Braunisch, C. Hu, G. Raiser, and G. J.
Vandentop 、 "Novel Microelectronic Packaging Method for Reduced Thermomechanical Stresses on Low Dielectric Constant Materials"、 [online] 、 平成 1 3 年 1 0 月 1 2 日 、 intel Co. H. P. 、 URL ： http : // ww. intel. com/research/ si licon/BBUし conferencefoi ls. pdf > 文献 3 ： T. Shimoto, K. Kikuchi, H. Honda, K. Rata, K. Baba, and K. Matsui "High- Performance Flip-Chip BGA based on Multi-Layer Thin-Film Packaging Technology", Proceedings of the 2002 IMAPS, p. 10 - 15.
上記文献 1および 2に開示されている技術は、 I Cチップを予め支持基板に固 定した後で、 ビルドアップ法により多層配線構造を形成するため、 I Cチップと 多層配線構造との位置合わせが困難である。 また、 I Cチップを予め支持基板に 固定した後に多層配線構造を形成するため、 多層配線構造に不良が生じた場合、 I Cチップの再利用が非常に困難である。 つまり、 多層配線構造の歩留まりが 1Vandentop, "Novel Microelectronic Packaging Method for Reduced Thermomechanical Stresses on Low Dielectric Constant Materials", [online], October 12, 2001, intel Co. HP, URL: http: // ww. Intel. Com / research / si licon / BBU and conferencefoi ls. pdf> Reference 3: T. Shimoto, K. Kikuchi, H. Honda, K. Rata, K. Baba, and K. Matsui "High-Performance Flip-Chip BGA based on Multi -Layer Thin-Film Packaging Technology ", Proceedings of the 2002 IMAPS, p. 10-15. The technologies disclosed in the above-mentioned references 1 and 2 form a multilayer wiring structure by a build-up method after the IC chip is fixed to a supporting substrate in advance, so that it is difficult to align the IC chip with the multilayer wiring structure. It is. In addition, since the multilayer wiring structure is formed after the IC chip is fixed to the supporting substrate in advance, it is very difficult to reuse the IC chip if a defect occurs in the multilayer wiring structure. In other words, the yield of the multilayer wiring structure is 1
0 0 %でない場合は、 非常に高価な I Cチップを無駄にする可能性が高い。 If it is not 0%, it is likely to waste very expensive IC chips.
また、 文献 3に開示されている技術は、 I Cチップとキャパシタとの距離を近 くするために、 最終的に支持基板を全面除去する必要がある。 このように支持基 板を除去するとチップ部品搭載基板として剛性に乏しく、 実装やその他のハンド リングを行うのが非常に困難になる。 加えて、 支持基板が除去されたチップ部品 搭载基板に対して剛性付与の目的で多層配線構造の最上層の表面にステフナを設 ける場合、 プロセス工程が増加するため、 作業効率的に好ましくない。 また、 I Cチップ搭載後にチップ部品搭載基板を加工する必要があるため、 当該加工時に In the technique disclosed in Reference 3, it is necessary to finally remove the entire supporting substrate in order to shorten the distance between the IC chip and the capacitor. When the support substrate is removed in this way, the rigidity of the chip component mounting substrate is poor, and mounting and other handling become extremely difficult. In addition, if a stiffener is provided on the surface of the uppermost layer of the multilayer wiring structure for the purpose of imparting rigidity to the chip component mounting substrate from which the supporting substrate has been removed, the number of process steps increases, which is not preferable in terms of work efficiency. Also, since it is necessary to process the chip component mounting board after mounting the IC chip,
1 Cチップが壊れる可能性がある。 発明の開示 1 C chip may be broken. Disclosure of the invention
そこで、 本発明の目的は、 電子部品搭載基板の低インダクタンス化を図るとと もに、 位置合わせ性および実用性に優れ且つ作業効率にも優れた電子部品搭載基 板の製造方法を提供することにある。 Accordingly, an object of the present invention is to provide a method of manufacturing an electronic component mounting board which is excellent in alignment, practicality, and work efficiency while reducing the inductance of the electronic component mounting board. It is in.
本発明の他の目的は、 このような方法により製造されたチップ部品搭載基板を 提供することにある。 Another object of the present invention is to provide a chip component mounting board manufactured by such a method.
本発明の第 1の側面によって提供される電子部品搭載基板の製造方法は、 金属 製の支持基板の表面に、 ビルド了ップ絶縁層およびビルドァップ配線パターンを 交互に形成するビルドアップ積層工程と、 前記支持基板の電子部品を載置する位 置に貫通孔を形成して、最内層のビルドアップ絶縁層を露出させる孔形成工程と、 前記支持基板の前記貫通孔を介して前記最内層のビルドアップ絶縁層に電子部品 を搭載する実装工程とを含むことを特徴としている。 The method for manufacturing an electronic component mounting board provided by the first aspect of the present invention includes: a build-up laminating step of alternately forming a build-up insulating layer and a build-up wiring pattern on a surface of a metal support board; A hole forming step of forming a through hole at a position where the electronic component is mounted on the support substrate to expose a build-up insulating layer of the innermost layer; and a build-up of the innermost layer via the through hole of the support substrate. And mounting the electronic component on the up-insulating layer.
このような製造方法によれば、 支持基板の表面にビルドアップ積層体を形成し た後に電子部品の搭載を行うことができる。 そのため、 ビルドアップ積層体に対
して電子部品を搭載する際の位置合わせは、 比較的容易に行うことができる。 ま た、ビルドアップ積層体を形成した後で電子部品の搭載を行うことができるので、 ビルドアップ積層体が適性に形成されたことを確認してから電子部品を搭載すれ ばよいので電子部品を無駄にすることがなく、 実用性に優れている。 さらに、 支 持基板は電子部品の搭載領域のみを除去するから、 支持基板の残りの部分がステ フナと同様の役割を果たす。 そのため、 実装やその他のハンドリングを行うのに 充分な剛性を有している。 したがって、 別途剛性付与を行う工程を設ける必要が なく、 作業効率的にも優れている。 According to such a manufacturing method, the electronic components can be mounted after the build-up laminate is formed on the surface of the support substrate. Therefore, build-up laminates Positioning when mounting electronic components can be performed relatively easily. Also, since the electronic components can be mounted after the build-up laminate is formed, the electronic components can be mounted after confirming that the build-up laminate has been properly formed. It is practical without waste. Further, since the support substrate removes only the mounting area for electronic components, the remaining portion of the support substrate plays a role similar to that of the stiffener. Therefore, it has sufficient rigidity for mounting and other handling. Therefore, there is no need to provide a separate step for imparting rigidity, and work efficiency is excellent.
好ましくは、 前記実装工程の後に前記貫通孔において前記電子部品の周りに生 じる隙間を絶縁性樹脂で封止する封止工程をさらに含んでいる。 これにより、 各 配線間の絶縁性が向上するのに加え、電子部品の搭載状態における安定度が増す。 そのため、 電子部品とビルドアップ積層体との間の電気的接続について、 より高 い信頼性を達成することができる。 Preferably, the method further includes a sealing step of sealing a gap generated around the electronic component in the through hole after the mounting step with an insulating resin. As a result, in addition to improving the insulation between the wirings, the stability in the mounted state of the electronic component is increased. Therefore, higher reliability can be achieved for the electrical connection between the electronic component and the build-up laminate.
好ましくは、 前記ビルドアップ積層工程の前に 2枚の支持基板の裏面同士を仮 接合する仮接合工程をさらに含み、 前記ビルドアップ積層工程の後で前記孔形成 工程の前に両支持基板を分離する分離工程をさらに含み、 前記ビルドアップ積層 工程は各支持基板の表面に対して行われる。 このような製造方法によれば、 ビル ドアップ積層工程において支持基板やビルドアップ絶縁層に熱がかかる際、 両者 の熱膨張率の差に起因して生じる反りを緩和することができる。 すなわち、 2枚 の支持基板の裏面同士を仮接合することによって、 一方の支持基板と当該支持基 板の表面に形成されたビルドアップ絶縁層との熱膨張率の差に起因する反りが生 じたとしても、 この反りとは正反対に、 他方の支持基板と当該他方の支持基板の 表面に形成されたビルドアップ絶縁層との熱膨張率の差に起因する反りが生じ、 互いに相殺しあう。 これにより、 実装信頼性が向上する。 Preferably, the method further includes a temporary bonding step of temporarily bonding the back surfaces of the two support substrates before the build-up lamination step, and separating the two support substrates after the build-up lamination step and before the hole forming step. The build-up laminating step is performed on the surface of each support substrate. According to such a manufacturing method, when heat is applied to the support substrate and the build-up insulating layer in the build-up laminating step, it is possible to reduce the warpage caused by the difference in the coefficient of thermal expansion between the two. That is, by temporarily bonding the back surfaces of the two support substrates, warpage occurs due to a difference in thermal expansion coefficient between one support substrate and a build-up insulating layer formed on the surface of the support substrate. Even if this is the case, the warpage occurs due to the difference in the coefficient of thermal expansion between the other support substrate and the build-up insulating layer formed on the surface of the other support substrate. Thereby, mounting reliability is improved.
好ましくは、 前記仮接合工程は、 各支持基板の外周部からはみ出す大きさの 2 枚の樹脂シートの間に前記両支持基板を挟み、 両樹脂シートを加熱下で真空ラミ ネートすることにより行う。 このような製造方法によれば、 2枚の支持基板は、 接着剤などを使うことなく接合状態を維持することができるとともに、 たとえば 前記外周部からはみ出している樹脂シートを切断するだけで 2枚の支持基板を容
易に分離することができる。 また、 樹脂シートの一部は、 ビルドアップ絶縁層の 最内層として用いることが可能であり、 作業効率的にも優れている。 Preferably, the temporary bonding step is performed by sandwiching the two support substrates between two resin sheets having a size protruding from the outer peripheral portion of each support substrate, and vacuum laminating the two resin sheets under heating. According to such a manufacturing method, the two supporting substrates can maintain the joined state without using an adhesive or the like, and for example, only by cutting the resin sheet protruding from the outer peripheral portion, the two supporting substrates are cut. Support substrate Can be easily separated. Also, a part of the resin sheet can be used as the innermost layer of the build-up insulating layer, which is excellent in work efficiency.
好ましくは、 前記仮接合工程の後に前記両樹脂シートの少なくともはみ出し部 に金属メツキ膜を形成するメツキ工程をさらに含んでいる。 このような製造方法 によれば、 ビルドァップ積層工程においてビルドアップ絶縁層上にビルドァップ 配線パターンを形成する際に表面粗化処理を行う場合でも、 前記金属メツキ膜に より前記はみ出し部の樹脂シートは表面粗ィヒ処理の影響を受けない。したがって、 ビルドアップ積層工程において多層形成する場合でも、 前記はみ出し部の樹脂シ 一トが破損したりすることがなく、 2枚の支持基板の仮接合状態をより安定して 維持することができる。 Preferably, the method further includes a plating step of forming a metal plating film on at least the protruding portions of the resin sheets after the temporary joining step. According to such a manufacturing method, even when a surface roughening process is performed when forming a build-up wiring pattern on a build-up insulating layer in a build-up laminating step, the resin sheet of the protruding portion is surfaced by the metal plating film. Unaffected by coarse treatment. Therefore, even when a multilayer is formed in the build-up lamination process, the resin sheet at the protruding portion is not damaged, and the temporary bonding state of the two support substrates can be more stably maintained.
好ましくは、 前記金属メッキ膜は、 前記最内層のビルドアップ絶縁層に対する 配線パターンと同時に形成される。 このような製造方法によれば、 金属メツキ膜 の形成を、 より作業効率よく行うことができる。 Preferably, the metal plating film is formed simultaneously with a wiring pattern for the innermost build-up insulating layer. According to such a manufacturing method, the metal plating film can be formed with higher working efficiency.
好ましくは、 前記メツキ工程の後に前記金属メツキ膜上に当該金属メツキ膜と は異なる材料の保護膜を形成する膜形成工程をさらに含んでいる。 このような製 造方法によれば、 金属メツキ膜が、 たとえばサブトラクティブ法を用いて配線パ ターンを形成する際に行われるエッチングなどにより除去されるのを防ぐことが できる。 これにより、 はみ出し部の樹月旨シートの破損を防ぐことができ、 2枚の 支持基板の仮接合状態をより安定して維持することができる。 Preferably, the method further includes a film forming step of forming a protective film of a material different from the metal plating film on the metal plating film after the plating step. According to such a manufacturing method, it is possible to prevent the metal plating film from being removed by, for example, etching performed when forming a wiring pattern using a subtractive method. This can prevent the judging sheet at the protruding portion from being damaged, and can more stably maintain the temporary joining state of the two support substrates.
本発明の好ましい実施の形態においては、 電子部品において、 最内層のビルド ァップ絶縁層におけるビルドァップ配線パターンが形成されていない裏面および /または支持基板の裏面を研磨する研磨工程をさらに有している。 このような製 造方法によれば、 電子部品搭載機板全体の薄肉小型化を図ることが可能となる。 本発明の第 2の側面によって提供される電子部品搭載基板は、 金属製の支持基 板と、 当該支持基板の表面にビルドァップ絶縁層およびビルドァップ配線パタ一 ンを交互に形成してなるビルドアップ積層体と、 当該ビルドアップ積層体に搭載 された電子部品と、 を備えた電子部品搭載基板であって、 前記支持基板は、 前記 電子部品を載置する位置に貫通孔を有しており、 前記電子部品は、 前記支持基板 の前記貫通孔を介して最内層のビルドアップ絶縁層におけるビルドアップ配線パ
ターンが形成されていない裏面に搭載されていることを特@としている。 In a preferred embodiment of the present invention, the electronic component further includes a polishing step of polishing a back surface of the innermost build-up insulating layer on which the build-up wiring pattern is not formed and / or a back surface of the support substrate. According to such a manufacturing method, it is possible to reduce the thickness and size of the entire electronic component mounting machine plate. The electronic component mounting board provided by the second aspect of the present invention is a build-up laminate formed by alternately forming a metal support board and a build-up insulating layer and a build-up wiring pattern on the surface of the support board. An electronic component mounting board comprising: a body; and an electronic component mounted on the build-up laminate, wherein the support substrate has a through hole at a position where the electronic component is mounted; The electronic component is connected to a build-up wiring path in the innermost build-up insulating layer through the through hole of the support substrate. It is characterized in that it is mounted on the back side where turns are not formed.
好ましくは、 前記貫通孔において前記電子部品の周りに生じる隙間は絶縁性樹 脂で封止されている。 Preferably, a gap generated around the electronic component in the through hole is sealed with an insulating resin.
好ましくは、 前記電子部品は I Cチップであり、 最外層のビルドアップ絶縁層 におけるビルドアップ配線パターンが形成された表面にキャパシタが搭載されて いる。 これにより、 I Cチップとキャパシタとの配線距離を短くすることができ る。 したがって、 インダクタンスを低減することができ、 ノイズの発生を抑制す ることができる。 Preferably, the electronic component is an IC chip, and a capacitor is mounted on a surface of the outermost build-up insulating layer on which the build-up wiring pattern is formed. As a result, the wiring distance between the IC chip and the capacitor can be reduced. Therefore, the inductance can be reduced, and the generation of noise can be suppressed.
本発明の好ましい実施の形態においては、 支持基板を構成する金属は、 一 6 5 °C〜 2 8 0 °Cの温度範囲における熱膨張係数が 1 p p m/K〜 2 0 p p mZKで ある。このような熱膨張係数を有する金属からなる支持基板を用いることにより、 比較的熱膨張係数が大きいビルドアップ積層体と比較的熱膨張係数が小さい電子 部品との差をより低減することができる。 したがって、 ビルドアップ積層体と電 子部品との間の電気的接続について、 より高い信頼性を達成することができる。 なお、 金属としては、 4 2ァロイ、 モリブデン、 コバール、 インバー、 4 2イン バー、 チタン、 銅/インバー z銅クラッド材、 ステンレス、 銅、 鉄、 ニッケル、 アルミニウムからなる群より選ばれるのが好ましい。 図面の簡単な説明 In a preferred embodiment of the present invention, the metal constituting the supporting substrate has a coefficient of thermal expansion of 1 ppm / K to 20 ppmZK in a temperature range of 165 ° C to 280 ° C. By using a supporting substrate made of a metal having such a coefficient of thermal expansion, the difference between the build-up laminate having a relatively large coefficient of thermal expansion and an electronic component having a relatively small coefficient of thermal expansion can be further reduced. Therefore, higher reliability of the electrical connection between the build-up laminate and the electronic component can be achieved. The metal is preferably selected from the group consisting of 42 alloy, molybdenum, kovar, invar, 42 invar, titanium, copper / invar z copper clad material, stainless steel, copper, iron, nickel, and aluminum. BRIEF DESCRIPTION OF THE FIGURES
図 1は、 本発明に係るチップ搭載基板の断面図である。 FIG. 1 is a sectional view of a chip mounting board according to the present invention.
図 2 a〜2 nは、 同チップ搭載基板の製造方法の一連の工程を示す断面図であ る。 2a to 2n are cross-sectional views showing a series of steps of a method for manufacturing the chip mounting board.
図 3は、 上記製造方法の一工程の変形例を表す断面図である。 FIG. 3 is a cross-sectional view illustrating a modification of one step of the manufacturing method.
図 4は、 上記製造方法の一工程の他の変形例を表す断面図である。 発明を実施するための最良の形態 FIG. 4 is a cross-sectional view illustrating another modified example of one step of the above manufacturing method. BEST MODE FOR CARRYING OUT THE INVENTION
図 1は、 本発明の実施の形態に係るチップ搭載基板 X Iの断面図である。 チッ プ搭載基板 X Iは、 表面 1 aおよび裏面 1 bを有する支持基板 1と、 表面 l aに 形成されたビルドアップ積層体 2と、 I Cチップ 3と、キャパシタ 4とを備える。
支持基板 1は、 I Cチップ 3を収容するための貫通孔 1 1を有している。 貫通 孔 1 1は、 支持基板 1の裏面 1 bから表面 1 aに至るように、 搭載する I Cチッ プ 3の形状に応じて形成されている。 また、 支持基板 1の全体形状としては、 た とえば板状であり、 その厚みは、 I Cチップ 3の厚みと同程度であることが好ま しいが、 当該形状や厚みは、 これらのものに限られない。 FIG. 1 is a cross-sectional view of a chip mounting board XI according to an embodiment of the present invention. The chip mounting substrate XI includes a support substrate 1 having a front surface 1a and a back surface 1b, a build-up laminate 2 formed on a front surface la, an IC chip 3, and a capacitor 4. The support substrate 1 has a through hole 11 for accommodating the IC chip 3. The through hole 11 is formed from the rear surface 1 b to the front surface 1 a of the support substrate 1 according to the shape of the IC chip 3 to be mounted. The overall shape of the support substrate 1 is, for example, plate-like, and its thickness is preferably approximately the same as the thickness of the IC chip 3. However, the shape and thickness are limited to these. I can't.
また、 支持基板 1は、 金属からなる。 この金属は、 一 6 5 °C〜2 8 0 °Cの温度 範囲における熱膨張係数が 1 p p m/K〜2 0 p p m/Kであるのが好ましい。 この金属を構成する材料としては、 4 2ァロイ、 モリブデン、 コパール、 インバ 一、 4 2インバー、 チタン、 銅/インバー Z銅クラッド材、 ステンレス、 銅、 鉄、 ニッケル、 アルミニウムなどが挙げられる。 The support substrate 1 is made of metal. The metal preferably has a coefficient of thermal expansion in the temperature range from 16 ° C. to 280 ° C. from 1 ppm / K to 20 ppm / K. Materials constituting this metal include 42 alloy, molybdenum, copal, Invar, 42 invar, titanium, copper / invar Z copper clad material, stainless steel, copper, iron, nickel, aluminum and the like.
ビルドアップ積層体 2は、 絶縁層 2 1 a〜 2 1 f と、 配線パターン 2 2 a〜 2 2 f と、 ビア 2 3と、 オーバーコート層 2 4とを含む。 絶縁層 2 1 aは、 その裏 面 2 1 1 aにて支持基板 1の表面 1 aに接合するように積層形成されており、 絶 縁層 2 1 aの表面 2 1 2 aには配線パターン 2 2 aが形成されている。 また、 絶 縁層 2 1 bは、 その裏面 2 l i bにて絶縁層 2 1 aの表面 2 1 2 aに接合するよ うに積層形成されており、 絶縁層 2 1 bの表面 2 1 2 bには配線パターン 2 2 b が形成されている。 さらに、 図 1に示したように絶縁層 2 1 bと同様に、 絶縁層 2 1 c〜2 1 f が順次積層形成されている。 ただし、 ビルドアップ積層体 2の積 層数は、 上記のものに限られず必要に応じて任意に定めればよい。 The build-up laminate 2 includes insulating layers 21a to 21f, wiring patterns 22a to 22f, vias 23, and overcoat layers 24. The insulating layer 21a is laminated and formed so as to be joined to the surface 1a of the support substrate 1 at the back surface 21a, and the wiring pattern is formed on the surface 21a of the insulating layer 21a. 2 2a is formed. The insulating layer 2 1b is formed so as to be bonded to the surface 2 12a of the insulating layer 21a at the back surface 2 lib, and is formed on the surface 2 1 2b of the insulating layer 2 1b. Has a wiring pattern 22b. Further, as shown in FIG. 1, similarly to the insulating layer 21b, insulating layers 21c to 21f are sequentially formed. However, the number of layers of the build-up laminate 2 is not limited to the above, and may be arbitrarily determined as needed.
絶縁層 2 1 a〜 2 1 f の構成材料としては、 一般的な熱硬化性樹脂を用いるこ とが好ましい。 当該熱硬化性樹脂としては、 たとえばポリイミド樹脂、 エポキシ 樹脂、 ビスマレイミ ド樹脂、 マレイミ ド樹脂、 シァネート樹脂、 熱硬化性ポリフ ニレンエーテル樹脂、 ポリフエ二レンオキサイド樹脂、 フッ素含有樹脂、 およ ぴ全芳香型ポリエステル系液晶ポリマー樹脂などが挙げられる。 なお、 絶縁層 2 1 a〜2 1 f の構成材料は、 上記のものに限られない。 As a constituent material of the insulating layers 21a to 21f, it is preferable to use a general thermosetting resin. Examples of the thermosetting resin include a polyimide resin, an epoxy resin, a bismaleimide resin, a maleimide resin, a cyanate resin, a thermosetting polyphenylene ether resin, a polyphenylene oxide resin, a fluorine-containing resin, and a wholly aromatic type. Examples include polyester-based liquid crystal polymer resins. Note that the constituent materials of the insulating layers 21a to 21f are not limited to those described above.
配線パターン 2 2 a〜 2 2 f は、 それぞれ絶縁層 2 1 a〜 2 1 f 上においてパ タ一ン形成されたものである。 層間の各配線パターン間 （たとえば配線パターン 2 2 aと配線パターン 2 2 bなど） は、 ビア 2 3によって、 電気的に接続されて いる。 なお、 ビア 2 3は、 後述する方法により配線パターン 2 2 a〜2 2 f と同
時に形成される。 The wiring patterns 22a to 22f are formed on the insulating layers 21a to 21f, respectively. The wiring patterns between the layers (for example, wiring pattern 22 a and wiring pattern 22 b) are electrically connected by vias 23. The vias 23 are the same as the wiring patterns 22 a to 22 f by the method described later. Sometimes formed.
オーバーコート層 2 4は、 最外層の絶縁層 2 1 f 上にパターン形成された配線 パターン 2 2 f を保護するために設けられ、 配線パターン 2 2 f の一部が臨むよ うに設けた開口部 2 4 aを有している。 オーバーコート層 2 4を構成する材料と しては、 絶縁層 2 1 a〜2 1 f の構成材料として上掲した樹脂や、 あるいは一般 的なソルダーレジストに用いられているエポキシァクリレート樹脂を用いること ができる。 Overcoat layer 2 4 is provided to protect the outermost insulating layer 2 1 f on the patterned wiring pattern 2 2 f, opening a part of the wiring pattern 2 2 f is provided in the Hare by faces It has 24 a. As a material for forming the overcoat layer 24, the resin listed above as a constituent material of the insulating layers 21a to 21f, or an epoxy acrylate resin used for a general solder resist is used. Can be used.
I Cチップ 3は、 図 1に示したように、 複数のボール電極 3 1を有しており、 支持基板 1の裏面 1 b側から貫通孔 1 1を介して最内層の絶縁層 2 1 aの裏面 2 1 1 aに搭載されている。 I Cチップ 3は、 その主要部分がシリコンなどの一般 的な半導体素子材料により構成されており、 熱膨張率 3 . 0〜 3 . 5 p p m/K を示す。 複数のボール電極 3 1は、 I Cチップ 3の表面 3 aにてグリッドアレイ 状に配列し、 ボールグリッドアレイを構成している。 ボール電極 3 1は、 金、 ま たは、 所定の組成のハンダよりなる。 また、 貫通孔 1 1において I Cチップ 3の 周りに生じる隙間は、 絶縁性樹脂により樹脂封止され、 樹脂封止部 3 2が形成さ れている。 この樹脂封止に用いられる絶縁性樹脂としては、 エポキシ樹脂、 ポリ イミ ド樹脂、 イソシァネート樹脂などが挙げられる。 As shown in FIG. 1, the IC chip 3 has a plurality of ball electrodes 31, and the innermost insulating layer 21 a from the back surface 1 b side of the support substrate 1 through the through hole 11. Mounted on the back 2 1 1a. The main part of the IC chip 3 is made of a general semiconductor element material such as silicon, and has a coefficient of thermal expansion of 3.0 to 3.5 ppm / K. The plurality of ball electrodes 31 are arranged in a grid array on the surface 3a of the IC chip 3 to form a ball grid array. The ball electrode 31 is made of gold or solder having a predetermined composition. Further, a gap formed around the IC chip 3 in the through hole 11 is resin-sealed with an insulating resin to form a resin-sealed portion 32. Examples of the insulating resin used for the resin sealing include an epoxy resin, a polyimide resin, and an isocyanate resin.
キャパシタ 4は、 図 1に示したように、 複数の電極部 4 1を有しており、 ォー バーコート層 2 4の表面 2 4 2側から開口部 2 4 aを介して、 最外層の絶縁層 2 1 f の表面 2 1 2 f に搭載されている。 キャパシタ 4の搭載数や容量は、 必要に 応じて任意に定めればよい。 As shown in FIG. 1, the capacitor 4 has a plurality of electrode portions 41, and the outermost layer of the outermost layer is formed from the surface 24 side of the overcoat layer 24 through the opening portion 24a. It is mounted on the surface 2 1 2 f of the insulating layer 2 1 f. The number and capacity of the capacitors 4 may be arbitrarily determined as necessary.
以下、 ビルドアップ法により本実施形態に係るチップ搭載基板 X 1を製造する のに好適な方法を、 図 2 a〜図 2 nを参照して説明する。 Hereinafter, a method suitable for manufacturing the chip mounting substrate X1 according to the present embodiment by a build-up method will be described with reference to FIGS. 2A to 2N.
チップ搭載基板 X 1の製造においては、 まず、 図 2 aに示すように、 2枚の支 持基板 1， 1 のそれぞれ表面 1 a， 1 a 'に脱脂 ·酸処理およびノまたは表面 粗化処理 （たとえば、 銅からなる支持基板の場合は、 C Z処理など） を施し、 2 枚の支持基板 1， 1 の裏面 1 b， 1 b '同士が対向するように重ね合わせて積 層支持基板 1 0を構成する。 In the manufacture of the chip mounting substrate X1, first, as shown in Fig. 2a, the surfaces 1a and 1a 'of the two supporting substrates 1 and 1 are degreased and acid-treated and surface-roughened. (For example, in the case of a support substrate made of copper, CZ treatment is performed), and the two support substrates 1 and 1 are stacked so that the back surfaces 1 b and 1 b ′ face each other. Is composed.
次に、 図 2 bに示すように、 絶縁性樹脂からなり、 各支持基板 1， 1 の外周
部 l c， 1 c 'からはみ出す大きさの 2枚の絶縁シート 2 0, 2 0 の間に積層 支持基板 1 0を挟み、 所定温度および所定時間で真空ラミネートが施される。 こ れにより、 2枚の支持基板 1 , 1 'は、 積層状態を維持することができる。 絶縁 シート 2 0， 2 0 'を構成する絶縁性樹脂としては、 上掲した絶縁層 2 1 a〜 2 1 f の構成材料と同様のものが挙げられる。 したがって、 絶縁シート 2 0, 2 0 'のうちの各支持基板 1， 1 を覆う部分は、 最内層の絶縁層 2 1 a , 2 1 a ' として機能する。 なお、 図示の簡素化の観点より、 図 2 bでは 1つのチップ搭載 基板 X Iに相当する支持基板 1 , 1 'に真空ラミネートを施こした状態で表して いるが、 たとえば複数個分のチップ搭載基板に対応する大きさの支持基板にまと めて真空ラミネ一トを施して、 後述の工程を行った後に複数個のチップ搭載基板 に分割してもよレ、。 Next, as shown in Fig. 2b, the outer periphery of each support substrate 1, 1 is made of insulating resin. The laminated supporting substrate 10 is sandwiched between two insulating sheets 20 and 20 having a size protruding from the portions lc and 1c ', and vacuum lamination is performed at a predetermined temperature and a predetermined time. As a result, the two support substrates 1 and 1 ′ can maintain a stacked state. Examples of the insulating resin constituting the insulating sheets 20 and 20 'include the same materials as those of the insulating layers 21a to 21f described above. Therefore, the portion of the insulating sheets 20 and 20 'that covers the support substrates 1 and 1 functions as the innermost insulating layers 21a and 21a'. From the viewpoint of simplification of the drawing, FIG. 2B shows a state in which the support substrates 1 and 1 ′ corresponding to one chip mounting substrate XI are vacuum-laminated. A support substrate having a size corresponding to the substrate may be subjected to vacuum lamination, and then divided into a plurality of chip mounting substrates after performing the steps described below.
次に、 絶縁層 2 1 a , 2 1 a 'が形成された積層支持基板 1 0の要部拡大図を 図 2 cに示す。 この図に示すように、 絶縁層 2 1 aの所定箇所において、 ビアホ ール 2 3 aを形成し、その後、 ビアホール 2 3 a内部における樹脂残渣の除去と、 ビアホール 2 3 aの内壁面および絶縁層 2 1 aの表面 2 1 1 bの粗化とを行うた めにデスミア処理を行う。 ビアホール 2 3 aの形成手段としては、 炭酸ガスレー ザ、 エキシマレーザ、 UV— Y AGレーザなどを採用することができる。 なお、 図 2 c〜2 hに示す工程は、 両支持基板支持基板 1， 1 ,について同じであるの で、 一方の支持基板 1についてのみ図示している。 Next, FIG. 2C is an enlarged view of a main part of the laminated support substrate 10 on which the insulating layers 21a and 21a 'are formed. As shown in this figure, a via hole 23a is formed at a predetermined portion of the insulating layer 21a, and then the resin residue inside the via hole 23a is removed, and the inner wall surface of the via hole 23a and the insulation are removed. Desmearing is performed to roughen the surface 211b of the layer 21a. As a means for forming the via hole 23a, a carbon dioxide laser, an excimer laser, a UV-YAG laser, or the like can be used. Note that the steps shown in FIGS. 2c to 2h are the same for both support substrates 1, 1, so that only one support substrate 1 is shown.
次に、 図 2 dに示すように、 無電解ニッケルメツキ法により、 ビアホール 2 3 aの底に厚さ 0. 5〜2 /i mの無電解ニッケルメツキ層 2 2 1 aを形成する。 そ の後、 無電解銅メツキ法により、 絶縁層 2 1 aの表面 2 1 1 bとビアホール 2 3 aの内壁面と無電解ニッケルメツキ層 2 2 1 a上とに厚さ 0. 1〜0. 5 の 無電解銅メツキ層 2 2 2 aを形成する。 この無電解銅メツキ層 2 2 2 aは、 後の 工程の電気メツキ処理における通電層として機能するシード層となる。 なお、 そ れぞれの無電解メツキ法における一連の処理としては、 公知の手法を採用するこ とができる。 Next, as shown in FIG. 2D, an electroless nickel plating layer 22a having a thickness of 0.5 to 2 / im is formed at the bottom of the via hole 23a by an electroless nickel plating method. Then, the thickness of 0.1 to 0 is applied to the surface 21b of the insulating layer 21a, the inner wall surface of the via hole 23a, and the upper surface of the electroless nickel plating layer 21a by the electroless copper plating method. .5 Electroless copper plating layer 2 2 2a is formed. The electroless copper plating layer 222 a serves as a seed layer that functions as a current-carrying layer in an electric plating process in a later step. In addition, as a series of processes in each electroless plating method, a known method can be adopted.
次に、 図 2 eに示すように、 無電解銅メツキ層 2 2 2 a上にレジストパターン 2 5を形成する。 具体的には、 無電解銅メツキ層 2 2 2 a上にドライフィルムレ
ジストをラミネートし、 所望の配線パターンに対応した露光処理および現像処理 により当該ドライフィルムレジストをパターニングすることによって、 レジスト パターン 2 5を形成する。 Next, as shown in FIG. 2e, a resist pattern 25 is formed on the electroless copper plating layer 222a. Specifically, dry film layer on electroless copper plating layer 22a A resist pattern 25 is formed by laminating a distant and patterning the dry film resist by an exposure process and a development process corresponding to a desired wiring pattern.
次に、 図 2 f に示すように、 無電解銅メツキ層 2 2 2 aを通電層として、 電気 銅メツキ処理を施す。 これにより、 レジストパターン 2 5の非マスク領域に、 厚 さ 1 0〜3 0 μ πιの電気鲖メツキ層 2 2 3 aを堆積成長させる。 電気銅メツキ法 としては、 たとえば、 酸性硫酸銅メツキ液を用いた公知の手法を採用することが できる。 Next, as shown in FIG. 2f, an electroless copper plating process is performed using the electroless copper plating layer 222a as a current-carrying layer. As a result, an electromechanical layer 223a having a thickness of 10 to 30 μπι is deposited and grown on the non-mask region of the resist pattern 25. As the electrolytic copper plating method, for example, a known method using an acidic copper sulfate plating solution can be employed.
次に、 図 2 gに示すように、 レジストパターン 2 5を剥離する。 剥離液として は、 水酸化ナトリゥム水溶液や有機ァミン系水溶液を用いることができる。 次に、 図 2 hに示すように、 電気銅メツキ層 2 2 3 aに覆われていない無電解 銅メツキ層 2 2 2 aを除去する。 具体的には、 無電解銅メツキ層 2 2 2 aは、 た とえば、 過酸化水素と硫酸との混合水溶液、 または、 塩化第二銅水溶液などを用 いてエッチング除去する。 この際、 エッチング液は無電角军銅メツキ層 2 2 2 aの 露出部分と電気銅メツキ層 2 2 3 aとに同様に作用するが、 上述したように、 無 電解銅メツキ層 2 2 2 aの厚さが電気銅メツキ層 2 2 3 aのそれよりもずつと薄 いので、 先に無電解銅メツキ層 2 2 2 aの露出部分のみが消失する。 この結果、 無電解銅メツキ層 2 2 2 aと電気銅メツキ層 2 2 3 aとを有する配線パターン 2 2 aが絶縁層 2 1 aの表面 2 1 1 b上にパターン形成されることになる。 Next, as shown in FIG. 2g, the resist pattern 25 is peeled off. As the stripping solution, a sodium hydroxide aqueous solution or an organic amine-based aqueous solution can be used. Next, as shown in FIG. 2h, the electroless copper plating layer 222a that is not covered with the electrolytic copper plating layer 222a is removed. Specifically, the electroless copper plating layer 222a is etched away using, for example, a mixed aqueous solution of hydrogen peroxide and sulfuric acid, or an aqueous cupric chloride solution. At this time, the etchant acts in the same manner on the exposed portion of the electroless copper plating layer 222 a and the electroless copper plating layer 222 a, but as described above, the electroless copper plating layer 222 a Is thinner than that of the electroplated copper plating layer 2 23 a, only the exposed portions of the electroless copper plating layer 22 2 a disappear first. As a result, a wiring pattern 2 2 a having an electroless copper plating layer 2 2 2 a and an electric copper plating layer 2 2 3 a is formed on the surface 2 1 1 b of the insulating layer 2 1 a. .
次に、 図 2 c〜2 hに示す一連の工程を所定回数 （たとえば 6回） 繰り返す。 その結果、 図 2 iに示すように、 支持基板 1について、 ビア 2 3を介して相互に 電気的に接続された 6層の配線パターン 2 2 a〜2 2 f と 6層の絶縁層 2 1 a〜 2 1 f が形成される。 また、 前述したように、 図 2 c〜2 hの工程は他方の支持 基板 1 についても行われるから、 同様にその表面にも、 ビア 2 3 'を介して相 互に電気的に接続された 6層の配線パターン 2 2 a 一と 6層の絶縁層 2 1 a が 形成される。 なお、 無電解ニッケルメツキ層の形成は、 最内層の絶縁層 2 l a , 2 1 a 'のみでもよい。 Next, the series of steps shown in FIGS. 2c to 2h is repeated a predetermined number of times (for example, six times). As a result, as shown in FIG. 2i, for the support substrate 1, the six-layer wiring patterns 22a to 22f electrically connected to each other via the vias 23 and the six insulating layers 21 a to 21 f are formed. In addition, as described above, since the steps of FIGS. 2c to 2h are performed on the other support substrate 1, similarly, the surfaces thereof are also electrically connected to each other through vias 23 '. Six wiring patterns 22a and six insulating layers 21a are formed. The electroless nickel plating layer may be formed only on the innermost insulating layers 21a and 21a '.
その後、 同じく図 2 iに示すように、 最外層の絶縁層 2 l f ， 2 1 f 上にソ ルダレジストを印刷し、 露光処理、 現像処理および加熱硬化処理を施すことによ
り開口部 2 4 a， 2 4 a を有するオーバーコート層 2 4， 2 4 ,を形成する。 さらに、 配線パターン 2 2 f , 2 2 f 'において開口部 2 4 a， 2 4 a 'により 露出している部分には、 無電解ニッケルメツキ法により、 配線パターン 2 2 f , 2 2 f 上に厚さ 0 . 5〜2 mの無電解ニッケルメツキ層 （図示せず） を形成 する。 Then, as shown in Fig. 2i, a solder resist is printed on the outermost insulating layers 2lf and 21f, and is exposed, developed, and heat-cured. The overcoat layers 24, 24 having the openings 24a, 24a are formed. Further, the portions of the wiring patterns 22 f and 22 f ′ exposed by the openings 24 a and 24 a ′ are formed on the wiring patterns 22 f and 22 f by electroless nickel plating. An electroless nickel plating layer (not shown) having a thickness of 0.5 to 2 m is formed.
次に、 図 2 jに示すように、 絶縁シート 2 0， 2 0 'において絶縁層 2 1 a , 2 1 a 'として用いない支持基板 1， 1 からのはみ出し部 （すなわち、 縁部 2 0 a , 2 0 a ' ) を切断除去する。 これにより積層支持基板 1 0の積層状態が解 除され、 2つの中間製品としての多層配線基板 Y 1， が得られる。 なお、 縁部 2 0 a， 2 0 a 'の切断除去は、 支持基板 1， 1 'の一部の切断を伴っても よい。 Next, as shown in FIG. 2j, the portions protruding from the supporting substrate 1, 1 that are not used as the insulating layers 21a, 21a 'in the insulating sheets 20, 20' (that is, the edge 20a). , 20 a '). As a result, the laminated state of the laminated supporting substrate 10 is released, and the multilayer wiring substrate Y1, as two intermediate products, is obtained. The removal of the edges 20a, 20a 'by cutting may be accompanied by cutting of a part of the supporting substrates 1, 1'.
以降の各工程は、 多層配線基板 Y 1のみについて説明を行うが、 多層配線基板 Y 1 'についても同様である。 In the following steps, only the multilayer wiring board Y1 will be described, but the same applies to the multilayer wiring board Y1 '.
次の工程においては、 図 2 kに示すように、 支持基板 1の裏面 1 b上にエッチ ングパターン 2 6を形成する。 具体的には、 裏面 1 b上にドライフィルムレジス トをラミネートし、 所望のエッチングパターンに対応した露光処理および現像処 理を施すことにより当該ドライフィルムレジストをパターユングすることによつ て、 エッチングパターン 2 6を形成する。 ' 次に、 図 2 1に示すように、 エッチングにより支持基板 1に貫通孔 1 1を形成 する。 具体的には、 支持基板 1は、 たとえば、 塩化第二銅水溶液、 または、 過酸 化水素と硫酸の混合水溶液などのェポキシ樹脂は溶解させないエッチング液を用 いて除去する。 この結果、 支持基板 1に貫通孔 1 1が形成されることになる。 な お、 ビア 2 3は、 ビアホール 2 3 aの底に設けた無電解ニッケルメツキ層 2 2 1 a (図 2 h参照） 力 Sバリアメタルとなり、 エッチングされない。 In the next step, an etching pattern 26 is formed on the back surface 1b of the support substrate 1, as shown in FIG. 2k. Specifically, by laminating a dry film resist on the back surface 1b and performing exposure processing and development processing corresponding to a desired etching pattern, the dry film resist is patterned by etching. A pattern 26 is formed. 'Next, as shown in FIG. 21, a through hole 11 is formed in the support substrate 1 by etching. Specifically, the support substrate 1 is removed using an etchant that does not dissolve an epoxy resin such as an aqueous cupric chloride solution or a mixed aqueous solution of hydrogen peroxide and sulfuric acid. As a result, a through hole 11 is formed in the support substrate 1. The via 23 is an electroless nickel plating layer 22 1 a (see FIG. 2 h) provided at the bottom of the via hole 23 a (see FIG. 2 h). The via 23 is not etched.
次に、 図 2 mに示すように、 エッチングパターン 2 6を剥離する。 剥離液とし ては、 水酸化ナトリゥム水溶液や有機ァミン系水溶液を用いることができる。 次に、 図示していないが、 無電解金メッキ法により、 貫通孔 1 1を介して露出 する無電解ニッケルメツキ層 2 2 1 a上に厚さ 1〜5 μ πιの無電解金メツキ層を 形成する。 なお、 無電解金メッキ法における一連の処理としては、 公知の手法を
採用することができる。 Next, as shown in FIG. 2m, the etching pattern 26 is peeled off. As the stripping solution, an aqueous solution of sodium hydroxide or an aqueous solution of an organic amine can be used. Next, although not shown, an electroless gold plating layer having a thickness of 1 to 5 μππ is formed on the electroless nickel plating layer 22 a exposed through the through hole 11 by an electroless gold plating method. I do. In addition, as a series of processes in the electroless gold plating method, a known method is used. Can be adopted.
次に、 図 2 nに示すように、 I Cチップ 3のボール電極 3 1とビア 2 3とを無 電解金メツキ層 （図示せず） を介して導通するように、 支持基板 1の裏 S 1 b側 から貫通孔 1 1を介して I Cチップ 3を最内層の絶縁層 2 1 aの裏面 2 1 1 aに 実装する。 Next, as shown in FIG. 2n, the back surface S 1 of the support substrate 1 is connected to the ball electrode 31 of the IC chip 3 and the via 23 via an electroless gold plating layer (not shown). The IC chip 3 is mounted on the back surface 211 a of the innermost insulating layer 21 a via the through hole 11 from the b side.
次に、 同じく図 2 nに示すように、 貫通孔 1 1と I Cチップ 3との間に生じた 隙間に絶縁性樹脂を注入して絶縁封止部 3 2を形成することにより、 当該隙間を 封止する。 Next, as also shown in FIG. 2n, an insulating resin is injected into a gap formed between the through hole 11 and the IC chip 3 to form an insulating sealing portion 32. Seal.
最後に、 同じく図 2 nに示すように、 オーバーコート層 2 4上にキャパシタ 4 を搭載する。 その際、 オーバーコート層 2 4の開口部 2 4 aを介してキャパシタ 4の電極部 4 1が最外層の配線パターン 2 2 f と電気的に接合される。 これによ つて、 図 1に示したチップ搭載基板 X Iが作製される。 Finally, the capacitor 4 is mounted on the overcoat layer 24, as also shown in FIG. At this time, the electrode portion 41 of the capacitor 4 is electrically connected to the outermost wiring pattern 22 f via the opening 24 a of the overcoat layer 24. Thus, the chip mounting substrate XI shown in FIG. 1 is manufactured.
上述の多層配線基板 Y 1 , Y 1 'の形成方法として、 積層支持基板 1 0に対し て絶縁シート 2 0 , 2 0 'を用いて真空ラミネートを施した後、 図 3に示したよ うに、 絶縁シート 2 0 , 2 0 'の縁部 2 0 a， 2 0 a '上に金属メッキ膜 5 0を 形成してから図 2 c〜2 hまでの各工程を行うようにしてもよレ、。 この金属メッ キ膜 5 0により、 ビルドアップ積層体 2の積層数が多く、 ビア 2 3の形成時に行 われるデスミア処理が多数回繰り返される場合においても、 金属メツキ膜 5 0に より縁部 2 0 a， 2 0 a が保護されるため、 縁部 2 0 a， 2 0 a 一における破 れゃ穴などの発生をより効果的に防ぐことができる。 なお、 金属メツキ膜 5 0の 構成材料としては、 銅ゃュッケルなどが挙げられる。 As a method of forming the above-mentioned multilayer wiring substrates Y 1 and Y 1 ′, the laminated support substrate 10 is subjected to vacuum lamination using insulating sheets 20 and 20 ′, and then, as shown in FIG. After forming the metal plating film 50 on the edges 20a and 20a 'of the sheets 20 and 20', the steps from Fig. 2c to 2h may be performed. The metal plating film 50 enables the edge portion 20 to be formed by the metal plating film 50 even when the number of build-up laminates 2 is large and the desmearing process performed when forming the via 23 is repeated many times. Since a and 20a are protected, it is possible to more effectively prevent the occurrence of broken holes or the like at the edges 20a and 20a. In addition, as a constituent material of the metal plating film 50, a copper rack or the like can be used.
金属メツキ膜 5 0は、 図 2 d〜 2 f に示したような無電解銅メツキと電気銅メ ツキを行う際に、縁部 2 0 a , 2 0 a 'に対しても同じ処理にて形成してもよい。 このようにすることにより、 金属メツキ膜 5 0を形成するために別工程を設ける 必要がなく、 作業効率が向上する。 When performing the electroless copper plating and the electrolytic copper plating as shown in FIGS. 2 d to 2 f, the metal plating film 50 is subjected to the same processing for the edges 20 a and 20 a ′. It may be formed. By doing so, it is not necessary to provide a separate step for forming the metal plating film 50, and the working efficiency is improved.
また、 上述の金属メツキ膜 5 0の構成材料を銅とした場合、 図 4に示したよう に、 当該金属メツキ膜 5 0上に、 さらに保護膜 5 1を形成してから図 2 c〜 2 h までの各工程を行うようにしてもよい。 この保護膜 5 1を設けたことにより、 ビ ルドアップ積層体 2の積層数が多く、 ビア 2 3の形成時に行われるシード層 （無
電解銅メツキ膜） のエッチング除去が多数回繰り返される場合においても金属メ ツキ膜 5 0がエッチング除去されるのを防ぐことができ、 ひいては縁部 2 0 a , 2 0 a 'における破れや穴などの発生をより効果的に防ぐことができる。 なお、 保護膜 5 1の構成材料としては、 ポリテトラフルォロエチレンやポリプロピレン などが挙げられる。 Further, when the constituent material of the metal plating film 50 is copper, as shown in FIG. 4, a protective film 51 is further formed on the metal plating film 50, and then, as shown in FIGS. Each step up to h may be performed. By providing this protective film 51, the number of build-up laminates 2 is large, and the seed layer (non- Even if the etching removal of the electrolytic copper plating film) is repeated many times, the metal plating film 50 can be prevented from being removed by etching, and as a result, tears or holes at the edges 20a and 20a 'can be prevented. Can be more effectively prevented. In addition, as a constituent material of the protective film 51, polytetrafluoroethylene, polypropylene, or the like can be used.
上述のチップ搭載基板 X 1は、 支持基板 1， 1 を 2枚積層した積層支持基板 1 0を用いて作製された力 S、 1枚の支持基板 1にビルドアップ積層体 2を形成し、 I Cチップ 3およびキャパシタ 4を搭載することにより作製してもよい。 また、 I Cチップ 3とキャパシタ 4の搭載位置を入れ換えてもよレ、。 さらに、 I Cチッ プ 3もしくはキャパシタ 4を貫通孔 1 1を介してビルドアップ積層体 2に搭載し た後、 支持基板 1の裏面 1 bと I Cチップ 3もしくはキャパシタ 4とを、 さらに 研磨する工程を設けてもよい。 The above-mentioned chip mounting substrate X1 is composed of a force S produced using a laminated supporting substrate 10 in which two supporting substrates 1 and 1 are laminated, a build-up laminate 2 formed on one supporting substrate 1, and an IC It may be manufactured by mounting the chip 3 and the capacitor 4. Also, the mounting positions of the IC chip 3 and the capacitor 4 may be interchanged. Further, after mounting the IC chip 3 or the capacitor 4 on the build-up laminate 2 through the through-hole 11, a step of further polishing the back surface 1 b of the support substrate 1 and the IC chip 3 or the capacitor 4 is performed. It may be provided.
上述のチップ搭載基板 X 1の製造においては、 図 2 c〜図 2 hを参照して、 セ ミアディティブ法により配線パターン 2 2 a , 2 2 a 'を形成する手法を説明し たが、 本発明では、 配線パターン 2 2 a , 2 2 a 'の形成において公知のサブト ラクティブ法またはフルアディティブ法を採用してもよレ、。 In the manufacture of the above-mentioned chip mounting substrate X1, a method of forming the wiring patterns 22a and 22a 'by the semi-additive method has been described with reference to FIGS. 2c to 2h. In the present invention, a known subtractive method or a fully additive method may be employed in forming the wiring patterns 22a and 22a '.
以上に説明した製造方法により形成されたチップ搭載基板 X Iは、 I Cチップ 3とキャパシタ 4との距離を短くすることができる。 これにより、 インダクタン スを低減することができ、 ノイズの発生を抑制することができる。 In the chip mounting substrate XI formed by the above-described manufacturing method, the distance between the IC chip 3 and the capacitor 4 can be reduced. Thereby, inductance can be reduced and generation of noise can be suppressed.
上記製造方法によれば、 支持基板 1の表面 1 aにビルドアップ積層体 2を形成 した後に I Cチップ 3の搭載を行うことができるので、 ビルドアップ積層体 2と I Cチップ 3との電気的導通を図るための位置合わせは比較的容易に行うことが できる。 また、 ビルドアップ積層体 2の形成後に I Cチップ 3の搭載を行うこと ができるので、 ビルドアップ積層体 2が適正に形成されたことを確認してから I Cチップ 3を搭載すればよいから I Cチップ 3を無駄にすることがなく、 実用性 に優れている。 さらに、 支持基板 1は、 I Cチップ 3の搭載領域のみを除去する ことにより貫通孔 1 1を形成する。 そのため、 支持基板 1の残りの部分がステフ ナと同様の役割を果たすことになり、 実装やその他のハンドリングを行うのに充 分な剛性を有している。 したがって、 別途剛性付与を行う工程を設ける必要がな
く、 作業効率的にも優れている。 According to the above manufacturing method, since the IC chip 3 can be mounted after the build-up laminate 2 is formed on the surface 1 a of the support substrate 1, the electrical continuity between the build-up laminate 2 and the IC chip 3 is achieved. Alignment for achieving alignment can be performed relatively easily. Also, since the IC chip 3 can be mounted after the build-up laminate 2 is formed, the IC chip 3 can be mounted after confirming that the build-up laminate 2 has been properly formed. It is excellent in practicality without wasting 3. Further, the support substrate 1 forms a through hole 11 by removing only the mounting area of the IC chip 3. Therefore, the remaining portion of the support substrate 1 plays a role similar to that of the stiffener, and has sufficient rigidity for mounting and other handling. Therefore, there is no need to provide a separate process for imparting rigidity. And work efficiency is excellent.
2枚の支持基板 1 , 1 ' を積層し、 積層支持基板 1 0としてビルドアップ積層 体 2 , 2 'の形成を行うことにより、 ビルドアップ積層体 2， 2 'や支持基板 1 , \ ' に熱がかかる際、 両者の熱膨張率の差に起因して生じる反りを緩和すること ができる。 すなわち、 2枚の支持基板 1， 1 ' の裏面同士を仮接合することによ つて、 一方の支持基板 1と当該支持基板の表面に形成されたビルドアップ積層体 2との熱膨張率の差に起因する反りが生じたとしても、 この反りとは正反対に、 他方の支持基板 1 ' と当該他方の支持基板の表面に形成されたビルドアップ積層 体 2 'との熱膨張率の差に起因する反りが生じ、互いに相殺しあう。 これにより、 実装信頼性が向上する。 By laminating the two support substrates 1 and 1 ′ and forming the build-up laminates 2 and 2 ′ as the laminated support substrate 10, the build-up laminates 2 and 2 ′ and the support substrates 1 and \ ′ are formed. When heat is applied, the warpage caused by the difference between the two coefficients of thermal expansion can be reduced. That is, by temporarily joining the back surfaces of the two support substrates 1 and 1 ′, the difference in the coefficient of thermal expansion between one support substrate 1 and the build-up laminate 2 formed on the surface of the support substrate is determined. Even if the warpage caused by the above occurs, the warpage is opposite to the warpage due to the difference in thermal expansion coefficient between the other support substrate 1 ′ and the build-up laminate 2 ′ formed on the surface of the other support substrate. Warping occurs and offset each other. Thereby, mounting reliability is improved.
貫通孔 1 1を介して搭載された I Cチップ 3と、 貫通孔 1 1およびビルドアッ プ積層体 2との間に生じる隙間を絶縁性樹脂で封止することにより、 各配線間の 絶縁性が向上するのに加え、 I Cチップ 3の搭載状態における安定度が増す。 そ のため、 I Cチップ 3とビルドアップ積層体 2との間の電気的接続についてより 高い信頼性を達成することができる。 また、 貫通孔 1 1を介して I Cチップ 3も しくはキャパシタ 4をビルドアップ積層体 2に搭載した後、 支持基板 1の裏面 1 bと、 I Cチップ 3もしくはキャパシタ 4をさらに研磨することにより、 チップ 搭載基板 X 1全体の薄肉化を図ることができる。 The gap between the IC chip 3 mounted through the through-hole 11 and the through-hole 11 and the build-up laminate 2 is sealed with insulating resin to improve the insulation between wirings. In addition, the stability of the mounted state of the IC chip 3 is increased. Therefore, higher reliability of the electrical connection between the IC chip 3 and the build-up laminate 2 can be achieved. Also, after mounting the IC chip 3 or the capacitor 4 on the build-up laminate 2 through the through hole 11, the back surface 1 b of the support substrate 1 and the IC chip 3 or the capacitor 4 are further polished, The thickness of the entire chip mounting substrate X1 can be reduced.
次に、 本発明を、 実施例をもとに具体的に説明する。 Next, the present invention will be specifically described based on examples.
〔実施例 1.〕 (Example 1.)
(チップ搭載基板の作製） (Production of chip mounting board)
支持基材として厚さ 0 . 5 mmであってサイズ 1 5 0 X 1 5 O mmの 2枚の銅 板を用意し、 それぞれビルドァップ積層体を形成する表面を脱脂 ·酸処理および C Z処理を施した。 その後、 2枚の銅板の各裏面同士が対向するように重ねたも のを、 厚さ 5 0 μ πιであってサイズ 2 0 0 X 2 0 O mmのエポキシ樹脂シート （ 商品名 ： S H— 9、 味の素製） 2枚で挟み込み、 真空ラミネータを用いて 1 3 0 °Cで 2分間圧着した。 さらに、 1 7 0 °Cで 3 0分間、 ラミネートすることにより 各銅板の表面に、 絶縁層を形成した。
次に、 炭酸ガスレーザを用いて各絶縁層にビアホール （直径 5 0 /z m) を所定 箇所に形成してデスミア処理を行った。 次に、 各ビアホールの底に厚さ 1 μ πιの 無電解ニッケル層を形成した。 次に、 各絶縁層および各無電解-ッケル層上に厚 さ 0 . 3 μ mの無電解銅メッキ層を形成した。 次に、 各無電解銅メッキ層上にド ライフイルムレジス ト （商品名： R Y— 3 0 4 0、 日立化成製） を所定のパター ンで形成し、 これをマスクとしつつ、 先に形成された無電解鲖メツキ層を通電層 として、 電気銅メツキ層を形成した。 ドライフィルムレジストを剥離した後、 そ れまでドライフィルムレジストにより被覆されていた無電解銅メッキ膜をェッチ ング除去した。 その後、 1 7 0 °Cで 6◦分間加熱することにより配線パターンぉ よびビアを形成した。 以降、 上述の、 絶縁層を形成する工程から配線パターンお よびビアを形成する工程までの一連の工程を 4回繰り返し行うことにより、 5層 の配線構造を形成した。 Two copper plates of 0.5 mm thick and 150 x 150 mm were prepared as a supporting base material, and the surfaces forming the build-up laminate were subjected to degreasing, acid treatment and CZ treatment, respectively. did. Then, the two copper plates were stacked so that their back surfaces face each other. An epoxy resin sheet with a thickness of 50 μππι and a size of 200 × 200 mm (Product name: SH-9) , Made of Ajinomoto) and pressed at 130 ° C for 2 minutes using a vacuum laminator. Furthermore, an insulating layer was formed on the surface of each copper plate by laminating at 170 ° C. for 30 minutes. Next, via holes (diameter 50 / zm) were formed in predetermined positions in each insulating layer using a carbon dioxide laser, and desmearing was performed. Next, an electroless nickel layer having a thickness of 1 μππ was formed at the bottom of each via hole. Next, an electroless copper plating layer having a thickness of 0.3 μm was formed on each insulating layer and each electroless nickel layer. Next, a dry film resist (trade name: RY-340, manufactured by Hitachi Chemical) is formed on each electroless copper plating layer with a predetermined pattern. The electroless copper plating layer was formed using the electroless plating layer as a current-carrying layer. After removing the dry film resist, the electroless copper plating film that had been covered with the dry film resist was removed by etching. Thereafter, the wiring pattern and the via were formed by heating at 170 ° C. for 6 ° minutes. Thereafter, the above-described series of steps from the step of forming the insulating layer to the step of forming the wiring pattern and the via was repeated four times to form a five-layer wiring structure.
次に、 スクリーン印刷およびフォトリソグラフィにより、 5層からなる配線構 造にオーバーコート層を積層形成した。 オーバーコート層の所定箇所には、 最後 に形成された配線パターンの一部が臨めるように開口部を設けた。 次に、 当該開 口部から臨む配線パターン上に厚さ 1 mの無電解ニッケル層を形成し、 続いて 厚さ 3 mの金メツキ層を形成することにより、 外部端子との接続を図るための ランド電極を形成した。 ここで形成されたランド電極は、 後に搭載されるキャパ シタの導電連絡部配置に対応して配置している。 Next, an overcoat layer was laminated on the five-layer wiring structure by screen printing and photolithography. An opening was provided at a predetermined position of the overcoat layer so that a part of the wiring pattern formed last could be seen. Next, a 1-m-thick electroless nickel layer is formed on the wiring pattern facing the opening, followed by a 3-m-thick gold plating layer to establish connection with external terminals. A land electrode was formed. The land electrodes formed here are arranged corresponding to the arrangement of the conductive connecting portions of the capacitor to be mounted later.
次に、 絶縁層を構成せず、 銅板の表面に形成されたビルドアップ積層体からは み出しているエポキシ樹脂シートを切断除去することにより、 2枚の銅板の積層 状態を解除した。 Next, the laminated state of the two copper plates was released by cutting and removing the epoxy resin sheet protruding from the build-up laminate formed on the surface of the copper plate without forming an insulating layer.
次に、 銅板の裏面にドライフィルムレジスト （商品名 ： N I T— 5 0、 日合モ 一トン製） を所定のパターンで形成し、 これをマスクとしつつ、 エッチング液と して塩化第 2銅水溶液 （関東化学製） を用いて、 銅板をエッチングし、 貫通孔を 形成した。 このとき、 ビアは、 ビアホールの底に形成した無電解ニッケル層がバ リアメタルとなりエッチングされなかった。 ドライフィルムレジストを剥離した 後、 当該貫通孔から臨むビアの無電解-ッケル層上に、 厚さ 3 i mの金メッキ層 を形成することにより、 外部端子との接続を図るためのランド電極を形成した。
ここで形成されたランド電極は、 後に搭載される I Cチップの電極配置に対応し て配置している。 Next, a dry film resist (trade name: NIT-50, manufactured by Nichigo Moton Co., Ltd.) is formed in a predetermined pattern on the back surface of the copper plate. (Kanto Kagaku) was used to etch the copper plate to form through holes. At this time, the via was not etched because the electroless nickel layer formed at the bottom of the via hole became a barrier metal. After stripping the dry film resist, a land electrode for connection with external terminals was formed by forming a 3 im thick gold plating layer on the electroless nickel layer of the via facing the through hole. . The land electrodes formed here are arranged corresponding to the electrode arrangement of the IC chip to be mounted later.
次に、 パッケージサイズに切断した後、 厚さ 0 . 5 mmの I Cチップは、 前記 貫通孔に収納するような形でランド電極を介してハンダ接合によりビルドアップ 積層体に搭載された。 次に、 I Cチップと貫通孔との間に生じた隙間をエポキシ 樹脂 （商品名 ： U 8 4 3 4— 6、 ナミックス製） で封止した。 また、 キャパシタ は、 ランド電極を介してハンダ接合によりビルドアップ積層体に搭載された。 Next, after cutting to a package size, the IC chip having a thickness of 0.5 mm was mounted on the build-up laminate by solder bonding via land electrodes in such a manner as to be housed in the through hole. Next, the gap created between the IC chip and the through-hole was sealed with epoxy resin (trade name: U84434-6, manufactured by Namics). The capacitor was mounted on the build-up laminate by solder bonding via the land electrode.
〔実施例 2〕 (Example 2)
(チップ搭載基板の作製） (Production of chip mounting board)
支持基材として厚さ 0 . 3 mmであってサイズ 1 5 0 X 1 5 0 mmの 2枚のス テンレス板を用意し、 それぞれビルドアップ積層体を形成する表面を脱脂 ·酸処 理および表面粗化処理を施した。 その後、 2枚のステンレス板の各裏面同士が対 向するように重ねたものを、 厚さ 5 0 μ mであってサイズ 2 0 0 X 2 0 O mmの エポキシ樹脂シート （商品名 ： S H— 9、 味の素製） 2枚で挟み込み、 真空ラミ ネータを用いて 1 3 0 °Cで 2分間圧着した。 さらに、 1 7 0 °Cで 3 0分間、 ラミ ネートすることにより各ステンレス板の表面に、 絶縁層を形成した。 Prepare two stainless steel plates with a thickness of 0.3 mm and a size of 150 x 150 mm as a supporting substrate, and degrease and acid-treat the surface that forms the build-up laminate, respectively. A roughening treatment was performed. After that, two stainless steel plates were stacked so that the back sides face each other, and a 50 μm thick epoxy resin sheet of size 200 × 200 mm (trade name: SH— 9, made by Ajinomoto Co., Ltd.) and pressed at 130 ° C for 2 minutes using a vacuum laminator. Further, an insulating layer was formed on the surface of each stainless steel plate by laminating at 170 ° C. for 30 minutes.
次に、 炭酸ガスレーザを用いて各絶縁層にビアホール （直径 5 0 μ πι) を所定 箇所に形成してデスミア処理を行った。 次に、 各ビアホールの底に厚さ 1 μ πιの 無電解ニッケル層を形成した。 次に、 各絶縁層おょぴ各無電解ニッケル層上に厚 さ 0 . 3 μ πιの無電解銅メツキ層を形成した。 また、 同時的に、 各エポキシ樹脂 シートの縁部 （絶縁層以外の部分） 上にも無電解鲖メツキを行い、 膜厚◦. 3 μ mの金属メツキ膜を形成した。 次に、 各無電解銅メツキ層上にドライフィルムレ ジスト （商品名 ： R Y—3 2 4 0、 日立化成製） を所定のパターンで形成し、 こ れをマスクとしつつ、 先に形成された無電解銅メツキ層を通電層として、 電気銅 メツキ層を形成した。 ドライフィルムレジス トを剥離した後、 それまでドライフ イルムレジストにより被覆されていた無電解銅メツキ膜をエッチング除去した。 その後、 1 7 0 °Cで 6 0分間加熱することにより配線パターンおよびビアを形成 した。 以降、 上述の、 絶縁層を形成する工程から配線パターンおよびビアを形成
する工程までの一連の工程を 4回繰り返し行うことにより、 5層の配線構造を形 成し 7こ。 Next, via holes (diameter: 50 μπι) were formed in predetermined positions in each insulating layer using a carbon dioxide laser, and desmearing was performed. Next, an electroless nickel layer having a thickness of 1 μππ was formed at the bottom of each via hole. Next, an electroless copper plating layer having a thickness of 0.3 μππ was formed on each insulating layer and each electroless nickel layer. At the same time, electroless plating was also performed on the edge (the portion other than the insulating layer) of each epoxy resin sheet to form a metal plating film having a thickness of 3 μm. Next, a dry film resist (trade name: RY-3240, manufactured by Hitachi Chemical) was formed in a predetermined pattern on each electroless copper plating layer. The electroless copper plating layer was formed using the electroless copper plating layer as a current-carrying layer. After peeling off the dry film resist, the electroless copper plating film that had been covered with the dry film resist was removed by etching. Thereafter, by heating at 170 ° C. for 60 minutes, a wiring pattern and a via were formed. Thereafter, a wiring pattern and a via are formed from the step of forming the insulating layer described above. By repeating the series of steps up to the four steps four times, a five-layer wiring structure was formed.
次に、 スクリーン印刷およびフォトリソグラフィにより、 5層からなる配線構 造にオーバーコート層を積層形成した。 オーバーコート層の所定箇所には、 最後 に形成された配線パターンの一部が臨めるように開口部を設けた。 次に、 当該開 口部から臨む配線パターン上に厚さ 1 μ πιの無電解ニッケル層を形成し、 続いて 厚さ の金メツキ層を形成することにより、 外部端子との接続を図るための ランド電極を形成した。 ここで形成されたランド電極は、 後に搭載されるキャパ シタの導電連絡部配置に対応して配置している。 Next, an overcoat layer was laminated on the five-layer wiring structure by screen printing and photolithography. An opening was provided at a predetermined position of the overcoat layer so that a part of the wiring pattern formed last could be seen. Next, an electroless nickel layer having a thickness of 1 μππ is formed on the wiring pattern facing the opening, and then a gold plating layer having a thickness is formed. A land electrode was formed. The land electrodes formed here are arranged corresponding to the arrangement of the conductive connecting portions of the capacitor to be mounted later.
次に、 絶縁層を構成せず、 ステンレス板の表面に形成されたビルドアップ積層 体からはみ出しているエポキシ樹脂シートを切断除去することにより、 2枚のス テンレス板の積層状態を解除した。 Next, the laminated state of the two stainless steel plates was released by cutting and removing the epoxy resin sheet protruding from the build-up laminate formed on the surface of the stainless steel plate without forming an insulating layer.
次に、 ステンレス板の裏面にドライフィルムレジスト （商品名： N I Τ - 4 0、 日合モートン製） を所定のパターンで形成し、 これをマスクとしつつ、 エツチン グ液を用いて、 ステンレス板をエッチングし、 貫通孔を形成した。 なお、 当該ェ ツチング液は、 5 0 w t %の塩化第 2鉄と、 6 3 w t %の硝酸と、 3 6 w t %の 塩酸とを 3 : 1 : 3 (=塩化第 2鉄：硝酸：塩酸） の割合で混合した混合液であ る。 このとき、 ビアは、 ビアホールの底に形成した無電解ニッケル層がバリアメ タルとなりエッチングされなかった。 ドライフィルムレジストを剥離した後、 当 該貫通孔から臨むビアの無電解ニッケル層上に、 厚さ 3 μ ηιの金メッキ層を形成 することにより、 外部端子との接続を図るためのランド電極を形成した。 ここで 形成されたランド電極は、 後に搭載される I Cチップの電極配置に対応して配置 している。 Next, a dry film resist (trade name: NI 4-40, manufactured by Nichigo Morton) is formed on the back surface of the stainless steel plate in a predetermined pattern, and using the mask as a mask, the stainless steel plate is etched using an etching solution. Etching was performed to form through holes. The etching solution was prepared by mixing 50 wt% of ferric chloride, 63 wt% of nitric acid, and 36 wt% of hydrochloric acid in a ratio of 3: 1: 3 (= ferric chloride: nitric acid: hydrochloric acid). This is a mixed solution mixed in the ratio of At this time, the via was not etched because the electroless nickel layer formed at the bottom of the via hole became a barrier metal. After stripping the dry film resist, a land electrode for connection with external terminals is formed by forming a gold plating layer with a thickness of 3 μηι on the electroless nickel layer of the via facing the through hole. did. The land electrodes formed here are arranged corresponding to the electrode arrangement of an IC chip to be mounted later.
次に、 パッケージサイズに切断した後、 厚さ 0 . 3 mmの I Cチップは、 前記 貫通孔に収納するような形でランド電極を介してハンダ接合によりビルドアップ 積層体に搭載された。 次に、 I Cチップと貫通孔との間に生じた隙間をエポキシ 樹脂 （商品名： U 8 4 3 4— 6、 ナミックス製） で封止した。 また、 キャパシタ は、 ランド電極を介してハンダ接合によりビルドアップ積層体に搭載された。 以上に説明したように、 本発明によると I Cチップとビルドアップ積層体との
位置合わせが比較的容易で、 ビルドアップ積層体の歩留まりに起因する I cチッ プの無駄の発生が抑制されるのに加え、 別途剛性付与することなく、 効率的に、 実装性に優れたチップ搭載基板の製造が行える。 また、 製造されたチップ搭載基 板は、 I Cチップとキャパシタとの間の距離が小さいためインダクタンスが小さ くなり、 ノイズが低減される。
Next, after being cut to a package size, the IC chip having a thickness of 0.3 mm was mounted on the build-up laminate by soldering via land electrodes in such a manner as to be housed in the through hole. Next, the gap created between the IC chip and the through-hole was sealed with epoxy resin (trade name: U84434-6, manufactured by Namics). The capacitor was mounted on the build-up laminate by solder bonding via the land electrode. As described above, according to the present invention, the IC chip and the build-up A chip that is relatively easy to align, suppresses waste of Ic chips due to the yield of the build-up laminate, and is efficient and has excellent mountability without additional rigidity. The mounting substrate can be manufactured. In addition, the manufactured chip mounting board has a small inductance due to a small distance between the IC chip and the capacitor, thereby reducing noise.
Claims
1 . 金属製の支持基板の表面に、 ビルドアップ絶縁層およびビルドアップ配線パ ターンを交互に形成するビルドァップ積層工程と、 1. A build-up laminating step of alternately forming build-up insulating layers and build-up wiring patterns on the surface of a metal support substrate;
前記支持基板の電子部品を載置する位置に貫通孔を形成して、 最内層のビル ドアップ絶縁層を露出させる孔形成工程と、 A hole forming step of forming a through hole at a position where the electronic component is mounted on the support substrate, and exposing an innermost build-up insulating layer;
前記支持基板の前記貫通孔を介して前記最内層のビルドアップ絶縁層に電子 部品を実装する実装工程とを含む、 電子部品搭載基板の製造方法。 A mounting step of mounting an electronic component on the innermost build-up insulating layer through the through hole of the support substrate.
2 . 前記実装工程の後に前記貫通孔において前記電子部品の周りに生じる隙間を 絶縁性樹脂で封止する封止工程をさらに含む、 請求項 1に記載の製造方法。 2. The manufacturing method according to claim 1, further comprising a sealing step of sealing a gap generated around the electronic component in the through hole after the mounting step with an insulating resin.
3 . 前記ビルドアップ積層工程の前に 2枚の支持基板の裏面同士を仮接合する仮 接合工程をさらに含み、 前記ビルドアップ積層工程の後で前記孔形成工程の前に 両支持基板を分離する分離工程をさらに含み、 前記ビルドアップ積層工程は各支 持基板の表面に対して行われる、 請求項 1に記載の製造方法。 3. The method further includes a temporary bonding step of temporarily bonding the back surfaces of the two support substrates before the build-up lamination step, and separating the two support substrates after the build-up lamination step and before the hole forming step. The manufacturing method according to claim 1, further comprising a separation step, wherein the build-up lamination step is performed on a surface of each support substrate.
4 . 前記仮接合工程は、 各支持基板の外周部からはみ出す大きさの 2枚の樹脂シ ートの間に前記両支持基板を挟み、 両樹脂シートを加熱下で真空ラミネートする ことにより行う、 請求項 3に記載の製造方法。 4. The temporary joining step is performed by sandwiching the two support substrates between two resin sheets having a size protruding from the outer peripheral portion of each support substrate, and vacuum laminating the two resin sheets under heating. The production method according to claim 3.
5 . 前記仮接合工程の後に前記両樹脂シートの少なくともはみ出し部に金属メッ キ膜を形成するメツキ工程をさらに含んでいる、 請求項 4に記載の製造方法。 5. The manufacturing method according to claim 4, further comprising a plating step of forming a metal plating film on at least the protruding portions of the two resin sheets after the temporary joining step.
6 . 前記金属メッキ膜は、 前記最内層のビルドアップ絶縁層に対する配線パタ一 ンと同時に形成される、 請求項 5に記載の製造方法。 6. The manufacturing method according to claim 5, wherein the metal plating film is formed simultaneously with a wiring pattern for the innermost build-up insulating layer.
7 . 前記メツキ工程の後に前記金属メツキ膜上に当該金属メツキ膜とは異なる材 料の保護膜を形成する膜形成工程をさらに含んでいる、 請求項 5に記載の製造方
法 7. The method according to claim 5, further comprising a film forming step of forming a protective film of a material different from the metal plating film on the metal plating film after the plating step. Law
8 . 金属製の支持基板と、 8. A metal support substrate,
当該支持基板の表面にビルドアップ絶縁層およびビルドアップ配線パターン を交互に形成してなるビルドアップ積層体と、 A build-up laminate formed by alternately forming build-up insulating layers and build-up wiring patterns on the surface of the support substrate;
当該ビノレドアップ積層体に搭載された電子部品と、 を備えた電子部品搭載基 板であって、 An electronic component mounted on the vinoredo-up laminate, and an electronic component mounting board comprising:
前記支持基板は、 前記電子部品を載置する位置に貫通孔を有しており、 前記電子部品は、 前記支持基板の前記貫通孔を介して最内層のビルドアップ 絶縁層におけるビルドアップ配線パターンが形成されていなレ、裏面に搭載されて いることを特徴とする、 電子部品搭載基板。 The support substrate has a through-hole at a position where the electronic component is placed, and the electronic component has a build-up wiring pattern in an innermost layer of the insulating layer through the through-hole of the support substrate. An electronic component mounting substrate, wherein the substrate is not formed and is mounted on the back surface.
9 . 前記貫通孔において前記電子部品の周りに生じる隙間は絶縁性榭脂で封止さ れている、 請求項 8に記載の電子部品搭載基板。 9. The electronic component mounting board according to claim 8, wherein a gap generated around the electronic component in the through hole is sealed with an insulating resin.
10. 前記電子部品は I Cチップであり、 最外層のビルドアップ絶縁層におけるビ ルドアップ配線パターンが形成された表面にキャパシタが搭載されている、 請求 項 8に記載の電子部品搭載基板。
10. The electronic component mounting board according to claim 8, wherein the electronic component is an IC chip, and a capacitor is mounted on a surface of the outermost build-up insulating layer on which a build-up wiring pattern is formed.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004566275A JP3999784B2 (en) | 2003-01-16 | 2003-01-16 | Manufacturing method of electronic component mounting board |
| PCT/JP2003/000326 WO2004064150A1 (en) | 2003-01-16 | 2003-01-16 | Method for manufacturing electronic component mount board and electronic mount board manufactured by this method |
| TW092101273A TW566065B (en) | 2003-01-16 | 2003-01-21 | Method of making electronic component-mounted substrate, and chip-mounted substrate made by using the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2003/000326 WO2004064150A1 (en) | 2003-01-16 | 2003-01-16 | Method for manufacturing electronic component mount board and electronic mount board manufactured by this method |
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| WO2004064150A1 true WO2004064150A1 (en) | 2004-07-29 |
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| PCT/JP2003/000326 WO2004064150A1 (en) | 2003-01-16 | 2003-01-16 | Method for manufacturing electronic component mount board and electronic mount board manufactured by this method |
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| Country | Link |
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| JP (1) | JP3999784B2 (en) |
| TW (1) | TW566065B (en) |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006066522A (en) * | 2004-08-25 | 2006-03-09 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
| JP2007266443A (en) * | 2006-03-29 | 2007-10-11 | Shinko Electric Ind Co Ltd | Manufacturing method of wiring substrate and manufacturing method of semiconductor device |
| JP2008198846A (en) * | 2007-02-14 | 2008-08-28 | Fujitsu Ltd | Multilayer wiring board and its manufacturing method |
| JP2009224415A (en) * | 2008-03-13 | 2009-10-01 | Ngk Spark Plug Co Ltd | Method of manufacturing multilayer wiring board, and intermediate product of multilayer wiring board, |
| JP2009278060A (en) * | 2008-05-13 | 2009-11-26 | Samsung Electro-Mechanics Co Ltd | Printed circuit board and manufacturing method thereof |
| JP2010114291A (en) * | 2008-11-07 | 2010-05-20 | Renesas Technology Corp | Electronic component having shield, and method for manufacturing the same |
| JP2011138868A (en) * | 2009-12-28 | 2011-07-14 | Ngk Spark Plug Co Ltd | Multilayer wiring substrate |
| TWI393231B (en) * | 2008-05-21 | 2013-04-11 | Unimicron Technology Corp | Substrate having semiconductor chip embedded therein and fabrication method thereof |
| JP2013093623A (en) * | 2013-02-18 | 2013-05-16 | Shinko Electric Ind Co Ltd | Semiconductor package |
| JP2018098491A (en) * | 2016-12-16 | 2018-06-21 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Printed circuit board, package and manufacturing method of printed circuit board |
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| TWI407870B (en) * | 2006-04-25 | 2013-09-01 | Ngk Spark Plug Co | Method for manufacturing wiring board |
| JP2015065400A (en) * | 2013-09-25 | 2015-04-09 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Element embedded printed circuit board and method of manufacturing the same |
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| US6031284A (en) * | 1997-03-14 | 2000-02-29 | Lg Semicon Co., Ltd. | Package body and semiconductor chip package using same |
| US20020001937A1 (en) * | 2000-06-30 | 2002-01-03 | Nec Corporation | Semiconductor package board using a metal base |
| JP2002026171A (en) * | 2000-07-06 | 2002-01-25 | Sumitomo Bakelite Co Ltd | Method for producing multilayer wiring board and multilayer wiring board |
| JP2002319760A (en) * | 2001-04-20 | 2002-10-31 | Ngk Spark Plug Co Ltd | Method for manufacturing wiring board |
-
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- 2003-01-16 JP JP2004566275A patent/JP3999784B2/en not_active Expired - Fee Related
- 2003-01-16 WO PCT/JP2003/000326 patent/WO2004064150A1/en active Application Filing
- 2003-01-21 TW TW092101273A patent/TW566065B/en not_active IP Right Cessation
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6031284A (en) * | 1997-03-14 | 2000-02-29 | Lg Semicon Co., Ltd. | Package body and semiconductor chip package using same |
| US20020001937A1 (en) * | 2000-06-30 | 2002-01-03 | Nec Corporation | Semiconductor package board using a metal base |
| JP2002026171A (en) * | 2000-07-06 | 2002-01-25 | Sumitomo Bakelite Co Ltd | Method for producing multilayer wiring board and multilayer wiring board |
| JP2002319760A (en) * | 2001-04-20 | 2002-10-31 | Ngk Spark Plug Co Ltd | Method for manufacturing wiring board |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006066522A (en) * | 2004-08-25 | 2006-03-09 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
| JP4528062B2 (en) * | 2004-08-25 | 2010-08-18 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| JP2007266443A (en) * | 2006-03-29 | 2007-10-11 | Shinko Electric Ind Co Ltd | Manufacturing method of wiring substrate and manufacturing method of semiconductor device |
| JP2008198846A (en) * | 2007-02-14 | 2008-08-28 | Fujitsu Ltd | Multilayer wiring board and its manufacturing method |
| JP2009224415A (en) * | 2008-03-13 | 2009-10-01 | Ngk Spark Plug Co Ltd | Method of manufacturing multilayer wiring board, and intermediate product of multilayer wiring board, |
| JP2009278060A (en) * | 2008-05-13 | 2009-11-26 | Samsung Electro-Mechanics Co Ltd | Printed circuit board and manufacturing method thereof |
| TWI393231B (en) * | 2008-05-21 | 2013-04-11 | Unimicron Technology Corp | Substrate having semiconductor chip embedded therein and fabrication method thereof |
| JP2010114291A (en) * | 2008-11-07 | 2010-05-20 | Renesas Technology Corp | Electronic component having shield, and method for manufacturing the same |
| US9001528B2 (en) | 2008-11-07 | 2015-04-07 | Renesas Electronics Corporation | Shielded electronic components and method of manufacturing the same |
| JP2011138868A (en) * | 2009-12-28 | 2011-07-14 | Ngk Spark Plug Co Ltd | Multilayer wiring substrate |
| JP2013093623A (en) * | 2013-02-18 | 2013-05-16 | Shinko Electric Ind Co Ltd | Semiconductor package |
| JP2018098491A (en) * | 2016-12-16 | 2018-06-21 | サムソン エレクトロ−メカニックス カンパニーリミテッド． | Printed circuit board, package and manufacturing method of printed circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPWO2004064150A1 (en) | 2006-05-18 |
| TW200414856A (en) | 2004-08-01 |
| TW566065B (en) | 2003-12-11 |
| JP3999784B2 (en) | 2007-10-31 |
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