JP2002319760A - Method for manufacturing wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a wiring board having a recess and a built-up layer formed only on the surface inexpensively without causing any damage on a wiring layer formed on the bottom of the recess. SOLUTION: The method for manufacturing a wiring board 1 comprises a step for forming through hole conductors 11 extending between the surface 3 and the rear surface 4 of a first core substrate 2, and forming a wiring layer 17 on the bottom of a recess 9 on the rear surface 4; a step for bonding the surface 7 of a second core substrate 6 to the rear surface 4 of the first core substrate 2 through an adhesive layer 5, and forming a board body H comprising the first and second core substrates 2 and 6 and having the recess 9 opening to the rear surface 8 of the core substrate 6; a step for making common through holes 13 extending between the surface 3 of the first core substrate 2 and the rear surface 8 of the second core substrate 6 except the recess 9; a step for filling the recess 9 with a filling material 9b; a step for forming a common through hole conductor 14 on the inner wall of the common through hole 13; and a step for forming wiring layers 16 and 19 on the surface 3 of the first core substrate 2, and on the rear surface 8 of the core substrate 6 in the board body H except the recess 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a surface of a core substrate.
The present invention relates to a method for manufacturing a wiring board having a build-up layer only above (one side) and a concave portion for mounting or incorporating an electronic component.

[0002]

2. Description of the Related Art FIG. 9 shows a cross section of a main part of a wiring board 40 in which a build-up layer is laminated only on a surface 42 of a core board 41. The core substrate 41 is made of a relatively thin glass-epoxy resin insulating material, and has a surface 42.
A through-hole conductor 45 and a filling resin 46 are individually formed on the inner walls of the plurality of through-holes 44 penetrating between the inner surface and the back surface 43. As shown in FIG.
A wiring pattern 48 having a predetermined pattern is formed on the front surface 42 of each of the first through-holes 42 and is individually connected to the upper end of each through-hole conductor 45. On the surface 42 and the wiring layer 48,
An insulating layer 50 of an epoxy resin is formed, and a wiring layer 4 is formed.
A filled via conductor 52 is formed at a predetermined position on 8.

As shown in FIG. 9, on an insulating layer 50,
An insulating layer 56 and a wiring layer 54 connected to the upper end of the via conductor 52 are formed. Such a wiring layer 54
A via conductor 58 is formed at a predetermined upper position, and a solder resist layer (insulating layer) 60 and a wiring layer 59 connected to the upper end of the via conductor 58 are formed on the insulating layer 56. The wiring layers 48, 54, 59 and the insulating layers 50, 56, 60 form a build-up layer. FIG.
As shown in FIG. 7, a plurality of solder bumps 62 projecting higher than the first main surface 61 are individually formed at predetermined positions on the wiring layer 59, and each bump 62 is an IC mounted on the first main surface 61. It is individually connected to the connection terminal 65 on the bottom surface of the chip (semiconductor element) 64. In addition, the adjacent solder bump 6
The distance (pitch) between the axes of the shafts 2 and 62 is about 200 μm or more.

In order to prevent the wiring board 40 from warping,
A copper reinforcing member (stiffener) 66 surrounding the C chip 64 is bonded on the first main surface 61. As shown in FIG. 9, a wiring layer 47 connected to the lower end of the through-hole conductor 45 and a solder resist layer (insulating layer) 49 are formed below the back surface 43 of the core substrate 41. A plurality of solder bumps 53 projecting below the second main surface 51 are individually formed at predetermined positions below the wiring layer 47, and each bump 53 is mounted on a chip capacitor mounted under the second main surface 51.
(Electronic components) 55 are individually connected to connection terminals 57.

[0005]

However, in the above-described wiring board 40, the core board 41 is thin and
Since the build-up layer is formed only on the surface 42, there is a problem that warpage occurs due to a difference in the coefficient of thermal expansion between the build-up layer and the core substrate 41. In order to prevent such a warpage of the wiring board 40, it is necessary to bond the reinforcing member 66 on the first main surface 61, and thus there is a problem that the cost is increased. The IC chip 64 is electrically connected to the chip capacitor 55 via the wiring layers 59, 54, 48, the via conductors 58, 52, the through-hole conductor 45, and the wiring layer 47. There is also a problem that the characteristic becomes unstable.

In order to stabilize the electrical characteristics such as reducing the crosstalk noise by bringing the IC chip 64 and the chip capacitor 55 closer to each other, a recess is formed in the core substrate, and an electronic component such as a chip capacitor is formed in the recess. It is conceivable to mount or incorporate components. However, in the recess formed in the core substrate, a wiring layer including a connection terminal for connecting to an electronic component is accurately formed, and
There is a problem that it is difficult to form a wiring layer on a portion other than the concave portion on the back surface side of the core substrate. That is, the wiring layer formed on the bottom of the concave portion is exposed to the plating solution when the back surface outside the concave portion is copper-plated.
Further, when an attempt is made to form the build-up layer on the surface of the core substrate having the concave portion on the opposite side to the concave portion, the core substrate is likely to be warped due to the concave portion, and the build-up layer is flatly and accurately formed on the surface. There was also a problem that it could not be formed. The present invention solves the problems in the conventional technique described above, and is a wiring board in which a build-up layer is formed only on the surface of a wiring board composed of a core substrate having a recess, and is formed at the bottom of the recess. An object of the present invention is to provide a method for manufacturing a wiring board that can be manufactured accurately and at low cost without damaging the wiring layer.

[0007]

According to the present invention, in order to solve the above-mentioned problems, two core substrates are used together, and a wiring layer formed at the bottom of a concave portion formed by the two core substrates is provided. It is made by paying attention to protecting the opening of the concave portion by closing it. That is, in the method for manufacturing a wiring board of the present invention (claim 1), in a first core substrate having a front surface and a back surface, a through-hole conductor penetrating between the front surface and the back surface is formed; Forming a wiring layer of a predetermined pattern at a predetermined position to be a bottom of the concave portion of the substrate body; and forming a wiring layer having a front surface and a rear surface on the back surface side of the first core substrate having the through-hole conductor, and By laminating the front side of the second core substrate having a through hole via an adhesive layer, the second core substrate is composed of the first core substrate and the second core substrate, and is opened on the back surface side of the second core substrate. A laminating step of forming a substrate main body having a concave portion, and a step of removing the surface of the first core substrate and the second
Forming a common through-hole penetrating with the back surface of the core substrate; closing the opening of the recess with a tape or filling the recess with a filler; A step of forming a through-hole conductor, and a step of forming a wiring pattern of a predetermined pattern on each of the front surface of the first core substrate and the back surface of the second core substrate in the substrate main body except for the concave portion. And the following.

According to this, since the opening of the recess formed by the first and second core substrates is closed with a tape or filled with a filler, the wiring layer formed at the bottom of the recess is not damaged. The wiring layer on the back surface of the second core substrate can be reliably formed. Also, the first
And the second core substrate is laminated to form a substrate body,
The resulting wiring board is less likely to be warped, and a conventional reinforcing material is not required, so that the step of bonding such a reinforcing material can be omitted and the manufacturing can be performed at low cost. In addition, a short conduction path can be formed between the electronic component mounted or built in the recess and the semiconductor element such as an IC chip mounted on the surface of the build-up layer formed above the surface of the first core substrate. It is also possible to improve electrical characteristics such as reducing loop inductance and resistance in such a path. In the present specification, the core substrate refers only to an insulating plate material, and does not include a wiring layer formed on the front surface and the back surface.

[0009] In addition, the present invention can include a method of manufacturing a wiring substrate, wherein the second core substrate is thicker than the first core substrate. In this case,
Since the relatively thick second core substrate is laminated on the relatively thin first core substrate, the entire wiring substrate is less likely to be warped, and a flat wiring substrate can be reliably provided. Also, the conduction path between the electronic component mounted or built in the recess and the semiconductor element such as an IC chip mounted on the surface of the build-up layer formed above the surface of the first core substrate is reliably shortened. It is also possible to improve electrical characteristics such as reducing loop inductance and the like in such a path.

After the step of forming a wiring layer of a predetermined pattern on each of the front surface of the first core substrate and the back surface of the second core substrate except for the concave portion,
A method of manufacturing a wiring board (claim 2), further comprising the step of forming a build-up layer including at least one wiring layer and a plurality of insulating layers only on the surface of the first core substrate in the substrate body. Included in the present invention. According to this, the second core substrate is laminated on the back surface side of the first core substrate via the adhesive layer to become a substrate main body, and the build-up layer is formed only on the surface (one side) of the first core substrate. To form
The manufacturing cost can be reduced as compared with the case where the build-up layers are formed on both surfaces of the substrate body.

Further, prior to the laminating step, a step of forming a wiring pattern of a predetermined pattern on each of the back surface of the first core substrate and the surface of the second core substrate excluding the recess is provided. A method for manufacturing a wiring board (claim 3) is also included in the present invention. According to this, in the laminating step, the wiring layer is also formed on the back surface of the first core substrate and the surface of the second core substrate with the adhesive layer interposed therebetween, so that the inside of the substrate body including the two core substrates is formed. Also, a plurality of wiring layers can be formed. As a result, it is possible to easily respond to a demand for higher density of the internal wiring.

[0012] In addition, the step of forming the build-up layer is performed in a state where the first substrate main body and the second substrate main body are laminated with the back surfaces of the second core substrates in both sides facing each other, and are exposed to the outside. The first in any substrate body
The present invention also includes a method of manufacturing a wiring board, which is performed above the surface of the core substrate. According to this,
Since the step of forming the build-up layer is performed in a state where the first substrate main body and the second substrate main body are stacked, the build-up layer is further flattened and formed accurately above the surface of the first core substrate. it can. In addition, since the build-up layers can be formed almost simultaneously on two (one) sets of substrate bodies, the number of manufacturing steps and manufacturing cost can be reduced.

In addition, according to any one of the above-described manufacturing methods, an electronic component that is electrically connected to the wiring layer (electronic component connection terminal) formed at the bottom of the concave portion is mounted in the concave portion. The present invention can also include a method for manufacturing a wiring board, which further includes a step of performing the above. In this case, the conduction path between the electronic component mounted in the recess and the IC chip mounted on the surface of the build-up layer formed above the surface of the first core substrate can be shortened. It is possible to manufacture a wiring board having high electric characteristics such as a reduction in loop inductance of the wiring board.

Further, after each of the steps, a step of incorporating an electronic component, which is electrically connected to the wiring layer (electronic component connection terminal) formed at the bottom of the concave portion, through the embedded resin in the concave portion. The present invention can also include a method of manufacturing a wiring board having the same. In this case, the electronic component can be firmly embedded in the recess. still,
The electronic components include passive components such as capacitors, inductors, resistors, and filters, low-noise amplifiers (LNA),
Active components such as transistors, semiconductor devices, and FETs, S
An AW filter, an LC filter, an antenna switch module, a coupler, a diplexer, and the like, and those obtained by making these chips are included, but are not limited thereto. Further, among them, different kinds of electronic components may be mounted or incorporated in the same recess.

[0015]

Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a cross section of a main part of a wiring board 1 obtained by the manufacturing method of the present invention. As shown in FIG. 1, the wiring substrate 1 is formed above a relatively thin first core substrate 2, a relatively thick second core substrate 6, and a surface 3 of the first core substrate 2. Wiring layer 1
6, 26, 30 and a build-up layer BU including insulating layers 24, 28, 32, and a concave portion 9 formed by the first and second core substrates 2, 6. First core substrate 2
Has a thickness of 100 to 400 μm having a front surface 3 and a back surface 4
m-glass-epoxy resin (in this embodiment, 2
In the vicinity of the center, a plurality of through-holes 10 having a diameter of about 150 μm penetrate, and along the inner wall of each through-hole 10, a copper through-hole conductor 11 and a filling resin 12 having a thickness of about 25 μm are formed. Have been.

As shown in FIG. 1, the second core substrate 6
It is made of a glass-epoxy resin having a front surface 7 and a back surface 8 and having a thickness of about 800 μm, and a recess 9 is formed near the center thereof. The recess 9 is approximately 14 mm in length and width in plan view.
Each has an almost square shape. The first core substrate 2 and the second core substrate 6 are laminated by laminating via a prepreg (adhesive layer) 5 having an adhesive property having a thickness of about 60 μm, and the substrate main body H is formed by these. Is done. As shown on the left and right of FIG. 1, a plurality of relatively long common through-holes 13 having a diameter of about 150 μm penetrate through the first and second core substrates 2 and 6 at positions excluding the concave portions 9. A copper common through-hole conductor 14 and a filling resin 15 having a thickness of about 25 μm are formed on the inner wall of the substrate 13.

As shown in FIG. 1, a copper wiring layer 17 having a predetermined pattern and made of copper and having a thickness of about 15 μm is formed on the back surface 4 of the first core substrate 2. The wiring layer (electronic component connection terminal) 17 located at the bottom of the recess 9 is connected to the lower end of the through-hole conductor 11, and the wiring layer 17 located above the prepreg 5 is connected to the middle of the common through-hole conductor 14. . A copper wiring layer 18 having a predetermined pattern and thickness is also formed below the prepreg 5 on the surface 7 of the second core substrate 6, and is connected to the middle of the common through-hole conductor 14.

Further, as shown in FIG. 1, on the surface 3 of the first core substrate 2, a copper wiring layer 1 having a predetermined pattern is formed.
6 are formed and connected to the upper ends of the through-hole conductors 11 and 14. An insulating layer 24 of an epoxy resin containing silica filler is formed on the front surface 3 and the wiring layer 16, and a filled via conductor 25 is formed at a predetermined position on the wiring layer 16. On the insulating layer 24, a similar insulating layer 28 and a wiring layer 26 connected to the upper end of the via conductor 25 are formed, and a filled via conductor 29 is formed at a predetermined position on the wiring layer 26. . Similarly, on the insulating layer 28, a solder resist layer
(Insulating layer) 32 and a wiring layer 30 connected to the upper end of the via conductor 29 are formed. The above insulating layers 24, 28, 3
2 and the wiring layers 26 and 30 form a build-up layer BU. The thickness of the insulating layer 24 and the like is about 30 μm, and the thickness of the solder resist layer 32 is about 25 μm.

As shown in FIG. 1, a plurality of solder bumps (IC connection terminals) 36 projecting higher than the first main surface (front surface) 34 are individually formed at predetermined positions on the wiring layer 30.
The bumps 36 are connected to a plurality of connection terminals 3 on the bottom surface of an IC chip (semiconductor element) 38 mounted on the first main surface 34.
9 individually. The bump 36 is formed of Sn-A
g-based, Pb-Sn-based, Sn-Ag-Cu-based, Sn-Cu
And a low melting point alloy such as a Sn-Zn-based alloy (Sn-Ag-based solder in the present embodiment), and the distance between the centers of the adjacent solder bumps 36, 36 is about 150 μm. In addition, the plurality of solder bumps 36 and the connection terminals 3
9 is embedded and protected by an underfill material (not shown).

As shown in FIG. 1, a plurality of chip capacitors (electronic components) 20 are inserted into the recess 9 formed by the first and second core substrates 2 and 6, and the solder 2
1 is implemented. Such a capacitor 20 has a plurality of electrodes 22 protruding from the upper ends of both side surfaces along the front-rear direction of FIG. 3.2mm × 1.6mm × ceramic capacitor
It has a size of 0.7 mm. The upper electrode 22 of the capacitor 20 is connected to the wiring layer (electronic component connection terminal) 17 located at the lower end of the through-hole conductor 11 and exposed in the recess 9 via the solder 21. The solder 21 is also made of a low melting point alloy (Sn-Sb based solder).

Further, as shown in FIG. 1, a solder resist (insulating) having a thickness similar to that described above, except under the concave portion 9, is provided below the back surface 8 of the second core substrate 6 and the wiring layer 19. A layer 33 is formed, and a wiring 33 extending from the wiring layer 19 and exposed in the opening 27 opening toward the second main surface 31 is formed. The wiring 33 has Ni
Further, the wiring board 1 is coated with Au plating and is used as a connection terminal to a printed board such as a motherboard (not shown) on which the wiring board 1 itself is mounted. In addition, a solder ball, a pin, or the like may be joined to the connection terminal of the wiring 33.

According to the wiring board 1 described above, the connection terminals 39 of the IC chip 38 mounted on the first main surface 34 and the electrodes 22 of the chip capacitor 20 mounted on the recess 9 are connected to the solder bumps 36 and the wirings. Layers 30, 26, 16, filled via conductors 29, 25, through-hole conductor 11 (thin first core substrate 2), wiring layer 17, and solder 21
Are connected by a short path. For this reason, loop inductance and resistance in such a path can be reduced, and stable conduction can be achieved. Moreover, the thin first
A thick second core substrate 6 is laminated on the core substrate 2 via a prepreg 5 to form a substrate body H and the first core substrate 2
Since the build-up layer BU is provided only on the surface 3 above, sufficient strength can be obtained. For this reason, it is not necessary to attach a reinforcing material as in the related art, and it is possible to manufacture at low cost.

Further, the plurality of solder bumps 36 protruding from the first main surface 34 not only include a wiring path passing through the through-hole conductor 11 penetrating the first core substrate 2 and conducting to the chip capacitor 20, but also a first and second solder bump 36. It can also be formed at a position corresponding to a wiring path passing through the common through-hole conductor 14 penetrating the second core substrates 2 and 6. In addition, a plurality of solder bumps 36 can be arranged at a high pitch of about 150 μm, and an IC chip 38 having a large number of connection terminals 39 can be mounted on these solder bumps 36. Accordingly, the wiring board 1 is free from warpage, has stable internal electrical characteristics, and has the solder bumps 36 arranged on the first main surface 34 at a high density.

The main manufacturing steps in the manufacturing method of the present invention for obtaining the wiring board 1 will be described with reference to FIGS. FIG. 2 (A) shows front and back surfaces 3 and 4 having a thickness of about 2
2 shows a cross section of a first core substrate 2 of 00 μm. A predetermined position in the central portion on the front surface 3 side of the core substrate 2 is pierced by a small diameter drill, or laser is irradiated.
As a result, as shown in FIG. 2B, a plurality of through holes 10 penetrating between the front and rear surfaces 3 and 4 and having an inner diameter of about 150 μm are formed in the center of the first core substrate 2.
The through hole 10 may be formed at a position near the periphery of the first core substrate 2 and at a position coaxial with a common through hole 13 described later.

Next, the entire surface of the first core substrate 2 having the plurality of through holes 10 and the inner wall of each through hole 10 are subjected to electroless copper plating and electrolytic copper plating. still,
A plating catalyst containing Pd is applied to the entire surface of the first core substrate 2 and the inner wall of each through hole 10 in advance. Further, the perforation of the through hole 10 and the copper plating are performed on a panel (a multi-piece board) including a plurality of core substrates 2 (product units).
You may go in the state of. As a result, as shown in FIG. 2 (C), the thickness along the inner wall of each through hole 10 is about 25 μm.
m through-hole conductors 11 are formed. At the same time, the first
The copper plating layers 3a,
4a are respectively formed.

Next, as shown in FIG. 2D, the hollow portion of each through-hole conductor 11 is filled with a filling resin 12 made of an epoxy resin containing an inorganic filler such as silica filler. Note that, instead of the filling resin 12, a conductive resin containing a large amount of metal powder or a non-conductive resin containing metal powder may be used. Further, after the front and back surfaces 3 and 4 of the first core substrate 2 are polished and removed to form the filling resin 12, the copper plating layers 3a and 4 on the front and back surfaces 3 and 4 of the core substrate 2 are formed.
Further, electrolytic copper plating is performed on a to form new copper plating layers 3b and 4b. Subsequently, the upper and lower ends of each filling resin 12 are plated with a lid, and the filling resin 12 is sealed. When no via conductor is formed directly above or below the filling resin 12, the formation of the cover plating may be omitted.

Further, an etching resist (not shown) having a predetermined pattern is formed on the copper plating layers 3a and 3b and the copper plating layers 4a and 4b on the front and rear surfaces 3 and 4 by a known photolithography technique. The copper plating layers 3a, 3b and the copper plating layers 4a, 4b exposed from the gaps between the patterns of the etching resist are etched (known subtractive method). As a result, as shown in FIG. 2E, wiring layers 16 and 17 are formed on the front and back surfaces 3 and 4 of the first core substrate 2 according to the pattern.

FIG. 3A shows a prepreg (adhesive layer: insulating layer) 5 having a thickness of about 60 μm and a thickness of about 800 μm on the back surface 4 side of the first core substrate 2 on which the wiring layers 16 and 17 are formed.
2 shows a state in which the second core substrate 6 is arranged. As shown in FIG. 3 (A), the second core substrate 6 has a front surface in a center portion.
A through hole 9a penetrating between the back surfaces 7, 8 is formed by punching or the like. The through hole 9a has a length and width of about 1
A wiring layer 18 having a predetermined pattern is formed in advance on the surface 7 of the core substrate 6 around the surface of the core substrate 6 by the same photolithography technique and etching as described above. A prepreg 5 having an adhesive property and a thickness of about 60 μm is disposed between the first core substrate 2 and the second core substrate 6, and the first and second core substrates 6 are arranged along the directions indicated by arrows in FIG. The second core substrates 2 and 6 are heated (about 190 ° C. × about 100 minutes) while pressurizing. The adhesive layer may be disposed by applying a liquid insulating material to the first core substrate 2 or the second core substrate 6 using a roll coater or the like, instead of attaching the film-like adhesive layer.

As a result, as shown in FIG.
The second core substrates 2 and 6 are integrally laminated via the prepreg 5. Thereby, the first and second core substrates 2, 6
A concave portion 9 formed on the back surface 8 side of the second core substrate 6
And a substrate main body H having a wiring layer 17 at the bottom (ceiling surface) of the concave portion 9 is formed. Next, from the front surface 3 side of the first core substrate 2 located on the left and right in FIG. 3B excluding the upper part of the concave portion 9, the substrate body H is perforated by a drill or laser irradiation similar to the above. Do. as a result,
As shown in FIG. 4A, a long common through hole 13 including the prepreg 5 and penetrating between the front and back surfaces 3 and 8 of the first and second core substrates 2 and 6 is provided on the left and right sides of the substrate body H. Multiple holes are drilled. Each through hole 13 penetrates through wiring layers 17 and 18 located above and below the prepreg 5 in the middle. FIG. 4A omits the vicinity of both left and right ends in FIG. Also, the common through hole 13
Can be formed coaxially along the axis of the through hole 10 previously drilled at the same position on the first core substrate 2. According to such a method, the positioning of each common through-hole 13 becomes easy.

Further, as shown in FIG. 4B, a filling material 9b made of an epoxy resin is filled in the concave portion 9 and the surface exposed to the outside after curing is made to be in contact with the back surface 8 of the second core substrate 6. Make one. In addition, a thermosetting resin such as phenol, melamine, polyester, and silicon may be used for the filler 9b in addition to the epoxy resin. Instead of filling with the filler 9b, as shown in FIG. 4 (b), a tape T made of a polyester resin and having a thickness of about 20 μm is formed around the back surface 8 so as to close the opening of the concave portion 9. You may paste it. Note that an adhesive is applied to the surface of the tape T, and the tape T is attached with the adhesive surface as the opening side of the recess 9. Examples of the material of the tape T include polyimide, polyester, PET, and fluororesin (trade name: Teflon). Of these, fluororesins are recommended from the viewpoint of heat resistance and chemical resistance. Furthermore, examples of the adhesive applied to the surface of the tape T include a silicone-based adhesive, an acrylic-based adhesive, and a thermoplastic rubber-based adhesive. Among these, silicone-based pressure-sensitive adhesives are recommended from the viewpoints of releasability (that is, ease of peeling) and heat resistance.

In the following, a description will be given of the substrate body H in which the recess 9 is filled with the filler 9b. In the state shown in FIG. 4B, the inner wall of each common through hole 13 and the first core substrate 2
After applying the same plating catalyst to the front surface 3 including the wiring layer 16 and the back surface 8 of the second core substrate 6, the entire surface is subjected to electroless copper plating and electrolytic electrolytic copper plating. Next, an etching resist is formed on the copper plating layers (not shown) formed on the front and back surfaces 3 and 8 of the first and second core substrates 2 and 6 in the same manner as described above, and etching is performed through the resist. .

As a result, as shown in FIG. 5A, a common through hole having a thickness of about 25 μm is formed along the inner wall of each common through hole 13 of the first and second core substrates 2 and 6 in the substrate body H. The hole conductors 14 are individually formed. Also,
On the back surface 8 of the second core substrate 6, a wiring layer 19 having a predetermined pattern and connected to the lower end of the common through-hole conductor 14 is formed, and the wiring layer 16 on the front surface 3 of the first core substrate 2 is formed. The inner wiring is connected to the upper end of the common through-hole conductor 14. Further, as shown in FIG. 5B, the same filling resin 1 as described above is placed in the hollow portion of each common through-hole conductor 14.
After the formation of No. 5, copper plating is performed on the front surface 3 of the first core substrate 2 and the back surface 8 of the second core substrate 6 in the same manner as described above, and then an etching resist is formed thereon and etched. As a result, the upper and lower ends of the filling resin 15 are lid-plated. In FIGS. 5A and 5B, the thickness of the wiring layer 16 is the same as in FIGS. 4A and 4B for convenience. In addition, when the via conductor is not formed directly above or below the filling resin 15, the lid plating may be omitted.

Next, when the filler 9b in the concave portion 9 is removed by, for example, spot facing using an end mill, FIG.
As shown in (B), the wiring layer 17 is provided at the bottom (ceiling surface) of the recess 9.
And the substrate body H having the wiring layers 16 and 19 on the front and back surfaces 3 and 8 of the first and second core substrates 2 and 6 can be obtained. When a resin that can be chemically etched is used for the filler 9b, the filler 9b may be subjected to chemical etching to remove it instead of the spot facing process. In addition, as shown in FIG. 4B, when the tape T attached to the opening of the recess 9 is peeled off, the same substrate body H as described above is obtained.

Next, a pair of substrate bodies H having the above-described recess 9 and the wiring layers 16, 17, and 19 are prepared, and as shown in FIG. 6, the first substrate body H1 and the second substrate body H2 are connected to each other. In a state where the back surfaces 8 of the second core substrates 6 are opposed to each other, a spacer is
(Prepreg) Laminate and restrain with S interposed. Accordingly, the first and second substrate bodies H1 and H2 are stacked symmetrically with each other and have a large thickness as a whole, exhibiting high rigidity, thereby preventing warpage. In the step of laminating the first substrate body H1 and the second substrate body H2, two panels (a large number) each having a plurality of these substrate bodies H1 and H2 (product units) individually along the plane direction are used. Alternatively, it may be performed using a single substrate.

Next, as shown in FIG. 7, an insulating layer 24 is formed above the surface 3 of the first core substrate 2 in one of the substrate main bodies H1 / H2, and a predetermined position on the wiring layer 16 is formed. Then, a filled via conductor 25 is formed. Thereafter, the insulating layer 28 forming the build-up layer BU together with the insulating layer 24,
The solder resist layer 32, the wiring layers 26 and 30, and the filled via conductors 25 and 29 are formed by a known build-up process.
(A semi-additive method, a full-additive method, a subtractive method, an insulating layer formed by laminating a film-like resin material, a photolithography technique, and the like). Further, a build-up layer BU and the like are formed above the surface 3 of the first core substrate 2 in the remaining substrate main bodies H2 / H1 in the same manner as described above. As a result, these build-up layers BU can be formed more evenly and more accurately. The process of forming the build-up layer BU may be performed in a state of two panels (multi-piece substrates) individually including a plurality of substrate bodies H1 and H2 (product units).

Next, when the spacer S is removed and the first and second substrate bodies H1 and H2 composed of the first and second core substrates 2 and 6 having the build-up layer BU are separated, FIG.
The state shown in FIG. Under the back surface 8 of the second core substrate 6 in the substrate body H, the same solder resist layer 2 as described above is formed.
3 and the wiring 33 in the wiring layer 19 exposed in the opening 27 opened on the surface (second main surface) 31 side of the Ni
And Au plating to form connection terminals. And
As shown in FIG. 8A, openings (pads) penetrating the solder resist layer 32 are formed at predetermined positions on the wiring layer 30, and the same low melting point alloy as described above is printed and filled inside the openings. Then, the surface of the solder resist layer 32 (the first
A solder bump 36 protruding from the main surface 34 is formed. At this time, the distance (pitch) between the centers of the adjacent solder bumps 36, 36 can be set to about 150 μm. Thus, the wiring board 1 shown in FIG. 1 is obtained.

The lamination of the first substrate body H1 and the second substrate body H2 may be performed in a state where the inside of the recess 9 is filled with the filler 9b or the opening thereof is closed with the tape T. .
In this case, the first substrate body H1 and the second substrate body H
2, after the build-up layers BU and the like are formed, the two are separated, and then the filler 9b and the tape T are removed. In the step of forming the solder resist layer 23, the opening 27, and the wiring (connection terminal) 33, the recess 9 shown in FIG. 5A is filled with the filler 9b, or FIG. This may be performed with the recess 9 closed with the tape T shown in b). In this case, after forming the solder resist layer 23 and the like, the filler 9b in the concave portion 9 or the tape T in the opening is removed together with the solder resist layer 23 located immediately below these.

A chip capacitor (electronic component) 2 is provided in the recess 9.
0, the wiring board 1 is mounted as shown in FIG.
A solder 21 made of a low melting point alloy (Sn-Sb solder) is formed below the wiring layer (electronic component connection terminal) 17 located at the bottom of the concave portion 9 in FIG. These solder 2
By connecting 1 to the electrode 22 projecting from the upper end of the chip capacitor 20, the chip capacitor 20 can be mounted in the recess 9 as shown in FIG. still,
The state shown in FIG. 8B is turned upside down by rotating by 180 °, and by filling a not-shown molten embedding resin into the concave portion 9 that opens upward, the chip capacitor 20 is filled with the embedding resin. It is also possible to bury and embed in the recess 9 through this. In this case, the chip capacitor 20 may be of a type having another electrode (not shown) projecting from the lower end thereof (close to the opening of the concave portion 9). Can also be connected.

According to the method of manufacturing the wiring board 1 described above, the recess 9 is filled with the filler 9b or the opening of the recess 9 is closed with the tape T, so that the wiring layer 17 formed at the bottom of the recess 9 is removed. The wiring layer 19 can be reliably formed on the back surface 8 of the second core substrate 6 without damage, and the common through-hole conductor 14 can be easily formed. Further, since the first and second core substrates 2 and 6 are laminated to form the substrate main body H, the wiring substrate 1 is less likely to warp, and the build-up layer BU can be formed flat and accurately. Further, the conventional reinforcing member is not required, and the step of bonding the reinforcing member can be omitted, and the manufacturing can be performed at low cost. Moreover, since the build-up layer BU is formed only above the surface 3 of the first core substrate 2 in a state where the first and second substrate main bodies H1 and H2 are stacked, the wiring substrate 1 can be manufactured at low cost. . Furthermore, the distance between the chip capacitor 20 mounted or built in the recess 9 and the IC chip 38 mounted on the surface 34 of the build-up layer BU can be shortened, so that the loop inductance in the conduction path between the two can be reduced. Can also be improved.

The present invention is not limited to the embodiments described above. The material of the first and second core substrates 2 and 6 is bismaleimide-triazine (BT) resin, epoxy resin, and similar heat resistance, mechanical strength, and flexibility, in addition to the glass-epoxy resin composite material. Using a glass woven fabric having properties and processing easiness, or a glass fiber-resin composite material that is a composite material of glass fiber such as glass woven fabric and a resin such as an epoxy resin, a polyimide resin, or a BT resin. Is also good. Alternatively, a composite material of an organic fiber such as a polyimide fiber and a resin, or a P
It is also possible to use a resin-resin composite material in which a resin such as an epoxy resin is impregnated into a fluorine resin having a three-dimensional network structure such as TFE.

Further, only one electronic component may be mounted or built in the recess 9. Alternatively, a plurality of recesses 9 are formed in one product unit in a multi-piece board (panel) including a large number of wiring boards (product units) 1 and a required number of electronic components are mounted in each recess 9. Or it may be built-in. Further, a unit in which a plurality of chip-shaped electronic components are bonded in advance between their side surfaces may be mounted in the recess 9 or the like. In addition, the chip-shaped electronic components include passive components such as chip-shaped inductors, resistors, and filters, transistors,
Active components such as a semiconductor element, an FET, and a low noise amplifier (LNA) are also included, and electronic components of different types can be mounted together in the same recess 9 of the wiring board 1.

The materials of the wiring layers 16 and 26, the through-hole conductors 11, etc. are Ag, Ni,
It may be formed of a Ni-Au type or the like, or may be formed by a method such as applying a conductive resin without using these metal plating layers. Further, the material of the insulating layers 24, 28 and the like has, besides the epoxy resin as a main component, a polyimide resin, a BT resin, a PPE resin, or a continuous pore having the same heat resistance and pattern moldability. A resin-resin composite material in which a resin such as an epoxy resin is impregnated with a fluorine-based resin having a three-dimensional network structure such as PTFE can also be used. The insulating layer may be formed by a method of applying a liquid resin by a roll coater, in addition to a method of thermocompression bonding an insulating resin film. Further, the composition of the glass cloth or glass filler mixed into the insulating layer may be any one of E glass, D glass, Q glass and S glass, or a combination of two or more of them. The via conductor may be a conformal via conductor that is not completely filled with a conductor, instead of the filled via conductor 25 or the like.
Alternatively, a staggered configuration in which the via conductors are stacked with their axes shifted may be used, or a configuration in which a wiring layer extending in the planar direction is interposed in the middle. Incidentally, except for the wiring layer formed on the bottom (ceiling surface) of the concave portion, no wiring layer was formed between the back surface of the first core substrate and the surface of the second core substrate,
It is also possible to directly laminate the first core substrate and the second core substrate via an adhesive layer.

[0043]

According to the above-described method of manufacturing a wiring board of the present invention (claim 1), the recess formed by the first and second core substrates is closed by filling it with a filler or the like. Therefore, the wiring layer can be reliably formed on the back surface of the second core substrate without damaging the wiring layer formed at the bottom of the concave portion. In addition, since the substrate body on which the first and second core substrates are laminated is unlikely to be warped and a conventional reinforcing material is not required, the step of bonding the reinforcing material can be omitted, and the manufacturing can be performed at low cost. Furthermore, a short conduction path can be formed between an electronic component mounted in the recess and a semiconductor element such as an IC chip mounted on the surface of the build-up layer formed above the surface of the first core substrate. It is also possible to contribute to the improvement of electrical characteristics such as reduction of loop inductance and the like in such a path.

According to the method of manufacturing a wiring board of the second aspect, since the build-up layers are formed only on one side of the substrate body composed of the first and second core substrates, the build-up layers are formed on both sides. As compared with the case, the manufacturing cost can be reduced. Furthermore, according to the method of manufacturing a wiring board of the third aspect, in the laminating step, the wiring layer is also formed on the back surface of the first core substrate and the front surface of the second core substrate with the adhesive layer interposed therebetween. A plurality of wiring layers can be formed inside the main body, and it is possible to easily respond to a demand for high density of internal wiring. In addition, claim 4
According to the method of manufacturing a wiring board, the build-up layer can be more flattened and formed accurately above the surface of the first core substrate, and the build-up layer can be substantially Since they can be formed simultaneously, the number of manufacturing steps and cost of the wiring board can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a main part of a wiring board obtained by a manufacturing method of the present invention.

FIGS. 2A to 2E are schematic views showing main manufacturing steps in the manufacturing method of the present invention.

FIGS. 3A and 3B are schematic views showing main manufacturing steps following FIG. 2E.

4 (A) and 4 (B) are schematic views showing main manufacturing steps following FIG. 3 (B), and FIG. 4 (b) is a partial schematic view showing steps in a form different from FIG. 3 (B).

FIGS. 5A and 5B are schematic views showing main manufacturing steps subsequent to FIG. 4B.

FIG. 6 is a schematic view showing main manufacturing steps of the manufacturing method of the present invention following FIG. 5 (B).

FIG. 7 is a schematic view showing main manufacturing steps of the manufacturing method of the present invention following FIG. 6;

FIGS. 8A and 8B are schematic diagrams showing main manufacturing steps following FIG. 7;

FIG. 9 is a sectional view showing a main part of a conventional wiring board.

[Explanation of symbols]

 1 ...... Wiring board 2 ...... First core board 3, 7 ...... Surface 4, 8 ………………………………………………………………………………………………………………………………………………… prepreg (adhesive layer) 6 …………… Recessed part 9a ………………………… Through hole 9b ………………………………… Filler 11 ……………………… … Through-hole conductor 13 ……………………… Common through-hole 14 ………………………… Common through-hole conductor 16 to 19, 26, 30… Wiring layers 24, 28, 32 Insulating layer H ………………………………………………………………………………………………………………… First substrate body H2 ………………………. …………………………………………………………………………… Layer T …………………………… Tape

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 23/12 N (72) Inventor Yukihiro Kimura 14-18 Takatsuji-cho, Mizuho-ku, Nagoya-shi, Aichi Japan F-term (reference) in Ceramics Co., Ltd. 5E346 AA02 AA22 AA43 BB15 CC04 CC09 CC32 DD02 DD03 DD25 DD32 DD33 DD44 EE09 EE33 FF04 FF07 FF15 GG15 GG17 GG22 GG28 HH02 HH25 HH32

Claims (4)

[Claims] 1. A first core substrate having a front surface and a back surface, a through hole conductor penetrating between the front surface and the back surface, and a predetermined position on the back surface which will be a bottom of a concave portion of the substrate body. Forming a wiring layer of a predetermined pattern on the first core substrate having the through-hole conductor, the front surface of the second core substrate having a front surface and a back surface, and having a through-hole in the center. Are laminated via an adhesive layer, thereby forming a substrate main body including the first core substrate and the second core substrate and having a concave portion opened on the back surface side of the second core substrate. The first substrate at a position excluding the concave portion of the substrate body
Forming a common through-hole penetrating between the front surface of the core substrate and the back surface of the second core substrate; and closing the opening of the recess with a tape or filling the recess with a filler. Forming a common through-hole conductor on the inner wall of the common through-hole; and positioning the common through-hole conductor at a position excluding the recess on the front surface of the first core substrate and the back surface of the second core substrate in the substrate body. Forming a wiring layer of the pattern,
A method for manufacturing a wiring board, comprising: 2. A surface of said first core substrate and said second core substrate.
After a step of forming a wiring layer of a predetermined pattern at a position on the back surface of the core substrate excluding the recess, only on the surface of the first core substrate in the substrate body,
The method for manufacturing a wiring board according to claim 1, further comprising a step of forming a build-up layer including at least one wiring layer and a plurality of insulating layers. 3. The method according to claim 1, further comprising, before the laminating step, a step of forming a wiring pattern having a predetermined pattern on each of the back surface of the first core substrate and the surface of the second core substrate except for the concave portion. The method for manufacturing a wiring board according to claim 1, wherein: 4. The step of forming the build-up layer includes the steps of: forming a first substrate main body and a second substrate main body into a second substrate main body;
The core substrates are laminated with their back surfaces facing each other,
The method according to claim 2, wherein the method is performed above a surface of the first core substrate in any of the substrate bodies exposed to the outside.