JP2005159330A - Method of manufacturing multilayer circuit board and multilayer circuit board manufactured by the same, and board with semiconductor chip mounted thereon and semiconductor package using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing multilayer circuit board that can surely eliminate smears in a desmear process without decreasing the productivity of the multilayer circuit board, prevent a reduction in adhesive strength between an interlayer dielectric and a wiring, and manufacture a highly reliable multilayer circuit board, and to provide a multilayer circuit board manufactured by the method, a board with semiconductor chips mounted thereon, and a semiconductor package using the board. <P>SOLUTION: The method of manufacturing a multilayer circuit board, in which n (n is an integer that is greater than or equal to 2) layers of metal layers are formed on the dielectric with one or more kinds of metal, comprises steps of: forming k (k is an integer that is greater than or equal to 1 and less than or equal to n-1) layers of metal layers on the dielectric; simultaneously forming an opening on the k layers of metal layers and dielectric; desmear-processing the inside of the opening; and further forming (n-k) layers of metal layers. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention relates to a multilayer circuit board manufacturing method, a multilayer circuit board obtained therefrom, a semiconductor chip mounting board, and a semiconductor package using the board.

  In the field of semiconductor packages, demands for higher integration and higher speed are increasing in recent years. As a semiconductor package corresponding to these, a package in which a semiconductor chip is mounted on a multilayer circuit board in which an insulating layer is formed on a glass epoxy core board has been proposed. Such a semiconductor package is mounted on a larger substrate called a mother board by external connection terminals of the semiconductor chip mounting substrate, and is connected to each other by wiring in the mother board. By adopting such a mounting form, 0.1 to 0.25 mm, which is the electrode interval of the semiconductor chip, can be expanded to 0.5 to 1.0 mm and mounted on the board.

  In general, interlayer connection of a multilayer circuit board is performed by forming a via hole and then forming a metal layer by plating in the via hole. In order to meet the demands for miniaturization, weight reduction, and high performance of electronic devices, it is required to reduce the diameter of the via hole. For this reason, the number of methods for forming a via hole with a laser has recently increased.

  Among various types of lasers, carbon dioxide lasers can drill holes in organic insulating resins such as epoxy resins and polyimide resins at high speed, and are most frequently used industrially for printed wiring boards. In this case, resin carbide (smear) remains at the bottom of the via hole. Therefore, a desmear process for removing smear using plasma, a permanganate aqueous solution, or the like is necessary.

  During the desmear process, the plasma and the permanganate aqueous solution are in contact with not only the bottom of the via hole but also the entire surface of the substrate. For this reason, when the contact surface is a resin surface, the roughness or functional group of the resin surface changes due to desmear, and there is a problem that the adhesive strength (peel strength) between the metal and the resin is lowered. In order to solve this problem, in Japanese Patent Laid-Open No. 4-3676, the copper foil is removed by etching only in the hole portion having the same size as the via hole diameter, and then the laser beam is irradiated to the same position to make a hole. A method is disclosed. The diameter of the laser beam used at this time is larger than the diameter of the via hole.

JP-A-4-3676

  In the method according to Japanese Patent Laid-Open No. 4-3676, a conventional type machine in which drilling for laser irradiation and etching for forming a circuit must be repeated twice, and only one etching for forming a circuit is required. Compared with the manufacturing method of the multilayer printed wiring board by the type drill drilling, it was the cause of lowering the productivity. Further, it is not easy to etch the hole portion of the outer layer circuit in accordance with the position of the inner layer circuit because high accuracy is required for the alignment.

  The object of the present invention is to improve the above-mentioned problems of the prior art, and the object is to remove smear reliably in the desmear process without reducing the productivity of the multilayer circuit board. In addition, a method for manufacturing a highly reliable multilayer circuit board capable of preventing a decrease in the adhesive strength between the interlayer insulating layer and the wiring, and a multilayer circuit board obtained from the method, a semiconductor chip mounting board, and a semiconductor package using the board are disclosed. Is to provide.

In order to achieve the above object, the present invention is configured as follows.
(1) A method for producing a multilayer circuit board, comprising a step of forming a metal layer of n (where n is an integer of n ≧ 2) layers of one or more metals on an insulating layer, wherein k is formed on the insulating layer. (Where k is an integer satisfying 1 ≦ k ≦ n−1) a step of forming a metal layer, a step of forming an opening in the metal layer and the insulating layer of the k layer, a step of desmearing the inside of the opening, The manufacturing method of the multilayer circuit board characterized by including the process of forming the metal layer of nk) layer further.
(2) The method for manufacturing a multilayer circuit board according to (1), wherein the desmear process is a process performed by a dry process.
(3) The method of manufacturing a multilayer circuit board according to (1), wherein the desmear process is a process using a dry process and a wet process in combination.
(4) The method of manufacturing a multilayer circuit board according to any one of (1) to (3), wherein the step of forming the opening is a step by laser processing.
(5) The method for producing a multilayer circuit board according to any one of (1) to (4), wherein the step of forming the n metal layers includes a step of forming at least one layer by a dry process.
(6) The step of forming the n metal layers includes the step of forming at least one layer by plating. (1) to (4) The method for manufacturing a multilayer circuit board according to any one of (1) to (4).
(7) The method for producing a multilayer circuit board according to any one of (1) to (6), wherein the thickness of the metal layer of the k layer is 1 μm or less.
(8) The method for producing a multilayer circuit board according to any one of (1) to (7), further including a step of forming the surface roughness of the insulating layer to 1 μm or less in terms of average roughness (Ra).
(9) A multilayer circuit board manufactured by any one of the manufacturing methods according to (1) to (8).
(10) A semiconductor chip mounting board using the multilayer circuit board according to (9), wherein a semiconductor chip connection terminal is provided on one side of the multilayer circuit board and an external connection terminal is provided on the other side. Chip mounting substrate.
(11) A semiconductor package comprising the semiconductor chip mounting substrate according to (10), a semiconductor chip mounted in a semiconductor chip mounting region, and a sealing resin that seals at least a face surface of the semiconductor chip.

  According to the method for manufacturing a multilayer circuit board of the present invention, it is possible to reliably remove smear in the desmear process without reducing productivity, and to prevent a decrease in adhesion strength between the interlayer insulating layer and the wiring. In addition, a highly reliable multilayer circuit board, a semiconductor chip mounting board, and a semiconductor package using the board can be provided. According to the substrate manufacturing method of the present invention, the adhesive strength between the resin and the metal (wiring) does not decrease during desmearing, and the reflow resistance and the reliability in the temperature cycle test can be improved. A multilayer circuit board, a semiconductor chip mounting board, and a semiconductor package having excellent mounting reliability can be manufactured.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, although a semiconductor chip mounting substrate is described as an example of the multilayer circuit board, it is not particularly limited.
(Semiconductor chip mounting substrate)
FIG. 1 shows a schematic cross-sectional view of one embodiment (two-sided build-up layer) of a semiconductor chip mounting substrate of the present invention. Here, an embodiment in which the build-up layer 104 that is an insulating layer is formed only on one side will be described, but the build-up layer (insulating layer) 104 may be formed on both sides as necessary. As shown in FIG. 1, the semiconductor chip mounting substrate of the present invention has a semiconductor chip connection terminal (not shown) and a first interlayer connection terminal 101 on a core substrate 100 which is an insulating layer on the side where the semiconductor chip is mounted. The first wiring 106a including is formed. A second wiring 106 b including the second interlayer connection terminal 103 is formed on the opposite side of the core substrate 100, and the first interlayer connection terminal 101 and the second interlayer connection terminal 103 are connected to the first interlayer connection terminal 103. Are electrically connected via an interlayer connection via hole (hereinafter referred to as a first via hole) 102. A buildup layer (insulating layer) 104 is formed on the second wiring of the core substrate 100, and a third wiring 106 c including a third interlayer connection terminal is formed on the buildup layer (insulating layer) 104. The second interlayer connection terminal 103 and the third interlayer connection terminal are electrically connected via a second interlayer connection blind via hole (hereinafter referred to as a second via hole) 108. When a plurality of buildup layers (insulating layers) 104 are formed, the same structure is stacked. For example, in the third wiring 106c, the third interlayer connection terminal is an interlayer connection terminal of the next buildup layer, Electrical connection is established via a third interlayer connection blind via hole (hereinafter referred to as a third via hole) 105. On the outermost buildup layer (insulating layer) 104, external connection terminals 107 connected to the mother board are formed. The shape of the wiring, the arrangement of each connection terminal, and the like are not particularly limited, and can be appropriately designed for manufacturing a semiconductor chip to be mounted and a target semiconductor package. Further, the semiconductor chip connection terminal and the first interlayer connection terminal 101 can be shared. Furthermore, an insulating coating 109 such as a solder resist can be provided on the outermost buildup layer (insulating layer) 104 as necessary.

(Core substrate)
The material of the core substrate 100 is not particularly limited, but an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, or the like can be used. As the organic substrate, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used. Furthermore, it is more preferable that a thermosetting organic insulating material is a main component. Thermosetting resins include phenol resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, silicone resin, resin synthesized from cyclopentadiene, tris (2-hydroxyethyl) ) Resin containing isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimetallate, furan resin, ketone resin, xylene resin, thermosetting containing condensed polycyclic aromatic Resin, benzocyclobutene resin, etc. can be used. Examples of the thermoplastic resin include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, and liquid crystal polymer. Moreover, what molded these resin so that it might become integral with a glass cloth, a glass nonwoven fabric, etc. may be used.

In consideration of the thermal expansion coefficient and insulation, it is preferable to use ceramic or glass. Among the glass, non-photosensitive glass includes soda lime glass (component example: SiO ₂ 65 to 75%, Al ₂ O ₃ 0.5 to 4%, CaO 5 to 15%, MgO 0.5 to 4%, Na ₂ O 10-20%), borosilicate glass (component example: SiO ₂ 65-80%, B ₂ O ₃ 5-25%, Al ₂ O ₃ 1-5%, CaO 5-8%, MgO 0.5 ˜2%, Na ₂ O 6-14%, K ₂ O 1-6%) and the like. Also, it includes those containing gold ions and silver ions as a photosensitive agent into Li _{2 O-SiO} 2 based crystallized glass as photosensitive glass. The thickness of the core substrate 100 is preferably in the range of 100 to 800 μm from the viewpoint of IVH formation, and more preferably in the range of 150 to 500 μm.

(Build-up layer)
The build-up layer 104 that is an insulating layer is preferably made of an insulating material. As the insulating material, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used. Furthermore, it is more preferable that a thermosetting organic insulating material is a main component. Thermosetting resins include phenol resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, silicone resin, resin synthesized from cyclopentadiene, tris (2-hydroxyethyl) ) Resin containing isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimetallate, furan resin, ketone resin, xylene resin, thermosetting containing condensed polycyclic aromatic Resin, benzocyclobutene resin, etc. can be used. Examples of the thermoplastic resin include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, and liquid crystal polymer. A filler may be added to the insulating material. Examples of the filler include silica, talc, aluminum hydroxide, aluminum borate, aluminum nitride, and alumina. As a method for forming the buildup layer (insulating layer) 104, a varnish-like insulating material can be formed by spin coater, comma coater, printing or the like, and then dried and cured. Alternatively, it may be formed in advance in a film shape and bonded to the core substrate 100 by pressing or laminating. Depending on the insulating material, it can be formed by impregnating a glass cloth or non-woven fabric with the material, forming a prepreg, and then bonding. Furthermore, varnish can be apply | coated to metal foil and it can also adhere | attach on the core board | substrate 100 after drying.

(Coefficient of thermal expansion)
The thermal expansion coefficient of the semiconductor chip and the thermal expansion coefficient of the core substrate 100 are approximated, and the thermal expansion coefficient of the core substrate 100 and the thermal expansion coefficient of the buildup layer (insulating layer) 104 are approximated. preferable. Furthermore, when the thermal expansion coefficients of the semiconductor chip, the core substrate 100, and the buildup layer (insulating layer) 104 are α1, α2, and α3 (ppm / ° C.), it is more preferable that α1 ≦ α2 ≦ α3. Specifically, the thermal expansion coefficient α2 of the core substrate 100 is preferably 7 to 13 ppm / ° C, and more preferably 9 to 11 ppm / ° C. The thermal expansion coefficient α3 of the buildup layer (insulating layer) 104 is preferably 10 to 40 ppm / ° C, more preferably 10 to 20 ppm / ° C.

(Young's modulus)
The Young's modulus of the buildup layer (insulating layer) 104 is preferably 1 to 5 GPa in terms of stress relaxation against thermal stress. The filler in the build-up layer (insulating layer) 104 is appropriately adjusted so that the build-up layer (insulating layer) 104 has a thermal expansion coefficient of 10 to 40 ppm / ° C. and a Young's modulus of 1 to 5 GPa. It is preferable to add.

(Flatness)
As for the flatness of the surface of the insulating layer such as the core substrate 100 and the buildup layer 104, the average roughness (Ra) is 1.0 μm or less, particularly 0.01 to 1.0 μm is preferable from the viewpoint of high-speed electric signal transmission characteristics. Furthermore, it is more preferable that it is 0.01-0.4 micrometer. When the thickness exceeds 1.0 μm, the width variation of the formed wiring is large, and the attenuation of the high-speed electrical signal tends to be large. If it is less than 0.01 μm, the peel strength tends to be insufficient. Similarly, the flatness of the wiring surface is preferably 1.0 μm or less in terms of average roughness (Ra), and more preferably 0.01 to 0.4 μm. That is, the interface between the core substrate 100 and the first wiring 106a, the interface between the core substrate 100 and the second wiring 106b, and the interface between the second wiring 106b and the buildup layer (insulating layer) 104 As for the interface between the build-up layer (insulating layer) 104 and the third wiring 106c, it is preferable that the unevenness of at least one of the interfaces is 1.0 μm or less in terms of Ra. In particular, 0.01 to 1.0 μm is preferable, and 0.01 to 0.4 μm is more preferable. In the present invention, Ra is an average roughness as described above, and can be measured using a stylus type surface roughness meter or the like (see JIS C 6481). The Ra of the surface of the core substrate 100 and the buildup layer (insulating layer) 104 can be measured using a stylus type surface roughness meter or the like.

(Manufacturing method of semiconductor chip mounting substrate)
The semiconductor chip mounting substrate can be manufactured by a combination of the following manufacturing methods. The order of the manufacturing process is not particularly limited as long as it does not depart from the object of the present invention.

(Formation of metal layer on insulating layer)
As a method of forming a metal layer of n (where n is an integer of n ≧ 2) with one or more kinds of metals on the insulating layer, there are a dry process, a wet process, and a method of bonding metals together. You may combine these methods.

(Metal layer formation by dry process)
Examples of the dry process include sputtering, vacuum heating deposition, and vacuum EB deposition. As the sputtering apparatus, dipolar sputtering, tripolar sputtering, quadrupolar sputtering, magnetron sputtering, mirrortron sputtering, or the like can be used. The metal layer that can be formed by sputtering may be Cr, Ni, Co, Pd, Zr, Zn, Cu, or an alloy thereof. The thickness of one metal layer that can be formed by sputtering is about 1 to 1000 nm, and a plurality of metal layers can be continuously formed. When a metal is formed on the insulating layer by sputtering, it is preferable to form a base metal in the first layer in order to improve adhesion with the insulating layer. The film thickness of the base metal is particularly preferably 5 to 200 nm, and Ni, Cr, Zn, Co, and alloys thereof are preferable as the metal. For the second and subsequent layers, the metal type and thickness may be selected as necessary. However, when forming the wiring of the multilayer circuit board, the second thin film copper layer is formed by sputtering 5 to 1000 nm using Cu as a target. Can be formed. The film thickness of the thin copper layer is preferably 200 to 500 nm, more preferably 100 to 500 nm.

(Metal layer formation by wet process)
A metal layer can be formed on the insulating layer by plating, which is a wet process. When the metal layer is formed by plating, it is preferable to roughen the surface of the insulating layer and form fine irregularities on the resin surface in order to obtain adhesive strength with the insulating layer. Either electroplating or electroless plating may be used for plating, but electroless plating is preferred when used for the first layer. When forming the wiring of the multilayer circuit board, it is preferable to use copper plating.

(Method of bonding metal foil)
The first metal layer can also be formed by bonding metal foils by pressing or laminating when the insulating layer has an adhesive function. However, when a thin metal layer is formed, it is very difficult to bond directly, so a method of thinning by attaching a thick metal foil and then thinning by etching or the like. There are ways to remove it. A copper / nickel / copper three-layer copper foil can be used as the former, and a peelable copper foil can be used as the latter. When a metal layer is formed on the carrier layer, a plurality of metal layers can be formed and bonded in advance by the dry process or the wet process. As the metal to be used, the layer that adheres to the insulating layer is preferably Ni, Cr, Zn, Co, and alloys thereof, and the layer that forms the wiring is preferably copper.

(Method of forming wiring on insulating layer)
As a method for forming a wiring on the insulating layer, an n (where n is an integer of n ≧ 2) layer of metal is formed on the insulating layer, and unnecessary portions of the metal layer are removed by etching. Method (subtract method), forming a metal layer of n (where n is an integer of n ≧ 2) with one or more kinds of metals on the insulating layer, and then forming the necessary wiring by electrolytic plating, then the metal layer Are removed by etching (semi-additive method) and n (where n is an integer of n ≧ 2) layer wiring (additive method) is formed by plating only at a necessary location on the insulating layer.

(Bahia Hall)
After forming a metal layer of k (where k is an integer of 1 ≦ k ≦ n−1) with one or more metals on the insulating layer, the metal layer and the insulating layer of k layer are opened from the metal layer side. For example, a via hole is formed. For example, when two metal layers (n = 2) are formed on the build-up layer (insulating layer) 104 by sputtering, which is a dry process, Ni is sputtered by 10 nm as the base metal of the first layer (k = 1). Then, the Ni layer and the buildup layer (insulating layer) 104 can be opened simultaneously to form a via hole. Thus, if it is a thin metal layer, it can process on the same conditions as the case where only an insulating layer is opened, and is preferable.

(Method of forming an opening)
Methods for forming openings include mechanical processing such as punching and drilling, laser beam processing, chemical etching processing using chemicals, and dry etching methods using plasma. In particular, it is more preferable to use a laser beam from the viewpoint that it is easy to drill holes simultaneously. The laser to be used is not limited, and a carbon dioxide laser, a YAG laser, an excimer laser, or the like can be used.

(Desmear)
As the smear removal of the via hole formed by the above-described method, a dry process, a wet process, or a process using a combination of a dry process and a wet process as necessary can be used. As the dry treatment, plasma treatment, reverse sputtering treatment, or ion gun treatment can be used. Furthermore, plasma processing includes atmospheric pressure plasma processing, vacuum plasma processing, and RIE processing, which can be selected as necessary. As a gas used for these treatments, nitrogen, oxygen, argon, freon (CF ₄ ), or a mixed gas thereof is preferable. For the wet treatment, an oxidizing agent such as chromate or permanganate can be used, but can also be carried out with water, an acid or alkali solution, a solvent, or the like, if necessary. In addition, if a k-layer metal layer is formed on the surface of the insulating layer except for the opening during desmearing, there is no damage to the surface of the insulating layer due to desmearing, so that it is possible to prevent a decrease in the adhesion between the insulating layer and the metal layer. Furthermore, it is also possible to use ultrasonic waves during wet processing. In the treatment using both the dry treatment and the wet treatment, the wet treatment may be performed after the dry treatment, or the dry treatment may be performed after the wet treatment. These selections may be appropriately selected depending on the insulating material to be used.

(Interlayer connection)
Interlayer connection is performed by forming metal layers from the (k + 1) th layer to the nth layer, or by filling with plating or conductive paste. The metal layer can be formed by a dry process only, a wet process only, or a process in which a dry process and a wet process are mixed. Further, the metal layers from the (k + 1) th layer to the nth layer may be formed including plating which is a wet process. When the semi-additive method is used as the wiring formation method, interlayer connection can be performed simultaneously with the formation of the wiring by plating, which is efficient and preferable. Further, after the desmear treatment, the metal layer once formed up to k layers can be removed by etching or the like to newly form an n-layer metal layer.

(Wiring formation by subtract method)
An etching resist is formed on the metal layer wiring formed by the above-mentioned method, and a chemical etching solution is sprayed on the portion exposed from the etching resist to remove the unnecessary metal layer by etching to form the wiring. can do. For example, when the metal layer is a copper layer, an etching resist material that can be used for an ordinary wiring board can be used as the etching resist, and a resist ink can be formed by silk screen printing or a photosensitive dry for etching resist. A film is laminated on the copper layer, and a photomask that transmits light is superimposed on the wiring shape thereon, exposed to ultraviolet rays, and unexposed portions are removed with a developer to form. As the chemical etching solution, a chemical etching solution used for a normal wiring board, such as a solution of cupric chloride and hydrochloric acid, a ferric chloride solution, a solution of sulfuric acid and hydrogen peroxide, and an ammonium persulfate solution can be used. Moreover, when a metal layer is comprised from a some metal, it can etch, combining a suitable etching liquid, respectively.

(Wiring formation by semi-additive method)
On the metal layer formed by the above-described method, a plating resist is formed in a necessary pattern, and wiring can be formed by electrolytic plating through the metal layer. Thereafter, the plating resist is peeled off, and finally the metal layer is removed by etching or the like to form a wiring. The semi-additive method is efficient and preferable because interlayer connection and wiring formation can be performed simultaneously.

(Wiring formation by additive method)
The wiring can also be formed by plating only a necessary portion on the surface of the core substrate 100, and a wiring forming technique by normal plating can be used. For example, after depositing a metal layer, which is a catalyst for electroless plating, on an insulating layer, a plating resist is formed on the surface portion where plating is not performed, and is immersed in an electroless plating solution and covered with the plating resist. Electroless plating is performed only on areas that do not exist. Thereafter, if necessary, the plating resist can be removed. Furthermore, a wiring having a height of 5 to 50 μm can be formed by electrolytic plating.

(Wiring shape)
The shape of the wiring is not particularly limited, but at least a semiconductor chip connection terminal (wire bond terminal, etc.) is mounted on the side where the semiconductor chip is mounted, and an external connection terminal (solder ball, etc.) electrically connected to the motherboard on the opposite side Are installed), a developed wiring connecting them, an interlayer connection terminal, and the like. The wiring arrangement is not particularly limited, but as shown in FIG. 2 (inner layer wiring, interlayer connection terminals, etc. are omitted), a fan-in type in which external connection terminals are formed inside the semiconductor chip connection terminals, 3 may be a fan-out type in which external connection terminals are formed outside the semiconductor chip connection terminals as shown in FIG. 3, or a combination of these.

  FIG. 2 is a plan view of a fan-in type semiconductor chip mounting substrate according to an embodiment of the present invention. FIG. 3 is a plan view of a fan-out type semiconductor chip mounting substrate according to another embodiment of the present invention. In the figure, reference numeral 13 denotes a semiconductor package region. In the case of the flip chip type, 14 is a die bond film adhesion region, and 15 is a semiconductor chip mounting region. Reference numeral 16 denotes a semiconductor chip connection terminal. In the case of the wire bond type, 17 is a die bond film adhesion region, and 18 is a semiconductor chip mounting region. Reference numeral 19 is an external connection terminal, and 20 is a developed wiring. Further, if necessary, a dummy pattern 21 that is not electrically connected to the semiconductor chip can be formed. The shape and arrangement of the dummy pattern are not particularly limited, but it is preferable to arrange the dummy pattern uniformly in the semiconductor mounting region. As a result, voids are less likely to occur when a semiconductor chip is mounted with a die bond adhesive, and reliability can be improved.

(Formation of insulation coating)
An insulating coating can be formed on the external connection terminal side of the semiconductor chip mounting substrate. The pattern can be formed by printing if it is a varnish-like material, but it is preferable to use a photosensitive solder resist, a coverlay film, or a film-like resist in order to ensure higher accuracy. As a material, an epoxy-based material, a polyimide-based material, an epoxy acrylate-based material, or a fluorene-based material can be used. Since such an insulating coating has shrinkage at the time of curing, if it is formed only on one side, a large warp tends to occur on the substrate. Therefore, an insulating coating can be formed on both surfaces of the semiconductor chip mounting substrate as necessary. In this case, since the warpage varies depending on the thickness of the insulating coating, it is more preferable to adjust the thickness of the insulating coating on both sides so that no warpage occurs experimentally. Furthermore, since the thermal expansion coefficient of the insulating coating is generally large, it is preferable to form such an insulating coating only on the outside of the semiconductor package region of the frame when the insulating coating is formed on the semiconductor chip mounting side. . The thickness of the insulating coating is preferably 5 to 50 μm, more preferably 10 to 30 μm. If the thickness exceeds 50 μm, the thickness of the entire semiconductor chip mounting substrate becomes thick, and if it is less than 5 μm, there may be a problem in insulation.

(Plating of wiring)
Nickel and gold plating can be sequentially applied to necessary portions of the wiring. Furthermore, nickel, palladium, or gold plating may be used as necessary. These platings are generally applied to semiconductor chip connection terminals of wiring and external connection terminals for electrical connection with a mother board or other semiconductor package. For this plating, either electroless plating or electrolytic plating may be used. Further, if necessary, it can be simultaneously applied to the surface of the metal pattern such as an exposed wiring, a dummy pattern, or a reinforcing pattern.

(Manufacturing process of semiconductor chip mounting substrate)
The semiconductor chip mounting substrate of the present invention can be manufactured by the following processes. 4A to 4H are schematic cross-sectional views showing an example of an embodiment according to the method for manufacturing a semiconductor chip mounting substrate of the present invention. However, the order of the manufacturing process is not particularly limited as long as it does not depart from the object of the present invention.

(Process a)
(Step a) is a step of forming the first wiring 106a on the core substrate 100 as shown in FIG. For example, an etching resist having a first wiring shape can be formed on the core substrate 100 having a copper layer formed on one side, and can be manufactured by a subtracting method using an etching solution such as copper chloride or iron chloride. In order to produce a copper layer on a glass substrate, it can be obtained by sputtering, vapor deposition, plating or the like. The first wiring 106a includes a first interlayer connection terminal 101 and a semiconductor chip connection terminal (a portion electrically connected to the semiconductor chip, not shown), and an additive method is used as a method for forming a fine wiring. Alternatively, the semi-additive method can be used.

(Process b)
(Step b) is a step of forming a first via hole 102 for connecting the first interlayer connection terminal and a second wiring to be described later, as shown in FIG. 4B. The via hole can be formed using laser light when the core substrate 100 is a non-photosensitive substrate. The laser beam to be used is not limited, and a carbon dioxide laser, a YAG laser, an excimer laser, or the like can be used. When the core substrate 100 is a photosensitive base material, a region other than the via hole is masked, and the via hole portion is irradiated with ultraviolet light. Thereafter, via holes are formed by heat treatment and etching. Further, when the core substrate 100 is a base material that can be directly etched, it can be formed by etching. The formed via hole can be filled with a conductive paste or plating in order to electrically connect the layers to form a conductive layer for interlayer connection.

(Process c)
(Step c) is a step of forming the second wiring 106b on the surface of the core substrate 100 opposite to the first wiring 106a, as shown in FIG. 4C. A copper layer is formed on the surface opposite to the first wiring of the core substrate 100 in the same manner as in the step (a), an etching resist is formed on the copper layer in a necessary wiring shape, and an etching solution such as copper chloride or iron chloride. Then, the second wiring is formed by the subtract method. The copper layer can be formed by sputtering, vapor deposition, plating, etc., as in (Step a). Note that the second wiring includes the second interlayer connection terminal 103, and an additive method or a semi-additive method can be used as a method for forming the fine wiring.

(Process d)
(Step d) is a step of forming a build-up layer (insulating layer) 104 as an insulating layer on the surface on which the second wiring is formed as shown in FIG. On the surface of the core substrate 100 and the surface of the second wiring 106b, build-up is performed by laminating and forming the varnish-like insulating material, spin coating, or laminating or pressing the film-like insulating material as described above. A layer (insulating layer) 104 can be obtained. When the insulating material includes a thermosetting material, the insulating material is further cured by heating. The heating conditions should just select the conditions suitable for material, and the conditions which a curvature and a twist do not generate | occur | produce after hardening are preferable.

  Before forming the buildup layer (insulating layer) 104, it is preferable to form a film (not shown) containing a coupling agent such as a silane coupling agent on the surface of the second wiring 106b. The film containing the coupling agent can improve the adhesion reliability between the surface of the second wiring 106b and the buildup layer (insulating layer) 104. The coupling agent used is preferably a silane coupling agent, for example, the silane coupling agent has a functional group such as an epoxy group, amino group, mercapto group, imidazole group, vinyl group, or methacryl group in the molecule, A solution containing one or a mixture of two or more of these silane coupling agents can be used. As the solvent used for the preparation of the silane coupling agent solution, water, alcohol, ketones or the like can be used. A small amount of acid such as acetic acid or hydrochloric acid can be added to promote hydrolysis of the coupling agent. The content of the coupling agent is 0.01 wt% to 5 wt%, preferably 0.1 wt% to 0.5 wt%, based on the entire solution. The film formation treatment with the coupling agent can be performed by a method of immersing in the coupling agent solution adjusted as described above, spraying the solution, applying, or the like. The core substrate 100 treated with the silane coupling agent is dried by natural drying, heat drying, or vacuum drying. Depending on the type of coupling agent to be used, the core substrate 100 may be washed with water or ultrasonically before drying. Is possible. Furthermore, it is preferable that the surface of the core substrate 100 before the silane coupling agent treatment is appropriately combined with degreasing treatment, alkali treatment, acid treatment, water washing and the like as necessary to clean the surface.

(Process e)
In step (e), a k-layer metal layer 106c1 is formed on the build-up layer (insulating layer) 104 as an adhesive metal layer (a metal layer provided to improve adhesion) as shown in FIG. It is a process to do. The k metal layer 106c1 is preferably a metal for ensuring adhesion between copper and the buildup layer (insulating layer) 104, and can be formed by sputtering, vapor deposition, or the like. Although a metal is not specifically limited, Metals, such as Cr, Ni, Co, Pd, Zr, Zn, Ni / Cr, Ni / Cu, can be used. Further, the thickness of the k metal layer 106c1 is preferably 1 μm (1000 nm) or less, more preferably 5 to 300 nm, and particularly preferably 5 to 100 nm.

(Process f)
(Step f) is a step of removing smear inside the via hole after forming the second via hole 108 on the k-layer metal layer 106c1 as shown in FIG. 4 (f). The formation of the via hole is preferably laser beam processing, and more preferably a carbon dioxide laser. As the smear removal, a dry process, a wet process, or a process using a combination of a dry process and a wet process as necessary can be used. As the dry treatment, plasma treatment, reverse sputtering treatment, or ion gun treatment can be used. Plasma processing includes atmospheric pressure plasma processing, vacuum plasma processing, and RIE processing, and vacuum plasma processing is preferable. For the wet treatment, an oxidizing agent such as chromate or permanganate can be used, but can also be carried out with water, an acid or alkali solution, a solvent, or the like, if necessary. Furthermore, it is also possible to use ultrasonic waves during wet processing. In the treatment using both the dry treatment and the wet treatment, the wet treatment may be performed after the dry treatment, or the dry treatment may be performed after the wet treatment. These selections may be appropriately selected depending on the insulating material to be used.

(Process g)
(Step g) is a step of forming the third wiring 106c on the build-up layer (insulating layer) 104 having the second via hole from which the smear has been removed, as shown in FIG. 4 (g). is there. A semi-additive method is preferable as a process for forming such fine wiring. That is, after a metal layer (not shown) is formed on the k-layer metal layer 106c1, a plating resist is formed in a necessary pattern, and the interlayer connection between the wiring and the second via hole 108 is performed by electrolytic plating through the metal layer. Can be formed simultaneously. Thereafter, the plating resist is peeled off, and finally the k metal layer 106c1 and the metal layer (not shown) are removed by etching or the like, whereby the third wiring 106c can be formed. Since the metal layer (not shown) is for interlayer connection inside the via hole, it is preferable to form the thin film copper layer by sputtering the adhesive metal again and then sputtering 100 to 500 nm using copper as a target. By repeating steps (d) to (g), two or more buildup layers (insulating layers) 104 may be formed as shown in FIG. In this case, the interlayer connection terminal formed on the outermost buildup layer (insulating layer) 104 becomes the external connection terminal 107.

(Process h)
In step (h), as shown in FIG. 4 (h), the next buildup layer (insulating layer) 104 is formed on the surface on which the third wiring 106 c is formed, and the buildup layer (insulating layer) 104 is formed. In this step, a third via hole 105 is formed, and an insulating coating 109 for protecting wirings other than the external connection terminal 107 is formed. As the insulating coating material, a solder resist is preferably used, and a thermosetting type or a photocurable type can be used, but a photocurable type capable of finishing the resist shape with high accuracy is more preferable.

(Shape of semiconductor chip mounting substrate)
The shape of the semiconductor chip mounting substrate is not particularly limited, but is preferably a frame shape as shown in FIG. By making the shape of the semiconductor chip mounting substrate in this way, it is possible to efficiently assemble the semiconductor package. Hereinafter, a preferable frame shape will be described in detail.

  FIG. 5A is an overall plan view showing an example of a frame shape of the semiconductor chip mounting substrate of the present invention, and FIG. 5B is an enlarged view of a broken line part of FIG. As shown in FIG. 5, a block 23 is formed in which a plurality of semiconductor package regions 13 (parts to be a single semiconductor package) are arranged in rows and columns at regular intervals. Further, such a block is formed in a plurality of rows and columns. Although only two blocks are shown in FIG. 5, the blocks may be arranged in a lattice shape as necessary. The space width between the blocks is not particularly limited, but 0.5 to 10 mm is preferable in consideration of effective use of the semiconductor chip mounting substrate. Here, the width of the space between the semiconductor package regions is preferably 50 to 500 μm, and more preferably 100 to 300 μm. Furthermore, it is most preferable that the blade width of the dicer used when the semiconductor package is cut later is made the same. By arranging the semiconductor package region in this way, the semiconductor chip mounting substrate 22 can be effectively used.

  Further, a positioning mark or the like such as the alignment guide hole 11 is preferably formed on the end portion of the semiconductor chip mounting substrate 22, and a pin hole by a through hole is more preferable. The shape and arrangement of the pin holes may be selected so as to match the forming method and the semiconductor package assembly apparatus. Furthermore, it is preferable to form a reinforcing pattern 24 in the space between the semiconductor package regions or outside the block. By forming the reinforcing pattern, the rigidity of the semiconductor chip mounting substrate is improved and the assembly of the semiconductor package is facilitated. In addition, the reinforcing pattern can prevent warping and twisting of the semiconductor chip mounting substrate, and can be formed on both sides of the substrate and further on the inner buildup layer (insulating layer) 104 as necessary. The reinforcing pattern may be separately manufactured and bonded to the semiconductor chip mounting substrate, but is preferably a metal pattern formed at the same time as the wiring formed in the semiconductor package region, and the surface thereof is similar to the wiring. More preferably, nickel or gold is plated or an insulating coating is applied. When the reinforcing pattern is such a metal, it can also be used as a plating lead for electrolytic plating. Moreover, it is preferable to form the cutting position alignment mark 25 at the time of cutting with a dicer outside the block. In this way, a semiconductor chip mounting substrate can be manufactured.

(Semiconductor package)
The semiconductor package includes the semiconductor chip mounting substrate, the semiconductor chip mounted on the semiconductor chip mounting substrate, and a resin that seals at least the face surface of the semiconductor chip.

  FIG. 6 is a schematic cross-sectional view showing an example of an embodiment of the flip chip type semiconductor package of the present invention. As shown in FIG. 6, the semiconductor package of the present invention is such that the semiconductor chip 111 is further mounted on the semiconductor chip mounting substrate of the present invention, and the semiconductor chip and the semiconductor chip connection terminal are connected using the connection bumps 112. It can be obtained by electrical connection by flip-chip connection. Furthermore, in these semiconductor packages, it is preferable to seal between the semiconductor chip and the semiconductor chip mounting substrate with an underfill material 113 such as a thermosetting resin, as illustrated. It is preferable that the thermal expansion coefficient of the underfill material approximates the thermal expansion coefficient of the semiconductor chip and the core substrate 100. More preferably, (thermal expansion coefficient of the semiconductor chip) ≦ (thermal expansion coefficient of the underfill material) ≦ (thermal expansion coefficient of the core substrate). Furthermore, the semiconductor chip can be mounted using an anisotropic conductive film (ACF) or an adhesive film (NCF) that does not contain conductive particles. In this case, there is no need for a step of sealing with an underfill material, which is efficient. Furthermore, it is more preferable to use ultrasonic waves in combination with the semiconductor chip because electrical connection can be performed at a low temperature and in a short time.

For example, solder balls 114 can be used as external connection terminals in order to make electrical connection with the motherboard. For the solder balls, eutectic solder or Pb-free solder is used. As a method for fixing the solder balls to the external connection terminals, an N ₂ reflow apparatus is generally used.

  FIG. 7 shows a cross-sectional view of an embodiment of a wire bond type semiconductor package. Although a general die bond paste can be used for mounting the semiconductor chip, it is more preferable to use a die bond film 117 as shown in FIG. The electrical connection between the semiconductor chip and the semiconductor chip connection terminal is generally performed by wire bonding using a gold wire 115. The semiconductor chip can be sealed by transfer molding using a semiconductor sealing resin 116. The sealing region may seal only a necessary part of the semiconductor chip, but may seal the entire semiconductor package region as shown in FIG. This is a particularly effective method in the case where a plurality of semiconductor package regions are arranged in rows and columns and the substrate and the sealing resin are cut simultaneously with a dicer or the like. Finally, each semiconductor package is cut using a dicer or the like.

EXAMPLES Next, although an Example is given and this invention is further demonstrated, this invention is not limited to these Examples.
(Example 1)
(Process a)
As shown in FIG. 4, a 0.4 mm thick soda glass substrate (thermal expansion coefficient 11 ppm / ° C.) is prepared as the core substrate 100, a 200 nm copper thin film is formed on one side by sputtering, and then 10 μm thick by electrolytic copper plating. Plating was performed to a thickness. Sputtering was performed under the conditions shown below using an equipment model number MLH-6315 manufactured by Nippon Vacuum Technology Co., Ltd. After that, an etching resist is formed in a portion to become the first wiring 106a, and etching is performed using a ferric chloride etchant to form the first wiring 106a (first interlayer connection terminal 101 and semiconductor chip connection terminal (not shown). ).
〔conditions〕
Current: 3.5A
Voltage: 500V
Argon flow rate: 35 SCCM
Pressure: 5 × 10 ⁻³ Torr (4.9 × 10 ⁻² Pa)
Deposition rate: 5 nm / second

(Process b)
A hole having a diameter of 50 μm was formed with a laser until it reached the first interlayer connection terminal from the surface opposite to the first wiring of the glass substrate on which the first wiring was formed. YAG laser LAVIA-UV2000 (manufactured by Sumitomo Heavy Industries, Ltd., trade name) was used as the laser, and the conditions were a frequency of 4 kHz, a shot number of 50, and a mask diameter of 0.4 mm. The obtained hole is filled with conductive paste MP-200V (trade name, manufactured by Hitachi Chemical Co., Ltd.), cured under conditions of 160 ° C. for 60 minutes, and electrically connected to the first interlayer connection terminal of the glass substrate. The first via holes 102 were formed by connection.

(Process c)
In order to electrically connect with the first via hole formed in (Step b), a copper thin film having a thickness of 200 nm is formed on the surface of the glass substrate opposite to the first wiring by sputtering, and then by electrolytic copper plating. Plating was performed to a thickness of 10 μm. Sputtering was performed in the same manner as in (Step a). Further, an etching resist is formed in the shape of the second wiring as in (Step a), and etching is performed using a ferric chloride etchant to include the second wiring 106b (including the second interlayer connection terminal 103). ) Was formed.

(Process d)
After the silane coupling agent treatment is performed on the surface on the second wiring side formed in (Step c) to form a film (not shown) containing the silane coupling agent on the wiring surface, a build-up that is an insulating layer Layer 104 was formed as follows. That is, using an insulating resin material FTF (manufactured by Hitachi Chemical Co., Ltd., trade name), an insulating layer having a thickness of 10 μm is formed by spin coating at 2000 rpm, and the temperature is 50 ° C. for 15 minutes, 100 ° C. for 15 minutes, 150 C. for 15 minutes and 200.degree. C. for 60 minutes, followed by heat curing to obtain a buildup layer 104 as an insulating layer. The buildup layer (insulating layer) 104 had a thermal expansion coefficient of 20 ppm / ° C. and a Young's modulus of 1.5 GPa.

(Process e)
On the build-up layer (insulating layer) 104 formed in (Step d), a 10 nm Ni layer was formed as a k-layer metal layer (adhesive metal layer) 106c1 by sputtering. Sputtering was performed under the conditions shown below using an equipment model number MLH-6315 manufactured by Nippon Vacuum Technology Co., Ltd.
〔conditions〕
Current: 5.0A
Voltage: 350V
Argon flow rate: 35 SCCM
Pressure: 5 × 10 ⁻³ Torr (4.9 × 10 ⁻² Pa)
Deposition rate: 0.3 nm / second

(Process f)
The second via hole 108 having a diameter of 70 μm was formed by laser until the second interlayer connection terminal 103 was reached from the top of the Ni layer which is the k metal layer (adhesive metal layer) 106c1. A carbon dioxide laser ML605GTX (trade name, manufactured by Mitsubishi Electric Corporation) was used as the laser, and the conditions were a frequency of 100 Hz, a shot number of 3, and a mask diameter of 0.9 mm. Next, the atmospheric pressure plasma apparatus AP-T02 (made by Sekisui Chemical Co., Ltd., trade name) was used to remove smear inside the second via hole 108. Plasma was performed under the following conditions.
〔conditions〕
Electrode spacing: 2mm
Oxygen flow rate: 1L / min Voltage: 60V x 90
Time: 5 minutes

(Process g)
In order to form the third wiring 106c and the interlayer connection of the second via hole 108, the Ni layer is 10 nm as the second adhesive metal layer 118 (FIG. 8) by sputtering, and the thin copper layer 119 (FIG. 8) is formed. 200 nm was formed. Sputtering was performed under the conditions shown below using MLH-6315 manufactured by Nippon Vacuum Technology Co., Ltd.
〔conditions〕
(Ni)
Current: 5.0A
Voltage: 350V
Argon flow rate: 35 SCCM
Pressure: 5 × 10 ⁻³ Torr (4.9 × 10 ⁻² Pa)
Deposition rate: 0.3 nm / second (copper)
Current: 3.5A
Voltage: 500V
Argon flow rate: 35 SCCM
Pressure: 5 × 10 ⁻³ Torr (4.9 × 10 ⁻² Pa)
Deposition rate: 5 nm / second

Next, a 20 μm-thick resist layer was formed by a spin coating method using a plating resist PMER P-LA900PM (trade name, manufactured by Tokyo Ohka Kogyo Co., Ltd.). Exposure was performed at 1000 mJ / cm ² , and immersion rocking was performed at 23 ° C. for 6 minutes using PMER developer P-7G to form a resist pattern of L / S = 10 μm / 10 μm. Then, pattern copper plating was performed about 5 micrometers using the copper sulfate plating solution. The plating resist was removed by dipping for 1 minute at room temperature using methyl ethyl ketone. For quick etching of the thin copper layer 119, the k metal layer (adhesive metal layer) 106c1 (Ni layer) and the second adhesive metal layer 118 (Ni layer), CPE-700 (manufactured by Mitsubishi Gas Chemical Co., Ltd., product) The third wiring 106c was formed by immersing and rocking at 30 ° C. for 30 seconds using a 5-fold diluted solution of No. 1). FIG. 8 shows a cross-sectional view of the second via hole portion.

(Process h)
Thereafter, the steps (d) to (step g) are repeated again to form a further outermost layer wiring including the buildup layer (insulating layer) 104 and the external connection terminal 107, and finally a solder resist 109 is formed. The fan-in type BGA semiconductor chip mounting substrate as shown in FIG. 1 (sectional view of one package), FIG. 2 (plan view of one package), and FIG. Produced.

(Process i)
The semiconductor chip 111 on which the connection bumps 112 are formed is applied to the semiconductor chip mounting region of the semiconductor chip mounting substrate manufactured by the above (steps a) to (step h) while applying ultrasonic waves using a flip chip bonder. A large number were installed. Furthermore, an underfill material 113 is injected from the end of the semiconductor chip into the gap between the semiconductor chip mounting substrate and the semiconductor chip, and primary curing is performed at 80 ° C. for 1 hour and secondary curing at 150 ° C. for 4 hours using an oven. went. Next, a lead / tin eutectic solder ball 114 having a diameter of 0.45 mm was fused to the external connection terminal using an N ₂ reflow apparatus. Finally, the semiconductor chip mounting substrate was cut with a dicer equipped with a blade having a width of 200 μm to produce the semiconductor package shown in FIG.

(Example 2)
(Process e)
On the build-up layer (insulating layer) 104 formed in (Step d), a Cr layer of 10 nm was formed as a k-layer metal layer (adhesive metal layer) 106c1 by sputtering. Sputtering was performed under the conditions shown below using an equipment model number MLH-6315 manufactured by Nippon Vacuum Technology Co., Ltd.
〔conditions〕
Current: 5.0A
Voltage: 350V
Argon flow rate: 35 SCCM
Pressure: 5 × 10 ⁻³ Torr (4.9 × 10 ⁻² Pa)
Deposition rate: 0.5 nm / second

(Process g)
CPE-700 (Mitsubishi Gas Chemical Co., Ltd., trade name) diluted 5 times for Cr metal layer (adhesive metal layer) 106c1 by sputtering to form a Cr layer of 10nm and for quick etching of thin copper layer 119 Using a liquid, etching is removed by immersing and shaking at 30 ° C. for 30 seconds, and quick etching of the k metal layer (adhesive metal layer) 106c1 (Cr layer) and the second adhesive metal layer 118 (Ni layer) is performed. (Step g) is the same as in Example 1 except that etching removal was performed by immersing and shaking in an etching solution having a composition of potassium ferricyanide 300 g / L and potassium hydroxide 50 g / L at 30 ° C. for 30 seconds.

(Step a) to (Step h)
Steps other than (Step e) and (Step g) are the same as in the first embodiment, and FIG. 1 (sectional view of one package), FIG. 3 (plan view of one package), and FIG. A wire bond type BGA semiconductor chip mounting substrate as shown in FIG.

(Process i)
Using a die bond film DF-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.) 117 in the semiconductor chip mounting region of the semiconductor chip mounting substrate manufactured by the above (step a) to (step h), the semiconductor chip 111 is formed. Installed as many as needed. Next, using a wire bonder UTC230 (trade name, manufactured by Shinkawa Co., Ltd.), a terminal on the semiconductor chip and a semiconductor chip connection terminal of the semiconductor chip mounting substrate were electrically connected by a gold wire 115 having a diameter of 25 μm. Furthermore, using CEL9200 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a sealing resin 116, the semiconductor chip is integrated into one block 23 shown in FIG. 5 at a pressure of 10 MPa, a temperature of 180 ° C., and a time of 90 seconds. Transfer molded. Next, heat treatment is performed in an oven at a temperature of 180 ° C. for 5 hours to completely cure the sealing resin and the die bond film, and a lead / tin eutectic solder ball 114 having a diameter of 0.45 mm is applied to the external connection terminal as an N ₂ reflow apparatus. Fused. Finally, the sealing resin and the semiconductor chip mounting substrate were simultaneously cut with a dicer equipped with a blade having a width of 200 μm to produce the semiconductor package shown in FIG.

(Comparative Example 1)
(Step e) is omitted, and a fan-in type BGA semiconductor chip mounting substrate and a semiconductor are formed in the same manner as in Example 1 except that via holes are directly formed in the buildup layer (insulating layer) 104 in (Step f). A package was produced.

The following tests were performed on the samples of each semiconductor package manufactured as described above.
(Semiconductor package reliability test)
After each semiconductor package sample was subjected to moisture absorption treatment, 22 samples were reflowed in a reflow oven with an ultimate temperature of 240 ° C. and a length of 2 m under the condition of 0.5 m / min to generate cracks (NG number) ). The results are shown in Table 1. Similarly, 22 semiconductor package samples were mounted on a 0.8mm thick motherboard, and a temperature cycle test was conducted at -55 to 125 ° C for 30 minutes each to check the connection reliability of the solder balls. The number of defects was defined as the NG number, and the results are shown in Table 1.

  Examples 1 and 2 manufactured by the manufacturing method of the present invention are excellent in connection reliability by a reflow test and a temperature cycle test. On the other hand, the comparative example 1 which does not depend on the manufacturing method of this invention is inferior to connection reliability. As described above, according to the substrate manufacturing method of the present invention, the adhesion strength between the resin and the metal (wiring) is not lowered during desmearing, and the reflow resistance and the reliability in the temperature cycle test are improved. Can do. Thus, a semiconductor package with excellent mounting reliability can be manufactured.

It is sectional drawing of the semiconductor chip mounting substrate to which one Embodiment of this invention is applied. It is a top view of the fan-in type semiconductor chip mounting substrate which is one Embodiment of this invention. It is a top view of the fan-out type semiconductor chip mounting substrate which is another embodiment of this invention. (A)-(h) is process drawing which shows one Embodiment of the manufacturing method of the semiconductor chip mounting substrate of this invention. (A) It is the whole top view showing an example of the frame shape of the semiconductor chip mounting substrate of this invention. (B) It is an enlarged view of the broken-line part of (a). 1 is a cross-sectional view of a flip chip type semiconductor package to which an embodiment of the present invention is applied. 1 is a cross-sectional view of a wire bond type semiconductor package to which an embodiment of the present invention is applied. It is sectional drawing of the via hole part of the semiconductor chip mounting substrate to which one Embodiment of this invention is applied.

Explanation of symbols

11 Alignment Guide Hole 13 Semiconductor Package Area 14 Die Bond Film Adhesive Area (Flip Chip Type)
15 Semiconductor chip mounting area (flip chip type)
16 Semiconductor chip connection terminal 17 Die bond film adhesion area (wire bond type)
18 Semiconductor chip mounting area (wire bond type)
19 External connection terminal 20 Expanded wiring 21 Dummy pattern 22 Semiconductor chip mounting substrate 23 Block 24 Reinforcement pattern 25 Cutting alignment mark 100 Core substrate 101 First interlayer connection terminal 102 First via hole 103 Second interlayer connection terminal 104 Build Up layer (insulating layer)
105 third via hole 106a first wiring 106b second wiring 106c third wiring 106c1 k layer metal layer (adhesive metal layer)
107 External connection terminal 108 Second via hole 109 Insulation coating (solder resist)
111 Semiconductor chip 112 Connection bump 113 Underfill material 114 Solder ball 115 Gold wire 116 Sealing resin 117 Die bond film 118 Second adhesive metal (Ni) layer 119 Thin film copper layer 120 Electrolytic copper plating layer

Claims (11)

  A method for manufacturing a multilayer circuit board, comprising a step of forming a metal layer of n (where n is an integer of n ≧ 2) from one or more metals on an insulating layer, wherein k (where k Is an integer satisfying 1 ≦ k ≦ n−1) a step of forming a metal layer, a step of forming an opening in the metal layer and the insulating layer of the k layer, a step of desmearing the inside of the opening, (n−k And a step of further forming a metal layer of the layer.   The method for manufacturing a multilayer circuit board according to claim 1, wherein the desmear process is a process performed by a dry process.   The method of manufacturing a multilayer circuit board according to claim 1, wherein the desmearing process is a process using both a dry process and a wet process.   The method for manufacturing a multilayer circuit board according to claim 1, wherein the step of forming the opening is a step by laser processing.   The method for producing a multilayer circuit board according to claim 1, wherein the step of forming the n metal layers includes a step of forming at least one layer by a dry process.   The method for producing a multilayer circuit board according to claim 1, wherein the step of forming the n metal layers includes a step of forming at least one layer by plating.   The method for manufacturing a multilayer circuit board according to claim 1, wherein the metal layer of the k layer is 1 μm or less.   The manufacturing method of the multilayer circuit board in any one of Claims 1-7 which further has the process of forming the surface roughness of the said insulating layer in 1 micrometer or less by average roughness (Ra).   A multilayer circuit board manufactured by the manufacturing method according to claim 1.   10. A semiconductor chip mounting board using the multilayer circuit board according to claim 9, wherein a semiconductor chip connection terminal is provided on one side of the multilayer circuit board and an external connection terminal is provided on the other side. . 11. A semiconductor package comprising the semiconductor chip mounting substrate according to claim 10, a semiconductor chip mounted in a semiconductor chip mounting area, and a sealing resin for sealing at least a face surface of the semiconductor chip.

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