JP4797407B2 - Wiring substrate manufacturing method, semiconductor chip mounting substrate manufacturing method, and semiconductor package manufacturing method - Google Patents

Description

  The present invention relates to a method for manufacturing a wiring substrate, a method for manufacturing a semiconductor chip mounting substrate, and a method for manufacturing a semiconductor package.

  The development of the information society in recent years has been remarkable, and consumer devices have been reduced in size, weight, performance, and functionality, such as personal computers and mobile phones. Industrial equipment includes wireless base stations, optical communication devices, and servers. In addition, there is a demand for improvement in functions in the same way regardless of whether it is large or small, such as routers and other network-related devices. In addition, with the increase in the amount of information transmitted, the frequency of signals handled tends to increase year by year, and high-speed processing and high-speed transmission technology are being developed. With regard to mounting relations, the development of system-on-chip (SoC), system-in-package (SiP), etc., as new high-density mounting technologies, as well as higher-speed and higher-performance LSIs such as CPUs, DSPs, and various types of memory are actively developed. Has been done.

  For this reason, build-up type multilayer wiring boards have come to be used for semiconductor chip mounting boards and motherboards in order to cope with high frequency, high density wiring, and high functionality. In the formation of high-density fine wiring, the wiring width / wiring interval (hereinafter referred to as L / S) = 50 μm / 50 μm is the limit of wiring that can be formed with high yield by the subtracting method in which wiring is formed by etching. In the formation of finer L / S = 35 μm / 35 μm wiring, a relatively thin metal layer (seed layer) is formed on the surface of the insulating layer, a plating resist is formed thereon, and wiring is formed by electroplating. A semi-additive method in which a seed layer is formed by a soft etching after the plating resist is removed after being formed to have a required thickness has been used. As a method for forming the seed layer, an electroless plating method or a method of laminating a thin metal foil is generally used.

  However, the electroless plating method requires a process of treating the surface of the insulating layer with a physical or chemical method to make the surface hydrophilic and roughened, and also has an adhesive force between the formed metal layer and the insulating layer. Low. Further, there is a problem that etching residue is likely to occur when the seed layer is etched. On the other hand, the method of laminating a thin metal foil has a problem that a thin seed layer cannot be formed because it is difficult to produce a metal foil of 1 μm or less.

  As a method for solving these problems, a method of forming a seed layer of 500 nm or less using a sputtering method has been known for a long time. Furthermore, in order to obtain a high adhesive force between the insulating layer and the seed layer, a method of improving the adhesive force by applying a reverse sputtering process as a pretreatment has been proposed (see Patent Document 1).

When reverse sputtering treatment is performed and the reverse sputtering treatment apparatus (vacuum chamber) uses stainless steel, the stainless steel itself also releases its constituent elements such as Fe, Ni, Co, etc. by the impact of ion particles in the plasma. To do. These released metals are embedded in the insulating layer by the impact of ion particles in the plasma, and a mixed layer composed of a resin and a metal forming the insulating layer is formed in the vicinity of the surface layer of the insulating layer. By forming this mixed layer, it is said that the adhesive force between the insulating layer and the seed layer is improved (see Patent Document 2).
Japanese Patent Laid-Open No. 7-045948 JP 7-335626 A

  However, in the reverse sputtering method as described above, it is difficult to preferentially embed a metal that contributes to improving the adhesive strength in the insulating layer, and the adhesive strength between the insulating layer and the seed layer must be applied for a long time. There was a problem that could not be improved. Furthermore, when the treatment is performed for a long time, there is a problem that the insulation resistance value between wirings to be formed later is lowered. The present invention improves the adhesiveness (peel strength) between an insulating layer and a metal layer, and also ensures insulation reliability between wirings to be formed later, whereby a highly reliable wiring board having a fine wiring (motherboard). And a manufacturing method of a semiconductor chip mounting substrate and a semiconductor package.

That is, the present invention is as follows.
1. In the method of manufacturing a wiring board in which one or more insulating layers and wirings are formed, a step of physically embedding the metal forming the metal layer in the insulating layer after forming the metal layer on the surface of the insulating layer; A method of manufacturing a wiring board, comprising the step of forming a wiring on the surface of the insulating layer.
2. Item 1. The metal layer is made of at least one metal selected from Al, Si, Ti, V, Cr, Mn, Fe, Co, Ni, Zn, Zr, Mo, Pd, and W. The manufacturing method of the wiring board as described in 2 ..
3. Item 3. The method for manufacturing a wiring board according to Item 1 or 2, wherein the step of physically embedding the metal forming the metal layer in the insulating layer is performed in a vacuum.
4). 4. The method for manufacturing a wiring board according to claim 3, wherein the step of physically embedding the metal forming the metal layer in the insulating layer uses a reverse sputtering treatment method.
5. 4. The method for manufacturing a wiring board according to claim 3, wherein the step of physically embedding the metal forming the metal layer in the insulating layer uses an ion gun treatment method.
6). 4. The method for manufacturing a wiring board according to claim 3, wherein the step of physically embedding the metal forming the metal layer in the insulating layer uses a plasma treatment method.
7). Item 3. The method according to any one of Items 3 to 6, wherein the step of forming a metal layer on the surface of the insulating layer and the step of physically embedding the metal forming the metal layer in the insulating layer are performed in a vacuum. A method for manufacturing a wiring board according to claim 1.
8). The step of physically embedding the metal forming the metal layer in the insulating layer is performed in a vacuum, and has a step of further forming a metal layer on the metal layer without taking out from the vacuum. Item 8. A method of manufacturing a wiring board according to any one of Items 3 to 7.
9. Item 9. The method for manufacturing a wiring board according to any one of Items 1 to 8, wherein the metal layer has a thickness of 0.1 nm to 100 nm.
10. Item 10. The method for manufacturing a wiring board according to any one of Items 3 to 9, wherein the step of physically embedding the metal forming the metal layer in the insulating layer is a treatment using an inert gas. .
11. Item 11. The method for manufacturing a wiring board according to any one of Items 1 to 10, further comprising a step of forming a semiconductor chip connection terminal on one surface of the wiring substrate and a step of forming an external connection terminal on the other surface. A method for manufacturing a semiconductor chip mounting substrate.
12 Item 12. A step of preparing a semiconductor chip mounting substrate manufactured by the method for manufacturing a semiconductor chip mounting substrate according to Item 11, a step of mounting a semiconductor chip on the semiconductor chip mounting substrate, and a step of sealing the semiconductor chip with a resin. A method of manufacturing a semiconductor package.

  Improves the adhesion (peel strength) between the insulating layer and the metal layer, and also ensures the insulation reliability between the wirings to be formed later, thereby providing a highly reliable wiring board (motherboard) and semiconductor chip having fine wiring It has become possible to provide a method for manufacturing a mounting substrate and a semiconductor package.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The method for manufacturing a wiring board according to the present invention is the method for manufacturing a wiring board in which one or more insulating layers and wirings are formed, and after the metal layer is formed on the surface of the insulating layer, the metal forming the metal layer is It is characterized by having a step of physically embedding in the insulating layer and a step of forming wiring on the surface of the insulating layer. Hereinafter, a semiconductor chip mounting substrate will be described as an example of a wiring substrate, but the present invention can be similarly applied to other general wiring substrates.

(Insulating layer)
As the insulating layer of the wiring board of the present invention, a thermosetting insulating material, a thermoplastic insulating material, or a mixed insulating material thereof can be used, but the insulating layer is mainly composed of a thermosetting insulating material. Is preferred. Thermosetting insulating materials include phenol resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, silicone resin, resin synthesized from cyclopentadiene, tris (2- Resins containing hydroxyethyl) isocyanurate, resins synthesized from aromatic nitriles, trimerized aromatic dicyanamide resins, resins containing triallyl trimetallate, furan resins, ketone resins, xylene resins, including condensed polycyclic aromatics A thermosetting resin, a benzocyclobutene resin, a norbornene resin, or the like can be used. Examples of the thermoplastic insulating material include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, and liquid crystal polymer. A filler may be added to the insulating material. Examples of the filler include silica, talc, aluminum hydroxide, aluminum borate, aluminum nitride, and alumina. The insulating layer as used in the present invention refers to an insulating substrate, a core substrate, a film, an interlayer insulating layer, a build-up layer, etc., formed using the organic insulating material.

(Metal layer)
The metal layer formed on the insulating layer is preferably a metal having an effect of improving the adhesion between the insulating layer and the metal layer. For example, Al, Si, Ti, V, Cr, Mn, Fe, Co, Ni, Zn, Zr , Mo, Pd, W, and the like can be used, and one or more of these metals can be combined. The thickness of the metal layer is not particularly limited as long as the metal can be physically embedded in the insulating layer, but it is preferably in the range of 0.1 nm to 100 nm because the metal can be embedded efficiently. 0.1 nm to 10 nm is more preferable, and 1 nm to 8 nm is particularly preferable. If the thickness of the metal layer exceeds 100 nm, it is difficult to form a mixed layer. If the thickness is less than 0.1 nm, the insulation resistance value between wirings formed later tends to decrease. Since the thickness of the metal layer is affected by the embedding method and processing conditions, it is preferable to obtain the optimum thickness in advance by experiments or the like.

(Metal layer formation method)
The metal layer can be formed on the insulating layer by sputtering, ion plating, cluster ion beam, chemical vapor deposition (CVD), plating, etc., but in vacuum such as sputtering. The method of doing is more preferable. For example, when the metal layer is formed by sputtering, the sputtering apparatus used can use multipolar sputtering such as bipolar sputtering and tripolar sputtering, magnetron sputtering, RF sputtering, mirrortron sputtering, and reactive sputtering. .

(Method of physically embedding the metal forming the metal layer in the insulating layer)
As a method of physically embedding the metal forming the metal layer in the insulating layer, there are a reverse sputtering treatment method, an ion gun treatment method, a plasma treatment method, a sand blast method, etc., for example, a reverse sputtering treatment method, an ion gun treatment method, etc. A method of processing in a vacuum such as a plasma processing method is more preferable. In these methods, the metal forming the metal layer can be preferentially embedded in the insulating layer, and the adhesive force between the insulating layer and the metal layer can be improved by efficiently forming the mixed layer. . In addition, the gas used in these treatments is preferably an inert gas in order to ensure the adhesive force between the insulating layer, the metal layer, and the metal layer further formed thereon. For example, when Cr is formed as a metal layer, Cr is oxidized by the treatment with oxygen gas, and the adhesive force between the metal layer further formed thereon and Cr is lowered. Examples of the inert gas include rare gas elements such as argon.

  When using a reverse sputtering treatment method, an ion gun treatment method, or a plasma treatment method, the sample may be burned. In that case, you may avoid by the method of inserting an insulator between the electrode of a device, and a sample, or the method of floating a sample in a vacuum. Alternatively, it may be avoided by conducting the device electrode and the metal layer. When using a reverse sputtering treatment method or a plasma treatment method, it may be avoided by changing the frequency of the voltage applied to the electrode of the apparatus.

(Reverse sputtering method)
The reverse sputtering treatment method is a treatment in which gas ions generated in a vacuum are applied to a sample (insulating layer). As a feature, when a metal layer is formed by sputtering, the metal layer can be easily formed and reverse sputtering treatment can be easily performed without taking it out of vacuum.

(Ion gun processing method)
The ion gun treatment is a treatment method in which ionized gas is accelerated and driven into a sample in a vacuum.

(Plasma treatment method)
Plasma treatment is a treatment method in which ions of a plasma gas are applied to a sample. The difference from the reverse sputtering treatment method is that plasma treatment such as alumite treatment can be performed on the vacuum chamber, so that impurities in the mixed layer formed on the sample surface can be reduced.

(Mixed layer)
The mixed layer is a layer made of a resin and a metal forming the insulating layer, and has an effect of improving the adhesive force between the insulating layer and the metal layer. Further, the metal in the mixed layer is Al, Si, Ti, V, Cr, Mn, Fe, Co, Ni, Zn, Zr, Mo, Pd, W, or a combination of one or more of these metals. It is preferable.

  When the metal is contained in the insulating layer, the metal concentration (atom%) in the mixed layer is at least equal to or higher than the metal concentration in the insulating layer, and may be 0.001 atom% or more and 3 atom% or less. Preferably, the content is 0.01 atom% or more and 1 atom% or less. In addition, the metal concentration distribution in the mixed layer varies depending on the treatment method used, but the surface parallel to the metal layer is preferably uniform in order to stabilize the adhesion. On the other hand, it is preferable that the surface perpendicular to the metal layer (depth direction) has a non-uniform metal concentration and is highest on the metal layer side and continuously decreases. If the metal concentration in the mixed layer is less than 0.001 atom%, the effect of improving the adhesiveness is low, and if it exceeds 3 atom%, the insulation resistance value of the mixed layer is lowered, and the insulation resistance value between wirings to be formed later Tends to decrease. The thickness of the mixed layer is not particularly limited, but is preferably 0.01 μm or more and 3 μm or less, and more preferably 0.03 μm or more and 1 μm or less. If the thickness of the mixed layer is less than 0.01 μm, the effect of improving the adhesiveness is low, and if it exceeds 3 μm, the insulation resistance value between wirings formed later tends to decrease.

  When the insulation resistance value is lowered by forming the mixed layer, the insulation layer can be improved by removing the mixed layer after the wiring is formed, if necessary. As a method for removing the mixed layer, a wet treatment method or a dry process treatment method can be used.

(Metal layer further formed on the metal layer)
The metal layer further formed on the metal layer of the seed layer is preferably a metal having a high adhesive force with the metal layer. For example, Al, Si, Ti, V, Cr, Mn, Fe, Co, Ni, Zn, Zr, Mo, Pd, W, Cu and mixed metals thereof are preferable. This further formed metal layer can be used as a seed layer or a wiring layer.

(Semiconductor chip mounting substrate)
FIG. 1 shows a schematic cross-sectional view of one embodiment (two single-sided interlayer insulating layers) of the semiconductor chip mounting substrate of the present invention. Although an embodiment in which an interlayer insulating layer (build-up layer) is formed only on one side will be described here, the interlayer insulating layer may be formed on both sides as shown in FIG. The present invention is also applicable to general wiring boards (single-sided boards, double-sided boards, multilayer boards, build-up boards, etc.).

  For example, as shown in FIG. 1, the semiconductor chip mounting substrate of the present invention has a first wiring 106a including a semiconductor chip connection terminal and a first interlayer connection terminal 101 on a core substrate 100 on which a semiconductor chip is mounted. Is formed. A second wiring 106b including the second interlayer connection terminal 103 is formed on the other side of the core substrate, and the first interlayer connection terminal and the second interlayer connection terminal are connected to the first interlayer connection of the core substrate. It is electrically connected through an IVH (via hole) 102 for use. An interlayer insulating layer 104 is formed on the second wiring side of the core substrate, and a third wiring 106c including a third interlayer connection terminal is formed on the interlayer insulating layer. The three interlayer connection terminals are electrically connected via the second interlayer connection IVH 108.

  When a plurality of interlayer insulating layers are formed, the same structure is stacked, and external connection terminals 107 connected to the mother board are formed on the outermost interlayer insulating layer. The shape of the wiring, the arrangement of each connection terminal, and the like are not particularly limited, and can be appropriately designed for manufacturing a semiconductor chip to be mounted and a target semiconductor package. Further, the semiconductor chip connection terminal and the first interlayer connection terminal can be shared. Furthermore, an insulating coating 109 such as a solder resist can be provided on the outermost interlayer insulating layer as necessary.

(Core substrate)
The material of the core substrate is not particularly limited, but an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, or the like can be used. In consideration of the thermal expansion coefficient and insulation, it is preferable to use ceramic or glass. Among the non-photosensitive glasses, soda-lime glass (component example: SiO ₂ : 65 to 75 wt%, Al ₂ O ₃ : 0.5 to 4 wt%, CaO: 5 to 15 wt%, MgO: 0.5 to _{4wt%, Na 2 O: 10~20wt} %), borosilicate glass (component _{example: SiO 2: 65~80wt%, B} 2 O 3: 5~25wt%, Al 2 O 3: 1~5wt%, CaO: _{5~8wt%, MgO: 0.5~2wt%,} Na 2 O: 6~14wt%, K 2 O: 1~6wt%) , and the like. Also, it includes those containing gold ions and silver ions as a photosensitive agent into Li _{2 O-SiO} 2 based crystallized glass as photosensitive glass.

  As the organic substrate, a substrate or a resin film obtained by laminating a material obtained by impregnating a glass cloth with a resin can be used. As the resin to be used, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used. Thermosetting resins include phenol resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, silicone resin, resin synthesized from cyclopentadiene, tris (2-hydroxyethyl) ) Resin containing isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimetallate, furan resin, ketone resin, xylene resin, thermosetting containing condensed polycyclic aromatic Resin, benzocyclobutene resin, norbornene resin and the like can be used. Examples of the thermoplastic resin include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, and liquid crystal polymer.

  A filler may be added to these resins. Examples of the filler include silica, talc, aluminum hydroxide, aluminum borate, aluminum nitride, and alumina. The thickness of the core substrate is preferably in the range of 100 to 800 μm from the viewpoint of IVH formation, and more preferably in the range of 150 to 500 μm.

(Coefficient of thermal expansion)
As described above, when an interlayer insulating layer is formed on the surface of the core substrate using a thermosetting insulating material, a thermoplastic insulating material resin, or a mixed insulating material thereof, the thermal expansion coefficient of the semiconductor chip and the core substrate It is preferable that the thermal expansion coefficient of the core substrate and the thermal expansion coefficient of the core substrate and the thermal expansion coefficient of the interlayer insulating layer are approximate, but it is not limited to this. Furthermore, when the thermal expansion coefficients of the semiconductor chip, the core substrate, and the interlayer insulating layer are α1, α2, and α3 (ppm / ° C.), it is more preferable that α1 ≦ α2 ≦ α3.

  Specifically, the thermal expansion coefficient α2 of the core substrate is preferably 7 to 13 ppm / ° C, more preferably 9 to 11 ppm / ° C. The thermal expansion coefficient α3 of the interlayer insulating layer is preferably 10 to 40 ppm / ° C, more preferably 10 to 20 ppm / ° C, and particularly preferably 11 to 17 ppm / ° C.

(Young's modulus)
The Young's modulus of the interlayer insulating layer is preferably 1 to 5 GPa from the viewpoint of stress relaxation against thermal stress. It is preferable to add the filler in the interlayer insulating layer by appropriately adjusting the addition amount so that the thermal expansion coefficient of the interlayer insulating layer is 10 to 40 ppm / ° C. and the Young's modulus is 1 to 5 GPa.

(Manufacturing method of semiconductor chip mounting substrate)
The semiconductor chip mounting substrate can be manufactured by a combination of the following manufacturing methods. The order of the manufacturing process is not particularly limited as long as it does not depart from the object of the present invention. The same can be done with a general wiring board.

(Wiring formation method)
The method for manufacturing a wiring board of the present invention includes a step of forming a wiring on the surface of the insulating layer. As a method of forming the wiring, a metal foil is formed on the surface of the core substrate or on the interlayer insulating layer. Method of removing unnecessary parts by etching (subtract method), method of forming wiring by plating only on necessary parts on the core substrate surface or interlayer insulating layer (additive method), on the core substrate surface or interlayer insulating layer There is a method (semi-additive method) in which a seed layer (thin metal layer) is formed on the substrate, a necessary wiring is formed by electrolytic plating, and then the seed layer is removed by etching. The present invention is particularly effective for wiring formation by the subtractive method and the semi-additive method.

(Wiring formation by etching)
Metal foil is formed on the core substrate or the interlayer insulating layer, etching resist is formed on the portions that are to be the wiring of the metal foil, and chemical etching solution is sprayed and sprayed on the portions exposed from the etching resist, thereby removing unnecessary metal foil. Can be removed by etching to form a wiring. For example, when a copper foil is used as the metal foil, an etching resist material that can be used for an ordinary wiring board can be used as the etching resist. For example, a resist ink is silk-screen printed to form an etching resist, or a negative photosensitive dry film for etching resist is laminated on a copper foil, and a photomask that transmits light is superimposed on the wiring shape. Then, an etching resist is formed by exposing with ultraviolet light and removing the unexposed portion with a developer.

(Wiring formation by plating)
Further, the wiring can be formed only by performing plating only on a necessary portion on the core substrate or the interlayer insulating layer, and a wiring forming technique by normal plating can be used. For example, after depositing the electroless plating catalyst on the core substrate, forming a plating resist on the surface portion where plating is not performed, immersing in an electroless plating solution, and only in locations not covered by the plating resist, Electroless plating is performed to form wiring.

(Wiring formation by semi-additive method)
In the wiring formation method by the semi-additive method, a seed layer is formed, a plating resist is formed in a necessary pattern thereon, and wiring is formed by electrolytic copper plating through the seed layer. Thereafter, the plating resist is peeled off, and finally the seed layer is removed by etching or the like to form a wiring.

(Semi-additive seed layer formation method)
In the electroplating process in the semi-additive method, the seed layer requires a thickness that allows a current to flow. There are two methods for forming the seed layer of the semi-additive method on the surface of the core substrate or the interlayer insulating layer, such as vapor deposition or plating, and a method of bonding a metal foil. Also, a subtractive metal foil can be formed by the same method.

(Formation of seed layer by vapor deposition or plating)
The seed layer can be formed by vapor deposition, sputtering, ion plating, cluster ion beam, chemical vapor deposition (CVD), plating, or the like on the core substrate surface or the interlayer insulating layer. . The present invention is a particularly effective means for forming a seed layer by vapor deposition, sputtering, ion plating, cluster ion beam, or chemical vapor deposition. For example, when a base metal and a thin film copper layer are formed by sputtering as a seed layer, the sputtering apparatus used is multipolar sputtering such as bipolar sputtering and tripolar sputtering, magnetron sputtering, RF sputtering, mirrortron sputtering, reaction Sputtering etc. can be used. The target used for sputtering is, for example, Al, Si, Ti, V, Cr, Mn, Fe, Co, Ni, Zn, Zr, Mo, Pd, W, Cu, and alloys thereof in order to ensure adhesion. Alternatively, more layers are used as a base metal and sputtering is performed at 0.1 to 50 nm. Thereafter, a thin film copper layer can be formed by sputtering 100 to 500 nm using copper as a target. Alternatively, it can be formed by electroless copper plating of 0.5 to 3 μm as a seed layer on the surface of the core substrate or on the interlayer insulating layer.

(Method of bonding metal foil)
When the core substrate or the interlayer insulating layer has an adhesive function, the seed layer can also be formed by bonding metal foils by pressing or laminating. However, since it is very difficult to directly bond thin metal foils, methods such as etching after thin metal foils are bonded, methods of peeling the carrier layer after bonding metal foils with carriers, etc. There is. For example, as the former, there is a three-layer copper foil of carrier copper / nickel / thin film copper, and carrier copper may be removed with an alkaline etching solution and nickel with a nickel etching solution. As the latter, a peelable copper foil using aluminum, copper, an insulating film or the like as a carrier can be used, and a seed layer of 5 μm or less can be formed. Alternatively, a 9 to 18 μm thick copper foil may be attached, and the seed layer may be formed by etching so that the thickness is 5 μm or less.

(Wiring shape)
The shape of the wiring is not particularly limited, but at least a semiconductor chip connection terminal 16 (wire bond terminal or the like) is provided on the side on which the semiconductor chip is mounted, and an external connection terminal (solder) electrically connected to the motherboard on the opposite side. A place where a ball or the like is mounted), a developed wiring that connects them, an interlayer connection terminal, and the like. The wiring arrangement is not particularly limited, but as shown in FIG. 3 (inner layer wiring, interlayer connection terminals, etc. are omitted), a fan-in type in which external connection terminals are formed inside the semiconductor chip connection terminals, 4 may be a fan-out type in which external connection terminals are formed outside the semiconductor chip connection terminals as shown in FIG. 4, or a combination of these. FIG. 5 is a plan view of the fan-in type semiconductor chip mounting substrate, and FIG. 6 is a plan view of the fan-out type semiconductor chip mounting substrate. The shape of the semiconductor chip connection terminal 16 is not particularly limited as long as wire bond connection or flip chip connection is possible. Moreover, wire-bond connection and flip-chip connection are possible for both fan-out and fan-in types. Further, if necessary, a dummy pattern 21 (see FIG. 6) that is not electrically connected to the semiconductor chip may be formed. The shape and arrangement of the dummy pattern are not particularly limited, but it is preferable to arrange the dummy pattern uniformly in the semiconductor mounting region. As a result, voids are less likely to occur when a semiconductor chip is mounted with a die bond adhesive, and reliability can be improved.

(Bahia Hall)
Since the semiconductor chip mounting substrate of the present invention has a plurality of wiring layers, via holes for electrically connecting the wirings of the respective layers can be provided. The via hole can be formed by providing a hole for connection in the core substrate or the interlayer insulating layer and filling the hole with a conductive paste, plating or the like. Examples of the hole processing method include mechanical processing such as punching and drilling, laser processing, chemical etching processing using a chemical solution, and dry etching processing using plasma. In addition, as a method for forming a via hole in the interlayer insulating layer, there is a method in which a conductive layer is previously formed on the interlayer insulating layer by a conductive paste or plating, and this is laminated on the core substrate by pressing or the like.

(Formation of insulation coating)
An insulating coating 109 (see FIGS. 1 to 4 and 8) can be formed on the external connection terminal side of the semiconductor chip mounting substrate. The pattern can be formed by printing if it is a varnish-like material, but it is preferable to use a photosensitive solder resist, a coverlay film, or a film-like resist in order to ensure higher accuracy. As a material, an epoxy-based material, a polyimide-based material, an epoxy acrylate-based material, or a fluorene-based material can be used.

  Since such an insulating coating has shrinkage at the time of curing, if it is formed only on one side, a large warp tends to occur on the substrate. Therefore, an insulating coating can be formed on both surfaces of the semiconductor chip mounting substrate as necessary. Furthermore, since the warpage varies depending on the thickness of the insulating coating, it is more preferable to adjust the thickness of the insulating coating on both sides so that no warpage occurs. In that case, it is preferable to conduct preliminary examination and determine the thicknesses of the insulating coatings on both sides. In order to obtain a thin semiconductor package, the thickness of the insulating coating is preferably 50 μm or less, and more preferably 30 μm or less.

(Plating on the wiring surface)
Nickel and gold plating can be sequentially applied to necessary portions of the wiring. Furthermore, nickel, palladium, or gold plating may be used as necessary. These platings are applied to the semiconductor chip connection terminals of the wiring and the external connection terminals for electrical connection with the mother board or other semiconductor package. For this plating, either electroless plating or electrolytic plating may be used.

(Manufacture of semiconductor chip mounting substrates)
Such a semiconductor chip mounting substrate can be manufactured, for example, by the following process. The same can be done with a general wiring board. 2A to 2G are schematic cross-sectional views showing an example of an embodiment of a method for manufacturing a semiconductor chip mounting substrate according to the present invention. However, the order of the manufacturing process is not particularly limited as long as it does not depart from the object of the present invention.

(Process a)
(Step a) is a step of forming the first wiring 106a on the core substrate 100 as shown in FIG. For example, an etching resist having a first wiring shape can be formed on a core substrate having a copper layer formed on one side, and wiring can be formed using an etching solution such as copper chloride or iron chloride. In order to produce a copper layer on a glass substrate, after forming a thin film by sputtering, vapor deposition, plating, etc., a copper layer can be obtained by plating to a desired thickness by electrolytic copper plating. In addition, before forming the wiring, physical vapor deposition by plasma assist (including vapor deposition, sputtering, ion plating, etc.), physical vapor deposition by applying a bias (including vapor deposition, sputtering, ion plating, etc.) ), A sputtering method, a method such as an ion gun that implants metal as ions, a plasma treatment, a heat treatment method, or the like may diffuse the metal to form a mixed layer on the core substrate surface. In addition, after forming a metal layer on the surface of the insulating layer, physical treatment may be performed to form a mixed layer, thereby ensuring adhesion between the insulating layer (core substrate) and the first wiring.

  Note that the first wiring 106a includes the first interlayer connection terminal 101 and the semiconductor chip connection terminal (portion electrically connected to the semiconductor chip), and a semi-additive method is used as a method for forming the fine wiring. Alternatively, the seed layer can be formed by the method of the present invention.

(Process b)
In step (b), as shown in FIG. 2B, a first interlayer connection IVH 102 (via hole) for connecting the first interlayer connection terminal 101 and a second wiring to be described later. Is a step of forming. The via hole can be formed by using laser light when the core substrate is a non-photosensitive substrate. Examples of the non-photosensitive substrate include the non-photosensitive glass described above, but are not limited thereto. In this case, the laser beam to be used is not limited, and a CO ₂ laser, a YAG laser, an excimer laser, or the like can be used. When the core substrate is a photosensitive base material, a region other than the via hole is masked, and the via hole portion is irradiated with ultraviolet light. Examples of the photosensitive base material include the above-described photosensitive glass, but are not limited thereto. In this case, via holes are formed by heat treatment and etching after irradiation with ultraviolet light. Further, when the core substrate is a base material that can be chemically etched by a chemical solution such as an organic solvent, a via hole can be formed by chemical etching. The formed via hole can be filled with a conductive paste or plating to form an electrically conductive layer for interlayer connection in order to electrically connect the interlayer.

(Process c)
Step (c) is a step of forming the second wiring 106b on the surface of the core substrate opposite to the first wiring 106a, as shown in FIG. 2 (c). A copper layer is formed on the surface opposite to the first wiring of the core substrate in the same manner as in the step (a), an etching resist is formed on the copper layer in a necessary wiring shape, and an etching solution such as copper chloride or iron chloride is added The second wiring is formed by using this. As a method for forming a copper layer, after forming a copper thin film as a seed layer by sputtering, vapor deposition, electroless plating, etc., as in (Step a), copper plating is performed to a desired thickness using electrolytic copper plating. A copper layer is obtained.

  Note that the second wiring includes the second interlayer connection terminal 103, and a semi-additive method may be used as a method for forming the fine wiring. Further, after forming a metal layer in the same manner as in (Step a), a physical treatment is performed to form a mixed layer, thereby ensuring adhesion between the insulating layer (core substrate) and the second wiring. Good.

(Process d)
(Step d) is a step of forming an interlayer insulating layer 104 on the surface on which the second wiring is formed as shown in FIG. First, after surface treatment is performed on the surface of the second wiring, an interlayer insulating layer 104 is formed on the surface of the core substrate 100 and the surface of the second wiring 106b. As described above, a thermosetting insulating material, a thermoplastic insulating material, or a mixed insulating material thereof can be used as an insulating material for the interlayer insulating layer 104. However, the thermosetting insulating material is a main component. Is preferred. In the case of a varnish-like insulating material, an interlayer insulating layer can be obtained by printing or spin coating, or in the case of a film-like insulating material, using a technique such as lamination or pressing. In the case where the insulating material includes a thermosetting insulating material, it is preferable to further heat and cure.

(Process e)
(Step e) is a step of forming a second interlayer connection IVH (via hole) 108 in the interlayer insulating layer as shown in FIG. 2 (e). A laser drilling machine can be used. A CO ₂ laser, a YAG laser, an excimer laser, or the like can be used as the type of laser used in the laser drilling machine, but a CO ₂ laser is preferable in terms of productivity and hole quality. Further, when the IVH diameter is less than 30 μm, a YAG laser capable of focusing the laser beam is suitable. In addition, when the interlayer insulating layer is a material that can be chemically etched by a chemical solution such as an organic solvent, a via hole can be formed by chemical etching.

(Process f)
In step (f), as shown in FIG. 2 (f), a third wiring 106c is formed on the interlayer insulating layer in which the second interlayer connection IVH (via hole) 108 is formed. It is. Further, as a process for forming a fine wiring of L / S = 35 μm / 35 μm or less, the above-described semi-additive method is preferable. In this process, a metal layer is formed on the interlayer insulating layer on the interlayer insulating layer in order to ensure adhesion between the interlayer insulating layer and the third wiring 106c. Next, a mixed layer of resin and metal is formed by a method of physically embedding the metal forming the metal layer in the interlayer insulating layer. Next, a seed layer is formed by further forming a metal layer by vapor deposition, sputtering, plating, or the like. Further, a plating resist is formed in a necessary pattern on the seed layer formed by the above-described method, and wiring is formed by electrolytic copper plating through the seed layer. Next, the plating resist is peeled off, and finally the seed layer is removed by etching or the like to form fine wiring. Note that the third wiring 106c includes a second interlayer connection terminal.

  (Step d) to (Step f) may be repeated to form two or more interlayer insulating layers 104 as shown in FIG. In this case, the interlayer connection terminal formed on the outermost interlayer insulating layer becomes the external connection terminal 107.

(Process g)
(Step g) is a step of forming an insulating coating 109 for protecting the wiring and the like other than the external connection terminals as shown in FIG. As the insulating coating material, a solder resist can be used, and a thermosetting type or an ultraviolet curing type can be used, but an ultraviolet curing type capable of finishing the resist shape with high accuracy is preferable.

(Shape of semiconductor chip mounting substrate)
The shape of the semiconductor chip mounting substrate 22 is not particularly limited, but is preferably a frame shape as shown in FIG. By making the shape of the semiconductor chip mounting substrate in this way, it is possible to efficiently assemble the semiconductor package. Hereinafter, a preferable frame shape will be described in detail.

  As shown in FIG. 7, a block 23 is formed in which a plurality of semiconductor package regions 13 (parts to be a single semiconductor package) are arranged in rows and columns at regular intervals. Further, such a block is formed in a plurality of rows and columns. Although only two blocks are shown in FIG. 7, the blocks may be arranged in a lattice shape as necessary. Here, the width of the space between the semiconductor package regions is preferably 50 to 500 μm, and more preferably 100 to 300 μm. Furthermore, it is most preferable that the blade width of the dicer used when the semiconductor package is cut later is made the same.

  By arranging the semiconductor package region in this way, the semiconductor chip mounting substrate can be effectively used. Further, a positioning mark 11 or the like is preferably formed at the end of the semiconductor chip mounting substrate, and more preferably a pin hole by a through hole. The shape and arrangement of the pin holes may be selected so as to match the forming method and the semiconductor package assembly apparatus.

  Furthermore, it is preferable to form a reinforcing pattern 24 in the space between the semiconductor package regions or outside the block. The reinforcing pattern may be separately manufactured and bonded to the semiconductor chip mounting substrate, but is preferably a metal pattern formed at the same time as the wiring formed in the semiconductor package region, and the surface thereof is similar to the wiring. More preferably, nickel or gold is plated or an insulating coating is applied. When the reinforcing pattern is such a metal, it can also be used as a plating lead for electrolytic plating. Moreover, it is preferable to form the cutting position alignment mark 25 at the time of cutting with a dicer outside the block. In this way, the frame-shaped semiconductor chip mounting substrate 22 can be manufactured.

(Semiconductor package)
FIG. 3 is a schematic cross-sectional view showing an example of an embodiment of a flip chip type semiconductor package using the present invention. As shown in FIG. 3, the semiconductor package of the present invention is such that the semiconductor chip 111 is further mounted on the semiconductor chip mounting substrate of the present invention, and the connection bumps 112 are connected between the semiconductor chip and the semiconductor chip connection terminals. It can be obtained by electrical connection by using flip chip connection.

  Further, in these semiconductor packages, it is preferable to seal between the semiconductor chip and the semiconductor chip mounting substrate with an underfill material 113 as shown in the figure. The thermal expansion coefficient of the underfill material is preferably close to the thermal expansion coefficient of the semiconductor chip and the core substrate 100, but is not limited thereto. More preferably, (thermal expansion coefficient of the semiconductor chip) ≦ (thermal expansion coefficient of the underfill material) ≦ (thermal expansion coefficient of the core substrate). Furthermore, the semiconductor chip can be mounted using an anisotropic conductive film (ACF) or an adhesive film (NCF) that does not contain conductive particles. In this case, since it is not necessary to seal with an underfill material, it is more preferable. Furthermore, it is particularly preferable to use ultrasonic waves together with the semiconductor chip because electrical connection can be made at a low temperature and in a short time.

  FIG. 4 shows a cross-sectional view of an embodiment of a wire bond type semiconductor package using the present invention. Although a general die bond paste can be used for mounting the semiconductor chip, it is more preferable to use a die bond film 117. The electrical connection between the semiconductor chip and the semiconductor chip connection terminal is generally performed by wire bonding using a gold wire 115. The semiconductor chip can be sealed by transfer molding using a semiconductor sealing resin 116. In that case, at least the face surface of the semiconductor chip is sealed with a semiconductor sealing resin, but only a necessary portion of the sealing region may be sealed, but the entire semiconductor package region is sealed as shown in FIG. It is more preferable to stop. This is a particularly effective method in the case where a plurality of semiconductor package regions are arranged in rows and columns and the substrate and the sealing resin are cut simultaneously with a dicer or the like.

For example, solder balls 114 can be used as the external connection terminals in order to make electrical connection with the motherboard. For the solder balls, eutectic solder or Pb-free solder is used. As a method for fixing the solder balls to the external connection terminals, an N ₂ reflow device is generally used, but the method is not limited to this.

  In a semiconductor chip mounting substrate in which a plurality of semiconductor package regions are arranged in rows and columns, the semiconductor package region is finally cut into individual semiconductor packages using a dicer or the like.

Example 1
A first embodiment of the present invention will be described with reference to FIGS.
(Process a)
A 0.4 mm thick soda glass substrate (thermal expansion coefficient 11 ppm / ° C.) was prepared as the core substrate 100, a 200 nm copper thin film was formed on one side by sputtering, and then plated to a thickness of 10 μm by electrolytic copper plating. Sputtering was performed under the condition 1 shown below using a load lock type sputtering apparatus model SIH-350-T08 (trade name, manufactured by ULVAC, Inc.). Thereafter, an etching resist is formed in a portion to be the first wiring 106a, and etching is performed using a ferric chloride etchant, thereby the first wiring 106a (including the first interlayer connection terminal 101 and the semiconductor chip connection terminal). Formed.
Condition 1
Power: 500W
Argon flow rate: 100 SCCM
Degree of vacuum: 7.0 × 10 ⁻¹ Pa
Substrate temperature: Room temperature (25 ° C)
Deposition rate: 52 nm / min

(Process b)
An IVH hole having a hole diameter of 50 μm was formed with a laser until it reached the first interlayer connection terminal from the surface opposite to the first wiring of the glass substrate on which the first wiring was formed. YAG laser LAVIA-UV2000 (manufactured by Sumitomo Heavy Industries, Ltd., trade name) was used as the laser, and IVH holes were formed under the conditions of a frequency of 4 kHz, a shot number of 50, and a mask diameter of 0.4 mm. The obtained IVH hole was filled with conductive paste MP-200V (trade name, manufactured by Hitachi Chemical Co., Ltd.), cured at 160 ° C. for 30 minutes, and electrically connected to the first interlayer connection terminal of the glass substrate. The first interlayer connection IVH (via hole) 102 was formed.

(Process c)
In order to electrically connect with the first interlayer connection IVH (via hole) 102 formed in (step b), a 200 nm copper thin film was formed on the surface of the glass substrate opposite to the first wiring by sputtering. After fabrication, plating was performed to a thickness of 10 μm by electrolytic copper plating. Sputtering was performed in the same manner as in (Step a). Further, as in (Step a), an etching resist is formed in the shape of the second wiring, and etching is performed using a ferric chloride etchant to perform the second wiring 106b (including the second interlayer connection terminal 103). Formed.

(Process d)
In the surface on the second wiring side formed in (Step c), as the surface treatment of the wiring, the acid degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) adjusted to 200 ml / L at a liquid temperature of 50 ° C. After immersing for 2 minutes, it was washed with hot water by immersing it in water at a liquid temperature of 50 ° C. for 2 minutes, and further washed with water for 1 minute. Subsequently, after being immersed in a 3.6N aqueous sulfuric acid solution for 1 minute and washed with water for 1 minute, it was immersed in a blackening treatment solution HIST-500 (trade name, manufactured by Hitachi Chemical Co., Ltd.) at 85 ° C. for 30 seconds. Thereafter, it was washed with water for 5 minutes, immersed in a reduction treatment solution HIST-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.) at 40 ° C. for 2 minutes for 40 seconds, and further washed with water for 10 minutes. After passing through this pretreatment step, it was immersed in an aqueous solution adjusted to pH 5 with acetic acid at 25 ° C. for 10 minutes in an aqueous solution adjusted so that the concentration of aminomethyltrimethylsilane was 0.5% by weight. Furthermore, it dried at normal temperature (25 degreeC), without washing with water.

  Next, the interlayer insulating layer 104 was formed as follows. That is, an insulating material varnish of a cyanate ester resin composition was applied on a glass substrate by a spin coating method at a condition of 1500 rpm to form an interlayer insulating layer having a thickness of 20 μm, and then from room temperature (25 ° C.) to 6 ° C. / Heating to 230 ° C. at a heating rate of min and thermosetting by holding at 230 ° C. for 80 minutes, a 15 μm interlayer insulating layer was formed.

(Process e)
An IVH hole having a hole diameter of 50 μm was formed with a laser until reaching the second interlayer connection terminal 103 from the surface of the interlayer insulating layer 104. YAG laser LAVIA-UV2000 (manufactured by Sumitomo Heavy Industries, Ltd., trade name) was used as the laser, and IVH holes were formed under the conditions of a frequency of 4 kHz, a shot number of 20 and a mask diameter of 0.4 mm.

(Process f)
Cr was formed as a metal layer on the interlayer insulating layer 104 by 5 nm sputtering. Sputtering was performed under the condition 2 shown below using a load lock type sputtering apparatus model SIH-350-T08 (trade name, manufactured by ULVAC, Inc.).
Condition 2
Power: 500W
Argon flow rate: 100 SCCM
Degree of vacuum: 7.0 × 10 ⁻¹ Pa
Substrate temperature: Room temperature (25 ° C)
Deposition rate: 34 nm / min

Next, as a method of physically embedding the metal in the interlayer insulating layer, a mixed layer of a cyanate ester resin composition (insulating material) and Cr is formed on the surface of the interlayer insulating layer by reverse sputtering without taking it out of vacuum. Formed. Formation of the mixed layer was confirmed by separately analyzing using XPS (X-ray photoelectron spectroscopy) or SIMS (secondary ion mass spectrometry). The mixed layer has a metal concentration of 0.1 atom% on the surface and continuously decreases in the depth direction, and is 0.01 atom% at a depth of 30 nm, and the metal is confirmed to a depth of 150 nm. . The metal in the mixed layer was mainly Cr. In addition, the reverse sputtering process was performed on condition 3 shown below using the load lock type sputtering apparatus type | mold SIH-350-T08 (The ULVAC, Inc. make, brand name).
Condition 3
Power: 500W
Argon flow rate: 100 SCCM
Degree of vacuum: 7.0 × 10 ⁻¹ Pa
Substrate temperature: Room temperature (25 ° C)
Processing time: 0.5 minutes

Further, a seed layer was prepared by forming a Cr layer of 5 nm and a thin film copper layer of 200 nm by sputtering without taking out from the vacuum. Sputtering was performed under the condition 4 shown below using a load lock type sputtering apparatus type SIH-350-T08 (trade name, manufactured by ULVAC, Inc.).
Condition 4
(Cr)
Power: 500W
Argon flow rate: 100 SCCM
Degree of vacuum: 7.0 × 10 ⁻¹ Pa
Substrate temperature: Room temperature (25 ° C)
Deposition rate: 34 nm / min
(copper)
Power: 500W
Argon flow rate: 100 SCCM
Degree of vacuum: 7.0 × 10 ⁻¹ Pa
Substrate temperature: Room temperature (25 ° C)
Deposition rate: 52 nm / min

Next, a plating resist layer having a thickness of 8 μm was formed on the thin film copper layer by a spin coating method using a plating resist AZ-10XT (trade name, manufactured by Clariant Japan Co., Ltd.). After that, exposure is performed under the condition of 550 mJ / cm ² , and immersion rocking is performed at 23 ° C. for 6 minutes using a developer AZ400K developer (trade name, manufactured by Clariant Japan Co., Ltd.), and a circuit resist of minimum L / S = 5 μm / 5 μm A pattern was formed. Then, pattern copper plating was performed 5 micrometers using the copper sulfate plating solution. The plating resist was removed by dipping for 1 minute at room temperature (25 ° C.) using N-methyl-2-pyrrolidone. As a quick etching of the seed layer, the etching of the thin film copper layer was removed by immersion rocking for 30 seconds at 30 ° C. using a 5-fold diluted solution of CPE-700 (trade name, manufactured by Mitsubishi Gas Chemical Co., Ltd.). In addition, quick etching of the Cr layer was removed by immersion rocking at 30 ° C. for 1 minute with an etching solution having a composition of potassium ferricyanide 300 g / L and potassium hydroxide 50 g / L. As described above, the wiring was formed by the semi-additive method.

(Process g)
Thereafter, steps (d) to (step f) are repeated again to form a further outermost layer wiring including the interlayer insulating layer and the external connection terminal 107, and finally, a solder resist as the insulating coating 109 is formed. A fan-in type BGA semiconductor chip mounting substrate as shown in FIG. 1 (sectional view of one package), FIG. 5 (plan view of one package), and FIG. did.

(Process h)
The semiconductor chip 111 on which the connection bumps 112 are formed is applied to the semiconductor chip mounting region of the semiconductor chip mounting substrate manufactured by the above (steps a) to (step g) while applying ultrasonic waves using a flip chip bonder. A large number were installed. Furthermore, an underfill material 113 is injected from the end of the semiconductor chip into the gap between the semiconductor chip mounting substrate and the semiconductor chip, and primary curing is performed at 80 ° C. for 1 hour and secondary curing at 150 ° C. for 4 hours using an oven. went. Next, a lead / tin eutectic solder ball 114 having a diameter of 0.45 mm was fused to the external connection terminal using an N ₂ reflow apparatus. Finally, the semiconductor chip mounting substrate was cut with a dicer equipped with a blade having a width of 200 μm to produce the semiconductor package shown in FIG.

(Example 2)
A second embodiment of the present invention will be described with reference to FIGS. The second embodiment is a method for producing an insulation resistance test substrate and a peel strength measurement substrate.
(Process a)
As shown in FIG. 9A, a 0.4 mm thick soda glass substrate (thermal expansion coefficient 11 ppm / ° C.) was prepared as the core substrate 100, and an insulating layer (build-up layer) was formed as follows. That is, using an insulating varnish of a cyanate ester resin composition, a spin coating method was applied on a glass substrate under conditions of 1500 rpm to form an insulating layer having a thickness of 20 μm, and then from room temperature (25 ° C.) to 6 ° C. The film was heated to 230 ° C. at a temperature increase rate of / min and held at 230 ° C. for 80 minutes for thermosetting to form a 15 μm build-up layer 104.

(Process b)
Cr was formed as a metal layer on the interlayer insulating layer (build-up layer) 104 by 5 nm sputtering. Sputtering was performed in the same manner as condition 2 shown in (Step f) of Example 1. Next, as a method of physically embedding the metal in the interlayer insulating layer, a mixed layer of a cyanate ester resin composition (insulating material) and Cr is formed on the surface of the interlayer insulating layer by reverse sputtering without taking it out of vacuum. Formed. The reverse sputtering conditions were the same as the condition 3 shown in (Step f) of Example 1. Further, a seed layer was prepared by forming a Cr layer of 5 nm and a thin film copper layer of 200 nm by sputtering without taking out from the vacuum. Sputtering was performed in the same manner as Condition 4 shown in (Step f) of Example 1.

Next, about the board | substrate for an insulation resistance test, the plating resist layer with a film thickness of 8 micrometers was formed on the thin film copper layer with the spin coat method using plating resist AZ-10XT (made by Clariant Japan KK, brand name). . Thereafter, exposure was performed under the condition of 550 mJ / cm ² , and the film was immersed and shaken at 23 ° C. for 6 minutes using a developer AZ400K developer (trade name, manufactured by Clariant Japan Co., Ltd.). The wiring length was 3 mm, L / S = 5 μm / 25 pairs of 5 μm, 7 μm / 7 μm, 10 μm / 10 μm, and 15 μm / 15 μm comb resist patterns were formed. Then, pattern copper plating was performed 5 micrometers using the copper sulfate plating solution. The plating resist was removed by dipping for 1 minute at room temperature (25 ° C.) using N-methyl-2-pyrrolidone. As a quick etching of the seed layer, the etching of the thin film copper layer was removed by immersion rocking for 30 seconds at 30 ° C. using a 5-fold diluted solution of CPE-700 (trade name, manufactured by Mitsubishi Gas Chemical Co., Ltd.). In addition, quick etching of the Cr layer was removed by immersion rocking at 30 ° C. for 1 minute with an etching solution having a composition of potassium ferricyanide 300 g / L and potassium hydroxide 50 g / L. As described above, the comb wiring 106 was formed by the semi-additive method.

  Moreover, about the board | substrate for a peel strength measurement, the plating resist layer with a film thickness of 50 micrometers was formed on the thin film copper layer using plating resist AZ-10XT (Clariant Japan KK make, brand name). Thereafter, exposure, development, and pattern copper plating were performed, and resist peeling and seed layer quick etching were performed to form a pattern wiring having a wiring width of 10 mm and a copper plating thickness of 35 μm. As described above, the wiring was formed by the semi-additive method.

(Process c)
With respect to the insulation resistance test substrate, (step a) was repeated again to further form a build-up layer, and an electrolytic corrosion resistance evaluation substrate having comb-shaped wiring 106 as shown in FIG. 10 was produced.

(Comparative Example 1)
In step (f), a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1 except that reverse sputtering treatment was not performed.

(Comparative Example 2)
(Step f) For fan-in type BGA, as in Example 1, except that the Cr layer was not formed on the interlayer insulating layer and the film thickness of the Cr layer formed after reverse sputtering was 10 nm. A semiconductor chip mounting substrate and a semiconductor package were produced.

(Comparative Example 3)
In (Step b), an insulation resistance test substrate and a peel strength measurement substrate were prepared in the same manner as in Example 2 except that reverse sputtering treatment was not performed.

(Comparative Example 4)
(Process b) In the same manner as in Example 2, except that the thickness of the Cr layer formed after the reverse sputtering treatment was changed to 10 nm without forming the Cr layer on the interlayer insulating layer, and A substrate for measuring peel strength was prepared.

  The reliability test of the following semiconductor packages was performed on Example 1 and Comparative Examples 1 and 2 manufactured as described above, and the results are shown in Table 1. Moreover, the insulation resistance test between wiring was done with respect to Example 2 and Comparative Examples 3-4, and the result was shown to Tables 2-5. Moreover, the peel strength of the copper wiring was measured for Example 2 and Comparative Examples 3 to 4, and the results are shown in Table 6.

(Semiconductor package reliability test)
The semiconductor packages of Example 1 and Comparative Examples 1 and 2 were subjected to moisture absorption treatment under conditions of 121 ° C., 2 atm saturation, and 2 hours, and then placed in a reflow furnace having an ultimate temperature of 240 ° C. and a length of 2 m at 0.5 m / min The sample was run under the conditions of the following, 22 samples were reflowed, and the occurrence of cracks was examined. The results are shown in Table 1.

(Insulation resistance test)
Using the insulation resistance test substrates produced in Example 2 and Comparative Examples 3 to 4, the insulation resistance test between the wirings of the comb pattern was performed with three samples. A digital multimeter model 3457A (trade name, manufactured by Hewlett-Packard Co., Ltd.) was used for the insulation resistance test. The measurement results of each insulation resistance are shown in Table 2 (L / S = 5 μm / 5 μm, 7 μm / 7 μm, 10 μm / 10 μm, 15 μm / 15 μm). The unit of the measurement result was Ω, and the result of 1 GΩ or more was shown as> 10 ⁹ .

(Measurement test for peel strength of copper wiring)
The peel strength (copper wiring peel strength) was measured using the peel strength measurement substrate prepared in Example 2 and Comparative Examples 3-4. The results are shown in Table 3.

  As shown in Examples 1 and 2, in the case of the present invention, the insulation resistance value between the wirings was 1 GΩ or more, and no crack was generated in the reliability test of the semiconductor package. On the other hand, as shown in Comparative Example 1 and Comparative Example 3, when the reverse sputtering treatment was not performed, the insulation resistance test value between the wirings was good, but in the reliability test of the semiconductor package, all Cracks occurred in this sample, and the peel strength (stripping strength of the copper wiring) was as low as 0.2 kN / m or less.

  Further, as shown in Comparative Example 2 and Comparative Example 4, when reverse sputtering treatment was performed without forming a metal layer on the insulating layer, there was no crack in the semiconductor package reliability test, and the peel strength was high. However, the insulation resistance value between the wirings was as low as 100 MΩ or less at any L / S, resulting in failure.

  Therefore, according to the present invention, after forming the metal layer on the insulating layer, the metal that physically forms the metal layer is embedded in the insulating layer, thereby making it possible to bond the insulating layer and the metal layer (peel strength). And the insulation reliability between wirings to be formed later can be secured. Thereby, a highly reliable wiring board (motherboard, semiconductor chip mounting board) having fine wiring and a semiconductor package can be manufactured.

1 is a cross-sectional view of a semiconductor chip mounting substrate to which an embodiment of the present invention is applied. (A)-(g) is process drawing which shows one Embodiment of the manufacturing method of the semiconductor chip mounting substrate of this invention. 1 is a cross-sectional view of a flip chip type semiconductor package to which an embodiment of the present invention is applied. 1 is a cross-sectional view of a wire bond type semiconductor package to which an embodiment of the present invention is applied. The top view of the fan-in type semiconductor chip mounting board | substrate of this invention. The top view of the fan-out type semiconductor chip mounting substrate of this invention. The top view showing the frame shape of the semiconductor chip mounting substrate of this invention. 1 is a cross-sectional view of a semiconductor chip mounting substrate to which an embodiment of the present invention is applied. (A)-(c) is process drawing which shows one Embodiment of the manufacturing method of the board | substrate for an insulation resistance test of this invention, and the board | substrate for a peel strength measurement. The top view of the comb-type wiring of the board | substrate for an insulation resistance test evaluated in one Example of this invention.

Explanation of symbols

11 Positioning mark (Guide hole for positioning)
13 Semiconductor Package Area 14 Die Bond Film Adhesive Area (Flip Chip Type)
15 Semiconductor chip mounting area (flip chip type)
16 Semiconductor chip connection terminal 17 Die bond film adhesion area (wire bond type)
18 Semiconductor chip mounting area (wire bond type)
DESCRIPTION OF SYMBOLS 19 External connection terminal 20 Deployment wiring 21 Dummy pattern 22 Semiconductor chip mounting board 23 Block 24 Reinforcement pattern 25 Cutting alignment mark 100 Core board 101 1st interlayer connection terminal 102 IVH (via hole) for 1st interlayer connection
103 Second interlayer connection terminal 104 Interlayer insulating layer (build-up layer)
105 Third layer connection IVH (via hole)
106 Comb wiring 106a First wiring 106b Second wiring 106c Third wiring 107 External connection terminal 108 Second interlayer connection IVH (via hole)
109 Insulating coating 111 Semiconductor chip 112 Connection bump 113 Underfill material 114 Solder ball 115 Gold wire 116 Semiconductor sealing resin 117 Die bond film

Claims (11)

In the method of manufacturing a wiring board in which one or more insulating layers and wirings are formed, a step of physically embedding the metal forming the metal layer in the insulating layer after forming the metal layer on the surface of the insulating layer; the have a step of forming a wiring on the insulating layer surface, the thickness of the metal layer, the manufacturing method of the wiring substrate, which is a 0.1 nm to 100 nm.   The metal layer is made of at least one metal selected from Al, Si, Ti, V, Cr, Mn, Fe, Co, Ni, Zn, Zr, Mo, Pd, and W. A manufacturing method of the wiring board according to 1.   The method for manufacturing a wiring board according to claim 1, wherein the step of physically embedding the metal forming the metal layer in the insulating layer is performed in a vacuum.   4. The method of manufacturing a wiring board according to claim 3, wherein the step of physically embedding the metal forming the metal layer in the insulating layer uses a reverse sputtering treatment method.   4. The method of manufacturing a wiring board according to claim 3, wherein the step of physically embedding the metal forming the metal layer in the insulating layer uses an ion gun treatment method.   The method for manufacturing a wiring board according to claim 3, wherein the step of physically embedding the metal forming the metal layer in the insulating layer uses a plasma treatment method.   7. The step of forming a metal layer on the surface of the insulating layer and the step of physically embedding the metal forming the metal layer in the insulating layer are performed in a vacuum. The manufacturing method of the wiring board in any one.   The step of physically embedding the metal forming the metal layer in the insulating layer is performed in a vacuum, and has a step of further forming a metal layer on the metal layer without taking out from the vacuum. 8. The method for manufacturing a wiring board according to claim 3, wherein The process for physically embedding a metal forming the metal layer in the insulating layer is a process using an inert gas, wherein the wiring board is manufactured according to any one of claims 3 to 8. Method. A claim 1-9 or method of manufacturing a wiring board according to the steps of forming a semiconductor chip connecting terminal on one surface of the wiring substrate, a step of forming external connection terminals on the other surface further A method for manufacturing a semiconductor chip mounting substrate, comprising: A step of preparing a semiconductor chip mounting substrate manufactured by the method for manufacturing a semiconductor chip mounting substrate according to claim 10 , a step of mounting a semiconductor chip on the semiconductor chip mounting substrate, and a step of sealing the semiconductor chip with a resin. A method of manufacturing a semiconductor package, comprising:

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