JP5691527B2 - Wiring board surface treatment method and wiring board treated by this surface treatment method - Google Patents

Description

  The present invention provides a surface treatment method for an insulating layer and a copper wiring in a wiring board having an insulating layer and a copper wiring formed on at least one main surface of the insulating layer, and further a surface treatment is performed by this surface treatment method. Related to the printed wiring board.

  The development of the information society in recent years is remarkable, and in the field of information processing equipment, there is a demand for improvement in the function of equipment regardless of whether it is large or small. For example, in the field of consumer devices, devices such as personal computers and mobile phones are being reduced in size, weight, performance and functionality. On the other hand, in the field of industrial equipment, wireless base stations, optical communication devices, and network-related equipment such as servers and routers are being studied in the same manner as described above. In addition, as the amount of information transmitted increases, the frequency of signals handled by information processing equipment tends to increase year by year, so that high-speed processing and high-speed transmission technology are being developed. For example, in terms of mounting, the development of system-on-chip (SoC), system-in-package (SiP), etc., as new high-density mounting technologies, along with higher speed and higher functionality of LSIs such as CPUs, DSPs, and various memories Has been done. Under such circumstances, it is necessary to cope with higher frequency, higher density wiring, and higher functionality for the semiconductor chip mounting substrate and the mother board. In recent years, a build-up type multilayer wiring board (hereinafter referred to as “build-up board”) in which fine wiring of line / space (L / S) = 15 μm / 15 μm or less has been used as a representative board. Has been.

  Formation of fine wiring on the substrate is usually performed by a subtractive method or a semi-additive method. In a general wiring formation process by the subtractive method, first, an etching resist is formed on the surface of the copper foil, and then exposure and development are performed to form a resist pattern. Next, an unnecessary copper foil is etched and a resist is removed to form a wiring.

  On the other hand, in the semi-additive method, a thin film copper (seed layer) is first formed on the surface of the insulating layer, then a plating resist is formed on the surface of the seed layer, and then exposure and development are performed to form a resist pattern. . Further, wiring is formed by performing electrolytic copper plating, resist stripping, and seed layer etching.

  In general, it is preferable to apply the latter semi-additive method in forming fine wiring of L / S = 15 μm / 15 μm or less.

  Formation of the seed layer in the semi-additive method is generally achieved by adsorbing palladium on the surface of the insulating layer and depositing electroless copper plating. Therefore, after etching the copper of the seed layer, it is necessary to remove palladium remaining on the surface of the insulating layer between the wirings to ensure insulation reliability between the wirings. In addition, when the insulating layer is multilayered, in order to improve the adhesive force between the insulating layers, the surface of the insulating layer is dissolved by etching or the like after the wiring is formed, and the surface is roughened.

  On the other hand, the build-up substrate is manufactured by alternately repeating the interlayer insulating layer forming step and the wiring forming step after the wiring is formed.

  In addition, an insulating layer such as a solder resist or a coverlay is formed on the outermost surface of the build-up board as necessary in order to protect the wiring other than the terminal portion such as the external connection terminal and the semiconductor chip connection terminal. .

  Therefore, in the build-up substrate, it is important to secure the adhesive strength between the wiring surface and the insulating layer and between the insulating layer and the insulating layer, and further to ensure the insulation reliability between the wirings. In recent years, the demand for fine wiring with L / S = 15 μm / 15 μm or less has been increasing in order to improve the functions of various devices. In order to improve electrical characteristics such as transmission speed in these fine wiring, It is also important to ensure smoothing and wiring accuracy.

  Several insulating layer surface treatment methods and wiring surface treatment methods have been proposed for the purpose of ensuring such various characteristics.

As an example of the insulating layer surface treatment method, a method using desmear treatment is known. The desmear process is a process for removing a resin residue (smear) generated during drilling performed at the time of manufacturing a wiring board. For example, the desmear process includes the following three processing steps (I) to (III). There is.
(I) A swelling step for swelling the surface of the insulating layer as a pretreatment for etching.
(II) An etching step of etching the surface of the insulating layer using an alkaline aqueous solution containing an oxidizing agent such as permanganate as shown in the following chemical reaction formula (1).

(III) A neutralization step of treating with an acidic solution as a post-treatment for reducing and removing permanganic acid.
By performing the desmear process comprised by said (I)-(III) with respect to the surface of a buildup board | substrate, the insulating layer surface between wiring is etched, the insulating layer surface is roughened, and the insulating layer surface Dirt such as smear and remaining palladium can be removed. This method does not remove palladium on the wiring.

  On the other hand, a copper surface treatment method as described below is known as a wiring surface treatment method for securing the adhesive strength between the wiring surface and the insulating layer.

  The first method is a method in which a roughened shape on the order of microns is given to the copper surface by etching, and the adhesive force between the copper surface and the insulating layer is secured by the anchor effect. For example, Patent Document 1 discloses a micron-order rough surface on a copper surface using an aqueous solution containing a main agent composed of an inorganic acid and a copper oxidizing agent and an auxiliary composed of at least one azole and at least one etching inhibitor. A method for imparting a modified shape is disclosed. As another example, Patent Document 2 discloses a method of performing chromate treatment and coupling agent treatment after forming continuous irregularities having a height of 1.5 to 5.0 μm by microetching. .

  In the first method, since an oxidation treatment is performed with an acidic solution containing an oxidizing agent, copper is dissolved by an acid simultaneously with the formation of copper oxide (CuO) by the oxidizing agent, as shown in chemical reaction formula (2) below. (Etching).

  1A and 1B are schematic cross-sectional views showing the state of the copper surface in each step in relation to a first method for imparting a micron-order roughened shape to the copper surface by the etching described above. As shown in FIG. 1A, the copper grain boundary part 200 is etched earlier than other parts, and a unique uneven shape as shown in FIG. 1B is formed. Therefore, as the reaction shown in the chemical reaction formula (2) progresses, the etching of copper progresses and the uneven shape becomes larger.

  The second method is to form fine metallic copper needle crystals by forming a concavo-convex shape with fine copper oxide needle crystals on the copper surface, and to provide a fine metal copper needle crystal to insulate the copper surface from the anchor effect. This is a method of ensuring the adhesive strength with the layer. For example, Patent Document 3 uses an alkaline aqueous solution containing an oxidizing agent such as sodium chlorite, and gives fine acicular crystals of copper oxide to the copper surface by immersing in the aqueous solution at around 80 ° C. Subsequently, a method of providing fine needle-like crystals of metallic copper by performing a reduction treatment using a solution in which at least one amine borane and a boron-based chemical are mixed is disclosed.

  In the second method, CuO is generated by the oxidizing agent as shown in the following chemical reaction formula (3).

  Further, unlike the first method described above, the second method performs treatment using an alkaline solution, and therefore, in terms of the potential-pH relationship, it is almost stable in the state of CuO. FIG. 2: is related with the 2nd method of providing the needle-shaped crystal | crystallization of a fine copper oxide on the copper surface mentioned above, (a1)-(c1) is typical sectional drawing which shows each process, (a2)-( c2) is the elements on larger scale which show typically the state of the copper surface in each process. As shown in FIG. 2 (b2), in this method, first, CuO needle-like crystal irregularities 201 are formed. After that, by performing a reduction treatment, as shown in FIG. 2 (c2), the concavity and convexity 202 of the metallic copper needle crystal is formed.

  In the oxidation treatment according to the chemical reaction formula (3), the reaction proceeds until the entire copper surface is covered with CuO. Therefore, as the copper surface is covered with CuO in a short time, that is, as the oxidation reaction rate increases, uniform and fine irregularities are formed in the CuO needle crystal. On the contrary, when the oxidation reaction rate is slow, non-uniform and partially long needle-like crystals are formed, and unevenness with variations is formed. Usually, in the second method, since the oxidation reaction rate is slow, uneven and partially elongated needle-like crystals 201 and 202 are formed as shown in FIGS. 2 (b2) and (c2).

  The third method is to discretely form a noble metal than copper on the copper surface, oxidize the copper, form irregularities with fine copper oxide needle crystals, and then perform a reduction treatment In this method, nano-level irregularities are formed by needle-like crystals of metallic copper, and the adhesion between the copper surface and the insulating layer is ensured by the anchor effect. Such a method is a method proposed by the present inventors in order to solve the problems in the first and second methods, and is disclosed in Patent Document 4.

  In the third method, the oxidation reaction rate is increased by providing a step of discretely forming noble metals on the copper surface before the oxidation treatment. When metals with different standard electrode potentials are brought into electrical contact as in the third method, more specifically, when noble metals are discretely formed on the copper surface, a metal that is easily oxidized (copper: Cu) Will share the anode and a metal (precious metal) that is difficult to oxidize will share the cathode. As a result, the reaction rate in the subsequent oxidation treatment is increased, and the oxidation is accelerated as compared with the case where copper is treated alone.

  FIG. 3 relates to the third method for imparting nano-level irregularities by the above-described metallic copper needle-like crystals, (a1) to (c1) are schematic cross-sectional views showing the respective steps, and (a2) to ( c2) is the elements on larger scale which show typically the state of the copper surface in each process. When copper is oxidized alone, uneven and partially elongated CuO needle-like crystals are formed as shown in FIG. 2 (b2). On the other hand, when the oxidation treatment is performed after discretely forming the noble metal 203 on the copper surface as shown in FIG. 3 (a1), uniform and fine needle crystals of CuO as shown in FIG. 3 (b2). Asperities 204 are formed. Subsequently, by performing reduction treatment of the CuO needle crystals, fine metal copper needle crystals 205 are formed as shown in FIG.

  In the fourth method, after a metal noble than copper is discretely formed on the copper surface, copper is oxidized to form irregularities due to fine copper oxide needle crystals, and then the copper oxide is converted into an acidic solution. In this method, the surface is melted to give nano level unevenness and the anchoring effect ensures the adhesion between the copper surface and the insulating layer. Such a method has been proposed by the present inventor as a further improved method of the third method, and is disclosed in Patent Document 5.

  In the fourth method, before the oxidation treatment, a step of discretely forming a noble metal on the copper surface, a step of performing an oxidation treatment using an alkaline solution containing an oxidizing agent, and then an acidic solution or a copper complexing agent The step of performing the treatment with the solution containing sucrose is characterized by being continuously performed.

  FIG. 4 is a schematic cross-sectional view showing each step in relation to a fourth method for imparting nano level irregularities by dissolving the above-described copper oxide with an acidic solution, and (a2). ) To (c2) are partial enlarged views schematically showing the state of the copper surface in each step. According to the fourth method, first, similarly to the third method, the noble metal 203 is discretely formed on the copper surface as shown in FIG. 4 (a2). Next, the copper surface is oxidized to form uniform and fine CuO needle crystal irregularities 204 as shown in FIG. 4 (b2). Then, by performing treatment with an acidic solution or a solution containing a copper complexing agent and selectively dissolving CuO, the unevenness of metallic copper that is not a fine needle shape as shown in FIG. 206 will be formed.

  As described above, in the production of a wiring board having a multilayer structure such as a build-up board, the insulation reliability between wirings is ensured, the bonding strength between the wiring surface and the insulating layer, and the bonding strength between the insulating layer and the insulating layer. In order to ensure this, normally, the insulating layer surface treatment by desmear treatment and the wiring surface treatment are performed separately.

JP 2000-282265 A Japanese Patent Laid-Open No. 9-246720 Japanese Patent No. 2656622 JP 2006-249519 A JP 2009-140998 A

  As described above, in the manufacture of a build-up substrate, generally, an insulating layer surface treatment by a desmear process is performed after wiring formation, and then a wiring surface treatment is performed. However, the conventional surface treatment method for the wiring board as described above has problems to be solved as described below, and these problems are obstacles to the application of the conventional surface treatment method to the build-up board for fine wiring. ing.

  First, according to the first method, irregularities of 1.5 to 5 μm are formed on the copper surface with Rz (ten-point average roughness), and an improvement in adhesive strength due to the anchor effect is observed. However, in the formation of fine wiring by the semi-additive method, the unevenness of the wiring surface has a rough shape exceeding 1 μm. Therefore, when a high-speed electric signal is passed through such wiring, the electric signal is generated by the skin effect. The transmission loss tends to increase due to the concentrated flow in the vicinity. Further, when the wiring is L / S = 15 μm / 15 μm or less, it tends to be difficult to maintain the wiring accuracy.

  Next, as in the first method, the second method is a technique for forming irregularities having a surface roughness Rz of 0.1 to 1.5 μm on the wiring surface and securing the adhesive strength by the anchor effect. It is. However, in the second method, the unevenness formed on the surface varies greatly, and when Rz <0.5 μm, the reliability of adhesion with the insulating resin at high temperatures and high humidity tends to decrease. There is. On the other hand, when Rz> 1.0 μm, the transmission loss tends to increase as in the first method. In addition, since the acicular crystals forming the irregularities are intricately entangled, depending on the physical properties such as the viscosity characteristics of the resin, the resin is less likely to be buried in the irregularities of the acicular crystals, and the adhesion reliability at high temperature and high humidity decreases. Tend. Furthermore, since the needle-like crystal of metallic copper with Rz ≧ 0.1 μm is easy to break and it is extremely difficult to perform the processing with the horizontal line, the workability regarding the processing of the thin plate is poor.

  The problems in the first and second methods can be solved by the third method proposed by the present inventors. According to the third method, the noble metal is discretely formed on the copper surface, and then oxidized with an alkaline solution containing an oxidizing agent to form copper oxide, and the surface has Rz of 0.001 to 1 μm. By forming fine irregularities, the adhesive strength between the copper surface and the insulating resin can be improved. In the third method, it is preferable to perform a reduction treatment using an alkaline solution further containing a reducing agent after the oxidation treatment in order to prevent dissolution of the copper oxide needle-like crystals in the through-hole connection plating step. However, since the unevenness obtained by the third method is formed by acicular crystals, the crystals partially overlap each other, and the degree is small compared to the second method, but depending on the viscosity characteristics of the resin, etc. There is a problem that the resin is difficult to be buried in the unevenness of the needle-like crystal. For this reason, the present inventors have proposed a fourth method as a further improved method of the third method. According to the fourth method, in the third method, after forming the copper oxide, the copper oxide is dissolved with an acidic solution to form fine irregularities with Rz of 0.001 to 1 μm on the surface. Therefore, it is possible to improve the adhesive strength between the copper surface and the insulating resin.

  As described above, the fourth method is excellent in that the adhesiveness with the insulating layer can be secured even when the surface roughness of the wiring is low. However, since there are many processing steps as compared with the first and second methods, there is a problem that productivity is inferior, and shortening of the steps is desired.

  As described above, there is a simpler and more effective method for ensuring the insulation reliability between the wirings and for the surface treatment of the wiring board for ensuring the adhesive strength between the wiring surface and the insulating layer and between the insulating layer and the insulating layer. It is desired. Accordingly, an object of the present invention is to improve the problems found in the above conventional methods. More specifically, without forming irregularities exceeding 1000 nm on the wiring surface, it is possible to ensure the insulation reliability between the wirings, and to secure the bonding strength between the wiring surface and the insulating layer and between the insulating layer and the insulating layer, It is an object of the present invention to provide a simple and effective insulating layer and copper wiring surface treatment method capable of shortening the manufacturing process of the wiring substrate, and a wiring substrate excellent in various reliability treated by this surface treatment method.

In order to achieve the above object, the present invention relates to the following items.
A first aspect of the present invention is a method for treating a surface of a wiring board comprising an insulating layer and a copper wiring formed on at least one main surface of the insulating layer, wherein (I) the surface of the insulating layer in the wiring board And (II) a step of forming irregularities on the surface of the copper wiring, wherein the step (I) and a part of the step (II) are simultaneously performed under the same processing conditions. The present invention relates to a surface treatment method for a wiring board.

  Here, the processing step (I) for dissolving the insulating layer surface includes (Ia) a swelling step for swelling the insulating layer surface, (Ib) an etching step for etching the insulating layer surface, and (Ic) the insulating layer. A neutralization step for neutralizing the surface, and the treatment step (II) for forming irregularities on the copper wiring surface is (IIa) a noble metal treatment step for forming a noble metal than copper on the copper wiring surface; (IIb) comprising an oxidation step for oxidizing the copper wiring surface, and (IIc) an acid treatment step for treating the copper wiring surface with an acidic solution, the treatment by the etching step (Ib) and the oxidation step (IIc), And it is preferable to perform simultaneously at least one of the process by the said neutralization process (Ic) and the said acid treatment process (IIc) on the same conditions.

  2nd of this invention is a surface treatment method of the wiring board provided with an insulating layer and the copper wiring formed on at least one main surface of this insulating layer, Comprising: (A) The copper wiring surface in the said wiring board A step of forming a metal nobler than copper, (B) a step of bringing the wiring board into contact with an alkaline solution containing an organic compound, and (C) an alkaline solution containing a permanganate. And (D) following the step (C), the step of bringing the wiring substrate into contact with an acidic solution containing a reducing agent for the permanganic acid. It relates to the processing method.

  Here, the surface treatment method of the 1st or 2nd wiring board of this invention is the process which forms a base metal rather than copper on the copper wiring surface as a post-process, and the process using the solution containing an azole compound And a step of performing at least one treatment selected from the group consisting of treatments using a coupling agent.

  Moreover, it is preferable that a metal more precious than the said copper is a metal selected from the group which consists of gold | metal | money, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium, and iridium.

Moreover, it is preferable that the formation amount of a metal more precious than the said copper is 0.001-40 micromol / dm < ² >.

  Moreover, it is preferable that the surface roughness of the said copper wiring after surface treatment is 1-1000 nm in Rz.

  3rd of this invention is related with the wiring board processed using the surface treatment method of the 1st or 2nd wiring board of this invention.

  According to the present invention, the desmear treatment performed to remove smear and residual palladium on the surface of the insulating layer between the copper wirings and ensure the adhesive strength between the insulating layers, and to secure the adhesive strength between the wiring surface and the insulating layer With respect to the wiring surface treatment to be carried out, a part of the steps in each treatment can be carried out at the same time under the same treatment conditions, so that the steps can be shortened compared with the conventional method in which each treatment is carried out separately. . Furthermore, it is possible to provide a surface treatment method for a wiring board capable of ensuring adhesive strength between a copper wiring surface and an insulating layer and improving various reliability without forming irregularities exceeding 1000 nm on the wiring surface. it can. The surface treatment method for a wiring board according to the present invention is applied to wiring members of various wiring boards such as multilayer printed wiring boards, motherboards such as build-up printed wiring boards, and semiconductor chip mounting boards such as rigid substrates and build-up substrates. Can be preferably used.

FIG. 1 is an explanatory view of a method (first method) for imparting a micron-order roughened shape to a copper surface by etching in relation to a conventional copper surface treatment technique, and (a) and (b) in each step. It is a typical sectional view showing the state of the copper surface. FIG. 2 is an explanatory view of a method (second method) for imparting fine copper oxide needle-like crystals to the copper surface in relation to the conventional copper surface treatment technology. (A1) to (c1) The typical sectional view to show, and (a2)-(c2) are the elements on larger scale which show typically the state of the copper surface in each process. FIG. 3 is an explanatory diagram of a method (third method) for imparting nano-level irregularities with metallic copper needle-like crystals in relation to the conventional copper surface treatment technology. (A1) to (c1) The typical sectional view to show, and (a2)-(c2) are the elements on larger scale which show typically the state of the copper surface in each process. FIG. 4 is an explanatory diagram of a method (fourth method) of dissolving copper oxide with an acidic solution and imparting nano-level irregularities (fourth method) with respect to the conventional copper surface treatment technology, and (a1) to (c1) are Typical sectional drawing which shows each process, and (a2)-(c2) are the elements on larger scale which show typically the state of the copper surface in each process. It is typical sectional drawing which shows an example of the semiconductor chip mounting substrate by this invention. It is typical sectional drawing which shows another example of the semiconductor chip mounting substrate by this invention. It is a top view which shows an example of the fan-in type semiconductor chip mounting board | substrate by this invention. It is a top view which shows an example of the fan-out type semiconductor chip mounting board | substrate by this invention. It is a figure which shows an example of the manufacturing method of the semiconductor chip mounting substrate by this invention, (a)-(g) is typical sectional drawing corresponding to each process. It is a figure which shows an example of the frame-shaped semiconductor chip mounting board | substrate by this invention, (a) is a top view, (b) is the elements on larger scale. It is typical sectional drawing which shows an example of the flip chip type semiconductor package by this invention. It is typical sectional drawing which shows an example of the wire bond type semiconductor package by this invention. It is process drawing which shows an example of the manufacturing method of the evaluation board | substrate for a test by this invention. It is process drawing which shows an example of the manufacturing method of the evaluation board | substrate for a test by this invention. It is a top view which shows the evaluation board | substrate for an electrolytic corrosion test produced in the Example.

  Hereinafter, the present invention will be described more specifically. In the following description, the surface treatment method for a wiring substrate according to the present invention is applied to a semiconductor chip mounting substrate as an example. However, the following description is only one embodiment of the present invention, and in other embodiments, the present invention can be applied as a surface treatment method for a motherboard such as a multilayer printed wiring board and a build-up board.

  The surface treatment method for a wiring board according to the present invention is one of (I) a desmear treatment step for dissolving the insulating layer surface and (II) a treatment step for forming irregularities on the wiring surface, which has been conventionally performed as separate steps. Are performed by the same process. More specifically, in the surface treatment method according to the present invention, the desmear treatment step (I) includes (Ia) a swelling step for swelling the insulating layer surface, (Ib) an etching step for etching the insulating layer surface, and (Ic) insulation. A treatment step (II) for forming irregularities on the copper wiring surface, (IIa) a noble metal treatment step for forming a noble metal than copper on the copper wiring surface, (IIb) And (IIc) an acid treatment step for treating the copper wiring surface with an acidic solution, and a treatment by the etching step (Ib) and the oxidation step (IIb). It is characterized in that at least one of the sum step (Ic) and the acid treatment step (IIc) is carried out simultaneously under the same conditions.

  Moreover, one embodiment of the surface treatment method for a wiring board according to the present invention includes (A) a step of forming a metal nobler than copper on the copper wiring surface of the wiring board, and (B) wiring in an alkaline solution containing an organic compound. A step of contacting the substrate, (C) a step of contacting the wiring substrate with an alkaline solution containing permanganate, and (D) a step of contacting the wiring substrate with an acidic solution containing a reducing agent for permanganic acid.

  The wiring surface roughness after the treatment is preferably 1 to 1000 nm in Rz. Moreover, it is more preferable that it is 1-300 nm by Rz, it is more preferable that it is 1-100 nm by Rz, and it is still more preferable that it is 1-50 nm. If Rz is less than 1 nm, the adhesive force with the insulating resin or the like tends to decrease gradually. On the other hand, when Rz exceeds 1000 nm, there is a tendency that a problem of an increase in transmission loss tends to occur, and there is a tendency that a wiring accuracy after processing is greatly shifted in a fine wiring. In addition, the surface roughness Rz described in the present specification intends a value measured using a contact surface roughness meter, an atomic force microscope (AFM), or the like.

  The unevenness of the wiring surface formed by the surface treatment method for a wiring board according to the present invention is as dense and uniform as the unevenness shape obtained by the fourth conventional copper surface treatment method. However, according to the present invention, the entire process can be shortened by performing part of the desmear process at the same time as the other processes. Here, the expression “dense and uniform” used in the present specification means that the shape of the copper surface was observed with a scanning electron microscope (SEM) or processed with a focused ion beam processing observation apparatus (FIB). Later, when the cross section is observed with a scanning ion microscope (SIM), it means that the unevenness formed by the crystals located on the surface of the metallic copper is dense and the unevenness of the unevenness is small.

  According to the method of the present invention, first, as in the conventional fourth method, the noble metal 203 is discretely formed on the surface of the copper wiring as shown in FIG. 4 (a2). Next, the copper wiring board is immersed in an alkaline solution containing an organic compound to swell the insulating layer. Thereafter, the surface of the insulating layer is etched by performing treatment with an alkaline solution containing a permanganate (oxidant), and at the same time, fine CuO irregularities as shown in FIG. It is formed. Furthermore, it is immersed in an acidic solution containing a reducing agent for permanganic acid, thereby performing a neutralization treatment for reducing and removing permanganic acid, and simultaneously dissolving CuO formed on the surface of the copper wiring with an acid. As a result, fine irregularities as shown in FIG. 4 (c2) are formed. As a result, irregularities are formed on the surface of the insulating layer between the wirings, and palladium adsorbed on the surface of the insulating layer is also removed along with the etching of the insulating layer.

  Next, the surface treatment method for a wiring board according to the present invention will be described in more detail for each process. In the present invention, prior to the treatment in each step, it is preferable to perform a degreasing treatment for cleaning the copper surface, a pickling treatment, or a pretreatment appropriately combining them.

(Step A: Step of forming a metal nobler than copper)
The method of discretely forming a noble metal on the copper wiring surface is not particularly limited, and the noble metal is uniformly dispersed on the copper wiring surface without completely covering the underlying copper wiring surface. Any method may be used as long as it can be applied. For example, methods such as electroless plating, electroplating, displacement plating, spray spraying, coating, sputtering, vapor deposition and the like can be mentioned, and among these, the method by displacement plating is preferable. Displacement plating is a method that uses the difference in ionization tendency between copper and noble metal than copper. By applying such a method, noble metal than copper can be easily and inexpensively dispersed on the copper surface. Can be formed.

  A metal nobler than copper intends a metal having a higher potential than that of copper. Such noble metal is not particularly limited, and a metal selected from gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium and iridium can be used.

The amount of metal that is nobler than copper formed discretely on the copper surface is not particularly limited. However, the formation amount is 0.001 to 40 μmol / dm ² because it is easy to obtain a fine, fine and uniform desirable uneven shape, and it is possible to secure sufficient adhesive strength with the insulating resin. It is preferable that Moreover, the formation amount is more preferably from 0.01~10μmol / dm ^2, and more preferably a 0.1~4μmol / dm ^2. If the formation amount is less than 0.001 μmol / dm ² , it tends to be difficult to form dense and uniform fine irregularities, and if it exceeds 40 μmol / dm ² , the adhesive strength with the insulating resin tends to be lowered. In addition, the amount of metal that was preciously formed on the surface of the copper wiring was discretely formed by dissolving the precious metal on the surface of the copper wiring with aqua regia and quantitatively analyzing the solution with an atomic absorption photometer. Can be obtained by performing The term “discrete” described in the present specification means a state in which the noble metal is not completely covered on the copper wiring surface and the noble metal is dispersed on the copper wiring surface. It is intended not to be limited by the amount. When the formation amount is 0.001 to 40 μmol / dm ^2, it is easy to discretely form noble metals on the copper wiring surface.

(Step B: Step of treating with an alkaline solution containing an organic compound)
The step of bringing the wiring board into contact with the alkaline solution containing the organic compound is for swelling the surface of the insulating layer and promoting the etching of the insulating layer in the next etching step. The organic compound is not particularly limited as long as the insulating layer can be sufficiently swollen. However, when a glycol compound or an ether compound is used, it is preferable because the swelling effect is high. More specifically, ethylene glycol can be used as the glycol compound. As the ether compound, diethylene glycol monobutyl ether can be used.

  Examples of the alkaline solution include those obtained by adding an alkali metal compound or alkaline earth metal compound such as sodium hydroxide, potassium hydroxide or sodium carbonate to a solvent such as water or water treated with an ion exchange resin. Is preferred. The temperature of this solution at the time of carrying out the treatment with an alkaline solution containing an organic compound is not particularly limited. However, in order to sufficiently swell the surface of the insulating layer, the temperature of the solution is preferably 55 to 85 ° C, more preferably 60 to 80 ° C, and particularly preferably 65 to 75 ° C. preferable. In one embodiment of the present invention, a solution obtained by mixing an aqueous sodium hydroxide solution and an organic compound such as 2- (2-butoxyethoxy) ethanol in Step B can be preferably used. Such a solution can also be obtained as a commercial product. In the present invention, for example, a swelling liquid “Circuposit Hole Plip 4123” (trade name) manufactured by Rohm & Haas Electronic Materials Co., Ltd. can be preferably used.

(Process C: Treatment with alkaline solution containing permanganate)
The step of bringing the wiring board into contact with an alkaline solution containing a permanganate is a step of etching the insulating layer surface and forming copper oxide on the copper wiring surface. In this step, palladium on the surface of the insulating layer between the copper wirings is removed, and irregularities for improving adhesion are formed on the surface of the insulating layer. Further, fine needle-like irregularities are formed on the surface of the copper wiring. According to the conventional method in which the surface treatment of the insulating layer and the copper wiring is performed separately, in general, in the desmear treatment for etching the surface of the insulating layer, an alkaline solution containing an oxidizing agent of a transition element such as permanganate is used. The roughening treatment used to form copper oxide on the surface of copper wiring contains oxidizers of typical elements such as chlorate, chlorite, hypochlorite, perchlorate, peroxodisulfate, etc. An alkaline solution is used. And, if an alkaline solution containing an oxidizing agent such as chlorate is used in the desmear process, the etching of the surface of the insulating layer does not proceed and the remaining palladium is removed, and the insulation reliability between the wirings It is known that it is difficult to ensure adhesion between insulating layers. In addition, when an alkaline solution containing permanganate is used in the roughening treatment of the copper wiring surface, it is compared with an alkaline solution containing an oxidizing agent such as chlorate generally used in the roughening treatment. Thus, an alkaline solution containing a permanganate has a small amount of copper oxide, and the copper oxide is deposited unevenly. Therefore, it is generally known that it is difficult to perform surface treatment of copper wiring using an alkaline solution containing permanganate.

  However, in the present invention, since the oxidation reaction rate on the surface of the copper wiring can be increased by discretely forming the noble metal on the surface of the copper wiring, the alkaline solution containing the permanganate is used. In addition, dense and uniform fine irregularities can be formed on the surface of the copper wiring. As the permanganate, sodium permanganate, potassium permanganate and the like can be used. The permanganate concentration of the alkaline solution containing the permanganate is preferably 0.01 to 1 mol / L. Furthermore, it is preferable that it is 0.1-0.8 mol / L, Most preferably, it is 0.3-0.5 mol / L. Moreover, the pH of the solution must be a value indicating alkalinity. Considering the stability of the permanganic acid solution, pH 12 or higher is preferable, and pH 13 or higher is more preferable. In addition, in order to adjust pH, solutions, such as sodium hydroxide and potassium hydroxide, can be used suitably.

  Moreover, the temperature of this solution at the time of performing the process processed with the alkaline solution containing a permanganate is not specifically limited. However, in order to sufficiently etch the insulating layer surface and oxidize the copper wiring surface, the temperature of the solution is preferably 20 to 95 ° C, more preferably 50 to 85 ° C, 60 A temperature of ˜80 ° C. is particularly preferred. Examples of the alkaline solution include those obtained by adding an alkali metal compound or alkaline earth metal compound such as sodium hydroxide, potassium hydroxide or sodium carbonate to a solvent such as water or water treated with an ion exchange resin. Is preferred. In one Embodiment of this invention, the solution obtained by mixing sodium hydroxide aqueous solution and sodium permanganate in the said process C can be used conveniently. Such a solution can also be obtained as a commercial product. In the present invention, for example, a permanganic acid solution “Circuposit MLB Promoter 213” (trade name) manufactured by Rohm & Haas Electronic Materials Co., Ltd. can be used.

(Step D: Step of treating with an acidic solution containing a reducing agent)
By the step of bringing the wiring board into contact with an acidic solution containing a reducing agent for permanganic acid, the surface of the insulating layer can be neutralized and the copper oxide on the surface of the copper wiring can be removed. In this step, permanganic acid on the surface of the insulating layer is neutralized and removed, and acicular copper oxide on the surface of the copper wiring is also removed, thereby forming fine irregularities that are not acicular. The reducing agent is not particularly limited as long as permanganic acid can be neutralized. For example, hydroxylamine sulfate and glyoxal can be used as the reducing agent.

  Moreover, the temperature of this solution at the time of performing the process processed with the acidic solution containing a reducing agent is not specifically limited. However, in consideration of safety in use and in order to satisfactorily perform neutralization treatment by reduction and removal of permanganic acid and selective removal of copper oxide crystals on the surface of the copper wiring, the temperature of the solution is 20 to 20%. 60 ° C is preferable, 35 to 50 ° C is more preferable, and 40 to 45 ° C is particularly preferable. In addition, the treatment time with the above solution may be appropriately determined so that the reduction and removal of permanganic acid and the copper oxide crystals can be selectively removed in consideration of the concentration and temperature of the solution. Acidic solutions include inorganic acids such as sulfuric acid, hydrochloric acid, nitric acid, malic acid and its salts, succinic acid and its salts, citric acid and its salts, glycolic acid and its salts, lactic acid and its salts, tartaric acid and its salts, etc. A solution containing an organic acid can be used. In one embodiment of the present invention, a solution obtained by mixing a sulfuric acid aqueous solution and hydroxylamine sulfate in Step D can be suitably used. Such a solution can also be obtained as a commercial product. In the present invention, for example, a neutralizing solution “Circuposit MLB216-4” (trade name) manufactured by Rohm & Haas Electronic Materials Co., Ltd. can be used.

(Order of each process)
In the above description, “process for forming a metal nobler than copper (step A)” — “process for treatment with alkaline solution containing organic compound (step B)” — “treatment with alkaline solution containing permanganate” Embodiment (step C)) — “step of treating with an acidic solution containing a reducing agent (step D)” in order. However, as another embodiment, the order of the A process and the B process can be reversed. Although any of the embodiments is applied, there is no significant difference in the characteristics after processing. However, since the current desmear processing apparatus sequentially performs the B process, the C process, and the D process as a series of processes, an existing apparatus is used. From the viewpoint that they can be used, it is preferable to perform processing in the order in the former embodiment.

(Process E: Process after Process D)
In this invention, after performing each process in above-mentioned A process-D process, it is desirable to implement the post-process for improving the adhesive strength of a copper wiring surface and an insulating layer continuously. Specifically, (E1) treatment for forming a base metal rather than copper on the copper wiring surface, (E2) treating the copper wiring surface with a solution containing an azole compound, or (E3) a coupling agent By performing post-processing such as processing the surface of the copper wiring, it is possible to further improve the adhesive strength with the insulating layer. These processes (E1), (E2), and (E3) can be performed in combination. Especially, when the process by (E1) is performed, there exists a tendency for the adhesive strength to a soldering resist to improve. Moreover, when the process by (E2) is performed, there exists a tendency for the adhesive strength to a buildup material to improve. Furthermore, when the processes according to (E1) and (E2) are performed in combination, it is possible to improve the adhesion strength to both the solder resist and the build-up material. These are clarified by examples described later. When processing is performed by combining the processes (E1) to (E3), it is preferable to perform the process according to (E1) first. More specifically, it is more preferable to perform the process (E2) or (E3) after the process (E1).

(E1: Process for forming base metal on the copper wiring surface)
After the step D described above, the base metal is formed on the surface of the copper wiring by applying a base metal more than copper to the surface of the copper wiring. However, the copper wiring surface is not necessarily completely covered. Here, the base metal intends a metal having a potential lower than that of copper. Although not bound by theory, it is presumed that the reoxidation of the copper wiring surface can be suppressed and the adhesion strength with the insulating layer can be improved by performing the above-described treatment with the base metal.

  The method for forming the base metal on the copper wiring surface is not particularly limited, but is preferably formed by electroless plating, electroplating, sputtering, vapor deposition, or the like, more preferably formed by electroless plating, and by electroless plating. It is particularly preferable to completely cover the copper wiring surface with a base metal.

  The base metal is not particularly limited, but a metal selected from the group consisting of Cr, Co, Ni, Zn, Sn, Mo and W is preferably used. In particular, Sn, Ni, and Co that can be deposited by electroless plating are preferable, and Sn is particularly preferable. Further, a plurality of base metals may be formed on the surface of the copper wiring. In that case, it is preferable to form Sn on the outermost surface.

  The solution containing Sn that can be used in electroless plating is preferably an acidic solution containing a tin salt and a sulfur compound. Any tin salt may be used as long as it dissolves in an acidic solution, but organic sulfonic acids and chlorides are preferred. The sulfur compound is preferably thiourea, organic sulfide or the like. The acidic solution is preferably an acidic solution containing one or more selected from inorganic acids and organic acids. Although not particularly limited, an acidic solution containing, for example, sulfuric acid, hydrochloric acid, nitric acid, tartaric acid, methanesulfonic acid, paratoluenesulfonic acid and the like is preferable. In addition, you may contain a phosphorus compound.

Further, the amount of base metal formed on the copper wiring surface (averaged layer thickness) is not particularly limited. However, it is preferable to appropriately adjust the formation amount of the base metal in consideration of Rz on the surface of the copper wiring. When the Rz on the copper wiring surface is 1-1000 nm, the base metal formation amount is preferably 0.61 to 305 μmol / dm ² (1 to 500 nm thickness), and the Rz on the copper wiring surface is 1 to 300 nm. The base metal formation amount is preferably 0.61 to 91.5 μmol / dm ² (thickness of 1 to 150 nm). Moreover, when Rz of the copper wiring surface is 1-100 nm or less, it is preferable that the formation amount of a base metal is 0.61-30.5 micromol / dm < ² > (thickness of 1-50 nm), and Rz of a copper wiring surface is In the case of 1 to 50 nm, the base metal formation amount is preferably 0.61 to 15.3 μmol / dm ² (thickness of 1 to 25 nm). By making the base metal formation amount 0.61 μmol / dm ² (1 nm thickness) or more, it becomes easy to suppress reoxidation of the copper wiring. Moreover, it becomes easy to improve adhesive strength with an insulating layer by making the formation amount of a base metal into the said range according to Rz value of the copper wiring surface. When the amount of base metal formed is too large, the anchor effect due to fine irregularities is lowered, and the adhesive strength with the insulating layer tends to be lowered. The amount of the base metal formed discretely on the surface of the copper wiring can be obtained by dissolving the base metal on the surface of the copper wiring with aqua regia and then quantitatively analyzing the dissolved solution with an atomic absorption photometer. .

  Furthermore, the adhesive strength between the copper wiring surface and the insulating layer can be further improved by performing a heat treatment after forming the base metal. The heat treatment is preferably performed at a temperature of 90 to 200 ° C, more preferably 110 to 170 ° C, and particularly preferably 130 to 150 ° C. By heating to a temperature of 90 ° C. or higher, the effect of improving the adhesive strength by the heat treatment is easily exhibited. On the other hand, by controlling the temperature of the heat treatment to 200 ° C. or lower, deterioration of the substrate containing an organic material can be prevented. However, the temperature of the heat treatment may be performed under a high temperature condition exceeding 200 ° C. as long as the substrate material such as an organic material is not affected by deterioration or the like.

  The heat treatment time is not particularly limited as long as a predetermined effect is obtained and the material is not affected by deterioration or the like. For example, the heat treatment time is preferably 20 to 120 minutes, more preferably 40 to 90 minutes. Although it does not specifically limit, when forming Sn as a base metal, it is preferable to implement heat processing over 20-120 minutes at the temperature of 110-170 degreeC after that, at the temperature of 130-150 degreeC, 40 It is more preferable to heat-treat for -90 minutes. After such a heat treatment, a degreasing treatment for cleaning the surface of the copper wiring, a pickling treatment, or a treatment appropriately combining these may be performed. In addition, also when performing the process and the coupling process by the solution containing an azole compound in combination with the process which forms a base metal on the copper wiring surface, it is preferable to carry out after a heat processing.

(E2: Treatment with a solution containing an azole compound)
After the step D described above, the copper wiring surface is treated with a solution containing an azole compound, whereby a layer made of the azole compound is formed on the copper wiring surface. Although not bound by theory, it is presumed that by performing such treatment, reoxidation of the surface of the copper wiring is suppressed and the adhesive strength with the insulating layer can be improved. The azole compound used for the solution containing the azole compound is a heterocyclic 5-membered ring compound containing one or more nitrogen atoms. For example, azole, diazole, triazole and tetrazole, and the solution containing an azole compound may be any solution containing at least one of these azole compounds. Diazole is particularly preferable from the viewpoint of improving the adhesive strength. Further, among diazoles, pyrazole (1,2-diazole) is preferable. In addition, in order to improve adhesive strength, the heterocyclic 5-membered ring structure itself containing nitrogen in an azole compound is important, and the presence or absence of a substituent is not particularly limited.

  In particular, when the treatment described above is performed using pyrazole as the azole compound, the treatment is preferably performed using a solution containing an azole compound having a pH of 7 to 12. Further, it is more preferable to perform the treatment using a solution having a pH of 8 to 11, and it is particularly preferable to perform the treatment using a solution having a pH of 9 to 10.

  In particular, when the treatment described above is performed using imidazole as the azole compound, the treatment is preferably performed using a solution containing an azole compound having a pH of 3 to 9. Furthermore, it is more preferable to process using the solution of pH 4-8, and it is especially preferable to process using the solution of pH 5-7.

  In particular, when the above treatment is performed using triazole and tetrazole as the azole compound, the treatment is preferably performed using a solution containing an azole compound having a pH of 0.1 to 3. Furthermore, it is more preferable to process using the solution of pH 0.1-2, and it is especially preferable to process using the solution of pH 0.1-1.

  The pH of the solution containing the azole compound can be adjusted by appropriately using sodium hydroxide solution, potassium hydroxide solution, hydrochloric acid, sulfuric acid solution, or the like. Buffering agents can be added to adjust the pH. In addition, pH can be measured with a pH meter using a general glass electrode. Specifically, for example, trade name: Model (F-51) manufactured by HORIBA, Ltd. can be used. Phthalate pH standard solution (pH: 4.01), neutral phosphate pH standard solution (pH: 6.86), and borate pH standard solution (pH: 9.18) as pH standard solutions It is obtained by calibrating the pH meter at three points and then measuring the value after the pH meter electrode is put into the solution and stabilized for 2 minutes or more. At this time, both the standard buffer solution and the solution temperature can be set to 25 ° C., for example.

  The concentration of the azole compound in the solution containing the azole compound is preferably 0.1 to 5000 ppm, more preferably 0.5 to 3000 ppm, and particularly preferably 1 to 1000 ppm. The treatment time with the solution containing the azole compound is not particularly limited, but is preferably adjusted as appropriate according to the type and concentration of the azole compound.

(E3: Coupling process)
After the step D described above, the strength of the adhesive with the insulating layer can be improved by treating the copper wiring surface with a coupling agent. In one embodiment of the present invention, it is preferable to perform a coupling treatment after (E1) treatment using a solution containing a base metal or (E2) after treatment with a solution containing an azole compound.

  Examples of the coupling agent used for the coupling treatment include a silane coupling agent, an aluminum coupling agent, a titanium coupling agent, a zirconium coupling agent, and the like, and these are one type or two or more types. May be used in combination. Of these, silane coupling agents are preferable, and the silane coupling agent has a functional group such as an epoxy group, amino group, mercapto group, imidazole group, vinyl group, or methacryl group in the molecule. Is preferred. The coupling agent can be used as a solution containing the same, and the solvent used for the preparation of the coupling agent solution is not particularly limited, but water, alcohol, ketones, etc. can be used. It is. Further, in order to promote hydrolysis of the coupling agent, an acid such as acetic acid or hydrochloric acid can be added in a small amount. The content of the coupling agent is preferably 0.01 to 5% by mass and more preferably 0.1 to 1.0% by mass with respect to the entire coupling agent solution.

  The above-described treatment with various solutions or the method of bringing them into contact with various solutions can be performed by a method of immersing the wiring board in each solution, a method of spraying or applying each solution to the wiring board, or the like. Moreover, although the wiring board processed with each solution is dried by natural drying, heat drying, or vacuum drying, depending on the kind of solution, it is preferable to perform water washing or ultrasonic cleaning before drying.

  The above-described surface treatment method for a wiring board according to the present invention is applicable to various uses such as multilayer printed wiring boards, motherboards such as build-up printed wiring boards, and semiconductor chip mounting boards such as rigid substrates and build-up substrates. It can be applied to a wiring board. Although it does not specifically limit, Embodiment which uses the surface treatment method of the wiring board by this invention below is illustrated.

(Semiconductor chip mounting substrate)
FIG. 5 is a schematic cross-sectional view showing an example of a semiconductor chip mounting substrate according to an embodiment of the present invention. FIG. 5 illustrates a case where two build-up layers (interlayer insulating layers) are formed only on one side of the core substrate 100. However, the build-up layer is not limited to the configuration shown in FIG. 5 and may be formed on both surfaces of the core substrate 100 as shown in FIG. 6 as necessary.

  As shown in FIG. 5, the semiconductor chip mounting substrate includes a semiconductor chip connection terminal (not shown) and a first interlayer connection terminal 101 on a core substrate 100 which is an insulating layer on the side where the semiconductor chip is mounted. One wiring 106a is formed. A second wiring 106 b including a second interlayer connection terminal 103 is formed on the other side of the core substrate 100, and the first interlayer connection terminal 101 and the second interlayer connection terminal 103 are connected to the second interlayer connection terminal 103 of the core substrate 100. Electrical connection is made through one interlayer connection IVH (interstitial via hole) 102. A buildup layer 104 is formed on the second wiring 106 b side of the core substrate 100, and a third wiring 106 c including a third interlayer connection terminal is formed on the buildup layer 104. The second interlayer connection terminal 103 and the third interlayer connection terminal are electrically connected through the second interlayer connection IVH 108.

  When a plurality of build-up layers are formed, the same structure is laminated, and an external connection terminal 107 connected to the motherboard is formed on the outermost build-up layer. The interlayer connection terminals are electrically connected via the third interlayer connection IVH 105. The shape of the wiring, the arrangement of each connection terminal, and the like are not particularly limited, and can be appropriately designed to manufacture a semiconductor chip to be mounted and a target semiconductor package. Further, the semiconductor chip connection terminal and the first interlayer connection terminal 101 can be shared. Furthermore, an insulating coating 109 such as a solder resist can be provided on the outermost buildup layer as necessary.

Hereinafter, although it does not specifically limit, the typical structural member and physical property of a semiconductor chip mounting substrate are demonstrated.
(Core substrate)
The material of the core substrate is not particularly limited, but an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate and the like can be used. In consideration of the thermal expansion coefficient and insulation, it is preferable to use a ceramic substrate or a glass substrate. The glass substrate may be non-photosensitive glass or photosensitive glass. The non-photosensitive glass, soda lime glass (component example SiO _2: 65 to 75 _{wt%, Al} 2 O 3: _0.5~4 wt%, CaO: 5 to 15 wt%, MgO: 0.5 to 4 _wt%, Na 2 O: 10 to 20 wt%), borosilicate glass (component example SiO _2: 65-80 _{wt%, B} 2 O 3: _{5~25 wt%, Al} 2 O 3: _1~5 wt% , CaO: 5 to 8 mass%, MgO: 0.5 to 2 mass%, Na ₂ O: 6 to 14 mass%, K ₂ O: 1 to 6 mass%) and the like. As the photosensitive glass, a Li _{2 O-SiO} 2 based crystallized glass include those containing gold ions and silver ions as a photosensitive agent.

  As the organic substrate, a substrate or a resin film obtained by laminating a material obtained by impregnating a glass cloth with a resin can be used. As the resin to be used, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used, but a thermosetting organic insulating material is preferable. Thermosetting resins include phenolic resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, polybenzimidazole resin, polyamide resin, polyamideimide resin, silicon resin, cyclohexane Resin synthesized from pentadiene, resin containing tris (2-hydroxyethyl) isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimetallate, furan resin, ketone resin, A xylene resin, a thermosetting resin containing a condensed polycyclic aromatic, a benzocyclobutene resin, or the like can be used. Examples of the thermoplastic resin include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, and liquid crystal polymer. A filler may be added to these resins. Examples of the filler include silica, talc, aluminum hydroxide, aluminum borate, aluminum nitride, and alumina. The thickness of the core substrate is preferably 100 to 800 μm from the viewpoint of IVH formation, and more preferably 150 to 500 μm.

(Build-up layer)
The interlayer insulating layer (build-up layer) is made of an insulating material, and a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used as the insulating material. The build-up layer preferably contains a thermosetting organic insulating material as a main component. Thermosetting resins include phenolic resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, polybenzimidazole resin, polyamide resin, polyamideimide resin, silicon resin, cyclohexane Resin synthesized from pentadiene, resin containing tris (2-hydroxyethyl) isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimetallate, furan resin, ketone resin, A xylene resin, a thermosetting resin containing a condensed polycyclic aromatic, a benzocyclobutene resin, or the like can be used. Examples of the thermoplastic resin include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, and liquid crystal polymer. A filler or the like may be added to the insulating material. Examples of the filler include silica, talc, aluminum hydroxide, aluminum borate, aluminum nitride, and alumina.

(Coefficient of thermal expansion)
Regarding the thermal expansion coefficient, it is preferable that the thermal expansion coefficient of the semiconductor chip and the thermal expansion coefficient of the core substrate are approximated, and that the thermal expansion coefficient of the core substrate and the thermal expansion coefficient of the buildup layer are approximated. However, it is not limited to these. Further, when the thermal expansion coefficients of the semiconductor chip, the core substrate, and the buildup layer are α1, α2, and α3 (ppm / ° C.), it is more preferable that α1 ≦ α2 ≦ α3. Specifically, the thermal expansion coefficient α2 of the core substrate is preferably 7 to 13 ppm / ° C, more preferably 9 to 11 ppm / ° C. The thermal expansion coefficient α3 of the buildup layer is preferably 10 to 40 ppm / ° C, more preferably 10 to 20 ppm / ° C, and particularly preferably 11 to 17 ppm / ° C.

(Young's modulus)
The Young's modulus of the buildup layer is preferably 1 to 5 GPa from the viewpoint of stress relaxation against thermal stress. It is preferable to add the filler in the buildup layer by appropriately adjusting the addition amount so that the thermal expansion coefficient of the buildup layer is 10 to 40 ppm / ° C. and the Young's modulus is 1 to 5 GPa.

(Resist)
Examples of the resist include an etching resist, a plating resist, a solder resist, and a coverlay. In order to use the etching resist and the plating resist for the purpose of forming the wiring, the etching resist and the plating resist are peeled off after the wiring is formed and do not remain on the substrate or the like. The solder resist or coverlay is formed on the surface of the substrate as an insulating coating because it is intended to protect wiring other than external connection terminals, semiconductor chip connection terminals, and the like. These resists can be used in liquid or film form, and preferably have photosensitivity.

(Manufacturing method of semiconductor chip mounting substrate)
The above-described semiconductor chip mounting substrate can be manufactured by appropriately combining the methods described below. The order of the manufacturing process is not particularly limited as long as it does not deviate from its purpose.

(Wiring formation method)
As a method of forming wiring when manufacturing a semiconductor chip mounting substrate, a method of forming a metal foil on the surface of a core substrate or a build-up layer and removing unnecessary portions of the metal foil by etching (subtractive method), a core A method in which wiring is formed only by plating on the substrate surface or build-up layer only by the necessary method (additive method), a thin metal layer (seed layer) is formed on the core substrate surface or build-up layer, and then electrolytic plating is performed. There is a method of removing a thin metal layer by etching (semi-additive method) after forming necessary wirings.

(Wiring formation by subtractive method)
An etching resist can be formed at a location to be a wiring on the metal foil, and a chemical etching solution can be sprayed and sprayed onto a portion exposed from the etching resist to remove an unnecessary metal foil to form a wiring. For example, when a copper foil is used as the metal foil, an etching resist material that can be used for a normal wiring substrate can be used as the etching resist. As a method of forming an etching resist, for example, there is a method of forming an etching resist by silk screen printing of a resist ink. Alternatively, a negative photosensitive dry film for etching resist is laminated on copper foil, and a photomask that transmits light is superimposed on the wiring shape on top of it, exposed to ultraviolet light, and unexposed areas are developed. There is also a method of forming an etching resist by removing with a liquid. As the chemical etching solution, a chemical etching solution used for an ordinary wiring board such as a solution of cupric chloride and hydrochloric acid, a ferric chloride solution, a solution of sulfuric acid and hydrogen peroxide, an ammonium persulfate solution, or the like can be used.

(Wiring formation by additive method)
Wiring can be formed by performing plating only on a necessary portion on the core substrate or the build-up layer. For this, a wiring forming technique by normal plating can be used. For example, after depositing the electroless plating catalyst on the core substrate, forming a plating resist on the surface portion where plating is not performed, immersing in an electroless plating solution, and only in locations not covered by the plating resist, Electroless plating is performed to form wiring.

(Wiring formation by semi-additive method)
A seed layer is formed on the surface of the core substrate or the build-up layer, and then a necessary wiring is formed by electrolytic plating, and then the seed layer is removed by etching, whereby the wiring can be formed. For example, a seed layer is formed on the core substrate surface or the buildup layer, a plating resist is formed in a necessary pattern on the formed seed layer, and wiring is formed by electrolytic copper plating through the seed layer. . Thereafter, the plating resist is peeled off, and finally the seed layer is removed by etching or the like, whereby the wiring can be formed. As a method for forming a seed layer used in the semi-additive method, there are a method by sputtering, vapor deposition, plating, and the like, and a method in which a metal foil is bonded. Further, a subtractive metal foil can be formed by the same method.

(Formation of seed layer by sputtering, vapor deposition, plating, etc.)
A seed layer can be formed on the core substrate surface or build-up layer by sputtering, vapor deposition, plating, or the like. For example, when a base metal and a thin film copper layer are formed by sputtering as a seed layer, the sputtering apparatus used to form the thin film copper layer is a bipolar sputtering, a three-pole sputtering, a four-pole sputtering, a magnetron sputtering, a mirror. Tron sputtering or the like can be used. The target used for sputtering uses, for example, a metal such as Cr, Ni, Co, Pd, Zr, Ni—Cr alloy, or Ni—Cu alloy as a base metal in order to ensure adhesion, and a sputtering thickness of 5 to 50 nm. Apply. Thereafter, a seed layer can be formed by sputtering with a thickness of 200 to 500 nm using copper as a target. Further, a seed layer made of plated copper having a thickness of 0.1 to 3 μm may be formed on the core substrate surface or the buildup layer by electroless copper plating. Usually, in electroless copper plating, palladium serving as a catalyst is adsorbed on the surface of an insulating layer to deposit plated copper. The seed layer formed of the plated copper needs to remove palladium remaining on the surface of the insulating layer between the wirings after the copper etching process. Normally, palladium can be removed at the same time as etching of the insulating layer by desmearing the surface of the insulating layer, but such processing needs to be performed separately from the surface treatment of the copper wiring. However, according to the surface treatment method for a wiring board according to the present invention, it is possible to perform the desmear treatment simultaneously with a part of the process of treating the copper wiring surface.

(Method of bonding metal foil)
When the core substrate or the build-up layer has an adhesive function, the seed layer can be formed by bonding metal foils by pressing or laminating. However, since it is very difficult to directly bond a thin metal layer, there are a method in which a thick metal foil is laminated and then thinned by etching or the like, a method in which a carrier-attached metal foil is bonded and a carrier layer is peeled off. . For example, as the former, there is a three-layer copper foil of carrier copper / nickel / thin film copper, and carrier copper can be removed with an alkaline etching solution and nickel can be removed with a nickel etching solution. As the latter, a peelable copper foil using aluminum, copper, an insulating material or the like as a carrier can be used, and a seed layer having a thickness of 5 μm or less can be formed. Alternatively, a seed layer may be formed by attaching a copper foil having a thickness of 9 to 18 [mu] m, and uniformly thinning it so as to have a thickness of 5 [mu] m or less by etching. A plating resist is formed in a necessary pattern on the seed layer formed by these methods, and wiring is formed by electrolytic copper plating through the seed layer. Thereafter, the plating resist is peeled off, and finally the seed layer is removed by etching or the like, whereby the wiring can be formed.

(Wiring shape)
The shape of the wiring is not particularly limited, but at least a semiconductor chip connection terminal (wire bond terminal, etc.) is mounted on the side where the semiconductor chip is mounted, and an external connection terminal (solder ball, etc.) electrically connected to the motherboard on the opposite side Are installed), a developed wiring for connecting them, an interlayer connection terminal, and the like. The wiring arrangement is not particularly limited, but a fan-in type semiconductor in which external connection terminals 19 are formed inside the semiconductor chip connection terminals 16 as shown in FIG. A chip mounting substrate, a fan-out type semiconductor chip mounting substrate in which external connection terminals 19 are formed outside the semiconductor chip connection terminals 16 as shown in FIG. 8, or a combination of these may be used. 7 and 8, 13 is a semiconductor package area, 14 is a die bond film adhesion area (flip chip type), 15 is a semiconductor chip mounting area (flip chip type), and 17 is a die bond film adhesion area (wire bond type). , 18 is a semiconductor chip mounting area (wire bond type), and 20 is a developed wiring. The shape of the semiconductor chip connection terminal 16 is not particularly limited as long as wire bond connection, flip chip connection, and the like are possible. Moreover, wire-bond connection, flip-chip connection, etc. are possible for both fan-out and fan-in types. Furthermore, if necessary, a dummy pattern 21 (see FIG. 8) that is not electrically connected to the semiconductor chip may be formed. The shape and arrangement of the dummy pattern 21 are not particularly limited, but are preferably arranged uniformly in the semiconductor chip mounting region. As a result, voids are less likely to occur when a semiconductor chip is mounted with a die bond adhesive, and reliability can be improved.

(Bahia Hall)
Since the multilayer semiconductor chip mounting substrate has a plurality of wiring layers, via holes for electrically connecting the wirings of the respective layers can be provided. The via hole can be formed by providing a hole for connection in the core substrate or the buildup layer and filling the hole with a conductive paste, plating or the like. Examples of the hole processing method include mechanical processing such as punching and drilling, laser processing, chemical etching processing using chemicals, and dry etching using plasma. In addition, as a method for forming a via hole in the buildup layer, there is a method in which a conductive layer is formed on the buildup layer in advance using a conductive paste, plating, or the like, and this is stacked on the core substrate by pressing or the like.

(Formation of insulation coating)
An insulating coating can be formed on the external connection terminal side of the semiconductor chip mounting substrate. The pattern can be formed by printing if it is a varnish-like material, but it is preferable to use a photosensitive solder resist, a coverlay film, or a film-like resist in order to ensure higher accuracy. As a material, an epoxy-based material, a polyimide-based material, an epoxy acrylate-based material, or a fluorene-based material can be used. Since such an insulating coating has shrinkage at the time of curing, if it is formed only on one side, a large warp tends to occur on the substrate. Therefore, an insulating coating can be formed on both surfaces of the semiconductor chip mounting substrate as necessary. Furthermore, since the warpage varies depending on the thickness of the insulating coating, it is more preferable to adjust the thickness of the insulating coating on both sides so that no warpage occurs. In that case, it is preferable to conduct preliminary examination and determine the thicknesses of the insulating coatings on both sides. In order to obtain a thin semiconductor package, the thickness of the insulating coating is preferably 50 μm or less, and more preferably 30 μm or less.

(Plating of wiring)
Nickel and gold plating can be sequentially applied to necessary portions of the wiring. Furthermore, nickel, palladium, or gold plating may be used as necessary. These platings are applied to the semiconductor chip connection terminals of the wiring and the external connection terminals for electrical connection with the mother board or other semiconductor package. For this plating, either electroless plating or electrolytic plating may be used.

  Hereinafter, a method for manufacturing a semiconductor chip mounting substrate will be described as an embodiment of the present invention. FIG. 9 is a diagram showing an example of a method for manufacturing a semiconductor chip mounting substrate according to the present invention, and (a) to (g) are schematic cross-sectional views corresponding to the respective steps. However, the order of the steps shown in the figure is not particularly limited as long as it does not depart from the object of the present invention.

(Process a)
Step (a) is a step of forming the first wiring 106a on the core substrate 100 as shown in FIG. 9 (a). In the formation of the first wiring 106a, for example, a pretreatment process is performed in which the copper layer of the core substrate 100 having a copper layer formed on one surface is degreased and then washed with hydrochloric acid or sulfuric acid. As shown in FIG. 9, when it is not assumed that the surface on which the first wiring 106a is formed is built up, the roughening process on the copper layer surface is usually unnecessary in the step (a). However, if necessary, the copper layer surface may be roughened by a conventional method as follows.

  First, as required, a metal selected from gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osnium, and iridium, which are noble metals than copper, is formed discretely. Next, an oxidation reaction is performed by immersing in an alkaline aqueous solution containing an oxidizing agent. Thereafter, a treatment with an acidic solution or a solution containing a copper complexing agent is further performed. Then, if necessary, at least one of a coupling treatment and a treatment with a solution containing an azole compound is performed, or after a treatment with a solution containing a base metal rather than copper, the coupling treatment and the azole compound are performed. You may provide the post-process process which performs at least 1 process of the process by the solution containing this. Regardless of the presence or absence of the post-treatment step, it is desirable that the surface of the wiring is treated so that Rz is 1 to 1000 nm by the above-described surface treatment step of the copper layer. Thereafter, an etching resist is formed in the shape of the first wiring 106a on the surface-treated copper layer as necessary, and an etching solution such as copper chloride, iron chloride, sulfuric acid-hydrogen peroxide, nitric acid-hydrogen peroxide, or the like. The first wiring 106a can be manufactured by etching the copper layer and removing the etching resist. Formation of the copper layer on the core substrate 100 is possible by forming a copper thin film by sputtering, vapor deposition, plating, or the like and then performing electrolytic copper plating until a desired thickness is achieved. Note that the first wiring 106a includes a first interlayer connection terminal 101 and a semiconductor chip connection terminal (portion electrically connected to the semiconductor chip), and a semi-additive method is used as a method for forming the fine wiring. Is preferred. Further, after the first wiring 106a is formed on the core substrate 100, a protective film (not shown) is immediately laminated on the surface of the first wiring 106a. By laminating the protective film, it is possible to prevent the first wiring 106a from being affected by the plating process or the like in the steps after the step (b).

(Process b)
In the step (b), as shown in FIG. 9B, a first interlayer connection IVH 102 for connecting the first interlayer connection terminal 101 and a second wiring 106b described later is formed. It is. When the core substrate 100 is a non-photosensitive substrate, the hole to be the first interlayer connection IVH 102 is formed by irradiating a laser beam such as a CO ₂ laser, a YAG laser, or an excimer laser to the hole. Can do. From the viewpoint of productivity and hole quality, it is preferable to use a CO ₂ laser. When the hole diameter is less than 30 μm, a YAG laser capable of focusing the laser beam is suitable. In addition, examples of the non-photosensitive substrate include, but are not limited to, the non-photosensitive glass described above. Further, when the core substrate 100 is a photosensitive base material, a region other than the portion serving as the first interlayer connection IVH 102 is masked and irradiated with ultraviolet light, and then holes are formed by heat treatment and etching. In addition, as a photosensitive base material, although photosensitive glass etc. which were mentioned above are mentioned, it is not limited to this. In addition, when the core substrate 100 is a base material that can be chemically etched by a chemical solution such as an organic solvent, holes can be formed by chemical etching. After the holes are formed, desmear treatment is performed as necessary to electrically connect the layers, and then the holes are made conductive by conductive paste, plating, etc., and the first IVH 102 for interlayer connection is formed. To do.

(Process c)
Step (c) is a step of forming the second wiring 106b on the surface of the core substrate 100 opposite to the first wiring 106a, as shown in FIG. 9C. The second wiring 106b can be formed on the surface of the core substrate 100 opposite to the first wiring 106a in the same manner as the first wiring 106a in the step (a). As a method for forming the copper layer, as in the step (a), after forming a copper thin film by sputtering, vapor deposition, plating or the like, electrolytic copper plating is performed until a desired thickness is obtained. Note that the second wiring 106b includes the second interlayer connection terminal 103, and a semi-additive method is preferably used as a method for forming the fine wiring.

(Process d)
Step (d) is a step of forming a buildup layer (interlayer insulating layer) 104 on the surface on which the second wiring 106b is formed, as shown in FIG. 9 (d). Here, first, it is preferable to provide a pretreatment step in which the surface of the second wiring 106b is degreased and washed with hydrochloric acid or sulfuric acid. Next, a roughening process is performed on the surface of the copper layer. In the embodiment in which the wiring is formed after filling the paste for the interlayer connection IVH formed in the previous step (b) and forming the copper layer by sputtering, there is no palladium under the copper layer. It is not necessary to perform a desmear treatment before the roughening treatment, and a conventional roughening treatment method for the copper surface can be applied. However, in the case of an embodiment in which IVH is made conductive or a copper layer is formed by electroless plating, since the palladium adheres to the insulating layer surface before the electroless copper plating, the roughening treatment for the copper layer surface Prior to this, desmear processing is required. Therefore, in the latter embodiment, it is preferable to apply the surface treatment method for a wiring board according to the present invention that can simultaneously perform desmearing and roughening of the wiring surface.

  More specifically, the surface treatment method according to the present invention is more specifically (A) a metal selected from gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium and iridium on the surface of the copper wiring. (B) an alkaline aqueous solution containing a permanganate, wherein a metal noble than at least one selected copper is discretely formed, and the insulating layer is swollen by immersing it in an alkaline aqueous solution containing (B) an organic compound. The surface of the insulating layer is dissolved and roughened by immersing in copper, and the surface of the copper wiring is oxidized and oxidized. (D) The surface of the insulating layer is neutralized and immersed in an acidic solution containing a reducing agent for permanganic acid. This can be done by removing the copper oxide on the surface. After performing the surface treatment, if necessary, after performing at least one treatment of a coupling treatment and a treatment containing a solution containing an azole compound or a treatment containing a base metal rather than copper You may provide the post-processing process which performs at least 1 process of the process by a coupling process and the solution containing an azole compound. Regardless of which treatment is performed, it is preferable that the roughness Rz of the copper wiring surface be 1-1000 nm.

  Next, the buildup layer 104 is formed on the surface of the core substrate 100 and the surface of the second wiring 106b. As the insulating material for the build-up layer 104, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used as described above, but the thermosetting material is preferably a main component. The buildup layer 104 can be formed by printing, spin coating or the like when the insulating material is varnished. Further, when the insulating material is in the form of a film, it can be performed by laminating or pressing. When the build-up layer 104 is formed by laminating, it may be sandwiched between upper and lower end plates like a press. When the insulating material includes a thermosetting material, it is desirable to further heat and cure.

(Process e)
The step (e) is a step of forming a hole for forming the second interlayer connection IVH 108 in the buildup layer 104 as shown in FIG. 9 (e). It can be performed in the same manner as the first interlayer connection IVH 102 in the step (b).

(Process f)
In the step (f), as shown in FIG. 9F, the third wiring 106c is formed on the buildup layer 104 in which the hole for forming the second interlayer connection IVH 108 is formed, and the IVH 108 is formed. This is a step of conducting. The semi-additive method described above is preferable as a process for making the IVH 108 conductive and forming fine wiring with L / S = 15 μm / 15 μm or less. Specifically, the aforementioned seed layer is formed on the buildup layer 104 and in the IVH 108 by electroless plating. In this case, a plating resist is formed on the seed layer in a necessary pattern, wiring is formed by electrolytic copper plating through the seed layer, the plating resist is peeled off, and finally the seed layer is removed by etching or the like. Thus, a fine wiring can be formed. Next, each process is performed in accordance with the surface treatment method for a wiring board according to the present invention. More specifically, if necessary, a degreasing treatment and a pretreatment for washing with hydrochloric acid or sulfuric acid are performed. (A) On the surface of the copper wiring, gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium and At least one kind of metal selected from metals selected from iridium is discretely formed, and (B) the insulating layer is swollen by immersing it in an alkaline aqueous solution containing an organic compound; The insulating layer surface is dissolved and roughened by dipping in an alkaline aqueous solution containing manganate, and the copper wiring surface is oxidized, and (D) the insulating layer is dipped in an acidic solution containing a reducing agent for permanganic acid. Neutralize the surface and remove copper oxide on the copper wiring surface. Thereafter, if necessary, at least one treatment of a coupling treatment and a treatment with a solution containing an azole compound is performed, or after a treatment with a solution containing a base metal rather than copper, the coupling treatment and the azole compound are performed. You may provide the post-process process which performs at least 1 process of the process by the solution containing. Regardless of the presence or absence of the post-treatment step, it is preferable that the surface of the wiring has an Rz of 1 to 1000 nm.

  Note that the steps (d) to (f) may be repeated to produce two or more buildup layers 104 as shown in FIG. In this case, the interlayer connection terminal formed in the outermost buildup layer becomes the external connection terminal 107. Thereafter, a solder resist is formed on portions other than the external connection terminals 107, and the external connection terminals 107 are exposed. The external connection terminal 107 is electrically connected to the third wiring through the third interlayer connection IVH 105.

  As an embodiment of the present invention, an example of a method for manufacturing a semiconductor chip mounting substrate has been described with reference to FIG. 9, but the shape of the semiconductor chip mounting substrate is not particularly limited. In one embodiment of the present invention, a frame shape as shown in FIG. 10 is preferable. By making the shape of the semiconductor chip mounting substrate 22 into a frame shape, the semiconductor package can be assembled efficiently. Hereinafter, the manufacture of the frame-shaped semiconductor chip mounting substrate will be described in detail.

  As shown in FIG. 10, first, a block 23 is formed in which a plurality of semiconductor package regions 13 (parts to be a single semiconductor package) are arranged in rows and columns at regular intervals. Further, such a block 23 is formed in a plurality of rows and columns. Although only two blocks are illustrated in FIG. 10, the blocks may be arranged in a lattice shape as necessary. Here, the width of the space between the semiconductor package regions is preferably 50 to 500 μm, and more preferably 100 to 300 μm. Furthermore, it is most preferable that the blade width of the dicer used when the semiconductor package is cut later is used.

  By arranging the semiconductor package region 13 in this way, the semiconductor chip mounting substrate 22 can be effectively used. Moreover, it is preferable to form the positioning mark 11 etc. in the edge part of the semiconductor chip mounting substrate 22, and it is more preferable that it is a pin hole by a through-hole. The shape and arrangement of the pin holes may be selected so as to match the forming method and the semiconductor package assembly apparatus.

  Furthermore, it is preferable to form a reinforcing pattern 24 in the space between the semiconductor package regions and outside the block 23. The reinforcing pattern 24 may be separately manufactured and bonded to the semiconductor chip mounting substrate 22, but is preferably a metal pattern formed simultaneously with the wiring formed in the semiconductor package region. More preferably, the surface of the reinforcing pattern 24 is plated with nickel, gold, or the like, which is the same as the wiring, or an insulating coating. When the reinforcing pattern 24 is made of such a metal, it can be used as a plating lead for electrolytic plating. Moreover, it is preferable to form the cutting alignment mark 25 at the time of cutting with a dicer outside the block 23. In this way, the frame-shaped semiconductor chip mounting substrate 22 can be manufactured.

(Semiconductor package)
FIG. 11 is a schematic cross-sectional view showing an example of a flip chip type semiconductor package according to the present invention. As shown in FIG. 11, in the semiconductor package, a semiconductor chip 111 is further mounted on the semiconductor chip mounting substrate described above. The semiconductor chip 111 and the semiconductor chip connection terminal are electrically connected by flip chip connection using the connection bump 112. In these semiconductor packages, it is preferable to seal between the semiconductor chip 111 and the semiconductor chip mounting substrate with an underfill material 113 as shown in the figure. The thermal expansion coefficient of the underfill material 113 is preferably approximate to the thermal expansion coefficients of the semiconductor chip 111 and the core substrate, but is not limited thereto. More preferably, the relationship is (thermal expansion coefficient of the semiconductor chip) ≦ (thermal expansion coefficient of the underfill material) ≦ (thermal expansion coefficient of the core substrate). The semiconductor chip can be mounted using an anisotropic conductive film or an adhesive film that does not contain conductive particles. In this case, since it is not necessary to seal with an underfill material, it is more preferable. Furthermore, it is particularly preferable to use ultrasonic waves together with the semiconductor chip because electrical connection can be performed at a low temperature and in a short time.

FIG. 12 is a schematic cross-sectional view showing an example of a wire bond type semiconductor package according to the present invention. A general die bond paste may be used for mounting the semiconductor chip, but it is more preferable to use a die bond film 117. Electrical connection between the semiconductor chip 111 and the semiconductor chip connection terminal is performed by wire bonding using a gold wire 115. The semiconductor chip 111 can be sealed by transfer molding using a semiconductor sealing resin 116. In this case, only a necessary portion of the sealing region may be sealed, for example, only the face surface of the semiconductor chip 111, but it is more preferable to seal the entire semiconductor package region as shown in FIG. This is a particularly effective method in the case where a plurality of semiconductor package regions are arranged in rows and columns and the substrate and the semiconductor sealing resin 116 are simultaneously cut with a dicer or the like. In addition, for example, a solder ball 114 can be mounted on the external connection terminal 107 for electrical connection with the motherboard. For the solder balls 114, eutectic solder or Pb-free solder is used. As a method of fixing the solder ball 114 to the external connection terminal 107, for example, an N ₂ reflow apparatus or the like can be used, but is not limited thereto. When a plurality of semiconductor packages formed by mounting a plurality of semiconductor chips on a semiconductor chip mounting substrate are manufactured, finally, each semiconductor package is cut using a dicer or the like.

  Hereinafter, although the present invention is explained in detail based on an example, the present invention is not limited to this.

1. The following Examples 1 to 10 and Comparative Examples 1 to 16A relate to the production of semiconductor package evaluation samples subjected to various surface treatments.
Example 1
A semiconductor package evaluation sample was prepared by applying the wiring board surface treatment method according to the present invention, and the reliability of the semiconductor package was evaluated. Hereinafter, a method for producing a sample for evaluation of a semiconductor package will be described with reference to each step diagram shown in FIG.

(Process a)
A 0.4 mm thick soda glass substrate (thermal expansion coefficient: 11 ppm / ° C.) was prepared as the core substrate 100, a 200 nm copper thin film was formed on one side by sputtering, and then plated to a thickness of 10 μm by electrolytic copper plating. In addition, sputtering was performed on the conditions 1 shown below using the product made from ULVAC, Inc. and apparatus model number: MLH-6315.

(Condition 1)
Current: 3.5A
Voltage: 500V
Argon flow rate: 35 SCCM (0.059 Pa · m ³ / s)
Pressure: 5 × 10 ⁻³ Torr (6.6 × 10 ⁻¹ Pa)
Deposition rate: 5 nm / second

  After that, an etching resist is formed in a portion to be the first wiring 106a, etched using a ferric chloride etchant, and the etching resist is removed, whereby the first wiring 106a (first interlayer connection terminal 101 is formed). And a semiconductor chip connection terminal).

(Process b)
A hole that becomes a first interlayer connection IVH 102 having a hole diameter of 50 μm with a laser until it reaches the first interlayer connection terminal 101 from the surface opposite to the first wiring 106a of the glass substrate on which the first wiring 106a is formed. Formed. A YAG laser: LAVIA-UV2000 (manufactured by Sumitomo Heavy Industries, Ltd., trade name) was used as the laser, and holes were formed under the conditions of frequency: 4 kHz, number of shots: 50, mask diameter: 0.4 mm. . Subsequently, the desmear process in a hole was performed. Thereafter, the hole is filled with a conductive paste: MP-200V (trade name, manufactured by Hitachi Chemical Co., Ltd.), cured at 160 ° C. for 30 minutes, and electrically connected to the first interlayer connection terminal 101 on the glass substrate. The first interlayer connection IVH102 was formed.

(Process c)
In order to electrically connect to the first interlayer connection IVH 102 formed in (Step b), after forming a 200 nm copper thin film by sputtering on the surface of the glass substrate opposite to the first wiring 106a, Plating was performed to a thickness of 10 μm by electrolytic copper plating. Sputtering was performed in the same manner as in (Step a). Thereafter, as in (Step a), an etching resist is formed in the shape of the second wiring 106b, etched using a ferric chloride etchant, and the etching resist is removed, whereby the second wiring 106b ( A second interlayer connection terminal 103 is formed.

(Step d-1)
The pretreatment was performed as follows on the wiring surface on the second wiring 106b side formed in (Step c). First, it was immersed in an acidic degreasing solution adjusted to 200 ml / L: Z-200 (trade name, manufactured by World Metal Co., Ltd.) at a liquid temperature of 50 ° C. for 2 minutes, and then immersed in water at a liquid temperature of 50 ° C. for 2 minutes. This was followed by hot water washing and further water washing for 1 minute. Subsequently, it was immersed in a 3.6 N sulfuric acid aqueous solution for 1 minute and washed with water for 1 minute.

(Step d-2)
The second wiring 106b that has undergone the pre-treatment step is immersed in a substituted palladium plating solution: SA-100 (manufactured by Hitachi Chemical Co., Ltd., trade name) for 3 minutes at 30 ° C., and is a metal nobler than copper. Palladium plating was applied at 1.0 μmol / dm ² and washed with water for 1 minute. Next, by dipping in an alkaline solution containing trisodium phosphate: 10 g / L and potassium hydroxide: 25 g / L for 3 minutes at 50 ° C. in an oxidation treatment solution containing sodium chlorite: 15 g / L. A 0.07 mg / cm ² copper oxide crystal was formed on the surface of the second wiring 106b. Then, after washing with water for 1 minute, the formed copper oxide crystals were selectively removed by immersing in an acidic solution of sulfuric acid: 20 g / L at 25 ° C. for 30 seconds to form fine irregularities on the copper surface. . Thereafter, it was washed with water for 5 minutes and dried at 85 ° C. for 30 minutes.

(Step d-3)
Next, an interlayer insulating layer (build-up layer 104) was formed on the surface on the second wiring 106b side as follows. That is, the build-up material: AS-ZII (trade name, manufactured by Hitachi Chemical Co., Ltd.) is vacuum-laminated, and the second wiring 106b under the conditions of evacuation time: 30 seconds, pressurization: 40 seconds, 0.5 MPa. A buildup layer was laminated on the side surface to form a resin layer having a thickness of 45 μm, and then thermally cured by holding at 180 ° C. for 90 minutes in an oven dryer to form the buildup layer 104.

(Process e)
From the surface of the build-up layer 104 formed along the above (step d-1) to (step d-3) until the second interlayer connection terminal 103 is reached by the laser, the second interlayer having a hole diameter of 50 μm is used. A hole to be the connection IVH 108 was formed. For the laser, YAG laser: LAVIA-UV2000 (manufactured by Sumitomo Heavy Industries, Ltd., trade name) was used, and holes were formed under the conditions of frequency: 4 kHz, number of shots: 20, mask diameter: 0.4 mm. . Thereafter, desmear treatment was performed. As a desmear treatment method, it was immersed in swelling liquid circular positive hole lip 4125 (trade name, manufactured by Rohm and Haas Electronic Materials Co., Ltd.) at 80 ° C. for 3 minutes and then washed with water for 3 minutes. Thereafter, the substrate was immersed in a permanganate solution circuposit MLB promoter 213 (trade name, manufactured by Rohm and Haas Electronic Materials Co., Ltd.) at 80 ° C. for 5 minutes and then washed with water for 3 minutes. Subsequently, it was immersed in a neutralizing liquid circuposit MLB216-4 (trade name, manufactured by Rohm and Haas Electronic Materials Co., Ltd.) at 40 ° C. for 3 minutes, washed with water for 3 minutes and dried at 85 ° C. for 30 minutes.

(Process f-1)
In order to form the third wiring 106c and the second interlayer connection IVH 108 on the buildup layer 104 formed in the above (step d-3), an electroless copper plating process is performed on the buildup layer 104. A seed layer was formed by forming a thin film copper layer having a thickness of 300 nm. The electroless copper plating was performed under the condition 2 shown below using each treatment solution manufactured by Hitachi Chemical Co., Ltd.

(Condition 2)
1 ... Cleaning (CLC-1100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), 50 ° C., 5 minutes)
2… Washing (40 ℃, 1 minute)
3. Washing with water (RT 2 minutes)
4 ... Pre-dip (PD-1300 (manufactured by Hitachi Chemical Co., Ltd., trade name), 30 ° C., 1 minute)
5 ... Activation (palladium) treatment (HS-1400 (manufactured by Hitachi Chemical Co., Ltd., trade name), 30 ° C., 5 minutes)
6 ... Washing with water (RT 2 minutes)
7 ... adhesion promotion treatment (ADP-1500 (manufactured by Hitachi Chemical Co., Ltd., trade name), 30 ° C., 5 minutes)
8 ... Washing with water (RT 2 minutes)
9 ... Electroless copper plating (CUST-1610 (manufactured by Hitachi Chemical Co., Ltd., trade name), 20 ° C., 20 minutes)
10 ... Washing with water (RT 2 minutes)
11 ... Drying (85 ° C, 30 minutes)

(Process f-2)
Next, a plating resist PMER P-LA900PM (manufactured by Tokyo Ohka Kogyo Co., Ltd., trade name) was applied onto the seed layer (on the thin film copper layer) by a spin coating method to form a plating resist layer having a thickness of 10 μm. . Next, after exposing the plating resist layer under conditions of 1000 mJ / cm ² , it was immersed in PMER developer P-7G (trade name, manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 6 minutes at 23 ° C., and L / S = 10 μm / 10 μm. The resist pattern was formed. Thereafter, electrolytic copper plating was performed using a copper sulfate plating solution to form a third wiring 106c having a thickness of about 5 μm. The plating resist was peeled off by immersion for 1 minute at room temperature (25 ° C.) using methyl ethyl ketone. In addition, for quick etching of the seed layer, a 5-fold diluted solution of CPE-700 (manufactured by Mitsubishi Gas Chemical Co., Ltd., trade name) is used for etching removal by immersing and shaking at 30 ° C. for 30 seconds. A wiring pattern was formed.

(Process f-3)
When wiring is formed by a semi-additive method using a seed layer of electroless copper plating, a desmear treatment under condition 3 shown below is performed in order to remove palladium between wirings after forming a wiring pattern by etching the seed layer. This is a common method. However, according to the surface treatment method of the present invention, it is possible to perform desmear treatment together with some of the steps in the wiring surface treatment described below. Therefore, here, without performing the desmear process under the following condition 3, the process f-4 shown below was performed following the process f-2.

(Condition 3)
1 ... Swelling treatment (Circuposit hole hole 4125 (Rohm and Haas Electronic Materials, trade name), 70 ° C., 5 minutes)
2. Washing with water (RT 3 minutes)
3. Permanganic acid treatment (Circuposit MLB promoter 213 (Rohm and Haas Electronic Materials, trade name), 70 ° C., 1 minute)
4. Washing with water (RT 3 minutes)
5 ... Neutralization treatment (Circuposit MLB216-4 (Rohm and Haas Electronic Materials Co., Ltd., trade name), 45 ° C, 5 minutes)
6 ... Washing with water (RT 2 minutes)
7… Dry (85 ℃, 30 minutes)

(Process f-4)
The surface of the wiring on the third wiring 106c side is immersed in an acidic degreasing solution adjusted to 200 ml / L: Z-200 (trade name, manufactured by World Metal Co., Ltd.) at a liquid temperature of 50 ° C. for 2 minutes. : Washed with hot water by immersing in water at 50 ° C. for 2 minutes, and further washed with water for 1 minute. Subsequently, it was immersed in a 3.6 N sulfuric acid aqueous solution for 1 minute and washed with water for 1 minute.

(Process f-5)
The substrate that has undergone the pretreatment step is immersed in a substituted palladium plating solution: SA-100 (manufactured by Hitachi Chemical Co., Ltd., trade name) at 30 ° C. for 3 minutes, and the surface of the third wiring 106c is nobler than copper. Palladium plating, which is a metal, was applied at 1.0 μmol / dm ² and washed with water for 1 minute.

(Process f-6)
The substrate subjected to the palladium treatment step was surface treated with an alkaline solution containing an organic compound. Specifically, it was immersed for 3 minutes at 70 ° C. in a swelling liquid circular positive hole lip 4125 (trade name, manufactured by Rohm and Haas Electronic Materials Co., Ltd.) and then washed with water for 3 minutes.

(Process f-7)
The substrate that had undergone the swelling treatment step was immersed in a permanganate solution circulation deposit MLB promoter 213 (trade name, manufactured by Rohm and Haas Electronic Materials Co., Ltd.) at 70 ° C. for 1 minute, and then washed with water for 3 minutes.

(Process f-8)
The substrate subjected to the permanganic acid treatment step was immersed in a neutralizing liquid circuposit MLB216-4 (Rohm and Haas Electronic Materials Co., Ltd., trade name) for 3 minutes at 40 ° C. and then washed with water for 2 minutes.

(Process f-9)
The board | substrate which passed through the said neutralization process process was dried for 30 minutes at 85 degreeC. As described above, by performing (Step f-5) to (Step f-9), formation of irregularities on the surface of the copper wiring and removal of palladium on the surface of the build-up material between the wirings were simultaneously performed.

(Process g)
The series of steps from the above (step d-3) to (step f-9) was repeated again, and the outermost layer wiring including the build-up layer and the external connection terminal 107 was further added. Finally, an insulating coating 109 is formed, and then the external connection terminal 107 and the semiconductor chip connection terminal are subjected to gold plating, and FIG. 5 (sectional view for one package), FIG. 7 (plan view for one package), Then, a fan-in type BGA semiconductor chip mounting substrate as shown in FIG. 10 (overall view of the semiconductor chip mounting substrate) was produced.

(Process h)
A desired number of semiconductor chips 111 having connection bumps 112 formed on the semiconductor chip mounting region of the semiconductor chip mounting substrate manufactured by the above (steps a) to (step g) are ultrasonicated using a flip chip bonder. It mounted while applying (refer FIG. 10). Further, an underfill material 113 is injected from the end of the semiconductor chip into the gap between the semiconductor chip mounting substrate and the semiconductor chip 111, and primary curing at 80 ° C. for 1 hour and secondary curing at 150 ° C. for 4 hours using an oven. Went. Next, lead / tin eutectic solder balls 114 having a diameter of 0.45 mm were fused to the external connection terminals 107 using an N ₂ reflow apparatus. Finally, the semiconductor chip mounting substrate was cut with a dicer equipped with a blade having a width of 200 μm to produce the semiconductor package shown in FIG.

(Example 2)
A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured in the same manner as in Example 1 except that a post-processing step was performed after (Step f-8) and then (Step f-9) was performed. In the post-processing step of the present embodiment, a coupling treatment step is performed in which the surface of the third wiring 106c is immersed in an aqueous solution of γ-aminopropyltriethoxysilane: 0.5% by mass at 30 ° C. for 1 minute, and further for 1 minute. Washed with water.

(Example 3)
A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured in the same manner as in Example 1 except that a post-processing step was performed after (Step f-8) and then (Step f-9) was performed. In the post-treatment process of the present embodiment, an azole treatment process is performed in which the surface of the third wiring 106c is immersed in 2-methylimidazole: 0.5% by mass aqueous solution adjusted to pH 6.5 with a sulfuric acid solution at 30 ° C. for 1 minute. And washed with water for an additional minute.

Example 4
A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured in the same manner as in Example 1 except that a post-processing step was performed after (Step f-8) and then (Step f-9) was performed. In the post-treatment process of this example, an azole treatment process is performed in which the surface of the third wiring 106c is immersed in a 3,5-dimethylpyrazole: 0.5% by mass aqueous solution adjusted to pH 9.5 at 30 ° C. for 1 minute. Further, it was washed with water for 1 minute.

(Example 5)
A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured in the same manner as in Example 1 except that a post-processing step was performed after (Step f-8) and then (Step f-9) was performed. In the post-processing step of the present embodiment, the surface of the third wiring 106c is applied to an electroless tin plating solution containing stannous chloride: 3 g / L, thiourea: 25 g / L, and tartaric acid: 25 g / L at 30 ° C. A metal formation treatment process that is more basic than copper immersed for 15 seconds was performed, and further washed with water for 1 minute.

(Example 6)
A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured in the same manner as in Example 1 except that a post-processing step was performed after (Step f-8) and then (Step f-9) was performed. In the post-treatment process of the present embodiment, the surface of the third wiring 106c is coated with nickel sulfate hexahydrate: 0.2 g / L, sodium citrate: 3 g / L, boric acid: 3 g / L, hypophosphorous acid. Sodium: 10 g / L, immersed in an electroless nickel plating solution of pH 9 at 50 ° C. for 120 seconds, then washed with water for 1 minute, stannous chloride: 3 g / L, thiourea: 25 g / L, tartaric acid: 25 g / L By a method of immersing in an electroless tin plating solution containing 30 seconds at 30 ° C., a metal forming treatment step that is more basic than copper was performed, and further washed with water for 1 minute.

(Example 7)
A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured in the same manner as in Example 1 except that a post-processing step was performed after (Step f-8) and then (Step f-9) was performed. In the post-processing step of the present embodiment, the surface of the third wiring 106c is coated with cobalt sulfate heptahydrate: 0.2 g / L, sodium citrate: 3 g / L, boric acid: 3 g / L, hypophosphorous acid. Sodium: 10 g / L, immersed in electroless cobalt plating solution of pH 8 at 50 ° C. for 120 seconds, then washed with water for 1 minute, stannous chloride: 3 g / L, thiourea: 25 g / L, tartaric acid: 25 g / L A metal formation treatment step that is more basic than copper was performed by a method of immersing in an electroless tin plating solution containing 30 seconds at 30 ° C. It was further washed with water for 1 minute.

(Example 8)
A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured in the same manner as in Example 1 except that a post-processing step was performed after (Step f-8) and then (Step f-9) was performed. did. In the post-processing step of the present embodiment, the surface of the third wiring 106c is applied to an electroless tin plating solution containing stannous chloride: 3 g / L, thiourea: 25 g / L, and tartaric acid: 25 g / L at 30 ° C. A metal formation treatment process that is less basic than copper was performed by a method of dipping for 15 seconds, and then washed with water for 1 minute. Moreover, the coupling process process which immerses for 3 minutes at 30 degreeC in (gamma) -aminopropyl triethoxysilane: 0.5 mass% aqueous solution was performed, and also it washed with water for 1 minute.

Example 9
A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured in the same manner as in Example 1 except that a post-processing step was performed after (Step f-8) and then (Step f-9) was performed. In the post-processing step of the present embodiment, the surface of the third wiring 106c is applied to an electroless tin plating solution containing stannous chloride: 3 g / L, thiourea: 25 g / L, and tartaric acid: 25 g / L at 30 ° C. By a method of immersing for 15 seconds, a metal forming treatment step that is more basic than copper was performed, followed by washing with water for 1 minute. Subsequently, the azole treatment step was carried out by a method of immersing in 3,5-dimethylpyrazole: 0.5 mass% aqueous solution adjusted to pH 9.5 with a sodium hydroxide solution at 30 ° C. for 1 minute, and further washed with water for 1 minute.

(Example 10)
For fan-in type BGA, all in the same manner as in Example 1 except that a post-treatment step was performed after (Step f-8) and then a heat treatment step was performed at 150 ° C. for 60 minutes after (Step f-9). A semiconductor chip mounting substrate and a semiconductor package were produced. In the post-processing step, the surface of the third wiring 106c is immersed in an electroless tin plating solution containing stannous chloride: 3 g / L, thiourea: 25 g / L, and tartaric acid: 25 g / L at 30 ° C. for 15 seconds. According to the method, a metal forming treatment step that is lower than copper was performed, and further washed with water for 1 minute.

(Comparative Example 1)
A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1 except that the replacement palladium plating treatment in (Step f-5) in (Step f) was not performed.

(Comparative Example 2)
After performing the desmear process of (process f-3) in (process f), the pre-process of (process f-4) was performed. Next, the treatment was performed as follows without performing the substitution palladium plating treatment in (Step f-5) and the respective treatments in (Step f-6) to (Step f-8). First, the substrate was immersed in an oxidation solution containing sodium chlorite: 15 g / L in an alkaline solution containing trisodium phosphate: 10 g / L and potassium hydroxide: 25 g / L at 85 ° C. for 3 minutes. Copper oxide crystals were formed on the surface of 106c. The obtained substrate was washed with water for 1 minute, and then immersed in an acidic solution of sulfuric acid: 20 g / L at 25 ° C. for 30 seconds to selectively remove the previously formed copper oxide crystals, thereby forming irregularities. . Thereafter, the obtained substrate was washed with water for 5 minutes. Subsequently, (step f-9) was performed after performing the above-described series of treatments. As described above, except for the above, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured in the same manner as in Example 1.

(Comparative Example 3)
After performing the desmear process of (process f-3) in (process f), the pre-process of (process f-4) was performed. Next, the treatment was performed as follows without performing the substitution palladium plating treatment in (Step f-5) and the respective treatments in (Step f-6) to (Step f-8). First, the substrate was immersed in an oxidation solution containing sodium chlorite: 15 g / L in an alkaline solution containing trisodium phosphate: 10 g / L and potassium hydroxide: 25 g / L at 85 ° C. for 3 minutes. Copper oxide crystals were formed on the surface of 106c. Thereafter, the obtained substrate was washed with water for 5 minutes, immersed in a reduction treatment solution HIST-100D (trade name, manufactured by Hitachi Chemical Co., Ltd.) for 3 minutes at 40 ° C., and further washed with water for 5 minutes. Subsequently, (step f-9) was performed after performing the above-described series of treatments. As described above, except for the above, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured in the same manner as in Example 1.

(Comparative Example 4)
After performing the desmear process of (process f-3) in (process f), the pre-process of (process f-4) was performed. Next, the treatment was performed as follows without performing the substitution palladium plating treatment in (Step f-5) and the respective treatments in (Step f-6) to (Step f-8). First, the substrate was immersed in MEC etch bond CZ8100 (trade name, manufactured by MEC Co., Ltd.), which is a microetching agent, at 40 ° C. for 1 minute and 30 seconds, and further washed with water for 2 minutes. Next, after performing such a series of treatments (step f-9) was performed. As described above, except for the above, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured in the same manner as in Example 1.

(Comparative Example 5)
After performing the desmear process of (process f-3) in (process f), the pre-process of (process f-4) was performed. Next, after the substitution palladium plating treatment in (Step f-5) was performed, each treatment in (Step f-6) to (Step f-8) was carried out as follows. First, the substrate is immersed in an oxidizing solution containing 15 g / L of sodium chlorite in an alkaline solution containing trisodium phosphate: 10 g / L and potassium hydroxide: 25 g / L at 50 ° C. for 3 minutes. Then, a copper oxide crystal was formed on the surface of the third wiring 106c. Then, the obtained board | substrate was washed with water for 1 minute, and was immersed in reduction processing liquid HIST-100D (Hitachi Chemical Industry Co., Ltd. make, brand name) for 3 minutes at 40 degreeC, and the unevenness | corrugation by the crystal | crystallization of metallic copper was formed. Thereafter, it was further washed with water for 5 minutes. Subsequently, (step f-9) was performed after performing the above-described series of treatments. As described above, except for the above, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured in the same manner as in Example 1.

(Comparative Example 6)
After performing the desmear process of (process f-3) in (process f), the pre-process of (process f-4) was performed. Next, after the substitution palladium plating treatment in (Step f-5), the treatment was carried out as follows without performing each treatment in (Step f-6) to (Step f-8). First, the substrate is immersed in an oxidizing solution containing 15 g / L of sodium chlorite in an alkaline solution containing trisodium phosphate: 10 g / L and potassium hydroxide: 25 g / L at 50 ° C. for 3 minutes. Then, a copper oxide crystal was formed on the surface of the third wiring 106c. Thereafter, the obtained substrate was washed with water for 1 minute, and immersed in an acidic solution of sulfuric acid: 20 g / L at 25 ° C. for 30 seconds, thereby selectively removing the formed copper oxide crystals and forming irregularities. . Thereafter, it was further washed with water for 1 minute. Subsequently, (step f-9) was performed after performing the above-described series of treatments. As described above, except for the above, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured in the same manner as in Example 1.

(Comparative Example 7)
After performing the desmear process of (process f-3) in (process f), the pre-process of (process f-4) was performed. Next, after the substitution palladium plating treatment in (Step f-5), the treatment was carried out as follows without performing each treatment in (Step f-6) to (Step f-8). First, the substrate is immersed in an oxidizing solution containing 15 g / L of sodium chlorite in an alkaline solution containing trisodium phosphate: 10 g / L and potassium hydroxide: 25 g / L at 50 ° C. for 3 minutes. Then, a copper oxide crystal was formed on the surface of the third wiring 106c. Thereafter, the obtained substrate was washed with water for 1 minute, and immersed in an acidic solution of sulfuric acid: 20 g / L at 25 ° C. for 30 seconds, thereby selectively removing the formed copper oxide crystals and forming irregularities. . Thereafter, it is further washed with water for 1 minute, and is a base metal than copper immersed in an electroless tin plating solution containing stannous chloride: 3 g / L, thiourea: 25 g / L, and tartaric acid: 25 g / L at 30 ° C. for 15 seconds. A formation process was performed. Thereafter, it was washed with water for 1 minute. Subsequently, (step f-9) was performed after performing the above-described series of treatments. As described above, except for the above, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured in the same manner as in Example 1.

(Comparative Example 8)
Similarly to Example 1, the pretreatment of (Step f-4) was performed without performing the desmear treatment of (Step f-3) in (Step f). Next, the treatment was performed as follows without performing the substitution palladium plating treatment in (Step f-5) and the respective treatments in (Step f-6) to (Step f-8). First, the substrate was immersed in an oxidation treatment solution at 85 ° C. for 3 minutes to form a copper oxide crystal on the surface of the wiring 106c. Thereafter, the obtained substrate is washed with water for 1 minute and then immersed in an acidic solution of sulfuric acid: 20 g / L at 25 ° C. for 30 seconds to selectively remove the formed copper oxide crystals and form irregularities. did. Thereafter, it was washed with water for 5 minutes. Subsequently, (step f-9) was performed after performing the above-described series of treatments. As described above, except for the above, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured in the same manner as in Example 1.

(Comparative Example 9)
Similarly to Example 1, the pretreatment of (Step f-4) was performed without performing the desmear treatment of (Step f-3) in (Step f). Next, the treatment was performed as follows without performing the substitution palladium plating treatment in (Step f-5) and the respective treatments in (Step f-6) to (Step f-8). First, the substrate was immersed in an oxidation treatment solution at 85 ° C. for 3 minutes to form a copper oxide crystal on the surface of the wiring 106c. Thereafter, the obtained substrate was washed with water for 5 minutes, immersed in a reduction treatment solution HIST-100D (trade name, manufactured by Hitachi Chemical Co., Ltd.) for 3 minutes at 40 ° C., and further washed with water for 5 minutes. Subsequently, (step f-9) was performed after performing the above-described series of treatments. As described above, except for the above, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured in the same manner as in Example 1.

(Comparative Example 10)
Similarly to Example 1, the pretreatment of (Step f-4) was performed without performing the desmear treatment of (Step f-3) in (Step f). Next, the treatment was performed as follows without performing the substitution palladium plating treatment in (Step f-5) and the respective treatments in (Step f-6) to (Step f-8). First, the substrate was immersed in MEC etch bond CZ8100 (trade name, manufactured by MEC Co., Ltd.), which is a microetching agent, at 40 ° C. for 1 minute and 30 seconds, and further washed with water for 2 minutes. Next, after performing such a series of treatments (step f-9) was performed. As described above, except for the above, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured in the same manner as in Example 1.

(Comparative Example 11)
Similarly to Example 1, the pretreatment of (Step f-4) was performed without performing the desmear treatment of (Step f-3) in (Step f). Next, after the substituted palladium plating treatment in (Step f-5), the treatment was performed as follows without carrying out (Step f-6) to (Step f-8). First, the substrate is immersed for 3 minutes at 50 ° C. in an oxidation treatment solution in which sodium chlorite: 15 g / L is added to an alkaline solution containing trisodium phosphate: 10 g / L and potassium hydroxide: 25 g / L. A copper oxide crystal was formed on the surface of the third wiring 106c. Then, the obtained board | substrate was washed with water for 1 minute, and was immersed in reduction processing liquid HIST-100D (Hitachi Chemical Industry Co., Ltd. make, brand name) for 3 minutes at 40 degreeC, and the unevenness | corrugation by the crystal | crystallization of metallic copper was formed. Thereafter, it was further washed with water for 5 minutes. Subsequently, (step f-9) was performed after performing the above-described series of treatments. As described above, except for the above, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured in the same manner as in Example 1.

(Comparative Example 12)
Similarly to Example 1, the pretreatment of (Step f-4) was performed without performing the desmear treatment of (Step f-3) in (Step f). Next, after the substituted palladium plating treatment in (Step f-5), the treatment was performed as follows without carrying out (Step f-6) to (Step f-8). First, the substrate is immersed in an oxidizing solution containing 15 g / L of sodium chlorite in an alkaline solution containing trisodium phosphate: 10 g / L and potassium hydroxide: 25 g / L at 50 ° C. for 3 minutes. Then, a copper oxide crystal was formed on the surface of the third wiring 106c. Thereafter, the obtained substrate was washed with water for 1 minute, and immersed in an acidic solution of sulfuric acid: 20 g / L at 25 ° C. for 30 seconds, thereby selectively removing the formed copper oxide crystals and forming irregularities. . Thereafter, it was further washed with water for 1 minute. Subsequently, (step f-9) was performed after performing the above-described series of treatments. As described above, except for the above, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured in the same manner as in Example 1.

(Comparative Example 13)
Similarly to Example 1, the pretreatment of (Step f-4) was performed without performing the desmear treatment of (Step f-3) in (Step f). Next, after the substituted palladium plating treatment in (Step f-5), the treatment was performed as follows without carrying out (Step f-6) to (Step f-8). First, the substrate is immersed for 3 minutes at 50 ° C. in an oxidation treatment solution in which sodium chlorite: 15 g / L is added to an alkaline solution containing trisodium phosphate: 10 g / L and potassium hydroxide: 25 g / L. A copper oxide crystal was formed on the surface of the third wiring 106c. Thereafter, the obtained substrate was washed with water for 1 minute, and immersed in an acidic solution of sulfuric acid: 20 g / L at 25 ° C. for 30 seconds, thereby selectively removing the formed copper oxide crystals and forming irregularities. . Thereafter, it is further washed with water for 1 minute, and is a base metal than copper immersed in an electroless tin plating solution containing stannous chloride: 3 g / L, thiourea: 25 g / L, and tartaric acid: 25 g / L at 30 ° C. for 15 seconds. A formation process was performed. Thereafter, it was washed with water for 1 minute. Subsequently, (step f-9) was performed after performing the above-described series of treatments. As described above, except for the above, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured in the same manner as in Example 1.

(Comparative Example 14)
A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1 except that the swelling treatment in (Step f-6) in (Step f) was not performed.

(Comparative Example 15)
A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1 except that the permanganate treatment in (Step f-7) in (Step f) was not performed.

(Comparative Example 16)
A fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1 except that the neutralization treatment in (Step f-8) in (Step f) was not performed.

(Comparative Example 16A)
After performing each process of (process f-4)-(process f-6), without performing the desmear process of (process f-3) in (process f), it changes to the alkaline solution containing permanganic acid. (Step f-7) was performed using an alkaline solution containing chlorate. More specifically, in the step (f-7), an alkaline solution containing chlorate is added to an alkaline solution containing trisodium phosphate: 10 g / L and potassium hydroxide: 25 g / L: sodium chlorite: 15 g. The solution added with / L was immersed in this solution at 50 ° C. for 3 minutes and then washed with water for 1 minute. In the step (f-8), an acidic solution of sulfuric acid: 20 g / L was used, immersed in this solution at 25 ° C. for 30 seconds, and then washed with water for 1 minute. As described above, except for the above, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were manufactured in the same manner as in Example 1.

2. Examples 11 to 20 and Comparative Examples 17 to 32A below relate to the production of electrolytic copper foil test pieces for evaluating the adhesiveness, smoothness, and surface shape of the copper surface after the surface treatment.
(Example 11)
In order to evaluate the adhesion between the build-up material and the copper surface after the surface treatment of the wiring board, the adhesion between the solder resist and the copper surface, the smoothness, and the surface shape, 18 μm electrolytic copper foil GTS-18 (Furukawa Circuit Foil Co., Ltd.) Electroplating was performed on the shiny surface of the company, product name) to prepare an electrolytic copper foil with a thickness of 50 μm. Thereafter, the electrolytic copper foil was cut into 5 cm × 8 cm (for adhesion test, copper surface smoothness evaluation, copper surface shape evaluation), and the electroplated surface of each electrolytic copper foil was subjected to Example 1 (step f-4). Each surface treatment (pretreatment, noble metal formation, swelling treatment, permanganate treatment, neutralization treatment, and drying) described in (Step f-9) was performed to prepare a test piece of electrolytic copper foil.

(Example 12)
As the surface treatment for the electrolytic copper foil, each surface treatment (pretreatment, noble metal formation, swelling treatment, permanganate treatment, neutralization treatment) described in (Step f-4) to (Step f-9) of Example 2 A test piece of electrolytic copper foil was produced in the same manner as in Example 11, except that the coupling treatment and drying were performed.

(Example 13)
As the surface treatment for the electrolytic copper foil, each surface treatment (pretreatment, noble metal formation, swelling treatment, permanganate treatment, neutralization treatment) described in (Step f-4) to (Step f-9) of Example 3 A test piece of electrolytic copper foil was prepared in the same manner as in Example 11 except that azole treatment: imidazole, dried).

(Example 14)
As surface treatment for the electrolytic copper foil, each surface treatment (pretreatment, noble metal formation, swelling treatment, permanganate treatment, neutralization treatment) described in (Step f-4) to (Step f-9) of Example 4 , Azole treatment: pyrazole, dried) A test piece of electrolytic copper foil was prepared in the same manner as in Example 11.

(Example 15)
As surface treatment for the electrolytic copper foil, each surface treatment (pretreatment, noble metal formation, swelling treatment, permanganate treatment, neutralization treatment) described in (Step f-4) to (Step f-9) of Example 5 A test piece of electrolytic copper foil was produced in the same manner as in Example 11 except that electroless tin plating treatment and drying were performed.

(Example 16)
As surface treatment for the electrolytic copper foil, each surface treatment (pretreatment, noble metal formation, swelling treatment, permanganate treatment, neutralization treatment) described in (Step f-4) to (Step f-9) of Example 6 A test piece of electrolytic copper foil was prepared in the same manner as in Example 11 except that electroless nickel plating treatment, electroless tin plating treatment, and drying were performed.

(Example 17)
As surface treatment for the electrolytic copper foil, each surface treatment (pretreatment, noble metal formation, swelling treatment, permanganic acid treatment, neutralization treatment) described in (Step f-4) to (Step f-9) of Example 7 A test piece of electrolytic copper foil was prepared in the same manner as in Example 11 except that electroless cobalt plating, electroless tin plating, and drying were performed.

(Example 18)
As surface treatment for the electrolytic copper foil, each surface treatment (pretreatment, noble metal formation, swelling treatment, permanganic acid treatment, neutralization treatment) described in (Step f-4) to (Step f-9) of Example 8 A test piece of electrolytic copper foil was prepared in the same manner as in Example 11 except that electroless tin plating treatment, coupling treatment, and drying were performed.

(Example 19)
As surface treatment for the electrolytic copper foil, each surface treatment (pretreatment, noble metal formation, swelling treatment, permanganate treatment, neutralization treatment) described in (Step f-4) to (Step f-9) of Example 9 A test piece of electrolytic copper foil was produced in the same manner as in Example 11 except that electroless tin plating treatment, azole treatment: pyrazole, and drying) were performed.

(Example 20)
As the surface treatment for the electrolytic copper foil, each surface treatment (pretreatment, noble metal formation, swelling treatment, permanganate treatment) by (Step f-4) to (Step f-9) of Example 10 and a heat treatment step at 150 ° C. A test piece of electrolytic copper foil was produced in the same manner as in Example 11, except that neutralization treatment, electroless tin plating treatment, drying, and 150 ° C. heat treatment were performed.

(Comparative Example 17)
As surface treatment for the electrolytic copper foil, each surface treatment (pretreatment, swelling treatment, permanganate treatment, neutralization treatment, drying) described in (Step f-4) to (Step f-9) of Comparative Example 1 A test piece of electrolytic copper foil was produced in the same manner as in Example 11 except that.

(Comparative Example 18)
As surface treatment for the electrolytic copper foil, each surface treatment (palladium removal treatment, pretreatment, oxidation treatment: 80 ° C., acidic solution treatment) described in (Step f-3) to (Step f-9) of Comparative Example 2 A test piece of electrolytic copper foil was produced in the same manner as in Example 11 except that (drying) was performed.

(Comparative Example 19)
As surface treatment for the electrolytic copper foil, each surface treatment (palladium removal treatment, pretreatment, oxidation treatment: 80 ° C., reduction treatment, drying) described in (Step f-3) to (Step f-9) of Comparative Example 3 A test piece of electrolytic copper foil was produced in the same manner as in Example 11 except that.

(Comparative Example 20)
As a surface treatment for the electrolytic copper foil, except that each surface treatment (palladium removal treatment, pretreatment, etching treatment, drying) described in (Step f-3) to (Step f-9) of Comparative Example 4 was performed. In the same manner as in Example 11, a test piece of electrolytic copper foil was produced.

(Comparative Example 21)
As the surface treatment for the electrolytic copper foil, each surface treatment (palladium removal treatment, pretreatment, palladium treatment, oxidation treatment) described in (Step f-3) to (Step f-9) of Comparative Example 5: 50 ° C., reduction A test piece of electrolytic copper foil was prepared in the same manner as in Example 11 except that the treatment and drying were performed.

(Comparative Example 22)
As surface treatment for the electrolytic copper foil, each surface treatment (palladium removal treatment, pretreatment, palladium treatment, oxidation treatment) described in (Step f-3) to (Step f-9) of Comparative Example 6: 50 ° C., acidity A test piece of electrolytic copper foil was prepared in the same manner as in Example 11 except that solution treatment and drying were performed.

(Comparative Example 23)
As the surface treatment for the electrolytic copper foil, each surface treatment (palladium removal treatment, pretreatment, palladium treatment, oxidation treatment) described in (Step f-3) to (Step f-9) of Comparative Example 7: 50 ° C., acidity A test piece of electrolytic copper foil was prepared in the same manner as in Example 11 except that solution treatment, electroless tin plating treatment, and drying were performed.

(Comparative Example 24)
As the surface treatment for the electrolytic copper foil, each surface treatment (pretreatment, oxidation treatment: 85 ° C., acidic solution treatment, drying) described in (Step f-4) to (Step f-9) of Comparative Example 8 was performed. A test piece of electrolytic copper foil was produced in the same manner as in Example 11 except that.

(Comparative Example 25)
As the surface treatment for the electrolytic copper foil, each surface treatment (pretreatment, oxidation treatment: 85 ° C., reduction treatment, drying) described in (Step f-4) to (Step f-9) of Comparative Example 9 was performed. Except that, an electrolytic copper foil test piece was prepared in the same manner as in Example 11.

(Comparative Example 26)
Example 11 except that each surface treatment (pretreatment, etching treatment, drying) described in (Step f-4) to (Step f-9) of Comparative Example 10 was performed as the surface treatment for the electrolytic copper foil. In the same manner as above, a test piece of electrolytic copper foil was prepared.

(Comparative Example 27)
As surface treatment for the electrolytic copper foil, each surface treatment described in (Step f-4) to (Step f-9) of Comparative Example 11 (pretreatment, palladium treatment, oxidation treatment: 50 ° C., reduction treatment, drying) A test piece of electrolytic copper foil was produced in the same manner as in Example 11 except that.

(Comparative Example 28)
As the surface treatment for the electrolytic copper foil, each surface treatment (pretreatment, palladium treatment, oxidation treatment: 50 ° C., acidic solution treatment, drying) described in (Step f-4) to (Step f-9) of Comparative Example 12 A test piece of electrolytic copper foil was produced in the same manner as in Example 11 except that.

(Comparative Example 29)
As the surface treatment for the electrolytic copper foil, each surface treatment (pretreatment, palladium treatment, oxidation treatment: 50 ° C., acidic solution treatment, no treatment) described in (Step f-4) to (Step f-9) of Comparative Example 13 A test piece of electrolytic copper foil was produced in the same manner as in Example 11 except that electrolytic tin plating treatment and drying were performed.

(Comparative Example 30)
As surface treatment for the electrolytic copper foil, each surface treatment (pretreatment, palladium treatment, permanganic acid treatment, neutralization treatment, drying) described in (Step f-4) to (Step f-9) of Comparative Example 14 A test piece of electrolytic copper foil was produced in the same manner as in Example 11 except that.

(Comparative Example 31)
As surface treatment for the electrolytic copper foil, each surface treatment (pretreatment, palladium treatment, swelling treatment, neutralization treatment, and drying) described in (Step f-4) to (Step f-9) of Comparative Example 15 was performed. A test piece of electrolytic copper foil was produced in the same manner as in Example 11 except that.

(Comparative Example 32)
As surface treatment for the electrolytic copper foil, each surface treatment (pretreatment, palladium treatment, swelling treatment, permanganate treatment, drying) described in (Step f-4) to (Step f-9) of Comparative Example 16 was performed. A test piece of electrolytic copper foil was produced in the same manner as in Example 11 except that it was applied.

(Comparative Example 32A)
As the surface treatment for the electrolytic copper foil, each surface treatment described in Comparative Example 16A (pretreatment, palladium treatment, swelling treatment, chloric acid treatment (oxidation treatment: 50 ° C.), neutralization treatment, drying) was performed. In the same manner as in Example 11, a test piece of electrolytic copper foil was produced.

3. Examples 21 to 30 and Comparative Examples 33 to 48A below relate to the production of an evaluation substrate for evaluating the insulation resistance value between the wirings and the PCT resistance.
(Example 21)
In order to evaluate the effect of the surface treatment of the wiring board in (Step f), an evaluation board was prepared as follows, and the insulation resistance value and the PCT resistance between the wirings were evaluated. FIG. 13 and FIG. 14 are process diagrams schematically showing the manufacturing process of the evaluation substrate, and each process diagram is a more detailed explanation of the (process f) described above with reference to FIG. . 13 and FIG. 14, (i) is a step of performing a desmear process after forming the buildup layer 104 on the core substrate 110, (ii) is a step of forming the seed layer 118, and (iii) is a plating step. A step of forming a resist pattern 119, (iv) a step of performing electroplating and forming a wiring 106, (v) a step of removing the plating resist, and (vi) a predetermined process after the seed layer 118 is removed. The process of giving and forming the buildup layer 104 is shown.

  More specifically, the evaluation substrate was produced as follows. First, a 0.4 mm thick soda glass substrate (thermal expansion coefficient 11 ppm / ° C.) was prepared as the core substrate 100 shown in FIGS. 13 and 14, and the buildup layer 104 was formed on one side as follows. That is, the build-up material AS-ZII (trade name, manufactured by Hitachi Chemical Co., Ltd.) is vacuum laminated on the surface of the core substrate 100 under the conditions of evacuation time: 30 seconds, pressurization: 40 seconds, 0.5 MPa. After laminating the build-up material to form a resin layer having a thickness of 45 μm, it was thermoset by holding at 180 ° C. for 90 minutes in an oven drier to form an interlayer insulating layer. Thereafter, the surface of the interlayer insulating layer was desmeared. As a desmear treatment method, it was immersed in swelling liquid circular positive hole lip 4125 (trade name, manufactured by Rohm and Haas Electronic Materials Co., Ltd.) at 80 ° C. for 3 minutes and then washed with water for 3 minutes. Thereafter, the substrate was immersed in a permanganate solution circuposit MLB promoter 213 (trade name, manufactured by Rohm and Haas Electronic Materials Co., Ltd.) at 80 ° C. for 5 minutes and then washed with water for 3 minutes. Subsequently, it was immersed in a neutralizing liquid circuposit MLB216-4 (trade name, manufactured by Rohm and Haas Electronic Materials Co., Ltd.) at 40 ° C. for 3 minutes, washed with water for 3 minutes, and dried at 85 ° C. for 30 minutes. Next, a seed layer was formed on the buildup layer in the same manner as in (Step f-1) of Example 1. Specifically, a copper thin film (seed layer 118) having a thickness of 300 nm was formed by electroless copper plating. The electroless copper plating was performed under the condition 2 described above using each treatment solution manufactured by Hitachi Chemical Co., Ltd.

Next, a wiring pattern was formed in the same manner as (Step f-2) in Example 1. Specifically, a plating resist PMER P-LA900PM (trade name, manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied on the seed layer 118 by a spin coating method to form a plating resist layer having a thickness of 10 μm. Next, after the plating resist layer was exposed under the condition of 1000 mJ / cm ² , it was immersed in PMER developer P-7G for 6 minutes at 23 ° C. to form a resist pattern 119 so that L / S = 10 μm / 10 μm. Thereafter, electrolytic copper plating was performed using a copper sulfate plating solution to form a wiring 106 having a thickness of about 5 μm. The plating resist was peeled off by immersion for 1 minute at room temperature (25 ° C.) using methyl ethyl ketone. In addition, for quick etching of the seed layer 118, a 5-fold diluted solution of CPE-700 (manufactured by Mitsubishi Gas Chemical Co., Ltd., trade name) is used for immersion removal at 30 ° C. for 30 seconds by etching. Then, the wiring 106 was formed.

  Each surface treatment (pretreatment, noble metal formation, swelling treatment, permanganate treatment, neutralization treatment, drying) described in (Step f-4) to (Step f-9) of Example 1 for the wiring 106 Then, an interlayer insulating layer (build-up layer 104) shown in FIG. 13 and a solder resist (insulating coating 109) shown in FIG. 14 are formed, and for evaluation of L / S = 10 μm / 10 μm shown in FIG. Thirty-two substrates were produced respectively.

(Example 22)
As each surface treatment, each surface treatment (pretreatment, noble metal formation, swelling treatment, permanganate treatment, neutralization treatment, coupling described in (Step f-4) to (Step f-9) of Example 2 A substrate for evaluation was produced in the same manner as in Example 21 except that the treatment and drying were performed.

(Example 23)
As each surface treatment, each surface treatment (pretreatment, noble metal formation, swelling treatment, permanganate treatment, neutralization treatment, azole treatment) described in (Step f-4) to (Step f-9) of Example 3 A substrate for evaluation was produced in the same manner as in Example 21 except that: imidazole was dried.

(Example 24)
As each surface treatment, each surface treatment (pretreatment, noble metal formation, swelling treatment, permanganate treatment, neutralization treatment, azole treatment) described in (Step f-4) to (Step f-9) of Example 4 A substrate for evaluation was produced in the same manner as in Example 21 except that: pyrazole, dried) was applied.

(Example 25)
As each surface treatment, each surface treatment (pretreatment, noble metal formation, swelling treatment, permanganate treatment, neutralization treatment, electroless treatment described in Example 5 (Step f-4) to (Step f-9). A substrate for evaluation was produced in the same manner as in Example 21 except that the tin plating treatment and drying were performed.

(Example 26)
As each surface treatment, each surface treatment (pretreatment, noble metal formation, swelling treatment, permanganic acid treatment, neutralization treatment, electroless treatment described in Example 6 (Step f-4) to (Step f-9). A substrate for evaluation was produced in the same manner as in Example 21 except that nickel plating, electroless tin plating, and drying were performed.

(Example 27)
As each surface treatment, each surface treatment (pretreatment, noble metal formation, swelling treatment, permanganate treatment, neutralization treatment, electroless treatment described in Example 7 (Step f-4) to (Step f-9). A substrate for evaluation was produced in the same manner as in Example 21 except that cobalt plating treatment, electroless tin plating treatment, and drying were performed.

(Example 28)
As each surface treatment, each surface treatment (pretreatment, noble metal formation, swelling treatment, permanganate treatment, neutralization treatment, electroless treatment described in Example 8 (Step f-4) to (Step f-9). A substrate for evaluation was produced in the same manner as in Example 21 except that tin plating, coupling, and drying were performed.

(Example 29)
As each surface treatment, each surface treatment (pretreatment, noble metal formation, swelling treatment, permanganate treatment, neutralization treatment, electroless treatment described in Example 9 (Step f-4) to (Step f-9). A substrate for evaluation was produced in the same manner as in Example 21 except that tin plating treatment, azole treatment: pyrazole, drying) were performed.

(Example 30)
As the surface treatment, each surface treatment (pretreatment, noble metal formation, swelling treatment, permanganate treatment, neutralization treatment, electroless tin described in Example 10 (Step f-4) to (Step f-9) A substrate for evaluation was produced in the same manner as in Example 21 except that plating treatment, drying, and heat treatment at 150 ° C. were performed.

(Comparative Example 33)
As each surface treatment, each surface treatment (pretreatment, swelling treatment, permanganic acid treatment, neutralization treatment, drying) described in (Step f-4) to (Step f-9) of Comparative Example 1 was performed. A substrate for evaluation was produced in the same manner as in Example 21 except for the above.

(Comparative Example 34)
As each surface treatment, each surface treatment (palladium removal treatment, pretreatment, oxidation treatment: 85 ° C., acidic solution treatment, drying) described in (Step f-3) to (Step f-9) of Comparative Example 2 was performed. A substrate for evaluation was produced in the same manner as in Example 21 except for the above.

(Comparative Example 35)
As each surface treatment, each surface treatment (palladium removal treatment, oxidation treatment: 85 ° C., reduction treatment, drying) described in (Step f-3) to (Step f-9) of Comparative Example 3 was performed. An evaluation substrate was produced in the same manner as in Example 21.

(Comparative Example 36)
Example except that each surface treatment (palladium removal treatment, pretreatment, etching treatment, drying) described in (Step f-3) to (Step f-9) of Comparative Example 4 was performed as each surface treatment. In the same manner as in Example 21, an evaluation substrate was produced.

(Comparative Example 37)
As each surface treatment, each surface treatment (palladium removal treatment, pretreatment, palladium treatment, oxidation treatment: 50 ° C., reduction treatment, drying described in (Step f-3) to (Step f-9) of Comparative Example 5 A substrate for evaluation was produced in the same manner as in Example 21 except that.

(Comparative Example 38)
As each surface treatment, each surface treatment (palladium removal treatment, pretreatment, palladium treatment, oxidation treatment: 50 ° C., acidic solution treatment, described in (Step f-3) to (Step f-9) of Comparative Example 6 A substrate for evaluation was produced in the same manner as in Example 21 except that (drying) was performed.

(Comparative Example 39)
As each surface treatment, each surface treatment (palladium removal treatment, pretreatment, palladium treatment, oxidation treatment: 50 ° C., acidic solution treatment, described in (Step f-3) to (Step f-9) of Comparative Example 7 A substrate for evaluation was produced in the same manner as in Example 21 except that electroless tin plating and drying were performed.

(Comparative Example 40)
As each surface treatment, each surface treatment (pretreatment, oxidation treatment: 85 ° C., acidic solution treatment, drying) described in (Step f-4) to (Step f-9) of Comparative Example 8 was performed. An evaluation substrate was produced in the same manner as in Example 21.

(Comparative Example 41)
As each surface treatment, except that each surface treatment (pretreatment, oxidation treatment: 80 ° C., reduction treatment, drying) described in (Step f-4) to (Step f-9) of Comparative Example 9 was performed. An evaluation substrate was produced in the same manner as in Example 21.

(Comparative Example 42)
Each surface treatment was performed in the same manner as in Example 21 except that each surface treatment (pretreatment, etching treatment, drying) described in (Step f-4) to (Step f-9) of Comparative Example 10 was performed. Thus, an evaluation substrate was produced.

(Comparative Example 43)
As each surface treatment, each surface treatment (pretreatment, palladium treatment, oxidation treatment: 50 ° C., reduction treatment, drying) described in (Step f-4) to (Step f-9) of Comparative Example 11 was performed. A substrate for evaluation was produced in the same manner as in Example 21 except for the above.

(Comparative Example 44)
As each surface treatment, each surface treatment (pretreatment, palladium treatment, oxidation treatment: 50 ° C., acidic solution treatment, drying) described in (Step f-4) to (Step f-9) of Comparative Example 12 is performed. A substrate for evaluation was produced in the same manner as in Example 21 except that.

(Comparative Example 45)
As each surface treatment, each surface treatment (pretreatment, palladium treatment, oxidation treatment: 50 ° C., acidic solution treatment, electroless tin plating described in (Step f-4) to (Step f-9) of Comparative Example 13 A substrate for evaluation was produced in the same manner as in Example 21 except that the treatment and drying were performed.

(Comparative Example 46)
As each surface treatment, each surface treatment (pretreatment, palladium treatment, permanganic acid treatment, neutralization treatment, drying) described in (Step f-3) to (Step f-9) of Comparative Example 14 was performed. A substrate for evaluation was produced in the same manner as in Example 21 except for the above.

(Comparative Example 47)
As each surface treatment, except for performing each surface treatment (pretreatment, palladium treatment, swelling treatment, neutralization treatment, drying) described in (Step f-3) to (Step f-9) of Comparative Example 15 An evaluation substrate was produced in the same manner as in Example 21.

(Comparative Example 48)
As each surface treatment, each surface treatment (pretreatment, palladium treatment, swelling treatment, permanganate treatment, drying) described in (Step f-3) to (Step f-9) of Comparative Example 16 was performed. Produced a substrate for evaluation in the same manner as in Example 21.

(Comparative Example 48A)
Implemented except that each surface treatment (pretreatment, palladium treatment, swelling treatment, chlorate treatment (oxidation treatment: 50 ° C.), neutralization treatment, drying) described in Comparative Example 16A was performed as each surface treatment. An evaluation substrate was produced in the same manner as in Example 21.

4). Evaluation of various characteristics (reliability test of semiconductor packages)
Moisture absorption treatment was performed on each of the 22 semiconductor package samples prepared in Examples 1 to 10 and Comparative Examples 1 to 16A. Subsequently, each sample was flowed in a reflow furnace having an ultimate temperature of 240 ° C. and a length of 2 m under the condition of 0.5 m / min, and reflow was performed. Then, the presence or absence of crack generation was examined for each sample, and the case where it occurred was determined as NG. The results are shown in Table 1. Each of the 22 semiconductor package samples was mounted on a 0.8 mm thick mother board, and a temperature cycle test was performed at −55 ° C. for 30 minutes to 125 ° C. for 30 minutes. At cycle number 1500, a multimeter 3457A (trade name, manufactured by Hewlett-Packard Company) was used to measure the conduction resistance value of the wiring. NG was determined when the measured resistance value changed by 10% or more from the initial resistance value. The results are shown in Table 1. However, in Comparative Example 4 and Comparative Example 10, the wiring accuracy could not be maintained, and the test substrate could not be manufactured.

(Adhesion test with build-up material 1)
AS-ZII (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a build-up material having a film thickness of 45 μm, is laminated on the electrolytic copper foils previously prepared in Examples 11 to 20 and Comparative Examples 17 to 32A. Temporary adhesion was performed for 40 seconds at a temperature of 110 ° C. and a pressure of 0.5 MPa with a vacuum pressure laminator (manufactured by Meiki Seisakusho Co., Ltd.). Then, copper foil and buildup resin were adhere | attached by hold | maintaining for 90 minutes at 180 degreeC with dryer. In addition, the said electrolytic copper foil is adhere | attached with the insulating layer (build-up resin) in the surface side which performed various surface treatments. Next, SR-7200 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a solder resist having a film thickness of 25 μm, was formed on the surface of the build-up resin to prepare an adhesion test substrate. For each of the adhesion test substrates obtained above, the initial (0 hour) adhesive strength, the adhesive strength after leaving at 150 ° C. for 120 hours and 240 hours, 121 ° C., 0.2 MPa for 48 hours and 96 hours of PCT The adhesive strength after standing was measured. The peel strength (N / m), which is an index of the adhesive strength, is measured using a rheometer NRM-3002D-H (trade name, manufactured by Fudo Kogyo Co., Ltd.) and the electrolytic copper foil is perpendicular to the substrate. The peeling was performed at a speed of 50 mm / min. The results are shown in Table 2.

(Adhesion test with build-up material 2)
ABF-GX-13 (Ajinomoto Fine Techno Co., Ltd., trade name), which is a build-up material having a film thickness of 45 μm, is laminated on the electrolytic copper foils prepared in Examples 11 to 20 and Comparative Examples 17 to 32A. Then, temporary adhesion was performed for 40 seconds at a temperature of 110 ° C. and a pressure of 0.5 MPa with a vacuum pressure laminator (manufactured by Meiki Seisakusho Co., Ltd.). Then, copper foil and buildup resin were adhere | attached by hold | maintaining for 90 minutes at 170 degreeC with dryer. In addition, the said electrolytic copper foil is adhere | attached with the insulating layer (build-up resin) in the surface side which performed various surface treatments. Next, SR-7200 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a solder resist having a film thickness of 25 μm, was formed on the surface of the build-up resin to prepare an adhesion test substrate. For each of the adhesion test substrates obtained above, the initial (0 hour) adhesive strength, the adhesive strength after leaving at 150 ° C. for 120 hours and 240 hours, 121 ° C., 0.2 MPa for 48 hours and 96 hours of PCT The adhesive strength after standing was measured. In addition, the measurement of the peel strength (N / m) used as the said parameter | index of adhesiveness uses rheometer NRM-3002D-H (the Fudo Kogyo Co., Ltd. make, brand name), and makes an electrolytic copper foil perpendicular to a board | substrate. The peeling was performed at a speed of 50 mm / min. The results are shown in Table 3.

(Adhesion test with solder resist)
SR-7200 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a solder resist having a film thickness of 25 μm, is applied onto the electrolytic copper foils previously prepared in Examples 11 to 20 and Comparative Examples 17 to 32A and cured. As a result, the copper foil and the solder resist were adhered to each other to produce an adhesion test substrate. In addition, the said electrolytic copper foil is adhere | attached with the insulating layer (solder resist) in the surface side which performed various surface treatments. For each of the adhesion test substrates obtained above, the initial (0 hour) adhesive strength, the adhesive strength after leaving at 150 ° C. for 120 hours and 240 hours, 121 ° C., 0.2 MPa for 48 hours and 96 hours of PCT The adhesive strength after standing was measured. In addition, the measurement of the peel strength (N / m) used as the said parameter | index of adhesiveness uses rheometer NRM-3002D-H (the Fudo Kogyo Co., Ltd. make, brand name), and makes an electrolytic copper foil perpendicular to a board | substrate. The peeling was performed at a speed of 50 mm / min. The results are shown in Table 4.

(Copper surface smoothness evaluation test)
The surface roughness (Rz) of the surface side subjected to the surface treatment of the electrolytic copper foils prepared in Examples 11 to 20 and Comparative Examples 17 to 32A previously was measured using a simple atomic force microscope (AFM) Nanopics 2100 (SII (Trade name) manufactured by Nanotechnology Co., Ltd.). The results are shown in Table 5.

(Condition 4)
Measurement length: 1 μm
SCAN SPEED: 1.35 μm / sec
FORCE REFERENCE: 160

(Insulation test between wires)
About each evaluation board | substrate previously described in Examples 21-30 and Comparative Examples 33-48A, the evaluation board 4 without the short circuit between wiring of L / S = 10 / 10micrometer and the disconnection of wiring as follows. A sheet was selected and the insulation resistance value between the wires was measured. However, the evaluation substrates of Comparative Example 36 and Comparative Example 42 were not measured because the wiring accuracy could not be maintained. First, using a digital ultra-high resistance microammeter R-8340A (trade name, manufactured by Advantest Co., Ltd.), a DC5V voltage was applied between the L / S wires at room temperature (25 ° C.) for 30 seconds, and the L / S wires The insulation resistance value between them was measured. A digital multimeter 3457A (trade name, manufactured by Hewlett-Packard Co., Ltd.) was used for measuring the insulation resistance of 1 GΩ or less. Next, in a constant temperature and humidity layer maintained at a temperature of 85 ° C. and a relative humidity of 85%, a voltage of DC 5 V is continuously applied between the L / S wirings, and the voltage is 24 hours, 48 hours, 96 hours, 200 hours, 500 hours. The insulation resistance value between the L / S wirings was measured in the same manner as described above after 1000 hours. In addition, the constant temperature and humidity chamber used EC-10HHPS (made by Hitachi, Ltd., a brand name), and measured until 1000 hours after throwing. Regarding the four evaluation boards measured as described above, when the minimum value of the insulation resistance value was less than 1 GΩ, it was “No (×)”, and when it was 1 GΩ or more, it was “Good”. The results are shown in Table 6.

(PCT resistance evaluation test)
About each board | substrate for evaluation described in Examples 21-30 and Comparative Examples 33-48A, the PCT resistance test (121 degreeC, 0.2 Mpa, 200 hours) was done. The evaluation method is between the wiring 106 and the insulating layer (build-up layer 104) after the test, between the insulating layer (build-up layer 104) and the insulating layer (build-up layer 104), and between the wiring 106 and the solder resist (insulating coating 109). A non-swelled or peeled layer between the insulating layer (build-up layer 104) and the solder resist (insulating coating 109) was regarded as a good product, and the number thereof was examined. The results are shown in Table 7. However, the evaluation substrates of Comparative Example 36 and Comparative Example 42 were not evaluated because the wiring accuracy could not be maintained.

  As described above, as is apparent from the results of Tables 1 to 7, according to the present invention, the removal of palladium remaining on the surface of the insulating layer between the wirings and the part of the copper wiring surface treatment are performed in the same process. As well as excellent results in various characteristics. More specifically, as shown in Table 1, the reliability of the semiconductor packages manufactured in Examples 1 to 10 was extremely good. Moreover, as shown in Table 5, even if the electrolytic copper foil produced in Examples 11-20 is the smooth surface whose Rz is 100 nm or less, as shown in Table 2 and Table 3, with the build-up resin, The adhesive strength (peel strength) after standing at 150 ° C. for 240 hours was improved by the coupling treatment and the azole treatment, and further improved and improved by the pyrazole treatment. The adhesive strength (peel strength) was further improved and improved by heat treatment even when electroless tin plating was performed. Further, as shown in Table 4, the adhesive strength (peel strength) after leaving with a solder resist at 150 ° C. for 240 hours and after leaving PCT was further improved and improved by performing electroless tin plating treatment. Further, as shown in Table 6, the inter-wiring insulation reliability in the evaluation boards produced in Examples 21 to 30 was extremely good at L / S = 10 μm / 10 μm. Furthermore, as shown in Table 7, the PCT resistance in the evaluation substrates produced in Examples 21 to 30 was subjected to electroless tin plating treatment, so that the buildup layer and the wiring, the buildup layer and the insulating layer, and the solder resist Between the wiring and between the solder resist and the insulating layer.

  On the other hand, in comparison with the present invention, when the conventional surface treatment method is applied, as shown in Comparative Examples 1 to 48A, the process is shortened and smoothness, adhesiveness, inter-wiring insulation reliability, PCT resistance It was not possible to satisfy all the characteristics due to sex.

  Therefore, according to the surface treatment method for a wiring board of the present invention, the process can be shortened, and the adhesion strength between the copper wiring surface and the insulating layer can be improved while the surface of the copper wiring is 100 nm or less. It becomes possible. As a result, it is possible to manufacture a wiring substrate and a semiconductor chip mounting substrate excellent in insulation reliability between wires and fine wiring, and a semiconductor package excellent in reflow resistance and temperature cycle performance.

11 ... Mark for positioning, 13 ... Semiconductor package region,
14 ... Die bond film adhesion area (flip chip type),
15 ... Semiconductor chip mounting area (flip chip type),
16 ... Semiconductor chip connection terminal, 17 ... Die bond film adhesion region (wire bond type),
18 ... Semiconductor chip mounting area (wire bond type), 19 ... External connection terminal, 20 ... Expanded wiring,
21 ... Dummy pattern, 22 ... Semiconductor chip mounting substrate, 23 ... Block, 24 ... Reinforcement pattern,
25. Cutting alignment mark,
DESCRIPTION OF SYMBOLS 100 ... Core board | substrate, 101 ... 1st interlayer connection terminal, 102 ... IVH for 1st interlayer connection,
103 ... second interlayer connection terminal, 104 ... build-up layer, 105 ... third interlayer connection IVH,
106 ... wiring, 106a ... first wiring, 106b ... second wiring, 106c ... third wiring,
107: External connection terminal, 108: IVH for second interlayer connection, 109: Insulation coating,
DESCRIPTION OF SYMBOLS 111 ... Semiconductor chip, 112 ... Connection bump, 113 ... Underfill material, 114 ... Solder ball, 115 ... Gold wire, 116 ... Semiconductor sealing resin, 117 ... Die bond film,
118 ... seed layer, 119 ... resist pattern,
200 ... Grain boundary part, 201 ... Concavity and convexity, 202 ... Concavity and convexity, 203 ... Precious metal, 204 ... Concavity and convexity,
205 ... unevenness, 206 ... unevenness

Claims (7)

A surface treatment method for a wiring board comprising an insulating layer and a copper wiring formed on at least one main surface of the insulating layer,
(I) a treatment step for dissolving the surface of the insulating layer in the wiring board;
(II) a treatment step of forming irregularities on the copper wiring surface,
The treatment step (I) for dissolving the surface of the insulating layer comprises
(Ia) a swelling step for swelling the surface of the insulating layer;
(Ib) an etching step for etching the surface of the insulating layer;
(Ic) a neutralization step of neutralizing the surface of the insulating layer,
A treatment step (II) for forming irregularities on the surface of the copper wiring,
(IIa) a noble metal treatment process for forming a noble metal than copper on the copper wiring surface;
(IIb) an oxidation step of oxidizing the copper wiring surface;
(IIc) an acid treatment step of treating the copper wiring surface with an acidic solution,
At least one of the treatment by the etching step (Ib) and the oxidation step (IIb) and the treatment by the neutralization step (Ic) and the acid treatment step (IIc) is simultaneously performed under the same conditions , Wiring board surface treatment method. A surface treatment method for a wiring board comprising an insulating layer and a copper wiring formed on at least one main surface of the insulating layer,
(A) forming a noble metal than copper on the copper wiring surface of the wiring board;
(B) contacting the wiring board with an alkaline solution containing an organic compound;
(C) contacting the wiring board with an alkaline solution containing permanganate;
(D) Subsequent to the step (C), the method further comprises a step of bringing the wiring substrate into contact with an acidic solution containing a reducing agent for the permanganic acid. Further, as a post-treatment, at least one treatment selected from the group consisting of a treatment that forms a base metal than copper on the copper wiring surface, a treatment that uses a solution containing an azole compound, and a treatment that uses a coupling agent. It characterized by having a step of performing a surface treatment method of a wiring substrate according to claim 1 or 2. Metal nobler than the copper, gold, silver, platinum, palladium, rhodium, wherein rhenium, ruthenium, osmium, and it is a metal selected from the group consisting of iridium, more of claims 1 to 3, 2. A surface treatment method for a wiring board according to claim 1. Forming amount of noble metal than the copper, characterized in that it is a 0.001~40μmol / dm ^2, the surface treatment method of a wiring board according to any one of claims 1-4. The surface roughness of the copper wiring after the surface treatment, characterized in that it is a 1~1000nm in Rz, the surface treatment method of a wiring board according to any one of claims 1-5. The wiring board processed using the surface treatment method of the wiring board of any one of Claims 1-6 .