JP2013093359A - Semiconductor chip mounting substrate and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor chip mounting substrate in which generation of bridges can be reduced even when micro wiring is formed, while ensuring excellent wire bondability and solder joint reliability, and to provide a semiconductor chip mounting substrate thus obtained.SOLUTION: In a process for forming a copper circuit by semi-additive method, electrolytic plating resist is formed, and after forming the copper circuit by electrolytic copper plating, an electroless nickel plating film is formed, thus forming an electroless nickel plating film that is a barrier film for suppressing diffusion of copper only at the upper part of the copper circuit. Thereafter, the electrolytic plating resist is peeled off, copper is removed by etching excepting a part becoming a conductor circuit, and a solder resist pattern is formed. On the copper circuit having an electrolytic nickel plating film formed at an upper part, an electroless palladium plating film is formed, followed by formation of an electroless gold plating film.

Description

  The present invention relates to a semiconductor chip mounting substrate and a method for manufacturing the same.

  In recent years, electronic devices such as personal computers, mobile phones, wireless base stations, optical communication devices, servers, and routers are becoming smaller, lighter, higher in performance, and higher in functionality regardless of size. In addition to increasing the speed and functionality of LSIs such as CPUs, DSPs, and various memories, high-density mounting technologies such as SoC (System on a chip) and SiP (System In Package) are also being developed.

For this reason, build-up type multilayer wiring boards are used for semiconductor chip mounting boards and motherboards. Further, due to advances in mounting technology such as a narrow multi-pin pitch of a package, a semiconductor chip mounting substrate has been changed from QFP (Quad Flat Package) to BGA (Ball Grid Array) / CSP (Chip Size).
Package) has evolved.

  For example, gold wire bonding is used to connect the semiconductor chip mounting substrate and the semiconductor chip. The semiconductor chip mounting substrate connected to the semiconductor chip is connected to a wiring board (motherboard) by solder balls. Therefore, the semiconductor chip mounting substrate usually has connection terminals for connection to the semiconductor chip or the wiring board. These connection terminals are often plated with gold in order to ensure good metal bonding with gold wires or solder.

  Conventionally, electrolytic gold plating has been widely applied as a method of applying gold plating to connection terminals. However, recently, as the wiring density is increased by downsizing the semiconductor chip mounting substrate, it is becoming difficult to secure wiring for performing electrolytic gold plating on the surface of the connection terminal. Therefore, as a method of gold plating on the connection terminals, an electroless gold plating (substitution gold plating or reduction gold plating) process that does not require a lead wire for electrolytic plating has begun to attract attention. For example, as described in Non-Patent Document 1 below, it is known to form an electroless nickel plating film / electroless gold plating film on the copper foil surface of the terminal portion.

  However, as described in Non-Patent Document 2, the method of electroless nickel plating / electroless gold plating compared with the method of electrolytic nickel plating / electrolytic gold plating, solder connection reliability and wire bonding after heat treatment It is known that the sex decreases.

  In addition, when electroless nickel plating is performed on the wiring, a phenomenon called “bridge” occurs in which an electroless nickel plating film is deposited between the wirings, which may cause a short circuit failure. In order to suppress this bridge, for example, a pretreatment liquid and a pretreatment method for suppressing a bridge as shown in Patent Documents 1 and 2 have been proposed. Moreover, as shown in Patent Document 3, an electroless plating catalyst solution for suppressing bridging has also been proposed.

Japanese Patent Laid-Open No. 9-241853 Japanese Patent No. 3387507 Japanese Patent Laid-Open No. 11-124680

“Circuit Technology”, Japan Institute of Electronics Packaging, 1993, Vol. 8, no. 5, P368-372 “Surface Technology”, Surface Technology Association, 2006, Vol. 57, no. 9, P616-621 "Proceedings of the 20th Electronics Packaging Conference", 23B-07, 2006 “ROHM and Hass homepage”, [online], Internet <URL: http: // www. rohmhaas. com / electronicmaterials / CBT / vol1 / papers / Effects of Conductor. pdf>

  By the way, in recent years, by using a wiring formation method such as a semi-additive method, an ultrafine pattern in which the distance between patterns is less than 50 μm, for example, wiring width / wiring spacing (hereinafter abbreviated as “L / S”). = Products having fine wiring of 35 μm / 35 μm are starting to be mass-produced.

  As a conventional technique for forming a connection terminal by applying electroless nickel plating to a circuit made of copper on a substrate having such an ultrafine pattern and forming electroless gold plating thereon, for example, as follows: There are known methods.

That is, the semi-additive method using a resin with copper foil,
(1) Laminating a resin with copper foil on the upper and lower sides of an inner layer plate having an inner layer circuit on the surface;
(2) providing an interstitial via hole (IVH) in a resin with a copper foil, and forming an electroless copper plating layer on the copper foil and inside the IVH;
(3) a step of forming an electroplating resist except a portion where a conductor circuit on the electroless copper plating layer is to be formed;
(4) A step of forming a copper circuit by electrolytic copper plating at a place where a conductor circuit is to be formed,
(5) a step of removing the electrolytic plating resist;
(6) A step of removing the copper foil and the electroless copper plating layer in a portion other than the portion where the conductor circuit is to be formed by etching using an etching solution,
(7) forming a solder resist pattern on the surface of the substrate on which the conductor circuit is formed;
(8) forming an electroless nickel plating film on the conductor circuit; and
(9) It is known to carry out by a step of further forming an electroless gold plating film on the outermost surface of the conductor circuit. That is, electroless nickel plating (step (8)) / electroless gold plating (step (9)) is performed on a specific portion on a conductor circuit made of copper, thereby forming a connection terminal.

  As described above, as the wiring density is increased due to downsizing of the semiconductor chip mounting substrate, the connection terminal portion is replaced with the conventional electrolytic nickel / electrolytic gold plating method, and an electroless plating technique that does not require a lead wire is used. It is becoming essential. Therefore, electroless nickel plating / electroless gold plating is applied even in the semi-additive method as described above.

  However, as a result of investigations by the present inventors, when performing electroless nickel plating on a fine wiring of about L / S = 35 μm / 35 μm using an electroless nickel plating solution, the insulation reliability between conductors is improved. It proved difficult to ensure enough. That is, even if the method of reducing bridges such as the pretreatment liquid and the pretreatment method described in Patent Documents 1 to 3 described above and the electroless plating catalyst liquid is applied, It has been found that a sufficient effect cannot be obtained because electroless nickel plating tends to be deposited on the substrate. In addition, in the case of such a fine wiring, when electroless nickel plating / electroless gold plating is applied, wire bonding performance and solder connection reliability are improved as compared with the case where electrolytic nickel plating / electrolytic gold plating is applied. It has also been found to be significantly lower.

  The present invention has been made in view of such circumstances, and even when fine wiring is formed, the occurrence of bridges can be reduced, and excellent wire bonding properties and solder connection reliability can be obtained. It is an object of the present invention to provide a method for manufacturing a semiconductor chip mounting substrate and a semiconductor chip mounting substrate obtained thereby.

In order to achieve the above object, a method that does not cause a “bridge” of electroless nickel plating in an ultra-fine pattern (for example, fine wiring of about L / S = 35 μm / 35 μm) such that the interval between patterns is less than 50 μm. As a result of intensive studies, in the process of forming a copper circuit by the semi-additive method, after forming an electroplating resist and forming a copper circuit by electrolytic copper plating, an electroless nickel plating film is formed and only on the upper part of the copper circuit It has been found that by forming an electroless nickel plating film that is a barrier film to suppress copper diffusion, the process of forming the electroless nickel plating film on the side of the copper circuit can be eliminated and the occurrence of "bridges" can be suppressed. It was.
Next, the electrolytic plating resist is peeled off, the copper other than the portion to be the conductor circuit is removed by etching, a solder resist pattern is formed, and the electroless palladium plating film is applied to the copper circuit on which the electrolytic nickel plating film is formed. Then, an electroless gold plating film is formed.

  In the conventional electrolytic nickel / electrolytic gold plating method, lead wires for electrolytic plating are necessary, so there is a limit to downsizing and increasing the density of the substrate for mounting a semiconductor chip. If necessary, nickel, palladium, and gold plating are performed by electroless plating, so there is no need for lead wires for electrolytic plating, and independent terminals can be plated. It is possible to cope with higher density.

That is, the present invention relates to the following.
1. The first layer in the laminate comprising: an inner layer plate having an inner layer circuit on the surface; and a first copper layer provided on the inner layer plate with an insulating layer therebetween so as to be partially connected to the inner layer circuit. A resist forming step for forming a resist on the copper layer except for a portion to be a conductor circuit, and a second copper layer is formed by electrolytic copper plating on the portion to be the conductor circuit on the first copper layer. Forming a conductive circuit comprising the first copper layer and the second copper layer, and forming a nickel layer by electroless nickel plating on at least a part of the conductive circuit; A nickel layer forming step; a resist removing step for removing the resist; an etching step for removing the first copper layer covered with the resist by etching; and the conductor circuit on which the nickel layer is formed. A metal layer forming step of forming a metal layer made of at least one metal selected from the group consisting of cobalt, palladium, and platinum by electroless plating or electrolytic plating, and the conductor on which the metal layer is formed. A method for manufacturing a semiconductor chip mounting substrate, comprising: a gold layer forming step of forming a gold layer on at least a part of a circuit by electroless gold plating.
2. Item 2. The semiconductor chip mounting according to Item 1, further comprising a solder resist forming step for forming a solder resist on the surface so that at least a part of the conductor circuit on which the nickel layer is formed is exposed after the etching step and before the gold layer forming step. Manufacturing method for industrial use.
3. In the resist forming step, a copper foil with resin in which an insulating layer mainly composed of a resin and a copper foil are laminated is laminated on the inner layer plate so that the insulating layer faces the inner layer plate side. A via hole is formed in the resin-coated copper foil laminated on the plate so that a part of the inner layer circuit is exposed, and a copper plating layer is formed by electroless copper plating so as to cover the copper foil and the via hole. After forming and obtaining a laminate having a first copper layer consisting of the copper foil and the copper plating layer and partially connected to the inner layer circuit, on the first copper layer in the laminate, Item 3. The method for manufacturing a semiconductor chip mounting substrate according to Item 1 or 2, wherein a resist is formed except for a portion to be a conductor circuit.
4). Item 4. The method for manufacturing a semiconductor chip mounting substrate according to Item 3, wherein the thickness of the copper foil in the resin-coated copper foil is 5 µm or less.
5. In the resist forming step, an insulating layer is formed by laminating a non-conductive film on the inner layer plate having the inner layer circuit on the surface, and one of the inner layer circuits is formed on the insulating layer laminated on the inner layer plate. A via hole is formed so that a portion is exposed, and a copper plating layer is formed by electroless copper plating so as to cover the inside of the insulating layer and the via hole. 3. The resist according to claim 1, wherein after obtaining a laminated body having a first copper layer to be connected, a resist is formed on the first copper layer in the laminated body except for a portion to be a conductor circuit. Manufacturing method of semiconductor chip mounting substrate.
6). After the conductor circuit forming step and before the nickel layer forming step, the nickel layer forming step has an upper resist forming step of further forming a resist and an upper resist covering the conductor circuit so that a part of the conductor circuit is exposed. The method according to any one of Items 1 to 5, wherein a nickel layer is formed on the conductor circuit in a portion exposed from the upper resist, and both the resist and the upper resist are removed in a resist removing step. Manufacturing method of semiconductor chip mounting substrate.
7). Item 7. The method for manufacturing a semiconductor chip mounting substrate according to any one of Items 1 to 6, wherein in the metal layer forming step, the palladium layer is formed by electroless palladium plating.
8). Item 8. The method for manufacturing a semiconductor chip mounting substrate according to Item 7, wherein, in the palladium layer forming step, the palladium layer is formed by performing reduced palladium plating after performing substitution palladium plating.
9. Any one of Items 1 to 8, wherein in the gold layer forming step, electroless gold plating is performed using an electroless gold plating solution containing a reducing agent, and the reducing agent is one that does not generate hydrogen gas by oxidation. The manufacturing method of the board | substrate for semiconductor chip mounting as described in a term.
10. Item 10. The method for manufacturing a semiconductor chip mounting substrate according to any one of Items 1 to 9, wherein at least a part of the conductor circuit is a solder connection terminal or a wire bonding terminal.
11. Item 11. A semiconductor chip mounting substrate obtained by the method for manufacturing a semiconductor chip mounting substrate according to any one of Items 1 to 10.

ADVANTAGE OF THE INVENTION According to this invention, even if it is a case where fine wiring is formed, the production | generation method of the board | substrate for semiconductor chip mounting which can reduce generation | occurrence | production of a bridge | bridging and can obtain the outstanding wire bonding property and solder connection reliability Can be provided.
Further, according to the present invention, since the gold layer can be formed by electroless gold plating in the conductor circuit, it is not necessary to use a lead wire as in the case of performing electrolytic plating, and fine wiring is formed. Also, the gold plating can be satisfactorily performed on the portion to be the independent terminal. Therefore, the manufacturing method of the present invention can cope with further miniaturization and higher density of the semiconductor chip mounting substrate.
Furthermore, according to the present invention, it is possible to provide a semiconductor chip mounting substrate in which the occurrence of bridges is reduced and which has excellent wire bonding properties and solder connection reliability.

It is process drawing which shows typically the manufacturing method of the semiconductor chip mounting substrate which concerns on 1st Embodiment. It is a schematic diagram which expands and shows the cross-sectional structure of the part of the conductor circuit after gold | metal layer formation in the case of performing the metal layer formation process of the board | substrate for semiconductor chip mounting concerning 1st Embodiment. It is process drawing which shows typically the manufacturing method of the semiconductor chip mounting substrate which concerns on 2nd Embodiment. It is a schematic diagram which expands and shows the cross-sectional structure of the part of the conductor circuit after gold | metal layer formation in the case of performing the metal layer formation process of the board | substrate for semiconductor chip mounting concerning 2nd Embodiment.

[First Embodiment]
Hereinafter, a preferred first embodiment of a method for manufacturing a semiconductor chip mounting substrate will be described. FIG. 1 is a process diagram schematically showing a method of manufacturing a semiconductor chip mounting substrate according to the first embodiment. The present embodiment is an example of a method for manufacturing a semiconductor chip mounting substrate by a semi-additive method in which an outer layer circuit is formed on an inner layer plate using a resin with a copper foil.

  In the present embodiment, first, as shown in FIG. 1A, an inner layer plate 1 is prepared. The inner layer board 1 is formed so as to penetrate the inner layer substrate 100, the inner layer circuit 102 provided on the surface thereof, and the inner layer substrate 100, and electrically connect the inner layer circuits 102 on both surfaces. 104. As each configuration in the inner layer plate 1, a known configuration applied to a circuit board can be applied without particular limitation.

  As a method for forming the inner layer plate 1, for example, the following method can be applied. First, after laminating copper foils on both surfaces of the inner layer substrate 100, an unnecessary portion of the copper foil is removed by etching (subtract method). There is a method (additive method) of forming the inner layer circuit 102 made of copper by electroless copper plating only at necessary portions on both surfaces. In addition, a thin metal layer (seed layer) is formed on the surface of the inner layer substrate 100 or a predetermined layer (build-up layer) further formed on the surface, and the inner layer circuit 102 is supported by electrolytic copper plating. A method of forming the inner layer circuit 102 (semi-additive method) by removing a thin metal layer where the pattern is not formed by etching after forming a desired pattern is also included.

  Next, as shown in FIG. 1 (b), a resin-coated copper foil 2 in which an insulating layer 21 mainly composed of a resin and a copper foil 22 are laminated on both surfaces of the inner layer plate 1 is used as the insulating layer. Lamination is performed so that 21 faces the inner layer plate 1 side (FIG. 1B). Lamination | stacking of the copper foil 2 with resin can be performed by laminating or pressing with respect to the inner layer board 1, for example. For example, a general vacuum press can be applied. In this case, the heating / pressurizing condition is preferably a condition suitable for the characteristics of the constituent material of the insulating layer 21 which is an interlayer insulating resin. For example, the temperature can be set to 150 ° C. to 250 ° C. and the pressure can be set to 1 MPa to 5 MPa. In the present embodiment, the copper foil 22 in such a resin-coated copper foil 2 functions as a seed layer, whereby the later-described copper plating layer 3 and second copper layer 5 can be formed. In addition, the insulating layer 21 of the copper foil with resin 2 before being laminated is in a B stage state.

  The thickness of the copper foil 22 in the resin-coated copper foil 2 is preferably 5 μm or less, and more preferably 3 μm or less. In addition, when the thickness of the copper foil is 5 μm or less, etching described later can be easily performed, and fine wiring can be easily formed.

  As the copper foil 22, it is preferable to use a peelable type or an etchable type. When the copper foil 22 is a peelable type, the carrier can be peeled off. When the copper foil 22 is an etchable type, the carrier can be etched to obtain a copper foil having a desired thickness. For example, in the case of the peelable type, the carrier can be peeled off by removing the metal oxide or organic material layer that becomes a peeling layer from the carrier by etching or the like. In the etchable type, when the metal foil is a copper foil and the carrier is an aluminum foil, only the carrier can be etched by using an alkaline solution. The thinner the copper foil 22 is in the range of functioning as a power feeding layer, the more suitable for forming fine wiring. Therefore, in order to obtain such a thickness, the thickness can be reduced by further etching. In that case, in the case of the peelable type, it is efficient and preferable to perform etching simultaneously with the removal of the release layer.

  The resin constituting the insulating layer 21 is an insulating resin, and as such a resin, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be applied. Especially, the organic insulating material which has thermosetting property is preferable. Thermosetting resins include phenolic resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, polybenzimidazole resin, polyamide resin, polyamideimide resin, silicone resin, cyclohexane Resin synthesized from pentadiene, resin containing tris (2-hydroxyethyl) isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimetallate, furan resin, ketone resin, Examples thereof include xylene resins, thermosetting resins containing condensed polycyclic aromatics, and benzocyclobutene resins. Examples of the thermoplastic resin include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, and liquid crystal polymer. The insulating layer 21 may be blended with an inorganic filler such as a silica filler as necessary, or a prepreg containing a glass cloth or the like may be used.

  Next, as shown in FIG.1 (c), the through-hole (via hole) which penetrates the resin-coated copper foil 2 and reaches the inner-layer plate 1 in a predetermined part of the resin-coated copper foil 2 laminated on the inner-layer plate 1 ). Thereby, an interstitial via hole (IVH) 10 is formed, and a part of the inner layer circuit 102 is exposed. The through hole can be formed by, for example, directly irradiating laser light having an ultraviolet wavelength to perform hole processing. As the ultraviolet wavelength laser, it is preferable to use the third harmonic (wavelength 355 nm) of a UV-YAG laser because relatively high energy can be obtained and the processing speed can be increased.

  Further, in the formation of IVH10, it is preferable to adjust the laser energy distribution and to make the cross-sectional shape of the via hole have a tapered shape because the plating property in the hole is improved. Further, it is preferable that the via hole diameter is 50 μm or less because the processing speed is increased. Moreover, since it is preferable from the viewpoint of ensuring reliability that the aspect ratio of the via hole (via hole height / via hole bottom diameter) is 1 or less, when forming the IVH 10, It is preferable to design the relationship between the thickness and the via hole diameter. In addition, since smear may be generated in the via hole, after the via hole is formed, the smear is removed by cleaning with permanganate, chromate, permanganate, etc. It is preferable to carry out.

  Next, as shown in FIG.1 (d), the copper plating layer 3 is formed by electroless copper plating so that the whole surface of the inner-layer board 1 in which the copper foil 2 with resin was laminated | stacked may be covered. Thus, the inner layer plate 1 and the first copper layer 31 composed of the copper foil 22 and the copper plating layer 3 provided with the insulating layer 21 so as to be partially connected to the inner layer circuit 102 of the inner layer plate 1 are provided. The laminated body which has is obtained. In this laminated body, since the surface of the copper foil 22 and the inside of the IVH 10 are continuously covered with the first copper layer 31, the copper foil 22 formed on the surface of the insulating layer 21, the inner layer circuit 102, Can be electrically connected.

  The copper plating layer 3 may be formed using an electroless copper plating method used for the formation of a general wiring board, and a catalyst serving as a nucleus of electroless copper plating is applied to a portion to be plated, This can be formed by thinning an electroless copper plating layer. As the catalyst, noble metal ions or palladium colloid can be used, and palladium is particularly preferable because of its high adhesion to the resin. For the electroless copper plating, an electroless copper plating solution mainly used for forming a wiring board containing copper sulfate, a complexing agent, formalin and sodium hydroxide as main components can be used.

  The thickness of the copper plating layer 3 may be a thickness that can supply power to 10 parts of IVH, and is preferably 0.1 to 1 μm. If the copper plating layer 3 is thinner than 0.1 μm, there is a fear that sufficient power feeding between the copper constituting the inner layer circuit 102 inside the IVH 10 and the copper foil 22 in the resin-coated copper foil 2 may not be obtained. On the other hand, if it is thicker than 1 μm, the thickness of the copper that must be etched increases in the etching process that removes copper other than the portion to be a conductor circuit described later by etching. Formation may be difficult. When the thickness of the copper plating layer 3 is 0.1 to 1 μm, sufficient power supply between the inner layer circuit 102 and the copper foil 22 is obtained, and the etching in the etching process is facilitated and good circuit formability is obtained. It will be obtained.

  Next, as shown in FIG. 1E, a resist 4 that is an electrolytic plating resist is formed at a desired position on the first copper layer 31 (resist forming step). The portion where the resist 4 is formed is a portion excluding a portion (including IVH10) to be a conductor circuit in the first copper layer 31. The resist 4 can be formed by applying a known resist forming method using a material described later. Note that the portion to be a conductor circuit includes an alignment pattern used for alignment.

  The thickness of the resist 4 is preferably equal to or greater than the total thickness of conductors to be subsequently plated. The resist 4 is preferably made of a resin. Resist composed of resin includes liquid resists such as PMER P-LA900PM (trade name, manufactured by Tokyo Ohka Co., Ltd.), HW-425 (Hitachi Chemical Industry Co., Ltd., trade name), RY-3025 (Hitachi Chemical). There are dry film resists such as Kogyo Co., Ltd., trade names).

  Next, as shown in FIG.1 (f), on the surface of the 1st copper layer 31, the 2nd copper layer 5 is formed by electrolytic copper plating, and the 1st copper layer 31 and the 2nd copper layer 5 is obtained (conductor circuit forming step). In this step, the second copper layer 5 is formed only on the portion where the resist 4 is not formed by electrolytic copper plating. Therefore, the second copper layer 5 is formed in a portion that should become the conductor circuit 51 on the first copper layer 31.

  The formation region of the second copper layer 5 is determined by the resist 4 as described above. Therefore, the electrolytic copper plating may be performed by attaching a lead wire to any part of the first copper layer 31 and can sufficiently cope with the case where the wiring density is increased. Electrolytic copper plating can be performed using known copper sulfate electroplating or pyrophosphate electroplating used in the production of a semiconductor chip mounting substrate.

  The thickness of the 2nd copper layer 5 should just be the thickness which can be used as a conductor circuit, and although it is based also on the target space, it is preferable in the range of 1-30 micrometers, and in the range of 3-25 micrometers. More preferably, it is more preferably in the range of 3 to 20 μm.

  Next, as shown in FIG.1 (g), the nickel layer 6 is further formed on the surface of the 2nd copper layer 5 by electroless nickel plating (nickel layer formation process). Also in this step, the nickel layer 6 is formed only on the portion where the resist 4 is not formed by electroless nickel plating. Therefore, the nickel layer 6 is formed in the entire region on the conductor circuit 51.

  The purity of the electroless nickel plating film is preferably 80% by mass or more. The film thickness of the electroless nickel plating film is preferably 0.6 to 8 μm, more preferably 0.8 to 5 μm, and still more preferably 1 to 3 μm. When the film thickness of the electroless nickel plating film is 0.6 μm or more, it becomes easy to obtain connection reliability when left at high temperature after soldering, and when it is 8 μm or less, good high frequency characteristics are obtained. It is easy to be done.

  When the purity of the electroless nickel plating film is 80% by mass or more, the required effect of improving connection reliability is easily obtained.

  Generally, in electroless nickel plating, a high temperature bath of 80 ° C or higher is often used, and it is easy to attack the electrolytic plating resist and the second electrolytic plating resist. It is preferable to do.

  Subsequent to such a nickel layer forming step, as shown in FIG. 1H, the resist 4 which is an electrolytic plating resist is removed (resist removing step). As a result, the portion of the first copper layer 31 (copper plating layer 3) covered with the resist 4 is exposed. The resist 4 can be removed by stripping the resist 4 using an alkaline stripping solution, sulfuric acid, or other commercially available resist stripping solution.

  Then, as shown in FIG. 1I, the portion of the first copper layer 31 (copper foil 22 and copper plating layer 3) covered with the resist 4 is removed by etching (etching step). As a result, all of the copper (first copper layer 31) other than the portion to be the conductor circuit 51 is removed, and the surface of the conductor circuit 51 composed of the first copper layer 31 and the second copper layer 5 is removed from the nickel layer 6. Is formed.

  Etching can be performed by immersing the substrate after removing the resist 4 in an etching solution. As an etchant, a solution containing an acid other than halogen and hydrogen peroxide as main components and a solvent and an additive in addition to the main components can be applied. As the solvent, water is preferably used from the viewpoint of cost, handleability, and safety, and alcohol or the like may be added to the water. Examples of the additive include a hydrogen peroxide stabilizer. Furthermore, examples of acids other than halogen include sulfuric acid and nitric acid, and sulfuric acid is preferably used. When etching is performed using such an etchant, the etching rate of the copper plating layer 3 is 80% or less of the etching rate of the copper foil 22 in order to obtain a circuit pattern having a designed top width, bottom width, and the like. It is preferable to adjust so that.

  When sulfuric acid is used as the acid other than halogen, it is preferable to use 10 to 300 g / L sulfuric acid and 10 to 200 g / L hydrogen peroxide as the concentration of the main component of the etching solution. Below this concentration, the etching rate is slow, and workability tends to deteriorate. On the other hand, if the concentration is higher than this, the etching rate becomes too fast, and it may be difficult to control the etching amount.

  It is preferable from the viewpoint of obtaining good workability that the etching rate of the first copper layer 31 is controlled to be 1 to 15 μm / min. Moreover, since the difference in etching rate due to the difference in crystal structure depends on the temperature of the etching solution, the temperature of the etching solution is preferably 20 to 50 ° C., and preferably 20 to 40 ° C. during the etching. It is more preferable. Further, the etching time may be appropriately determined and applied so that a desired conductor pattern width is formed. From the viewpoint of improving workability and etching uniformity, the etching time is 10 seconds to 10 minutes. It is preferable to be in the range.

  After the etching process, as shown in FIG. 1 (j), before performing the gold layer forming process, which will be described later, the solder is formed on the surface so that at least a part of the conductor circuit 51 on which the nickel layer 6 is formed is exposed. It is preferable to perform a solder resist forming step for forming the resist 7. The solder resist 7 can be formed, for example, so as to cover the conductor circuit 51 (circuit pattern) on which the nickel layer 6 is formed except for the portion to be the wire bonding terminal or the solder connection terminal. By forming such a solder resist 7 before the gold layer forming step, the gold layer 9 can be formed only at a desired position, and the conductor circuit can be protected during electroless gold plating. In addition, the cost can be reduced.

  As the solder resist 7, a thermosetting or ultraviolet curable resin can be used, and among them, an ultraviolet curable type capable of processing the resist shape with high accuracy is preferable. For example, an epoxy resin, a polyimide resin, an epoxy acrylate resin, or a fluorene resin material can be used. The solder resist pattern can be formed by printing if it is a varnish-like material, but from the viewpoint of further improving accuracy, a photosensitive solder resist, a coverlay film, and a film-like resist are used. It is more preferable to apply the known pattern forming method.

  Thereafter, as shown in FIG. 1 (k), a portion of the conductor circuit (circuit pattern) on which the nickel layer 6 is formed, in which the solder resist 7 is not formed, is selected from the group consisting of cobalt, palladium, and platinum. A metal layer 8 selected from at least one kind of metal is formed. Thereby, the metal layer 8 is formed so that the upper surface and side surface of the conductor circuit in which the nickel layer 6 was formed may be covered. The metal layer 8 selected from at least one metal selected from the group consisting of cobalt, palladium, and platinum includes a case where impurities are contained in addition to cobalt, palladium, and platinum. For example, when a palladium metal layer is formed by electroless palladium plating, it may contain phosphorus derived from a reducing agent to form a palladium-phosphorus alloy.

  It should be noted that such a metal layer forming step may be performed after the nickel layer forming step and before the resist removing step (not shown). In this case, the metal layer 8 is formed only on the portion to be a conductor circuit by the resist 4. Therefore, the metal layer 8 is formed on the upper surface of the nickel layer 6 on the conductor circuit.

  When a layer made of cobalt, palladium and platinum is formed as the metal layer 8, these metal layers 8 are formed between the nickel layer 6 and the gold layer 9, and nickel in the nickel layer 6 diffuses into the gold layer 9. Can be prevented. Therefore, good wire bonding properties tend to be easily obtained. Even when the metal layer 8 is formed only on the upper surface of the nickel layer 6, the same effect can be obtained because nickel can be prevented from diffusing to the upper surface to be wire bonded. Of these, palladium is particularly preferable. When palladium is used as the metal layer 8, since the plating solution has high stability, the effect of suppressing the diffusion of nickel is good, and the wire bonding property can be further enhanced. Further, when the solder connection is performed on the gold layer 9, the solder connection reliability may be improved by containing a small amount of palladium.

  When forming the metal layer 8 (palladium layer) made of palladium, the palladium layer is preferably formed by electroless palladium plating. As electroless palladium plating, substituted palladium plating or reduced palladium plating using a reducing agent can be applied. As a method for forming a palladium layer by electroless palladium plating, a method in which reduced palladium plating is performed after displacement palladium plating is particularly preferable. This is because the electroless palladium plating reaction tends to hardly occur on the nickel layer 6 formed by electrolytic nickel plating. A palladium layer can be satisfactorily formed by preliminarily depositing and depositing palladium by substitution palladium plating and then depositing a palladium layer by reduction-type palladium plating.

  The thickness of the palladium layer is preferably 0.03 to 0.5 μm, more preferably 0.01 to 0.3 μm, and further preferably 0.03 to 0.2 μm. When the thickness of the palladium layer exceeds 0.5 μm, the effect of forming the palladium layer is not improved any more, and it tends to be not economical. On the other hand, if the thickness is smaller than 0.03 μm, a portion where the palladium layer is not deposited is likely to be included, and the effect of improving the connection reliability by forming the palladium layer may not be sufficiently obtained.

Although it does not specifically limit as a supply source of palladium of the plating solution used for electroless palladium plating, Palladium compounds, such as palladium chloride, sodium palladium chloride, palladium ammonium chloride, palladium sulfate, palladium nitrate, palladium acetate, palladium oxide, etc. are mentioned. It is done. Specifically, acidic palladium chloride “PdCl ₂ / HCl”, tetraamminepalladium nitrate “Pd (NH ₃ ) ₄ (NO ₃ ) ₂ ”, dinitrodiammine palladium “Pd (NH ₃ ) ₂ (NO ₂ ) ₂ ”, dicyano Diammine palladium “Pd (CN) ₂ (NH ₃ ) ₂ ”, dichlorotetraammine palladium “Pd (NH ₃ ) ₄ Cl ₂ ”, palladium sulfamate “Pd (NH ₂ SO ₃ ) ₂ ”, diammine palladium sulfate “Pd (NH ₃ ) ₂ SO ₄ ”, tetraamminepalladium oxalate“ Pd (NH ₃ ) ₄ C ₂ O ₄ ”, palladium sulfate“ PdSO ₄ ”and the like can be applied. Further, the buffering agent added to the plating solution is not particularly limited.

  The palladium layer formed by electroless palladium plating preferably has a palladium purity of 90% by mass or more, more preferably 99% by mass or more, and particularly preferably close to 100% by mass. When the purity of palladium is less than 90% by mass, precipitation on the nickel layer 6 hardly occurs during the formation thereof, and wire bonding property and solder connection reliability may be deteriorated.

  When a formic acid compound is used as a reducing agent used in electroless palladium plating, the purity of the obtained palladium layer is likely to be 99% by mass or more, and uniform precipitation is possible. In addition, when a phosphorus-containing compound such as hypophosphorous acid or phosphorous acid or a boron-containing compound is used as the reducing agent, the resulting palladium layer becomes a palladium-phosphorus alloy or palladium-boron alloy. It is preferable to adjust the concentration, pH, bath temperature and the like of the reducing agent so that the purity of palladium is 90% by mass or more.

Further, the palladium layer is not necessarily formed by electroless palladium plating, and can be formed by electrolytic palladium plating. In that case, the source of palladium for the electrolytic palladium plating solution used for electrolytic palladium is not particularly limited, and palladium compounds such as palladium chloride, sodium palladium chloride, palladium ammonium chloride, palladium sulfate, palladium nitrate, palladium acetate, palladium oxide, etc. Can be applied. Specifically, acidic palladium chloride (PdCl ₂ / HCl), tetraammine palladium sulfate (Pd (NH ₃ ) ₄ SO ₄ ), palladium nitrate sodium salt (Pd (NO ₃ ) ₂ / H ₂ SO ₄ ), dinitrodiammine palladium (Pd (NH ₃ ) ₂ (NO ₂ ) ₂ ), dicyanodiammine palladium (Pd (CN) ₂ (NH ₃ ) ₂ ), dichlorotetraammine palladium (Pd (NH ₃ ) ₄ Cl ₂ ), palladium sulfamate (Pd ( NH ₂ SO ₃ ) ₂ ), diammine palladium sulfate (Pd (NH ₃ ) ₂ SO ₄ ), tetraammine palladium oxalate (Pd (NH ₃ ) ₄ C ₂ O ₄ ), palladium sulfate (PdSO ₄ ) and the like. Moreover, it does not specifically limit about the buffering agent etc. which are contained in an electrolytic palladium plating solution, It is possible to apply what is contained in a well-known electrolytic palladium plating solution.

  Thereafter, as shown in FIG. 1 (l), a gold layer 9 is formed by electroless gold plating on the portion where the metal layer 8 is formed (gold layer forming step). Thereby, the gold layer 9 is formed so as to cover the upper surface and the side surface of the conductor circuit 51 on which the nickel layer 6 is formed, and this portion can suitably function as a connection terminal such as a wire bonding terminal or a solder connection terminal. It becomes like this.

  The gold layer 9 can be formed, for example, by substitution / reduction gold plating or by electroless gold plating in which reduction gold plating is performed after substitution gold plating. Alternatively, the gold layer 9 can be formed by performing electrolytic gold plating before the location where the gold layer 9 is formed becomes an independent terminal, and then performing reduction-type electroless gold plating. Electroless gold plating may be performed using either method as long as the effect of the present invention is obtained, but the method of performing reduction type gold plating after performing substitution gold plating is good with the underlying metal. The method of performing substitution / reduction gold plating is preferable from the viewpoint of obtaining adhesion, and it is difficult to elute the lower layer metal during plating, and there is a tendency that a good gold layer 9 can be formed.

  When reducing gold plating is performed after displacement gold plating, specifically, with a displacement gold plating solution such as HGS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), about 0.01 to 0.1 μm. After forming a gold plating base film (substitution gold plating film), a reduced electroless gold plating solution such as HGS-2000 (manufactured by Hitachi Chemical Co., Ltd., trade name) is used. Examples thereof include a method of forming a gold plating finish layer (reduced gold plating film) of about 1 μm. However, the method of electroless gold plating is not limited to this, and any method that is suitable for gold plating that is usually performed can be applied without limitation.

  FIG. 2 is an enlarged schematic view showing a cross-sectional configuration of a portion of the conductor circuit after the gold layer 9 is formed in the first embodiment. Here, an example is shown in which electroless gold plating for forming the gold layer 9 is performed by performing reduction-type gold plating after the displacement gold plating as described above. As shown in FIG. 2, in this portion, a copper foil 22, a copper plating layer 3, a second copper layer 5, and a nickel layer 6 are formed on an insulating layer 24 formed on the surface of the inner layer plate 1 (not shown). Are stacked in this order, and a gold layer 9 composed of a metal layer 8, a displacement gold plating film 91, and a reduction-type gold plating film 92 is formed so as to cover the upper surface and side surfaces of these stacked structures.

  The displacement gold plating film 91 can be formed on the surface on which the metal layer 8 is formed. Plating solutions used for displacement gold plating include those containing a cyanide compound and those containing no cyanide compound, but any plating solution can be used. Of these, those containing a cyanide compound are preferred. For this reason, the uniformity of the displacement gold plating in the copper constituting the conductor circuit 51 is better when the plating solution containing cyan is used than when the plating solution containing no cyan is used. Can be mentioned. After performing substitution gold plating with such a cyanide-containing plating solution, if reduction-type gold plating as described later is performed, the gold layer 9 tends to grow uniformly.

  The reduction-type gold plating film 92 can further form a gold film on the replacement gold plating film 91. Therefore, it is possible to form the thick gold layer 9 by performing reduction-type gold plating following substitution gold plating. A plating solution used for reduction-type gold plating can form a gold layer in an autocatalytic manner by containing a reducing agent. These plating solutions include those containing a cyanide compound and those not containing a cyanide compound, but any plating solution can be used.

  As a reducing agent for the plating solution used for reduction-type gold plating, one that does not generate hydrogen gas by oxidation is preferable. Here, examples of the reducing agent that does not generate or hardly generates hydrogen gas include ascorbic acid, urea-based compounds, and phenyl-based compounds. Examples of the reducing agent that generates hydrogen gas include phosphinates and hydrazine. The gold plating solution containing such a reducing agent is preferably one that can be used at a temperature of about 60 to 80 ° C.

  On the other hand, in substitution / reduction gold plating, substitution gold plating and reduction type gold plating reaction are performed in the same solution, and the gold layer 9 can be formed on the surface on which the metal layer 8 is formed in the same manner as the substitution gold plating. . Such plating solutions include those containing a cyanide compound and those containing no cyanide compound, and any plating solution can be used. In addition, after the substitution / reduction gold plating, electroless gold plating can be further performed to increase the thickness of the gold layer.

  The gold layer 9 thus formed is preferably made of gold having a purity of 99% by mass or more. When the gold purity of the gold layer 9 is less than 99% by mass, the reliability of connection may be lowered when this portion is applied as a terminal. From the viewpoint of further improving connection reliability, the purity of the gold layer is more preferably 99.5% by mass or more.

  The thickness of the gold layer 9 is preferably 0.005 to 3 μm, more preferably 0.03 to 1 μm, and still more preferably 0.1 μm to 0.5 μm. By making the thickness of the gold layer 9 0.005 μm or more, wire bonding tends to be facilitated when this portion is used as a terminal. On the other hand, even if the thickness exceeds 3 μm, the effect is not greatly improved. Therefore, it is preferably 3 μm or less from the economical viewpoint.

  Through the above steps, the conductor circuit 51 which is the outer layer circuit is formed on both surfaces of the inner layer plate 1 with the insulating layer 21 therebetween, and the nickel layer 6 and the gold layer 9 are further formed on necessary portions of the conductor circuit 51. A semiconductor chip mounting substrate having a configuration is obtained. In such a semiconductor chip mounting substrate, the portion of the conductor circuit on which the nickel layer 6, the metal layer 8, and the gold layer 9 are formed can function as a wire bonding terminal or a solder connection terminal. It is possible to connect with parts and the like.

[Second Embodiment]
Next, a preferred second embodiment of the method for manufacturing a semiconductor chip mounting substrate will be described. FIG. 3 is a process diagram schematically showing a method for manufacturing a semiconductor chip mounting substrate according to the second embodiment. The present embodiment is an example of a method for manufacturing a semiconductor chip mounting substrate by a semi-additive method, including a step of forming a copper plating layer after laminating a buildup film on an inner layer plate.

  In the present embodiment, first, as shown in FIG. 3A, an inner layer plate 1 is prepared. The inner layer plate 1 can be prepared in the same manner as in the first embodiment described above. Next, as shown in FIG. 3B, a buildup film is laminated or pressed on both surfaces of the inner layer plate 1 to form an insulating layer 23. This build-up film is a film having no electrical conductivity, and is made of a resin material having an insulating property. As such a resin material, the same constituent material as that of the insulating layer 21 mainly composed of the resin in the above-described resin-coated copper foil 2 can be applied, and an inorganic filler such as a silica filler may be blended. The build-up film before lamination is in the B stage state.

  Next, as shown in FIG. 3C, a through hole (via hole) that penetrates the insulating layer 23 and reaches the inner layer plate 1 is formed in a predetermined portion of the insulating layer 23 laminated on the inner layer plate 1. As a result, the IVH 10 is formed, and a part of the inner layer circuit 102 is exposed. The formation of the through hole can also be performed in the same manner as the formation of the through hole for the resin-coated copper foil 2 in the first embodiment.

  Next, as shown in FIG. 3D, the copper plating layer 3 is formed by electroless copper plating so as to cover the entire surface of the inner layer plate 1 on which the insulating layer 23 is laminated. Thereby, the laminated body provided with the 1st copper layer 31 which consists only of the copper plating layer 3 which provided the inner layer board 1 and the insulating layer 23 so that it might connect with the inner layer circuit 102 of the inner layer board 1 in part. can get. In this laminated body, since the copper plating layer 3 is continuously formed up to the inside of the IVH 10, the copper plating layer 3 (first copper layer 31) formed on the surface of the insulating layer 23, the inner layer circuit 102, Can be electrically connected.

  After such a laminate is formed, the resist forming process, the conductor circuit forming process, the nickel layer forming process, the resist removing process, the etching process, the solder resist forming process, and the metal layer are performed in the same manner as in the first embodiment. A formation process and a gold layer formation process are sequentially performed (FIGS. 3E to 3L).

  FIG. 4 is an enlarged schematic view showing a cross-sectional configuration of a portion of the conductor circuit after the gold layer 9 is formed in the second embodiment. Here, an example is shown in which electroless gold plating for forming the gold layer 9 is performed by performing reduction-type gold plating after the displacement gold plating as described above. As shown in FIG. 4, in this portion, the copper plating layer 3, the second copper layer 5, and the nickel layer 6 are laminated in this order on the insulating layer 24 formed on the surface of the inner layer plate 1 (not shown). Then, a gold layer 9 composed of a metal layer 8, a displacement gold plating film 91, and a reduction-type gold plating film 92 is formed so as to cover the upper surface and side surfaces of these laminated structures.

  The preferred embodiments of the present invention have been described above. According to the manufacturing method of the present invention as described above, even when fine wiring is formed, the occurrence of bridges can be reduced and excellent wire bonding can be achieved. Thus, a semiconductor chip mounting substrate capable of obtaining high reliability and solder connection reliability can be obtained. The factors for obtaining these effects by the present inventor are not necessarily clear, but are presumed to be as follows.

(bridge)
First of all, the factors that have conventionally caused bridges to easily occur due to electroless nickel plating are: (1) etching residue between wirings, and (2) no residue remaining between wirings when copper wiring is formed by electroless copper plating. Palladium catalyst residue for electrolytic copper plating, (3) Palladium catalyst residue by substitution palladium plating treatment before electroless nickel plating, (4) Hypophosphorous acid generally used as a reducing agent in electroless plating It is considered that hydrogen gas, etc. generated by the oxidation of the compound act in a complex manner.

  That is, as the miniaturization progresses and the hydrogen gas concentration between the wirings increases, the activity of the electroless nickel plating reaction between the wirings increases, so that the above (1) to (3) ), The electroless nickel plating is likely to be deposited, and this causes a bridge. Further, even when there is no residue as in (1) to (3), the hydrogen gas concentration between the wirings is increased during electroless nickel plating, so that nickel is reduced in this part. In some cases, an alloy layer formed by direct electroless nickel plating is deposited, which may become a bridge.

  Furthermore, the nickel film formed on the side surface of the wiring by electroless nickel plating becomes thicker than the electroless nickel plating film on the top surface of the wiring because the plating activity on the side surface of the wiring increases due to the increase in hydrogen gas concentration. easy. In particular, this tendency becomes stronger as the distance between the wirings becomes smaller, and this also becomes a factor that a bridge is easily generated.

  Here, in the pretreatment liquid and the pretreatment method for suppressing the conventional bridge, or the catalyst for electroless plating, the inventors have described the following factors that cannot suppress the occurrence of the bridge after the electroless nickel plating treatment. I think so.

  That is, the conventional pretreatment liquid, pretreatment method and electroless plating catalyst liquid inactivate the etching residue (1) or the palladium catalyst residue (2) described above, or (3) palladium. It is thought to reduce the amount of catalyst residue. However, the cause of the bridge may be the hydrogen gas (4) as described above. However, in the conventional pretreatment liquid, the pretreatment method, and the electroless plating catalyst liquid, the hydrogen gas is generated between the wirings. It is considered that the generation of bridges cannot be sufficiently suppressed because the effect of suppressing the direct adsorption of the alloy layer by electroless nickel plating cannot be obtained.

  Normally, even when electroless gold plating is performed on a copper circuit, “bridge” hardly occurs. In electroless nickel plating, hypophosphorous acid is generally used as a reducing agent, but hydrogen gas is generated along with its oxidation, which increases the activity of the plating solution near the wiring. Etching residue, palladium catalyst residue for electroless copper plating, or direct nickel deposition is likely to occur.

  In contrast, in electroless gold plating, there are few cases where hydrogen gas is generated as a reducing agent by oxidation of hypophosphorous acid, etc., and ascorbic acid, urea compounds, phenyl compounds, etc. are often used. Therefore, it is considered that the generation of hydrogen gas hardly occurs during electroless gold plating, and therefore “bridge” does not occur.

  Further, since the electroless nickel plating solution is used at a high temperature of 80 to 95 ° C., the deposition rate is fast, for example, 0.2 to 0.3 μm / min. Since it is used at a temperature of about 60 to 80 ° C., the deposition rate is 0.005 to 0.03 μm / min, and even if hydrogen gas is generated, the activity is low. Such a difference in activity due to a difference in the deposition rate is considered to be a factor that determines whether or not “bridge” occurs.

  In contrast, in the present invention, electroless nickel plating is performed on a conductor circuit made of copper in a state where a resist is present, and after removing the resist, electroless gold plating is performed. That is, since the electroless nickel plating is performed on the conductor circuit, the items (1) to (4) described above are less likely to cause a bridge. Furthermore, since the resist is present in the portion other than the conductor circuit, this also greatly suppresses the occurrence of the bridge.

(Solder connection reliability)
When electroless nickel / electroless gold plating is performed on a copper circuit as in the conventional case, as described in Non-Patent Document 2, the electroless nickel plating layer is dissolved by the displacement gold plating reaction, and the fragile layer is formed. Sometimes formed. In this fragile layer, the electroless nickel generally applied is electroless nickel-phosphorus alloy plating, and only nickel is easily eluted in the subsequent displacement gold plating reaction, so that phosphorus is concentrated and remains dissolved. It is thought that it is formed by. And the solder connection reliability falls by formation of such a weak layer.

  On the other hand, in the present invention, after forming the solder resist, the electroless palladium plating is performed on the copper wiring having the upper surface electroless nickel plated, so that the electroless nickel-phosphorus can be used in the subsequent substitution gold plating reaction. Since elution of nickel during alloy plating is suppressed, a fragile layer is hardly formed. For this reason, it is considered that good solder connection reliability can be obtained.

(Wire bonding property)
In the case of conventional electroless nickel / electroless gold plating, as described in Non-Patent Document 2 described above, it has been shown that the wire bonding property is remarkably lowered with heat treatment. The reason why the wire bondability deteriorates as described above is that nickel from the electroless nickel film diffuses in the grain boundary of the gold plating film, and thereby nickel migrates to the surface of the gold plating film, and nickel oxide on this surface. Can be considered. And it is thought that the nickel oxide produced in this way obstructs the adhesion between the gold wire and the gold plating film, leading to a decrease in wire bonding property.

  On the other hand, in the present invention, after forming the solder resist, by performing electroless palladium plating on the copper wiring having the electroless nickel plating on the upper surface, nickel on the upper surface of the copper wiring is prevented from diffusing to the gold surface. At the same time, copper diffusion on the side surface of the copper wiring is suppressed, and it is considered that good wire bondability can be obtained even after the heat treatment.

(High frequency characteristics)
As in Non-Patent Document 3, it is known that the electroless nickel plating film on both sides of the copper wiring has a large effect on the transmission loss. In the present invention, the electroless nickel plating is applied to both sides of the copper wiring. Since it is not deposited, it has excellent high frequency characteristics as compared with conventional electroless nickel / electroless gold plating. Although electrolytic nickel plating can be formed on the upper part of the wiring, as in Non-Patent Document 4, electroless nickel plating has a lower skin resistance than electrolytic nickel plating and is advantageous for higher frequency. Furthermore, while the electrolytic nickel plating film is pure Ni, the electroless nickel plating generally contains phosphorus, so that it has better barrier properties than the electrolytic nickel plating film, and excellent solder connection reliability. is expected. As in Non-Patent Document 4, when nickel plating becomes thick, high frequency characteristics deteriorate, and therefore electroless nickel plating that can be made thinner than electrolytic nickel plating can cope with higher frequencies. Think.

  The preferred embodiments of the semiconductor chip mounting substrate and the manufacturing method thereof according to the present invention have been described above. However, the present invention is not necessarily limited to the above-described embodiments, and may be changed as appropriate without departing from the spirit of the present invention. May be performed.

  For example, in the above embodiment, the nickel layer 6 is formed by electroless nickel plating on the entire region of the second copper layer 5 (conductor circuit), but the nickel layer 6 is formed on the second copper layer 5. You may make it form partially in a predetermined position. Specifically, after forming the second copper layer 5, a resist (upper resist) is formed except for a portion where the nickel layer 6 is formed on the copper layer 3, and this upper resist is formed in the nickel layer forming step. The nickel layer 6 can be formed only on the second copper layer 5 on which no is formed. In this case, the areas not to be used as solder connection terminals or wire bonding terminals on the conductor circuit (second copper layer 5) are not covered with the nickel layer 6 and are in direct contact with the solder resist 7 formed thereon. It becomes like this. Since the solder resist 7 often has higher adhesion to copper than nickel, the above-described configuration can increase the adhesion of the solder resist 7 and further improve the reliability.

  In the above-described embodiment, the example in which the outer layer conductor circuit is formed on both surfaces of the inner layer plate has been described. However, the present invention is not necessarily limited thereto. For example, the outer layer conductor circuit is formed only on one surface side of the inner layer plate. It may be. Furthermore, it is good also as a multilayer board provided with the multilayer conductor circuit by using the semiconductor chip mounting board | substrate obtained above as an inner layer board, and repeating the same process.

Example 1
(Manufacture of semiconductor chip mounting substrates)
(1a) Preparation of inner layer board First, as shown in FIG. 1 (a), a glass cloth base epoxy copper clad laminate having a thickness of 0.2 mm, in which a copper foil having a thickness of 18 μm is bonded to both sides of an insulating base. Prepare MCL-E-679 (trade name, manufactured by Hitachi Chemical Co., Ltd.), remove the unnecessary copper foil by etching, form a through hole, and form the inner layer circuit 102 on the surface The obtained inner layer plate (inner layer plate 1) was obtained.

(1b) Lamination of copper foil with resin As shown in FIG. 1 (b), MCF-7000LX (Hitachi Chemical Co., Ltd.) in which an adhesive (insulating layer 21) is applied to a copper foil 22 having a thickness of 3 μm on both surfaces of the inner layer plate 1. Kogyo Co., Ltd., product name) was laminated by heating and pressing for 60 minutes under the conditions of 170 ° C. and 30 kgf / cm ² (2.9 MPa).

(1c) Formation of IVH As shown in FIG. 1 (c), a carbon dioxide gas impact laser drilling machine L-500 (manufactured by Sumitomo Heavy Industries, Ltd., trade name), a non-through hole with a diameter of 80 μm from above the copper foil 22 Opened IVH10. Furthermore, the substrate after IVH10 formation was immersed in a mixed aqueous solution of potassium permanganate 65 g / L and sodium hydroxide 40 g / L at a liquid temperature of 70 ° C. for 20 minutes to remove smears in the holes.

(1d) Electroless copper plating As shown in FIG.1 (d), the board | substrate after the process of (1c) is 15 degreeC at 25 degreeC to HS-202B (made by Hitachi Chemical Co., Ltd., brand name) which is a palladium solution. The catalyst was applied to the surface of the copper foil 22 by dipping for a minute. Then, using CUST-201 (trade name, manufactured by Hitachi Chemical Co., Ltd.), electroless copper plating was performed at a liquid temperature of 25 ° C. for 30 minutes. Thus, an electroless copper plating layer (copper plating layer 3) having a thickness of 0.3 μm was formed on the copper foil 22 and the surface in the IVH 10.

(1e) Formation of Electrolytic Plating Resist As shown in FIG. 1 (e), dry film photoresist RY-3025 (manufactured by Hitachi Chemical Co., Ltd., trade name) is laminated on the surface of the electroless copper plating layer. The photoresist was exposed to ultraviolet light through a photomask that masks the portion where electrolytic copper plating should be performed, and then developed to form an electrolytic plating resist (resist 4).

(1f) Electrolytic Copper Plating As shown in FIG. 1 (f), an electrolytic copper plating is 20 μm on the copper plating layer 3 using a copper sulfate bath under conditions of a liquid temperature of 25 ° C. and a current density of 1.0 A / dm ^2. The second copper layer 5 having a pattern shape of circuit conductor width / circuit conductor interval (L / S) = 35/35 μm was formed so as to obtain an appropriate thickness. Further, an electrolytic copper plating film (second copper layer 5) was formed on the surface opposite to the surface on which the pattern shape was formed so that a pad having a land diameter of 600 μm for connecting solder balls was formed.
(1g) Electroless Nickel Plating As shown in FIG. 1 (g), electroless nickel plating solution ICP-Nicolon KZ (Okuno Pharmaceutical Co., Ltd., trade name) is immersed for 8 minutes at 70 ° C., and electroless A nickel plating film was deposited by 1 μm.

(1h) Stripping of electroplating resist As shown in FIG. 1 (h), the electroplating resist was removed using HTO (trade name, manufactured by Nichigo Morton Co., Ltd.) which is a resist stripping solution.

(1i) Etching As shown in FIG. 1 (i), a portion of copper (copper) covered with an electroplating resist using an etching solution having a composition of 20 g / L sulfuric acid and 10 g / L hydrogen peroxide as main components. The foil 22 and the copper plating layer 3) were removed by etching.

(1j) Formation of Solder Resist As shown in FIG. 1 (j), a photosensitive solder resist “PSR-4000 AUS5” (trade name, manufactured by Taiyo Ink Manufacturing Co., Ltd.) is applied to the upper surface of the substrate after etching. It was applied with a roll coater so that the thickness after curing was 40 μm. Subsequently, by performing exposure and development, a solder resist 7 having an opening at a desired location on the conductor circuit was formed. Further, a solder resist 7 having an opening diameter of 500 μm was formed on the upper surface of a copper pad having a land diameter of 600 μm in order to form a solder ball connection pad on the lower surface.

(1k) Electroless Palladium Plating As shown in FIG. 1 (k), the electroless palladium plating film is immersed in APP (Ishihara Pharmaceutical Co., Ltd., trade name), which is an electroless palladium plating solution, for 6 minutes at 50 ° C. Was deposited by 0.1 μm.

(1l) Electroless gold plating The substrate after the formation of the solder resist 7 was immersed in HGS-100 (Hitachi Chemical Industry Co., Ltd., a trade name), which is a displacement gold plating solution, for 2 minutes and further washed with water for 1 minute. . Subsequently, it was immersed in HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is a reduced gold plating solution for 45 minutes at 70 ° C., and further washed with water for 5 minutes to form an electroless gold plating film. The total film thickness of the electroless gold plating film obtained by displacement gold plating and reduction type gold plating was 0.5 μm. In the present example and the following examples and comparative examples, the thickness of the nickel layer, the palladium layer, and the gold layer is the fluorescent X-ray film thickness meter SFT9500 (trade name, manufactured by SII Nano Technology Co., Ltd.). And measured.

  In this way, a semiconductor chip mounting substrate having terminal portions covered with the gold layer 9 on the upper and lower surfaces as shown in FIG. In this semiconductor chip mounting substrate, the upper terminal portion corresponds to a wire bonding connection terminal, and the lower terminal portion corresponds to a solder connection terminal. The semiconductor chip mounting substrate has 1000 of each of these terminals (the same applies to the following examples and comparative examples).

(Characteristic evaluation)
(1) Fine wiring formability About the semiconductor chip mounting substrate obtained above, the fine wiring formability after electroless gold plating was evaluated according to the following criteria. The obtained results are shown in Table 1.

A: The bridge is not formed, the plating film is formed well on the terminal portion, and the circuit conductor interval is 25 μm or more.
B: Plating partially protrudes and precipitates on the outer periphery of the terminal portion, and the distance between the circuit conductors is 20 μm or more and less than 25 μm.
C: Plating partially protrudes and deposits on the outer periphery of the terminal portion, and the circuit conductor interval is 15 μm or more and less than 20 μm.
D: Plating partially protrudes from the outer periphery of the terminal portion and deposits, and the distance between the circuit conductors is 5 μm or more and less than 15 μm.
E: Plating partially protrudes and precipitates on the outer periphery of the terminal portion, and the distance between the circuit conductors is less than 5 μm.

(2) Wire bonding property About the board | substrate for semiconductor chip mounting obtained above, the wire bonding property (wire bonding connectivity) of the connection terminal was evaluated by the following reference | standard.

That is, a plurality of semiconductor chip mounting substrates corresponding to Example 1 were subjected to heat treatment at 150 ° C. for 3, 10, 50, 100, and 200 hours, and wire bonding was performed when each heat treatment time had elapsed. It was. Wire bonding was performed using gold wires with a wire diameter of 28 μm at all 1000 wire bonding connection terminals. As a wire bonding apparatus, UTC200-Super2 (manufactured by Shinkawa Co., Ltd., trade name) is used, bonding temperature (heat block temperature): 165 ° C., bond load: 70 gf, ultrasonic output: 90 PLS, ultrasonic time: 25 ms It was.
That is, a plurality of semiconductor chip mounting substrates corresponding to Example 1 were subjected to heat treatment at 150 ° C. for 3, 10, 50, 100, and 200 hours, and wire bonding was performed when each heat treatment time had elapsed. It was. Wire bonding was performed using gold wires with a wire diameter of 28 μm at all 1000 wire bonding connection terminals. As a wire bonding apparatus, UTC200-Super2 (manufactured by Shinkawa Co., Ltd., trade name) is used, bonding temperature (heat block temperature): 165 ° C., bond load: 70 gf, ultrasonic output: 90 PLS, ultrasonic time: 25 ms It was.

(3) Solder connection reliability About the semiconductor chip mounting substrate obtained above, the solder connection reliability of the connection terminals was evaluated according to the following criteria.
That is, after connecting Sn-3.0Ag-0.5Cu solder balls of φ0.76 mm to 1000 solder connection terminals on a semiconductor chip mounting substrate in a reflow furnace (peak temperature 252 ° C.), impact resistance Using a high-speed bond tester 4000HS (trade name, manufactured by Daisy Corporation), a shear (shear) test of the solder balls was performed under the condition of about 200 mm / sec (leaving time 0 h). In addition, after preparing a plurality of semiconductor chip mounting substrates to which solder balls are connected by reflow and leaving them at 150 ° C. for 100, 300, and 1000 hours, respectively, a solder ball shear (shear) test is similarly performed on these substrates. It was.

The evaluation criteria of solder connection reliability are as follows, and evaluation was performed for each terminal based on such criteria. The obtained results are shown in Table 1.
A: Breakage due to shearing in the solder balls was observed in all 1000 connection terminals for solder.
B: Fractures in modes other than shearing due to shear in the solder balls were observed at 1 to 10 locations.
C: Breakage in modes other than shearing due to shear in the solder balls was observed at 11 to 100 locations.
D: Breakage in modes other than shearing due to shear in the solder balls was observed at 101 or more locations.

(Example 2)
(Manufacture of semiconductor chip mounting substrates)
(2a) Preparation of inner layer board First, as shown in FIG. 3 (a), a glass cloth base epoxy copper clad laminate having a thickness of 0.2 mm in which a copper foil having a thickness of 18 μm is bonded to both sides of an insulating base. A plate MCL-E-679 (manufactured by Hitachi Chemical Co., Ltd., trade name) is prepared, the copper foil at the unnecessary portion is removed by etching, a through hole is formed, and an inner layer circuit is formed on the surface. An inner layer plate (inner layer plate 1) was obtained.

(2b) Lamination of resin layer As shown in FIG. 3 (b), thermosetting insulating resin film ABF-45H (Ajinomoto Fine Techno Co., Ltd., trade name) is applied to both surfaces of the inner layer plate at 170 ° C., 30 kgf / The laminate was heated and pressed for 60 minutes under the condition of cm ² (2.9 MPa).

(2c) Formation of IVH As shown in FIG. 3 (c), carbon dioxide gas impact laser drilling machine L-500 (manufactured by Sumitomo Heavy Industries, Ltd., trade name) has a non-through hole with a diameter of 80 μm from the top of the buildup film. Opened IVH10. Furthermore, the substrate after IVH10 formation was immersed in a mixed aqueous solution of potassium permanganate 65 g / L and sodium hydroxide 40 g / L at a liquid temperature of 70 ° C. for 20 minutes to remove smears in the holes.

(2d) Electroless Copper Plating As shown in FIG. 3 (d), the substrate after the step (2c) is applied to HS-202B (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a palladium solution, at 25 ° C. The catalyst was given to the copper foil surface by dipping for a minute. Then, using CUST-201 (trade name, manufactured by Hitachi Chemical Co., Ltd.), electroless copper plating was performed at a liquid temperature of 25 ° C. for 30 minutes. As a result, an electroless copper plating layer (copper plating layer 3) having a thickness of 0.3 μm was formed on the copper foil and on the surface in IVH.

(2e) Formation of electrolytic plating resist As shown in FIG. 3 (e), dry film photoresist RY-3025 (manufactured by Hitachi Chemical Co., Ltd., trade name) is laminated on the surface of the electroless copper plating layer. The photoresist was exposed to ultraviolet light through a photomask that masks the portion where electrolytic copper plating should be performed, and then developed to form an electrolytic plating resist (resist 4).

(2f) Electrolytic copper plating As shown in FIG. 3 (f), an electrolytic copper plating is 20 μm on the copper plating layer 3 using a copper sulfate bath under conditions of a liquid temperature of 25 ° C. and a current density of 1.0 A / dm ^2. The second copper layer 5 having a pattern shape of circuit conductor width / circuit conductor interval (L / S) = 35/35 μm was formed so as to obtain an appropriate thickness. Further, an electrolytic copper plating film (second copper layer 5) was formed on the surface opposite to the surface on which the pattern shape was formed so that a pad having a land diameter of 600 μm for connecting solder balls was formed.

(2g) Electroless Nickel Plating As shown in FIG. 3 (g), electroless nickel plating solution ICP-Nicolon KZ (Okuno Pharmaceutical Co., Ltd., trade name) is immersed for 8 minutes at 70 ° C., and electroless A nickel plating film was deposited by 1 μm.
[Step 1g: Electroless nickel plating step]
As shown in FIG. 3 (g), it is immersed in ICP-Nicolon KZ (Okuno Pharmaceutical Co., Ltd., trade name) which is an electroless nickel plating solution at 70 ° C. for 8 minutes to deposit 1 μm of the electroless nickel plating film. It was.

(2h) Stripping of electroplating resist As shown in FIG. 3 (h), the electroplating resist was removed using HTO (trade name, manufactured by Nichigo Morton Co., Ltd.) which is a resist stripping solution.

(2i) Etching As shown in FIG. 3 (i), the copper in the portion covered with the electrolytic plating resist is etched using an etching solution having a composition of 20 g / L sulfuric acid and 10 g / L hydrogen peroxide as main components. Removed.

(2j) Formation of Solder Resist As shown in FIG. 3 (j), a photosensitive solder resist “PSR-4000 AUS5” (trade name, manufactured by Taiyo Ink Manufacturing Co., Ltd.) is applied to the upper surface of the substrate after etching. It was applied with a roll coater so that the thickness after curing was 40 μm. Subsequently, by performing exposure and development, a solder resist 7 having an opening at a desired location on the conductor circuit was formed. Further, a solder resist 7 having an opening diameter of 500 μm was formed on the upper surface of a copper pad having a land diameter of 600 μm in order to form a solder ball connection pad on the lower surface.

(2k) Electroless Palladium Plating As shown in FIG. 3 (k), the electroless palladium plating film is immersed in APP (Ishihara Pharmaceutical Co., Ltd., trade name) which is an electroless palladium plating solution for 6 minutes at 50 ° C. Was deposited by 0.1 μm.
(2l) Electroless gold plating The substrate after the formation of the solder resist 7 was immersed in HGS-100 (Hitachi Chemical Industry Co., Ltd., trade name) which is a displacement gold plating solution for 2 minutes, and further washed with water for 1 minute. . Subsequently, it was immersed in HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is a reduced gold plating solution for 45 minutes at 70 ° C., and further washed with water for 5 minutes to form an electroless gold plating film. The total film thickness of the electroless gold plating film obtained by displacement gold plating and reduction type gold plating was 0.5 μm.

(Characteristic evaluation)
The obtained semiconductor chip mounting substrate was evaluated in the same manner as in Example 1 for fine wiring formability, wire bonding connection reliability, and solder connection reliability. The obtained results are shown in Table 1.

[Comparative Example 1]
(Manufacture of semiconductor chip mounting substrates)
After performing steps (1a) to (1f) in Example 1, steps (1h) to (1j) were performed without performing steps (1g) (electroless nickel plating).

  Next, the substrate after the solder resist formation was immersed in SA-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a plating activation treatment solution, at 25 ° C. for 5 minutes, washed with water for 1 minute, It was immersed in nickel PS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is an electroless nickel plating solution, at 85 ° C. for 12 minutes and washed with water for 1 minute. Thereby, a 3 μm electroless nickel plating film was formed on the second copper layer.

  Thereafter, the substrate after the formation of the electroless nickel plating film was immersed in HGS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), a substitution gold plating solution, at 85 ° C. for 10 minutes, and then washed with water for 1 minute. Then, it was immersed in HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a reduced gold plating solution, at 70 ° C. for 45 minutes and washed with water for 5 minutes. Thus, a semiconductor chip mounting substrate was obtained. The total film thickness of the gold layer obtained by displacement gold plating and reduction type gold plating was 0.5 μm.

(Characteristic evaluation)
The obtained semiconductor chip mounting substrate was evaluated in the same manner as in Example 1 for fine wiring formability, wire bonding connection reliability, and solder connection reliability. The obtained results are shown in Table 1.
[Comparative Example 2]
(Manufacture of semiconductor chip mounting substrates)
After performing the steps (1a) to (1f) in Example 1, the steps (1h) to (1j) were performed without performing the steps (1g) (electrolytic nickel plating).

Subsequently, the substrate after the formation of the solder resist 7 is immersed in a substituted palladium plating solution having the following composition, which is a plating activation treatment solution, for 5 minutes, and then washed with water and dried, and then substituted palladium plated on the second copper layer. A film was formed.
Composition of substituted palladium plating solution As palladium chloride (palladium): 100 mg / L
Ammonium chloride: 10 g / L
pH: 2 (adjusted with hydrochloric acid)

  Next, the substrate after the treatment with the substituted palladium plating solution was immersed in a treatment solution having the following composition, then washed with water and dried.

Next, the substrate after the treatment with the substituted palladium plating solution was immersed in a treatment solution having the following composition, then washed with water and dried.
Composition of treatment liquid Potassium thiosulfate: 50 g / L
pH adjuster: Sodium citrate pH: 6

Then, the treated substrate was immersed in ICP-Nicolon KZ (Okuno Pharmaceutical Co., Ltd., trade name), which is an electroless nickel plating solution, at 70 ° C. for 8 minutes, and then washed with water for 1 minute. Thereby, a 1 μm electroless nickel plating film was formed on the palladium plating film. Subsequently, this substrate was immersed in HGS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a displacement gold plating solution, at 85 ° C. for 10 minutes, washed with water for 1 minute, and then reduced with a reduced gold plating solution. It was immersed in a certain HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.) at 70 ° C. for 45 minutes and washed with water for 5 minutes. Thus, a semiconductor chip mounting substrate was obtained. The total film thickness of the gold layer obtained by displacement gold plating and reduction type gold plating was 0.5 μm.
(Characteristic evaluation)
The obtained semiconductor chip mounting substrate was evaluated in the same manner as in Example 1 for fine wiring formability, wire bonding connection reliability, and solder connection reliability. The obtained results are shown in Table 1.

[Comparative Example 3]
(Manufacture of semiconductor chip mounting substrates)
After performing steps (1a) to (1f) in Example 1, steps (1h) to (1j) were performed without performing steps (1g) (electroless nickel plating).

Subsequently, after immersing in a substituted palladium plating solution having the following composition as a plating activation treatment solution for 5 minutes, washing and drying were performed to form a substituted palladium plating film on the second copper layer.
Composition of substituted palladium plating solution Hydrochloric acid (35%): 70 ml / L
As palladium chloride (palladium): 50 mg / L
Hypophosphorous acid: 100 mg / L
Acidity: About 0.8N (normative)

  Next, the substrate after the treatment with the substituted palladium plating solution was immersed in ICP-Nicolon KZ (Okuno Pharmaceutical Co., Ltd., trade name, which is an electroless nickel plating solution for 8 minutes at 70 ° C., and washed with water for 1 minute. As a result, an electroless nickel plating film having a thickness of 1 μm was formed on the palladium plating film, and this substrate was then placed on HGS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.) as a displacement gold plating solution. After immersing at 85 ° C. for 10 minutes and washing with water for 1 minute, it was immersed for 45 minutes at 70 ° C. in HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which was a reduced gold plating solution, and washed with water for 5 minutes. As a result, a semiconductor chip mounting substrate was obtained, and the total film thickness of the gold layers obtained by displacement gold plating and reduction type gold plating was 0.5 μm.

(Characteristic evaluation)
The obtained semiconductor chip mounting substrate was evaluated in the same manner as in Example 1 for fine wiring formability, wire bonding connection reliability, and solder connection reliability. The obtained results are shown in Table 1.
[Comparative Example 4]
(Manufacture of semiconductor chip mounting substrates)
In the step (1g), using the electrolytic nickel plating solution having the following composition containing a brightener (primary brightener), the second copper layer under the conditions of a liquid temperature of 55 ° C. and a current density of 1.5 A / dm ^2. A substrate for mounting a semiconductor chip was obtained in the same manner as in Example 1 except that electrolytic nickel plating was performed so that a thickness of about 1 μm was obtained and a nickel layer was formed on the second copper layer. Composition of electrolytic nickel plating solution Nickel sulfate: 240 g / L
Nickel chloride: 45g / L
Boric acid: 30 g / L
Surfactant: 3ml / L
(Nippon High Purity Chemical Co., Ltd., trade name: pit inhibitor # 62)
Saccharin (brightener): 2 g / L
pH: 4

(Characteristic evaluation)
The obtained semiconductor chip mounting substrate was evaluated in the same manner as in Example 1 for fine wiring formability, wire bonding connection reliability, and solder connection reliability. The obtained results are shown in Table 1.

DESCRIPTION OF SYMBOLS 1 ... Inner layer board, 100 ... Board | substrate for inner layer, 102 ... Inner layer circuit, 104 ... Via for inner layer, 2 ... Copper foil with resin, 21 ... Insulating layer, 22 ... Copper foil, 23 ... Insulating layer (build-up film), 24 Insulating layer, 3 ... Copper plating layer (electroless copper plating film), 31 ... First copper layer, 4 ... Resist, 5 ... Second copper layer (electrolytic copper plating film), 51 ... Conductor circuit, 6 ... Nickel layer (electroless nickel plating film), 7 ... solder resist, 8 ... metal layer (electroless palladium plating film), 9 ... gold layer (electroless gold plating film), 91 ... substitution gold plating film, 92 ... reduction type Gold plating film, 10 ... Interstitial via hole (IVH)

Claims (11)

The first layer in the laminate comprising: an inner layer plate having an inner layer circuit on the surface; and a first copper layer provided on the inner layer plate with an insulating layer therebetween so as to be partially connected to the inner layer circuit. A resist forming step of forming a resist on the copper layer except for a portion to be a conductor circuit;
A second copper layer is formed by electrolytic copper plating on a portion to be the conductor circuit on the first copper layer, and the conductor circuit including the first copper layer and the second copper layer is formed. A conductor circuit forming step to obtain;
A nickel layer forming step of forming a nickel layer by electroless nickel plating on at least a part of the conductor circuit;
A resist removing step for removing the resist;
An etching step of removing the portion of the first copper layer covered with the resist by etching;
Metal layer formation in which a metal layer made of at least one metal selected from the group consisting of cobalt, palladium and platinum is formed on at least a part of the conductor circuit on which the nickel layer is formed by electroless plating or electrolytic plating A gold layer forming step of forming a gold layer by electroless gold plating on at least a part of the conductor circuit on which the metal layer is formed;
A method for manufacturing a semiconductor chip mounting substrate having:   The semiconductor chip according to claim 1, further comprising a solder resist forming step for forming a solder resist on the surface so that at least a part of the conductor circuit on which the nickel layer is formed is exposed after the etching step and before the gold layer forming step. Manufacturing method of mounting substrate. In the resist formation process,
On the inner layer plate, a copper foil with a resin in which an insulating layer mainly composed of a resin and a copper foil are laminated, the insulating layer is laminated so as to face the inner layer plate side,
In the copper foil with resin laminated on the inner layer plate, a via hole is formed so that a part of the inner layer circuit is exposed,
A copper plating layer is formed by electroless copper plating so as to cover the inside of the copper foil and the via hole, and a first copper layer comprising the copper foil and the copper plating layer and partially connected to the inner layer circuit is formed. After obtaining a laminate having
The manufacturing method of the board | substrate for semiconductor chip mounting of Claim 1 or 2 which forms a resist on the said 1st copper layer in the said laminated body except the part which should become a conductor circuit.   The thickness of the copper foil in the copper foil with resin is 5 micrometers or less, The manufacturing method of the board | substrate for semiconductor chip mounting of Claim 3 characterized by the above-mentioned. In the resist formation process,
On the inner layer plate having the inner layer circuit on the surface, a non-conductive film is laminated to form an insulating layer,
Forming a via hole in the insulating layer laminated on the inner layer plate so that a part of the inner layer circuit is exposed;
Forming a copper plating layer by electroless copper plating so as to cover the insulating layer and the via hole, and comprising a first copper layer made of the copper plating layer and partially connected to the inner layer circuit; After getting
The manufacturing method of the board | substrate for semiconductor chip mounting of Claim 1 or 2 which forms a resist on the said 1st copper layer in the said laminated body except the part which should become a conductor circuit. After the conductor circuit forming step, before the nickel layer forming step, an upper resist forming step of further forming a resist and an upper resist covering the conductor circuit so that a part of the conductor circuit is exposed,
In the nickel layer forming step, a nickel layer is formed on the conductor circuit in a portion exposed from the upper resist,
The method for manufacturing a semiconductor chip mounting substrate according to claim 1, wherein both the resist and the upper resist are removed in the resist removing step.   The manufacturing method of the board | substrate for semiconductor chip mounting as described in any one of Claims 1-6 which forms a palladium layer by electroless palladium plating in a metal layer formation process.   8. The method for manufacturing a semiconductor chip mounting substrate according to claim 7, wherein, in the palladium layer forming step, the palladium layer is formed by performing reduced palladium plating after performing substitution palladium plating.   In the gold layer forming step, electroless gold plating is performed using an electroless gold plating solution containing a reducing agent, and the reducing agent is one that does not generate hydrogen gas by oxidation. A method for manufacturing a semiconductor chip mounting substrate according to one item.   The method for manufacturing a semiconductor chip mounting substrate according to claim 1, wherein at least a part of the conductor circuit is a solder connection terminal or a wire bonding terminal.   A semiconductor chip mounting substrate obtained by the method for manufacturing a semiconductor chip mounting substrate according to claim 1.

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