JP5938948B2 - Semiconductor chip mounting substrate and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor chip mounting substrate and a method for manufacturing the same.

  In recent years, electronic devices such as personal computers, mobile phones, wireless base stations, optical communication devices, servers, and routers are becoming smaller, lighter, higher in performance, and higher in functionality regardless of size. In addition to increasing the speed and functionality of LSIs such as CPUs, DSPs, and various memories, high-density mounting technologies such as SoC (System on a Chip) and SiP (System in Package) are also being developed.

  For this reason, build-up type multilayer wiring boards are used for semiconductor chip mounting boards and motherboards. In addition, due to advances in mounting technology such as a narrower package multi-pin pitch, a semiconductor chip mounting substrate has evolved from QFP (Quad Flat Package) to BGA (Ball Grid Array) / CSP (Chip Size Package) mounting. .

  For example, gold wire bonding is used to connect the semiconductor chip mounting substrate and the semiconductor chip. The semiconductor chip mounting substrate connected to the semiconductor chip is connected to a wiring board (motherboard) by solder balls. Therefore, the semiconductor chip mounting substrate usually has connection terminals for connection to the semiconductor chip or the wiring board. These connection terminals are often plated with gold in order to ensure good metal bonding with gold wires or solder.

  Conventionally, electrolytic gold plating has been widely applied as a method of applying gold plating to connection terminals. However, recently, as the wiring density is increased by downsizing the semiconductor chip mounting substrate, it is becoming difficult to secure wiring for performing electrolytic gold plating on the surface of the connection terminal. Therefore, as a method of gold plating on the connection terminals, an electroless gold plating (substitution gold plating or reduction gold plating) process that does not require a lead wire for electrolytic plating has begun to attract attention. For example, as described in Non-Patent Document 1 below, it is known to form an electroless nickel plating film / electroless gold plating film on the copper foil surface of the terminal portion.

  However, as described in Non-Patent Document 2, in the method of electroless nickel plating / electroless gold plating, compared to the method of electrolytic nickel plating / electrolytic gold plating, solder connection reliability and wire bonding after heat treatment are performed. It is known that the sex decreases.

  In addition, when electroless nickel plating is performed on the wiring, a phenomenon called “bridge” occurs in which an electroless nickel plating film is deposited between the wirings, which may cause a short circuit failure. In order to suppress this bridge, for example, a pretreatment liquid and a pretreatment method for suppressing a bridge as shown in Patent Documents 1 and 2 have been proposed. Moreover, as shown in Patent Document 3, an electroless plating catalyst solution for suppressing bridging has also been proposed.

  However, even if the pretreatment liquid and the pretreatment method described in Patent Documents 1 to 3 described above, or the technique of reducing the bridge such as the electroless plating catalyst liquid is applied, the conductor is Since electroless nickel plating easily deposits on the substrate in the meantime, it is difficult to obtain a sufficient effect. Therefore, Patent Document 4 discloses a laminate having an inner layer plate having an inner layer circuit on its surface and a first copper layer provided on the inner layer plate with an insulating layer therebetween so as to be partially connected to the inner layer circuit. Forming a resist on the first copper layer except for a portion to be a conductor circuit, and forming a second copper by electrolytic copper plating on the portion to be a conductor circuit on the first copper layer. Forming a layer to obtain a conductor circuit comprising a first copper layer and a second copper layer, and at least a part of the conductor circuit on the opposite side of the conductor circuit by electrolytic nickel plating Etching a nickel layer forming step of forming a nickel layer having an average crystal grain size of 0.25 μm or more on the surface, a resist removing step of removing the resist, and a portion of the first copper layer covered with the resist Etcher removed by When, on at least a part of the conductor circuit layer of nickel is formed, the manufacturing method of the semiconductor chip mounting substrate comprising a gold layer forming step of forming a gold layer by electroless gold plating has been proposed.

  According to such a method of Patent Document 4, since electrolytic nickel plating is performed to form a nickel layer before removing the resist, portions other than the conductor circuit are covered with the resist during electrolytic nickel plating. Therefore, the side surface of the conductor circuit is not plated, and as a result, the bridge can be effectively suppressed. Therefore, this method is effective for suppressing bridging when fine wiring is formed.

Japanese Patent Laid-Open No. 9-241853 Japanese Patent No. 3387507 Japanese Patent Laid-Open No. 11-124680 JP 2011-060824 A

Journal of Printed Circuit Society “Circuit Technology” (1993 Vol. 8 No. 5 pages 368-372) Surface technology (2006, Vol. 57 No. 9, pages 616-621)

  In the method of manufacturing a semiconductor chip mounting substrate described in Patent Document 4 described above, a nickel layer is formed from a nickel layer by forming a nickel layer having an average value of the crystal grain size on the gold layer side surface of 0.25 μm or more. It is possible to suppress the diffusion of nickel into the gold layer, whereby a good wire bonding property can be obtained in the gold layer.

  Here, the diffusion of nickel from the nickel layer to the gold layer can also be suppressed by providing a predetermined metal layer between the nickel layer and the gold layer, and in particular, forming a palladium layer as the metal layer. Thus, it has been found that nickel diffusion can be effectively reduced. As a method for forming the palladium layer, both electrolytic palladium plating and electroless palladium plating are conceivable. However, when the palladium layer is formed by electrolytic palladium plating, the variation in film thickness increases, and it tends to be difficult to obtain a certain thickness. For this reason, when electrolytic palladium plating is performed, areas that are thicker than the minimum necessary thickness are inevitably formed, so that the amount of expensive palladium used increases, which makes it possible to manufacture semiconductor chip mounting substrates. There is an inconvenience that the cost required increases. On the other hand, in the case of electroless palladium plating, since the film thickness variation of the palladium layer can be extremely small, it is possible to form a film with a predetermined thickness at a lower cost than when the palladium layer is formed by electrolytic palladium plating. .

  However, as a result of the study by the present inventors, when a palladium layer is formed on a nickel layer by electroless palladium plating, if the crystal grain size near the surface of the nickel layer is large, a reduction reaction due to electroless palladium plating hardly occurs. It became clear. Further, it has been found that even when the treatment is performed with the reduced palladium plating solution after the treatment with the substitutional palladium plating solution, the reduction reaction hardly proceeds.

  Further, by forming a palladium layer on the nickel layer, diffusion of nickel to the gold surface due to a thermal history such as die bonding before wire bonding can be suppressed. However, when a palladium plating film is formed on a nickel layer having a large average value of the crystal grain size, the thickness tends to be thin, and therefore, when a high temperature treatment exceeding 175 ° C. is performed, nickel diffusion is suppressed. It turned out that the effect tends to be insufficient.

  The present invention has been made in view of such circumstances, a semiconductor that has excellent wire bonding properties, can reduce the occurrence of bridges when forming fine wiring, and has excellent solder connection reliability. An object is to provide a method for manufacturing a chip mounting substrate and a semiconductor chip mounting substrate obtained thereby.

  In order to achieve the above object, the present inventors have intensively studied, and when forming a nickel layer on a conductor circuit, it is possible to suppress the occurrence of bridging by suppressing nickel plating on the side surface of the conductor circuit. In addition, by making the average value of the crystal grain size on the surface of the nickel layer 0.15 μm or less, the nickel layer has a sufficient film thickness by electroless palladium plating, and the film thickness variation The inventors have found that it is possible to form a small palladium layer, and arrived at the present invention.

  That is, the method for manufacturing a substrate for mounting a semiconductor chip according to the present invention includes an inner layer plate having an inner layer circuit on the surface, and a first layer provided on the inner layer plate with an insulating layer therebetween so as to be partially connected to the inner layer circuit. A resist forming step of forming a resist on a first copper layer in a laminate having a copper layer, except for a portion to be a conductor circuit, and a portion to be a conductor circuit on the first copper layer, A conductor circuit forming step of forming a second copper layer by copper plating to obtain a conductor circuit composed of the first copper layer and the second copper layer, and electrolytic nickel plating on at least part of the conductor circuit, A nickel layer forming step for forming a nickel layer having an average crystal grain size of 0.15 μm or less on the surface opposite to the conductor circuit; and at least part of the nickel layer by electroless palladium plating Forming a layer A palladium layer forming step, a resist removing step of removing the resist, an etching step of removing a portion of the first copper layer covered with the resist by etching, and a nickel layer and a first palladium layer are formed. A gold layer forming step of forming a gold layer by electroless gold plating on at least a part of the conductor circuit.

  In the method for manufacturing a semiconductor chip mounting substrate according to the present invention, a resist for electrolytic plating is formed on the first copper layer in accordance with the pattern of the conductor circuit, and then the second copper layer is formed by electrolytic copper plating. Subsequently, a nickel layer is formed by electrolytic nickel plating. Thus, when performing electrolytic nickel plating, since the resist is present in portions other than the conductor circuit, this can prevent the nickel plating from being applied to the side surface of the conductor circuit. Therefore, according to the present invention, even when an ultrafine pattern is used, the formation of bridges is greatly reduced. In addition, the formation of the nickel layer on the conductor circuit as described above is performed by electrolytic nickel plating instead of electroless nickel plating. Therefore, even in the case of fine wiring, wire bonding and solder connection reliability are good. Can also be obtained.

Furthermore, in the present invention, since the first palladium layer is formed on the nickel layer by electroless palladium plating, in the obtained semiconductor chip mounting substrate, the first palladium is interposed between the nickel layer and the gold layer. There will be intervening layers. As a result, it is possible to effectively reduce the diffusion of nickel from the nickel layer to the gold layer at the time of wire bonding or heat treatment before wire bonding, and excellent wire bonding properties can be obtained. In addition, since the first palladium layer is formed by electroless palladium plating, the first palladium layer having a sufficient film thickness and having a small film thickness variation can be obtained. In addition to sufficiently suppressing the diffusion of nickel from the nickel layer to the gold layer, it is also possible to suppress an increase in manufacturing cost due to the formation of the palladium layer.
In the present invention, since the formation of the first palladium layer and the gold layer on the nickel layer is performed by electroless palladium plating and electroless gold plating, it is necessary to use a lead wire as in the case of performing electrolytic plating. Even if the fine wiring is formed, palladium plating and gold plating can be satisfactorily performed on the portion to be the independent terminal. Therefore, it is possible to cope with further downsizing and high density of the semiconductor chip mounting substrate.

  In such a method of manufacturing a semiconductor chip mounting substrate, for example, at least a part of the conductor circuit is used as a connection terminal such as a solder connection terminal or a wire bonding terminal. By forming the first palladium layer and the gold layer, it is possible to obtain a semiconductor chip mounting substrate with good wire bonding property and solder connection reliability.

  After the etching step, before the gold layer forming step, performing a solder resist forming step of forming a solder resist on the surface so that at least a part of the conductor circuit on which the nickel layer and the first palladium layer are formed is exposed. Can do. By forming such a solder resist before forming the gold layer, it becomes easy to form the gold layer only at a predetermined position and protect the circuit during electroless gold plating.

  The resist formation step may be performed according to the following procedure. That is, a copper foil with a resin in which an insulating layer mainly composed of a resin and a copper foil are laminated on the inner layer plate is laminated so that the insulating layer faces the inner layer plate side, and is laminated on the inner layer plate. A via hole is formed in the copper foil with resin so that a part of the inner layer circuit is exposed, and a copper plating layer is formed by electroless copper plating so as to cover the inside of the copper foil and the via hole. After obtaining a laminate having a first copper layer composed of layers and partially connected to the inner layer circuit, a resist is formed on the first copper layer in the laminate except for a portion to be a conductor circuit. Also good. According to such a resist formation step, sufficient power can be obtained between the copper constituting the inner layer circuit inside the via hole and the copper foil in the copper foil with resin.

  In this case, the copper foil in the resin-coated copper foil and the copper plating layer formed by electroless copper plating can function as a seed layer, and the first copper layer made of these also has a second copper on the upper part thereof. A conductor circuit is formed by laminating layers. And according to said resist formation process, it becomes possible to obtain a laminated body provided with such a 1st copper layer favorably. The seed layer refers to a metal film that serves as a base for performing electroplating.

  In such a resist formation step, the thickness of the copper foil in the resin-coated copper foil is preferably 5 μm or less. In this case, since the copper foil as the seed layer is thin, it is easy to remove the seed layer (copper foil) remaining in the portion other than the conductor circuit after removing the resist. Furthermore, it can be formed satisfactorily.

  Moreover, you may perform the said resist formation process in the following procedures. That is, an insulating layer is formed by laminating a non-conductive film on an inner layer plate having an inner layer circuit on the surface, and a part of the inner layer circuit is exposed to the insulating layer laminated on the inner layer plate. A via hole is formed, a copper plating layer is formed by electroless copper plating so as to cover the inside of the insulating layer and the via hole, and a laminate having a first copper layer made of a copper plating layer and partially connected to the inner layer circuit After obtaining the body, a resist may be formed on the first copper layer in the laminated body except for a portion to be a conductor circuit.

  In this case, the copper plating layer functions as a seed layer, and a second copper layer is laminated as it is to form a first copper layer that becomes a conductor circuit. And according to said resist formation process, it becomes possible to obtain a laminated body provided with such a 1st copper layer favorably on an inner layer board.

  Thus, when only a copper plating layer becomes a seed layer, since it is easy to make thickness thin compared with the case where copper foil and a copper plating layer become a seed layer, the viewpoint which makes it easy to remove a seed layer in an etching process, for example Then, it tends to be favorable. However, when the seed layer is formed of a copper foil and a copper plating layer, the catalyst applied before electroless copper plating adheres to the copper foil surface, so the surface of the insulating layer (inside IVH) Is not granted directly. If a catalyst adheres to the insulating layer, the catalyst may remain on the surface of the insulating layer even after the seed layer is removed. As a result, a plating film is deposited between the conductor circuits due to the action of this catalyst, which causes a short circuit failure. May be. Therefore, it is preferable that the seed layer is formed of a copper foil and a copper plating layer from the viewpoint of making it difficult for short-circuit defects due to such a catalyst to occur.

  In the method for manufacturing a semiconductor chip mounting substrate of the present invention, after the solder resist forming step and before the gold layer forming step, on the conductor circuit on which the nickel layer and the first palladium layer exposed from the solder resist are formed, You may have a 2nd palladium layer formation process which forms a 2nd palladium layer by electroless palladium plating. By forming such a second palladium layer, it is possible to suppress the diffusion of copper on the surface of the gold layer on the side surface of the conductor circuit during the heat treatment before wire bonding.

  In the gold layer forming step, electroless gold plating can be performed using an electroless gold plating solution containing a reducing agent, and a reducing agent that does not generate hydrogen gas by oxidation can also be used. By using such a reducing agent, it becomes possible to suppress abnormal deposition of gold plating due to hydrogen gas generated accompanying oxidation.

  In the gold layer forming step, the gold layer may be formed by performing reduction gold plating after performing substitution gold plating. According to such a gold layer forming step, good adhesion to the lower layer metal can be obtained by displacement gold plating, and further, better wire bonding properties can be obtained by thickening the gold layer by reduction-type gold plating. It becomes like this.

  The thickness of the gold layer is preferably 0.005 μm or more. With such a thickness, wire bonding at the time of terminal connection is facilitated.

  The present invention also provides a semiconductor chip mounting substrate obtained by the production method of the present invention. Such a semiconductor chip mounting substrate does not generate a bridge during manufacturing as described above, so that a short circuit failure hardly occurs, and it has excellent wire bonding property and solder connection reliability.

  ADVANTAGE OF THE INVENTION According to this invention, even if it is a case where fine wiring is formed, the production | generation method of the board | substrate for semiconductor chip mounting which can reduce generation | occurrence | production of a bridge | bridging and can obtain the outstanding wire bonding property and solder connection reliability Can be provided.

  In particular, in the nickel layer forming step, an electrolytic nickel layer having an average crystal grain size on the surface opposite to the conductor circuit of 0.15 μm or less is formed to be relatively thick (thickness of 0.1 μm or more). It becomes possible to form a palladium plating film by electroless plating, and even when high temperature treatment such as 175 ° C. is performed before wire bonding, the effect of suppressing nickel diffusion is sufficiently obtained, and wire bonding properties are obtained. Thus, a semiconductor chip mounting substrate having a good quality can be obtained.

  In the present invention, since a gold layer can be formed by electroless gold plating in the conductor circuit, it is not necessary to use a lead wire as in the case of performing electrolytic plating, and it is independent even if fine wiring is formed. Gold plating can be satisfactorily performed on the portion to be the terminal. Therefore, the manufacturing method of the present invention can cope with further miniaturization and higher density of the semiconductor chip mounting substrate.

  Furthermore, according to the present invention, there is provided a semiconductor chip mounting substrate that can be obtained by the manufacturing method of the present invention, has reduced occurrence of bridges, and has excellent wire bonding properties and solder connection reliability. It becomes possible.

It is process drawing which shows typically the manufacturing method of the semiconductor chip mounting substrate which concerns on 1st Embodiment. It is process drawing which shows typically the manufacturing method of the semiconductor chip mounting substrate which concerns on 1st Embodiment. It is process drawing which shows typically the manufacturing method of the semiconductor chip mounting substrate which concerns on 1st Embodiment. It is a schematic diagram which expands and shows the cross-sectional structure of the part of the conductor circuit 50 after gold layer 8 formation. It is process drawing which shows typically the manufacturing method of the semiconductor chip mounting substrate which concerns on 2nd Embodiment. It is process drawing which shows typically the manufacturing method of the semiconductor chip mounting substrate which concerns on 2nd Embodiment. It is process drawing which shows typically the manufacturing method of the semiconductor chip mounting substrate which concerns on 2nd Embodiment.

  Preferred embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant descriptions are omitted.

[First Embodiment]
A preferred embodiment of a method for manufacturing a semiconductor chip mounting substrate will be described below. 1, 2 and 3 are process diagrams schematically showing a method for manufacturing a semiconductor chip mounting substrate according to the present embodiment. The present embodiment is an example of a method for manufacturing a semiconductor chip mounting substrate by a semi-additive method in which an outer layer circuit is formed on an inner layer plate using a resin with a copper foil.

  In the present embodiment, first, as shown in FIG. 1A, an inner layer plate 1 is prepared. The inner layer board 1 is formed so as to penetrate the inner layer substrate 100, the inner layer circuit 102 provided on the surface thereof, and the inner layer substrate, and the inner layer vias 104 electrically connecting the inner layer circuits 102 on both surfaces. And. As each configuration in the inner layer plate 1, a known configuration applied to a circuit board can be applied without particular limitation.

  As a method for forming the inner layer plate 1, for example, the following method can be applied. First, after laminating copper foil as a metal layer on both surfaces of the inner layer substrate 100, an unnecessary portion of the copper foil is removed by etching (subtract method). A method (additive method) of forming the inner layer circuit 102 made of copper by electroless copper plating only at necessary portions on both surfaces of the substrate 100 for use. In addition, a thin metal layer (seed layer) is formed on the surface of the inner layer substrate 100 or a predetermined layer (build-up layer) further formed on the surface, and the inner layer circuit 102 is supported by electrolytic copper plating. A method of forming the inner layer circuit 102 (semi-additive method) by removing a thin metal layer where the pattern is not formed by etching after forming a desired pattern is also included.

  Next, as shown in FIG. 1 (b), a resin-coated copper foil 2 in which an insulating layer 21 mainly composed of a resin and a copper foil 22 are laminated on both surfaces of the inner layer plate 1 is used as the insulating layer. Lamination is performed so that 21 faces the inner layer plate 1 side (FIG. 1B). Lamination | stacking of the copper foil 2 with resin can be performed by laminating or pressing with respect to the inner layer board 1, for example. For example, a general vacuum press can be applied. In this case, the heating / pressurizing condition is preferably a condition suitable for the characteristics of the constituent material of the insulating layer 21 which is an interlayer insulating resin. For example, the temperature can be set to 150 ° C. to 250 ° C. and the pressure can be set to 1 MPa to 5 MPa. In the present embodiment, the copper foil 22 in such a resin-coated copper foil 2 functions as a seed layer, whereby the later-described copper plating layer 3 and second copper layer 5 can be formed.

  The thickness of the copper foil 22 in the resin-coated copper foil 2 is preferably 5 μm or less, and more preferably 3 μm or less. In addition, when the thickness of the copper foil is 5 μm or less, etching described later can be easily performed, and fine wiring can be easily formed.

  As the copper foil 22, it is preferable to use a peelable type or an etchable type. When the copper foil 22 is a peelable type, the carrier can be peeled off. When the copper foil 22 is an etchable type, the carrier can be etched to obtain a copper foil having a desired thickness. For example, in the case of the peelable type, the carrier can be peeled off by removing the metal oxide or organic material layer that becomes a peeling layer from the carrier by etching or the like. In the etchable type, when the metal foil is a copper foil and the carrier is an Al foil, only the carrier can be etched by using an alkaline solution. The thinner the copper foil 22 is in the range of functioning as a power feeding layer, the more suitable for forming fine wiring. Therefore, in order to obtain such a thickness, the thickness can be reduced by further etching. In that case, in the case of the peelable type, it is efficient and preferable to perform etching simultaneously with the removal of the release layer.

  The resin constituting the insulating layer 21 is an insulating resin, and as such a resin, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be applied. Especially, the organic insulating material which has thermosetting property is preferable. Thermosetting resins include phenolic resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, polybenzimidazole resin, polyamide resin, polyamideimide resin, silicone resin, cyclohexane Resin synthesized from pentadiene, resin containing tris (2-hydroxyethyl) isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimetallate, furan resin, ketone resin, Examples thereof include xylene resins, thermosetting resins containing condensed polycyclic aromatics, and benzocyclobutene resins. Examples of the thermoplastic resin include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, and liquid crystal polymer. The insulating layer 21 may be blended with an inorganic filler such as a silica filler as necessary, or a prepreg containing a glass cloth or the like may be used.

  Next, as shown in FIG.1 (c), the through-hole (via hole) which penetrates the resin-coated copper foil 2 and reaches the inner-layer plate 1 in a predetermined part of the resin-coated copper foil 2 laminated on the inner-layer plate 1 ). Thereby, an interstitial via hole (IVH) 30 is formed, and a part of the inner layer circuit 102 is exposed. The through hole can be formed by, for example, directly irradiating laser light having an ultraviolet wavelength to perform hole processing. As the ultraviolet wavelength laser, it is preferable to use the third harmonic (wavelength 355 nm) of a UV-YAG laser because relatively high energy can be obtained and the processing speed can be increased.

  Further, in the formation of IVH30, it is preferable to adjust the laser energy distribution and make the cross-sectional shape of the via hole tapered so that the plating property in the hole is improved. Further, it is preferable that the via hole diameter is 50 μm or less because the processing speed is increased. In addition, since it is preferable that the aspect ratio of the via hole (via hole height / via hole bottom diameter) is 1 or less from the viewpoint of ensuring reliability, the IVH 30 is formed when such an insulating layer 21 is formed. It is preferable to design the relationship between the thickness and the via hole diameter. In addition, since smear may be generated in the via hole, after the via hole is formed, the smear is removed by cleaning with permanganate, chromate, permanganate, etc. It is preferable to carry out.

  Next, as shown in FIG.1 (d), the copper plating layer 3 is formed by electroless copper plating so that the whole surface of the inner layer board 1 in which the copper foil 22 with resin was laminated | stacked may be covered. Thus, the inner layer plate 1 and the first copper layer 32 made of the copper foil 22 and the copper plating layer 3 provided with the insulating layer 21 so as to be partially connected to the inner layer circuit 102 of the inner layer plate 1 are provided. The laminated body 110 which has is obtained. In this laminated body 110, the surface of the copper foil 22 and the inside of the IVH 30 are continuously covered with the first copper layer 32, so the copper foil 22 formed on the surface of the insulating layer 21 and the inner layer circuit 102. Can be electrically connected.

  The copper plating layer 3 may be formed using an electroless copper plating method used for the formation of a general wiring board, and a catalyst serving as a nucleus of electroless copper plating is applied to a portion to be plated, This can be formed by thinning an electroless copper plating layer. As the catalyst, noble metal ions or palladium colloid can be used, and palladium is particularly preferable because of its high adhesion to the resin. For the electroless copper plating, an electroless copper plating solution mainly used for forming a wiring board containing copper sulfate, a complexing agent, formalin and sodium hydroxide as main components can be used.

  The thickness of the copper plating layer 3 may be a thickness that enables power supply to 30 parts of IVH, and is preferably 0.1 to 1 μm. If the copper plating layer 3 is thinner than 0.1 μm, there is a possibility that power supply between the copper constituting the inner layer circuit 102 inside the IVH 30 and the copper foil 22 in the resin-coated copper foil 2 may not be sufficiently obtained. On the other hand, if it is thicker than 1 μm, the thickness of the copper that must be etched increases in the etching process that removes copper other than the portion to be a conductor circuit described later by etching. Formation may be difficult. When the thickness of the copper plating layer 3 is 0.1 to 1 μm, sufficient power supply between the inner layer circuit 102 and the copper foil 22 is obtained, and the etching in the etching process is facilitated and good circuit formability is obtained. It will be obtained.

  Next, as shown in FIG. 2E, a resist 4 that is an electrolytic plating resist is formed at a desired position on the first copper layer 32 (resist formation step). The portion where the resist 4 is formed is a portion excluding a portion (including IVH 30) to be a conductor circuit in the first copper layer 32. The resist 4 can be formed by applying a known resist forming method using a material described later. Note that the portion to be a conductor circuit includes an alignment pattern used for alignment.

  The thickness of the resist 4 is preferably equal to or greater than the total thickness of conductors to be subsequently plated. The resist 4 is preferably made of a resin. Resist composed of resin includes liquid resists such as PMER P-LA900PM (trade name, manufactured by Tokyo Ohka Co., Ltd.), HW-425 (Hitachi Chemical Industry Co., Ltd., trade name), RY-3025 (Hitachi Chemical). There are dry film resists such as Kogyo Co., Ltd., trade names).

  Next, as shown in FIG.2 (f), the 2nd copper layer 5 is formed on the surface of the 1st copper layer 32 by electrolytic copper plating, and the 1st copper layer 32 and the 2nd copper layer 5 is obtained (conductor circuit forming step). In this step, the second copper layer 5 is formed only on the portion where the resist 4 is not formed by electrolytic copper plating. Therefore, the second copper layer 5 is formed in a portion to be the conductor circuit 50 on the first copper layer 32.

  The formation region of the second copper layer 5 is determined by the resist 4 as described above. Therefore, the electrolytic copper plating may be performed by attaching a lead wire to any part of the first copper layer 32, and can sufficiently cope with the case where the wiring density is increased. Electrolytic copper plating can be performed using known copper sulfate electroplating or pyrophosphate electroplating used in the production of a semiconductor chip mounting substrate.

  The thickness of the 2nd copper layer 5 should just be the thickness which can be used as a conductor circuit, and although it is based also on the target space, it is preferable in the range of 1-30 micrometers, and in the range of 3-25 micrometers. More preferably, it is more preferably in the range of 3 to 20 μm.

  Next, as shown in FIG. 2G, a nickel layer 6 is further formed on the surface of the second copper layer 5 by electrolytic nickel plating (nickel layer forming step). Also in this step, the nickel layer 6 is formed only on the portion where the resist 4 is not formed by electrolytic nickel plating. Therefore, the nickel layer 6 is formed in the entire region on the conductor circuit 50. Also in this step, a lead wire may be attached to any part of the conductor circuit 50 and electrolytic nickel plating may be performed.

  The electrolytic nickel plating can be performed, for example, by immersing the entire substrate after the conductor circuit forming step in an electrolytic nickel plating solution. Electrolytic nickel plating solutions include Watts bath (nickel plating bath mainly composed of nickel sulfate, nickel chloride and boric acid), sulfamic acid bath (nickel plating bath mainly composed of nickel sulfamate and boric acid), borofluoride A bath or the like can be used. In particular, the deposited film from the watt bath has good adhesion to the conductor circuit 50 serving as a base, and tends to increase the corrosion resistance. Therefore, it is preferable to use a Watt bath for electrolytic nickel plating.

  The nickel layer 6 is formed so that the average value of the crystal grain diameter of nickel on the surface opposite to the conductor circuit 50, that is, the surface in contact with the palladium layer 13 as described later, is 0.15 μm or less. The average value of the crystal grain size on the surface of the nickel layer 6 is preferably 0.1 μm or less, more preferably 0.07 μm or less, and the smaller the crystal grain size, the better. Generally, a brightening agent is added to the electrolytic nickel plating solution, and the brightening agent obtains a gloss by reducing crystal grains. Therefore, in order to obtain the crystal grain size as described above, the electrolytic nickel plating solution is preferably added with a certain amount of brightener.

  Electroless nickel generally applied to nickel plating is electroless nickel-phosphorus alloy plating, and an amorphous film is formed, whereas a film formed by electrolytic nickel is crystalline. Therefore, the nickel crystal grains are likely to be larger in the electrolytic nickel film than in the electroless nickel film. Therefore, in this embodiment, it is preferable to use an electrolytic nickel plating solution containing a brightener in order to form the nickel layer 6 having an average value of the surface crystal grain system of 0.1 μm or less by electrolytic nickel plating. There are two types of brighteners for electrolytic nickel plating solutions: primary brighteners and secondary brighteners. The primary brightener has the function of imparting gloss by refining the crystals of the film. It works to fill small scratches that cannot be obtained with a primary brightener, that is, to give a leveling effect. Examples of the primary brightener include aromatic sulfonic acids (such as benzenesulfonic acid), aromatic sulfonamides (such as p-toluenesulfonic acid amide), and aromatic sulfonamides (such as saccharin). Secondary brighteners include aldehydes (formaldehyde, etc.), allyl, vinyl compounds (allylsulfonic acid, etc.), acetylene compounds (2-butyl 1,4-thiol, etc.), nitriles (ethyl cyanohydrin, etc.) Is mentioned. The electrolytic nickel plating solution may contain a primary brightener or may contain only a primary brightener. In order to obtain the nickel layer 6 having a crystal system near the surface, the brightener content in the electrolytic nickel plating solution is preferably 1 to 10 g / L, and more preferably 1 to 5 g / L. preferable.

  The thickness of the nickel layer 6 formed by electrolytic nickel plating is preferably 0.4 to 10 μm, more preferably 0.6 to 8 μm, and even more preferably 1 to 6 μm. By setting the thickness of the nickel layer 6 to 0.4 μm or more, an effect as a barrier film of a conductor circuit made of copper in the lower layer can be sufficiently obtained, thereby improving the solder connection reliability. If the thickness is 0.4 μm or more, the growth of nickel crystal grains depends on the plating solution, and a plating film with small crystal grains can be formed. However, even if it exceeds 10 μm, these effects are not greatly improved and it is not economical. Therefore, the thickness of the nickel layer 6 is preferably 10 μm or less.

In electrolytic nickel plating, the current density tends to affect crystal growth. Specifically, the current density in the electrolytic nickel plating is preferably 0.3~4A / dm ^2, more preferably 0.3~1.5A / dm ^2, 0.3~ More preferably, it is 1.0 A / dm ² . By setting the current density to 0.3 A / dm ² or more, partial unprecipitation of nickel can be suppressed. The lower the current density within the above range, the smaller the crystal grains of nickel, so the lower the current density, the better. In addition, when the current density is 4 A / dm ² or less, the occurrence of rough plating (generally called “burning”) tends to be suppressed.

  Following such a nickel layer forming step, as shown in FIG. 2H, a palladium layer 13 (first palladium layer) is formed on the nickel layer 6 by electroless palladium plating. In this step, the palladium layer 13 is formed only on the portion where the resist 4 is not formed by electroless palladium plating. Therefore, the palladium layer 13 is formed in the entire region on the nickel layer 6.

  In the present embodiment, as described above, the average value of the crystal grain size of the surface of the nickel layer 6 on the side where the palladium layer 13 is formed is 0.15 μm or less. By forming such a nickel layer 6, it is extremely possible to form the palladium layer 13 by electroless palladium plating, compared to the case where a nickel layer having an average surface grain size exceeding 0.15 μm is formed. It becomes easy.

  Here, on the nickel layer having an average surface crystal grain size larger than 0.15 μm, after reduction treatment by electroless palladium plating or treatment with a substitutional palladium plating solution, reduced palladium is used. When the treatment with the plating solution is performed, the reduction reaction hardly occurs, and the formation of the palladium layer is difficult. The reason is considered as follows. That is, when a palladium film is formed on a nickel layer by electroless palladium plating, it is necessary to first dissolve nickel by a substitution reaction to deposit and deposit a certain amount of palladium. Thus, the reaction by electroless palladium plating proceeds on the palladium on which a certain amount or more of the substitution is deposited. At this time, the substitution reaction proceeds from a defect portion of the crystal such as a crystal grain boundary. Therefore, the larger the crystal grain size of nickel, the lower the density of crystal grain boundaries on the surface, so that the substitution reaction itself is less likely to occur. As a result, it is considered that substitution deposition of a certain amount or more of palladium necessary for the progress of the electroless palladium plating reaction does not occur, and the electroless palladium reaction does not proceed. On the other hand, in this embodiment, by making the crystal grain size on the surface of the nickel layer 6 0.15 μm or less, a substitution reaction of palladium is likely to occur, and thereby a certain amount or more of palladium can be deposited. As a result, it is considered that the electroless palladium plating reaction easily proceeds.

  By forming the palladium layer 13 on the nickel layer 6 as in this embodiment, peeling of the gold layer 8 can be greatly reduced. For example, when the palladium layer 13 is not formed and only the nickel layer 6 is formed, the surface of the nickel layer 6 is likely to be oxidized by subsequent etching or heat treatment when forming the solder resist. When the surface of the nickel layer 6 is oxidized, the adhesion between the nickel layer 6 and the gold layer 8 is lowered, so that the gold layer 8 may be peeled off from the nickel layer 6 when wire bonding is performed. On the other hand, by forming the palladium layer 13, the palladium film is not easily affected by etching or heat treatment, and the surface is also difficult to oxidize. Therefore, sufficient adhesion between the gold layer 8 and the palladium layer 13 can be obtained. Even during bonding, the gold layer 8 does not easily peel off. As a result, sufficient wire bonding properties can be obtained. In addition, when forming a solder resist as will be described later, since the palladium film has higher adhesion to the solder resist than to the nickel film, the formation of the palladium layer 13 is very difficult from the viewpoint of adhesion to the solder resist. To be advantageous.

  For the formation of the palladium layer 13, substitutional palladium plating or reduced palladium plating using a reducing agent can be applied. As a method for forming the palladium layer 13 by electroless palladium plating, a method in which reduced palladium plating is performed after displacement palladium plating is particularly preferable. This is because the electroless palladium plating reaction tends to hardly occur on the nickel layer 6 formed by electrolytic nickel plating. The palladium layer 13 can be satisfactorily formed by preliminarily precipitating and precipitating palladium by displacement palladium plating, and then further precipitating palladium by reduced palladium plating. Note that the palladium layer 13 may contain impurities. For example, when hypophosphorous acid is used as the reducing agent, since phosphorus is eutectoid from hypophosphorous acid, the palladium layer 13 may be a palladium-phosphorus alloy.

  The thickness of the palladium layer 13 is preferably 0.03 to 0.5 μm, more preferably 0.05 to 0.4 μm, and still more preferably 0.1 to 0.3 μm. If the thickness of the palladium layer 13 exceeds 0.5 μm, the effect due to the formation of the layer does not improve any more, and the cost tends to increase excessively. On the other hand, if the thickness is less than 0.03 μm, a portion where the palladium layer is not formed is likely to be included, and the effect of improving the connection reliability by forming the palladium layer 13 may not be sufficiently obtained. In particular, considering that a high temperature treatment at 175 ° C. or higher is performed before wire bonding, the electroless palladium layer 13 is preferably thicker than 0.1 μm in order to obtain a sufficient effect.

The source of palladium for the plating solution used for electroless palladium plating is not particularly limited. Examples thereof include palladium compounds such as palladium chloride, sodium palladium chloride, palladium ammonium chloride, palladium sulfate, palladium nitrate, palladium acetate, and palladium oxide. Specifically, acidic palladium chloride “PdCl ₂ / HCl”, tetraamminepalladium nitrate “Pd (NH ₃ ) ₄ (NO ₃ ) ₂ ”, palladium (II) nitrate dihydrate “Pd (NO ₃ ) ₂ · 2H ₂ O ”, dinitrodiammine palladium“ Pd (NH ₃ ) ₂ (NO ₂ ) ₂ ”, dicyanodiammine palladium“ Pd (CN) ₂ (NH ₃ ) ₂ ”, dichlorotetraammine palladium“ Pd (NH ₃ ) ₄ Cl ₂ ” , Palladium sulfamate “Pd (NH ₂ SO ₃ ) ₂ ”, diammine palladium sulfate “Pd (NH ₃ ) ₂ SO ₄ ”, tetraammine palladium oxalate “Pd (NH ₃ ) ₄ C ₂ O ₄ ”, palladium sulfate “PdSO” ₄ "etc. can be applied. Further, the buffering agent added to the plating solution is not particularly limited.

  The palladium layer 13 formed by electroless palladium plating preferably has a palladium purity of 90% by mass or more, more preferably 99% by mass or more, and particularly preferably close to 100% by mass. When the purity of palladium is 90% by mass or more, precipitation on the nickel layer 6 is facilitated at the time of formation, and the wire bonding property and the solder connection reliability are hardly lowered.

  When a formic acid compound is used as the reducing agent used for electroless palladium plating, the purity of the obtained palladium layer tends to be 99% by mass or more, and uniform precipitation is possible. On the other hand, when a phosphorus-containing compound such as hypophosphorous acid or phosphorous acid or a boron-containing compound is used as the reducing agent, the resulting palladium layer tends to be a palladium-phosphorus alloy or a palladium-boron alloy. In that case, it is preferable to adjust the concentration, pH, bath temperature, etc. of the reducing agent so that the purity of palladium is 90% by weight or more.

  Following such an electroless palladium layer forming step, as shown in FIG. 3I, the resist 4 which is an electrolytic plating resist is removed (resist removing step). As a result, the portion of the first copper layer 32 (copper plating layer 3) covered with the resist 4 is exposed. The resist 4 can be removed by stripping the resist 4 using an alkaline stripping solution, sulfuric acid, or other commercially available resist stripping solution.

  Then, as shown in FIG. 3J, the portion of the first copper layer 32 (copper foil 22 and copper plating layer 3) covered with the resist 4 is removed by etching (etching step). As a result, all of the copper (first copper layer 32) other than the portion to be the conductor circuit is removed, and the surface of the conductor circuit 50 composed of the first copper layer 32 and the second copper layer 5 is removed from the nickel layer 6 and A circuit pattern covered with the first palladium layer 13 is formed.

  Etching can be performed by immersing the substrate after removing the resist 4 in an etching solution. As an etchant, a solution containing an acid other than halogen and hydrogen peroxide as main components and a solvent and an additive in addition to the main components can be applied. As the solvent, water is preferably used from the viewpoint of cost, handleability, and safety, and alcohol or the like may be added to the water. Examples of the additive include a hydrogen peroxide stabilizer. Furthermore, examples of acids other than halogen include sulfuric acid and nitric acid, and sulfuric acid is preferably used. When etching is performed using such an etchant, the etching rate of the copper plating layer 3 is 80% or less of the etching rate of the copper foil 22 in order to obtain a circuit pattern having a designed top width, bottom width, and the like. It is preferable to adjust so that.

  When sulfuric acid is used as the acid other than halogen, it is preferable to use 10 to 300 g / L sulfuric acid and 10 to 200 g / L hydrogen peroxide as the concentration of the main component of the etching solution. Below this concentration, the etching rate is slow, and workability tends to deteriorate. On the other hand, if the concentration is higher than this, the etching rate becomes too fast, and it may be difficult to control the etching amount.

  The etching rate of the first copper layer 32 is preferably controlled so as to be 1 to 15 μm / min from the viewpoint of obtaining good workability. Moreover, since the difference in etching rate due to the difference in crystal structure depends on the temperature of the etching solution, the temperature of the etching solution is preferably 20 to 50 ° C., and preferably 20 to 40 ° C. during the etching. It is more preferable. Further, the etching time may be appropriately determined and applied so that a desired conductor pattern width is formed. From the viewpoint of improving workability and etching uniformity, the etching time is 10 seconds to 10 minutes. It is preferable to be in the range.

  Furthermore, after the etching process, the first copper layer 32 (copper plating layer 3) partially remaining on the surface of the insulating layer between the conductor circuits 50 composed of the first copper layer 32 and the second copper layer 5 by desmear treatment. ) Is preferably removed together with the resin. By removing the first copper layer 32 (copper plating layer 3) partially remaining on the surface of the insulating layer, gold deposition on the first copper layer 32 partially remaining on the surface of the insulating layer is suppressed. This makes it possible to further improve the insulation reliability.

  After the etching step, as shown in FIG. 3 (k), at least a part of the conductor circuit 50 on which the nickel layer 6 and the palladium layer 13 are formed is exposed before the gold layer forming step described later is performed. It is preferable to perform a solder resist forming step of forming the solder resist 7 on the surface. The solder resist 7 may be formed, for example, so as to cover the conductor circuit 50 (circuit pattern) on which the nickel layer 6 and the palladium layer 13 are formed, except for the portion to be a wire bonding terminal or a solder connection terminal. it can. By forming such a solder resist 7 before the gold layer forming step, it becomes possible to form the gold layer 8 only at a desired position and to protect the conductor circuit during electroless gold plating. In addition, the cost can be reduced.

  As the solder resist 7, a thermosetting or ultraviolet curable resin can be used, and among them, an ultraviolet curable type capable of processing the resist shape with high accuracy is preferable. For example, an epoxy resin, a polyimide resin, an epoxy acrylate resin, or a fluorene resin material can be used. The solder resist pattern can be formed by printing if it is a varnish-like material, but from the viewpoint of further improving accuracy, a photosensitive solder resist, a coverlay film, and a film-like resist are used. It is more preferable to apply the known pattern forming method.

  Thereafter, as shown in FIG. 3 (l), the portion of the conductor circuit 50 (circuit pattern) in which the nickel layer 6 and the palladium layer 13 are formed without the solder resist 7 is formed by electroless gold plating. Gold layer 8 is formed (gold layer forming step). Thereby, the gold layer 8 is formed so as to cover the upper surface and the side surface of the conductor circuit 50 on which the nickel layer 6 and the first palladium layer 13 are formed, and this portion is used as a wire bonding terminal, a solder connection terminal, or the like. It can function suitably as a connection terminal.

  Although not shown, the nickel layer 6 and the palladium layer 13 are formed after the formation of the solder resist 7 in FIG. 3 (k) and before the gold layer 8 is formed by electroless gold plating in FIG. 3 (l). Further, a palladium layer (second palladium layer) may be formed on the conductor circuit 50 by electroless palladium plating. At this time, the second palladium layer is preferably formed so as to cover the surface and side surfaces of the conductor circuit 50. Thereby, the conductor circuit 50 of the part used as a connection terminal becomes a structure covered with the nickel layer 6, the palladium layer 13, and the 2nd palladium layer. Thereby, in particular, the first copper layer 32 (copper foil 22 and copper plating layer 3) and the second copper layer 5 exposed on the side surface of the conductor circuit 50 can be further covered with palladium, and wire bonding is performed. It becomes possible to suppress the diffusion of copper on the surface of the gold layer 8 during the previous heat treatment or the like.

  The gold layer 8 can be formed, for example, by substitution / reduction gold plating, or by electroless gold plating in which reduction gold plating is performed after substitution gold plating. Alternatively, the gold layer 8 can be formed by performing electrolytic gold plating before the location where the gold layer 8 is formed becomes an independent terminal, and then performing reduction-type electroless gold plating. Electroless gold plating may be performed using either method as long as the effect of the present invention can be obtained. However, the method of performing reduction-type gold plating after performing substitution gold plating is performed by using a lower layer metal (in this case). Is preferable from the viewpoint of obtaining good adhesion to palladium. On the other hand, the method of performing substitution / reduction gold plating is difficult to elute the lower layer metal (in this case, palladium) during plating, and tends to form a good gold layer 8.

  When reducing gold plating is performed after displacement gold plating, specifically, about 0.01 to 0.1 μm with a displacement gold plating solution such as HGS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.). After forming a gold plating base film (substitution gold plating film) of 0.1%, a reduced electroless gold plating solution such as HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.) A method of forming a gold plating finish layer (reduction type gold plating film) of about ˜1 μm is mentioned. However, the method of electroless gold plating is not limited to this, and any method that is suitable for gold plating that is usually performed can be applied without limitation.

  FIG. 4 is an enlarged schematic view showing a cross-sectional configuration of a portion of the conductor circuit 50 after the gold layer 8 is formed. Here, an example is shown in which electroless gold plating for forming the gold layer 8 is performed by performing reduction-type gold plating after the replacement gold plating as described above. As shown in FIG. 3, in this portion, a copper foil 22, a copper plating layer 3, a second copper layer 5, and a nickel layer 6 are formed on the insulating layer 21 formed on the surface of the inner layer plate 1 (not shown). And the palladium layer 13 is laminated | stacked in this order, and the gold layer 8 which consists of the substituted gold plating film 11 and the reduction | restoration type gold plating film 9 is formed so that the upper surface and side surface of these laminated structures may be covered.

  The displacement gold plating film 11 can be formed on the upper surface and the side surface of the conductor circuit 50 on which the nickel layer 6 and the palladium layer 13 are formed. Plating solutions used for displacement gold plating include those containing a cyanide compound and those containing no cyanide compound, but any plating solution can be used. Of these, those containing a cyanide compound are preferred. For this reason, the uniformity of the displacement gold plating in the copper constituting the conductor circuit 50 is better when the plating solution containing cyan is used than when the plating solution containing no cyan is used. Can be mentioned. After performing the displacement gold plating with such a plating solution containing cyan, if a reduction type gold plating as will be described later is performed, the gold layer 8 tends to grow uniformly.

  The reduction-type gold plating film 9 can further form a gold film on the replacement gold plating film 11. Therefore, it is possible to form a thick gold layer 8 by performing reduction-type gold plating following substitution gold plating. The plating solution used for reduction-type gold plating can form a gold layer in an autocatalytic manner by containing a reducing agent. These plating solutions include those containing a cyanide compound and those not containing a cyanide compound, but any plating solution can be used.

  As the reducing agent for the plating solution used for reduction-type gold plating, one that does not generate hydrogen gas by oxidation is preferable. Here, examples of the reducing agent that does not generate or hardly generates hydrogen gas include ascorbic acid, urea-based compounds, and phenyl-based compounds. Examples of the reducing agent that generates hydrogen gas include phosphinates and hydrazine. The gold plating solution containing such a reducing agent is preferably one that can be used at a temperature of about 60 to 80 ° C.

  On the other hand, substitution / reduction gold plating is a method in which substitution gold plating and reduction-type gold plating reaction are performed in the same solution, and similarly to substitution gold plating, the upper and side surfaces of the conductor circuit 50 on which the nickel layer 6 is formed. The gold layer 8 can be formed. Such plating solutions include those containing a cyanide compound and those containing no cyanide compound, and any plating solution can be used. In addition, after the substitution / reduction gold plating, electroless gold plating can be further performed to increase the thickness of the gold layer.

  The gold layer 8 thus formed is preferably made of gold having a purity of 99% by weight or more. By setting the gold purity of the gold layer 8 to 99% by weight or more, the reliability of the connection is hardly lowered when this portion is applied as a terminal. From the viewpoint of further improving connection reliability, the purity of the gold layer is more preferably 99.5% by weight or more.

  The thickness of the gold layer 8 is preferably 0.005 to 3 μm, more preferably 0.03 to 1 μm, and still more preferably 0.1 μm to 0.5 μm. By making the thickness of the gold layer 8 0.005 μm or more, wire bonding tends to be facilitated when this portion is used as a terminal. On the other hand, even if the thickness exceeds 3 μm, the effect is not greatly improved.

  Through the above steps, the conductor circuit 50 which is the outer layer circuit is formed on both surfaces of the inner layer plate 1 with the insulating layer 21 therebetween, and the nickel layer 6, the palladium layer 13 and the gold layer 8 are further formed in necessary portions of the conductor circuit 50. A semiconductor chip mounting substrate 10 having a configuration in which is formed is obtained. In such a semiconductor chip mounting substrate 10, the portion of the conductor circuit 50 on which the nickel layer 6, the palladium layer 13 and the gold layer 8 are formed can function as a wire bonding terminal or a solder connection terminal. Thus, it is possible to connect with chip parts and the like.

  The preferred embodiments of the present invention have been described above. According to the manufacturing method of the present invention as described above, even when fine wiring is formed, the occurrence of bridges can be reduced and excellent wire bonding can be achieved. Thus, a semiconductor chip mounting substrate capable of obtaining high reliability and solder connection reliability can be obtained. The factors for obtaining these effects by the present inventor are not necessarily clear, but are presumed to be as follows.

(bridge)
First of all, the factors that have conventionally caused bridges to easily occur due to electroless nickel plating are: (1) etching residue between wirings, and (2) no residue remaining between wirings when copper wiring is formed by electroless copper plating. Pd catalyst residue for electrolytic copper plating, (3) Pd catalyst residue by substitution Pd plating treatment before electroless nickel plating, (4) Hypophosphorous acid generally used as a reducing agent in electroless plating It is considered that hydrogen gas, etc. generated by the oxidation of the compound act in a complex manner.

  That is, as the miniaturization progresses and the hydrogen gas concentration between the wirings increases, the activity of the electroless nickel plating reaction between the wirings increases, so that the above (1) to (3) ), The electroless nickel plating is likely to be deposited, and this causes a bridge. Further, even when there is no residue as in (1) to (3), the hydrogen gas concentration between the wirings is increased during electroless nickel plating, so that nickel is reduced in this part. In some cases, an alloy layer formed by direct electroless nickel plating is deposited, which may become a bridge.

  Furthermore, the nickel film formed on the side surface of the wiring by electroless nickel plating becomes thicker than the electroless nickel plating film on the top surface of the wiring because the plating activity on the side surface of the wiring increases due to the increase in hydrogen gas concentration. easy. In particular, this tendency becomes stronger as the distance between the wirings becomes smaller, and this also becomes a factor that a bridge is easily generated.

  Here, in the pretreatment liquid and the pretreatment method for suppressing the conventional bridge, or the catalyst for electroless plating, the inventors have described the following factors that cannot suppress the occurrence of the bridge after the electroless nickel plating treatment. I think so.

  That is, the conventional pretreatment liquid, the pretreatment method and the electroless plating catalyst liquid inactivate the etching residue (1) or the Pd catalyst residue (2) described above, or the Pd of (3). It is thought to reduce the amount of catalyst residue. However, the cause of the bridge may be the hydrogen gas (4) as described above. However, in the conventional pretreatment liquid, the pretreatment method, and the electroless plating catalyst liquid, the hydrogen gas is generated between the wirings. It is considered that the generation of bridges cannot be sufficiently suppressed because the effect of suppressing the direct adsorption of the alloy layer by electroless nickel plating cannot be obtained.

  Normally, even when electroless gold plating is performed on a copper circuit, “bridge” hardly occurs. In electroless nickel plating, hypophosphorous acid is generally used as a reducing agent, but hydrogen gas is generated along with its oxidation, which increases the activity of the plating solution near the wiring. Etching residue, Pd catalyst residue for electroless copper plating, or direct nickel deposition is likely to occur.

  In contrast, in electroless gold plating, there are few cases where hydrogen gas is generated as a reducing agent by oxidation of hypophosphorous acid, etc., and ascorbic acid, urea compounds, phenyl compounds, etc. are often used. Therefore, it is considered that the generation of hydrogen gas hardly occurs during electroless gold plating, and therefore “bridge” does not occur.

  Further, since the electroless nickel plating solution is used at a high temperature of 80 to 95 ° C., the deposition rate is fast, for example, 0.2 to 0.3 μm / min. Since it is used at a temperature of about 60 to 80 ° C., the deposition rate is 0.005 to 0.03 μm / min, and even if hydrogen gas is generated, the activity is low. Such a difference in activity due to a difference in the deposition rate is considered to be a factor that determines whether or not “bridge” occurs.

  On the other hand, in this embodiment, electroless nickel plating is performed on a conductor circuit made of copper in a state where a resist exists, and after removing the resist, electroless gold plating is performed. That is, since electrolytic nickel plating is performed on the conductor circuit, the items (1) to (4) described above are less likely to cause a bridge. Furthermore, since the resist is present in the portion other than the conductor circuit, this also greatly suppresses the occurrence of the bridge.

(Solder connection reliability)
When electroless nickel / electroless gold plating is performed on a copper circuit as in the conventional case, as described in Non-Patent Document 2, the electroless nickel plating layer is dissolved by the displacement gold plating reaction, and the fragile layer is formed. Sometimes formed. In this fragile layer, the electroless nickel generally applied is electroless nickel-phosphorus alloy plating, and only nickel is easily eluted in the subsequent displacement gold plating reaction, so that phosphorus is concentrated and remains dissolved. It is thought that it is formed by. And the solder connection reliability falls by formation of such a weak layer.

  On the other hand, when performing electrolytic nickel plating / electroless palladium plating / electroless gold plating on the conductor circuit as in this embodiment, the nickel plating surface is protected with palladium, so nickel and a displacement gold plating solution Does not come into contact, and nickel elution does not occur. Therefore, according to the electrolytic nickel plating / electroless palladium plating / electroless gold plating in the present embodiment, it is considered that extremely high solder connection reliability can be obtained.

(Wire bonding property)
In the case of conventional electroless nickel / electroless gold plating, as described in Non-Patent Document 2 described above, it has been shown that the wire bonding property is remarkably lowered with heat treatment. The reason why the wire bondability deteriorates as described above is that nickel from the electroless nickel film diffuses in the grain boundary of the gold plating film, and thereby nickel migrates to the surface of the gold plating film, and nickel oxide on this surface. Can be considered. And it is thought that the nickel oxide produced in this way obstructs the adhesion between the gold wire and the gold plating film, leading to a decrease in wire bonding property.

On the other hand, in this embodiment, since electrolytic nickel / electroless palladium / electroless gold plating is applied on the conductor circuit, palladium can function as a barrier film that suppresses the diffusion of nickel. As a result, superior wire bonding properties can be obtained as compared with the conventional electroless nickel / electroless gold plating.
[Second Embodiment]
Next, a preferred second embodiment of the method for manufacturing a semiconductor chip mounting substrate will be described. 5, 6 and 7 are process diagrams schematically showing a method of manufacturing a semiconductor chip mounting substrate according to the second embodiment. The present embodiment is an example of a method for manufacturing a semiconductor chip mounting substrate by a semi-additive method, including a step of forming a copper plating layer after laminating a buildup film on an inner layer plate.

  In the present embodiment, first, as shown in FIG. 5A, the inner layer plate 1 is prepared. The inner layer plate 1 can be prepared in the same manner as in the first embodiment described above. Next, as shown in FIG. 5 (b), an insulating layer 15 is formed by laminating or pressing a buildup film on both surfaces of the inner layer plate 1. This build-up film is a film having no electrical conductivity, and is made of a resin material having an insulating property. As such a resin material, the same constituent material as that of the insulating layer 21 mainly composed of the resin in the resin-coated conductor foil 2 described above can be applied, and an inorganic filler such as a silica filler may be blended. The build-up film before lamination is in the B stage state.

  Next, as shown in FIG. 5C, a through hole (via hole) that penetrates the insulating layer 15 and reaches the inner layer plate 1 is formed in a predetermined portion of the insulating layer 15 laminated on the inner layer plate 1. As a result, an interstitial via hole (IVH) 30 is formed, and a part of the inner layer circuit 102 is exposed. The formation of the through hole can also be performed in the same manner as the formation of the through hole for the resin-coated copper foil 2 in the first embodiment.

  Next, as shown in FIG. 5D, the copper plating layer 3 is formed by electroless copper plating so as to cover the entire surface of the inner layer plate 1 on which the insulating layer 15 is laminated. Thereby, the laminated body 120 provided with the 1st copper layer 32 which consists only of the copper plating layer 3 which provided the inner layer board 1 and the inner layer circuit 102 of the inner layer board 1, and the insulating layer 15 was provided so that it might connect in part. Is obtained. In this laminated body 120, since the copper plating layer 3 is continuously formed to the inside of the IVH 30, the copper plating layer 3 (first copper layer 32) formed on the surface of the insulating layer 15 and the inner layer circuit 102 are formed. Can be electrically connected.

  After such a laminate 120 is formed, the resist forming process, the conductor circuit forming process, the nickel layer forming process, the resist removing process, the etching process, the solder resist forming process, and the gold are performed in the same manner as in the first embodiment. The layer forming process is sequentially performed.

  That is, as shown in FIG. 6 (e), an electrolytic plating resist is applied to a portion of the laminate 120 excluding a portion (including IVH30) to be a conductor circuit on the first copper layer 32 (copper plating layer 3). A certain resist 4 is formed (resist forming step). Next, as shown in FIG. 6 (f), the second copper layer 5 is formed on the surface of the first copper layer 32 by electrolytic copper plating, and the first copper layer 32 and the second copper layer 5 are formed. Is obtained (conductor circuit forming step).

  Then, as shown in FIG. 6G, after the nickel layer 6 is further formed on the surface of the second copper layer 5 by electrolytic nickel plating (nickel layer forming step), as shown in FIG. 6H. Then, the palladium layer 13 is formed.

  When the palladium layer 13 is formed, as shown in FIG. 7I, the resist 4 which is an electrolytic plating resist is removed (resist removing step). After that, as shown in FIG. 7 (j), the portion of the first copper layer 32 (copper plating layer 3) covered with the resist 4 is removed by etching (etching process), and then the process shown in FIG. As shown, a solder resist forming step for forming a solder resist 7 on the surface is performed so that at least a part of the conductor circuit 50 on which the nickel layer 6 is formed is exposed.

  Then, as shown in FIG. 7L, the gold layer 8 is formed by electroless gold plating on the portion of the conductor circuit 50 (circuit pattern) on which the nickel layer 6 is formed, on which the solder resist 7 is not formed. Form (gold layer forming step). Thereby, the gold layer 8 is formed so as to cover the upper surface and the side surface of the conductor circuit 50 on which the nickel layer 6 is formed.

  Through the above steps, the conductor circuit 50 which is an outer layer circuit is formed on both surfaces of the inner layer plate 1 with the insulating layer 15 therebetween, and the nickel layer 6, the palladium layer 13 and the gold layer 8 are further formed in necessary portions of the conductor circuit 50. A semiconductor chip mounting substrate 10 having a configuration in which is formed is obtained. In such a semiconductor chip mounting substrate 10, the portion of the conductor circuit 50 on which the nickel layer 6, the palladium layer 13 and the gold layer 8 are formed can function as a wire bonding terminal or a solder connection terminal. Thus, it is possible to connect with chip parts and the like.

  The preferred embodiments of the semiconductor chip mounting substrate and the manufacturing method thereof according to the present invention have been described above. However, the present invention is not necessarily limited to the above-described embodiments, and may be changed as appropriate without departing from the spirit of the present invention. May be performed.

  In the above-described embodiment, the example in which the outer layer conductor circuit is formed on both surfaces of the inner layer plate has been described. However, the present invention is not necessarily limited thereto. For example, the outer layer conductor circuit is formed only on one surface side of the inner layer plate. It may be. Furthermore, it is good also as a multilayer board provided with the multilayer conductor circuit by using the semiconductor chip mounting board | substrate obtained above as an inner layer board, and repeating the same process.

[Example 1]
(Manufacture of semiconductor chip mounting substrates)
(1a) Preparation of inner layer board First, as shown in FIG. 1 (a), a glass cloth base epoxy copper clad laminate having a thickness of 0.2 mm, in which a copper foil having a thickness of 18 μm is bonded to both sides of an insulating base. A plate MCL-E-679 (manufactured by Hitachi Chemical Co., Ltd., trade name) is prepared, the copper foil at the unnecessary portion is removed by etching, a through hole is formed, and an inner layer circuit is formed on the surface. An inner layer plate (inner layer plate 1) was obtained.

(1b) Lamination of resin-attached copper foil As shown in FIG. 1 (b), MCF-7000LX (Hitachi Chemical Industry Co., Ltd.) in which an adhesive (insulating layer 21) is applied to a copper foil 22 having a thickness of 3 μm on both surfaces of the inner layer plate. Co., Ltd., trade name) was laminated by heating and pressing for 60 minutes under the conditions of 170 ° C. and 30 kgf / cm ² .

(1c) Formation of IVH As shown in FIG. 1 (c), a carbon dioxide gas impact laser drilling machine L-500 (manufactured by Sumitomo Heavy Industries, Ltd., trade name), a non-through hole with a diameter of 80 μm from above the copper foil 22 I opened IVH30. Furthermore, the substrate after IVH30 formation was immersed in a mixed aqueous solution of potassium permanganate 65 g / L and sodium hydroxide 40 g / L at a liquid temperature of 70 ° C. for 20 minutes to remove smears in the holes.

(1d) Electroless copper plating As shown in FIG.1 (d), the board | substrate after the process of (1c) is 15 degreeC at 25 degreeC to HS-202B (made by Hitachi Chemical Co., Ltd., brand name) which is a palladium solution. The catalyst was applied to the surface of the copper foil 22 by dipping for a minute. Then, using CUST-201 (trade name, manufactured by Hitachi Chemical Co., Ltd.), electroless copper plating was performed at a liquid temperature of 25 ° C. for 30 minutes. Thus, an electroless copper plating layer (copper plating layer 3) having a thickness of 0.3 μm was formed on the copper foil 21 and the surface in the IVH 30.

(1e) Formation of electrolytic plating resist As shown in FIG. 2 (e), dry film photoresist RY-3025 (manufactured by Hitachi Chemical Co., Ltd., trade name) is laminated on the surface of the electroless copper plating layer. The photoresist was exposed to ultraviolet light through a photomask that masks the portion where electrolytic copper plating should be performed, and then developed to form an electrolytic plating resist (resist 4).

(1f) Electrolytic Copper Plating As shown in FIG. 2 (f), an electrolytic copper plating is 20 μm on the copper plating layer 3 using a copper sulfate bath at a liquid temperature of 25 ° C. and a current density of 1.0 A / dm ^2. The second copper layer 5 having a pattern shape of circuit conductor width / circuit conductor interval (L / S) = 35/35 μm was formed so as to obtain an appropriate thickness. Further, an electrolytic copper plating film (second copper layer 5) was formed on the surface opposite to the surface on which the pattern shape was formed so that a pad having a land diameter of 600 μm for connecting solder balls was formed.

(1g) Electrolytic nickel plating As shown in FIG. 2 (g), using an electrolytic nickel plating solution having the following composition that does not contain a brightener, under conditions of a liquid temperature of 55 ° C. and a current density of 1.5 A / dm ² , Electrolytic nickel plating was performed on the electrolytic copper plating layer so as to obtain a thickness of about 3 μm, and an electrolytic nickel film (nickel layer 6) was formed.
Composition of electrolytic nickel plating solution (Watt bath) Nickel sulfate: 240 g / L
Nickel chloride: 45g / L
Boric acid: 30 g / L
Surfactant: 3ml / L
(Nippon High Purity Chemical Co., Ltd., trade name: pit inhibitor # 62)
Saccharin (brightener): 1.5 g / L
pH: 4

(1h) Electroless Palladium Plating As shown in FIG. 2 (h), the substrate after electrolytic nickel plating is placed on a pallet (trade name, manufactured by Kojima Chemical Co., Ltd.) that is a reduced palladium plating solution at 70 ° C. for 2 minutes. The palladium layer 13 was formed by immersing and depositing a 0.2 μm reduced palladium plating film on the nickel layer 6.

(1i) Stripping of Electroplating Resist As shown in FIG. 3 (i), the electrolytic plating resist was removed using HTO (trade name, manufactured by Nichigo Morton Co., Ltd.) which is a resist stripping solution.

(1j) Etching As shown in FIG. 3 (j), using an etching solution having a composition of sulfuric acid 20 g / L and hydrogen peroxide 10 g / L as the main components, the copper (copper) covered with the electrolytic plating resist The foil 21 and the copper plating layer 3) were removed by etching.

(1k) Formation of solder resist As shown in FIG. 3 (k), a photosensitive solder resist “PSR-4000 AUS5” (trade name, manufactured by Taiyo Ink Manufacturing Co., Ltd.) is applied to the upper surface of the substrate after etching. It was applied with a roll coater so that the thickness after curing was 40 μm. Subsequently, by performing exposure and development, a solder resist 7 having an opening at a desired location on the conductor circuit was formed. Further, a solder resist 7 having an opening diameter of 500 μm was formed on the upper surface of a copper pad having a land diameter of 600 μm in order to form a solder ball connection pad on the lower surface.

(1 l) Electroless gold plating As shown in FIG. 3 (l), the substrate after the formation of the solder resist 7 is placed on HGS-100 (Hitachi Chemical Industry Co., Ltd., trade name) as a replacement gold plating solution at 85 ° C. It was immersed for 2 minutes and further washed with water for 1 minute. Next, it is immersed in HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a reduced type gold plating solution, at 70 ° C. for 45 minutes, and further washed with water for 5 minutes to obtain an electroless gold plating film (gold layer 8 ) Was formed. The total film thickness of the electroless gold plating film obtained by displacement gold plating and reduction type gold plating was 0.5 μm. In the present example and the following examples and comparative examples, the thickness of the nickel layer, the palladium layer, and the gold layer is the fluorescent X-ray film thickness meter SFT9500 (trade name, manufactured by SII Nano Technology Co., Ltd.). And measured.

  In this manner, a semiconductor chip mounting substrate having terminal portions covered with the gold layer 8 on the upper and lower surfaces as shown in FIG. In this semiconductor chip mounting substrate, the upper terminal portion corresponds to a wire bonding connection terminal, and the lower terminal portion corresponds to a solder connection terminal. The semiconductor chip mounting substrate has 1000 of each of these terminals (the same applies to the following examples and comparative examples).

(Characteristic evaluation)
(1) Fine wiring formability About the semiconductor chip mounting substrate obtained above, the fine wiring formability after electroless gold plating was evaluated according to the following criteria. The obtained results are shown in Table 1.
A: The bridge is not formed, the plating film is formed well on the terminal portion, and the circuit conductor interval is 25 μm or more.
B: Plating partially protrudes and precipitates on the outer periphery of the terminal portion, and the distance between the circuit conductors is 20 μm or more and less than 25 μm.
C: Plating partially protrudes and deposits on the outer periphery of the terminal portion, and the circuit conductor interval is 15 μm or more and less than 20 μm.
D: Plating partially protrudes from the outer periphery of the terminal portion and deposits, and the distance between the circuit conductors is 5 μm or more and less than 15 μm.
E: Plating partially protrudes and precipitates on the outer periphery of the terminal portion, and the distance between the circuit conductors is less than 5 μm.

(2) Wire bonding property About the board | substrate for semiconductor chip mounting obtained above, the wire bonding property (wire bonding connectivity) of the connection terminal was evaluated by the following reference | standard.
That is, a plurality of semiconductor chip mounting substrates corresponding to Example 1 were subjected to heat treatment at 175 ° C. for 3, 10, 50, 100, and 200 hours, and wire bonding was performed when each heat treatment time had elapsed. It was. Wire bonding was performed using gold wires with a wire diameter of 28 μm at all 1000 wire bonding connection terminals. As the wire bonding apparatus, UTC200-Super2 (Shinkawa Co., Ltd., trade name) was used, bonding temperature (heat block temperature): 165 ° C., bond load: 70 gf, ultrasonic output: 90 PLS, ultrasonic time: 25 ms. did.

After wire bonding, a gold wire pull test is performed to measure the strength until the gold wire is pulled and detached from the terminal using a bond tester (trade name: BT2400PC, manufactured by Dage). Connection reliability was evaluated for each terminal. The obtained results are shown in Table 1. Thereafter, conditions satisfying the criteria of A were judged as good after heat treatment at 175 ° C. for 50 hours.
A: The average value of wire pull strength is 10 g or more B: The average value of wire pull strength is 8 g or more and less than 10 g C: The average value of wire pull strength is 3 g or more and less than 8 g D: The average value of wire pull strength is less than 3 g

(3) Solder connection reliability About the semiconductor chip mounting substrate obtained above, the solder connection reliability of the connection terminals was evaluated according to the following criteria.
That is, after connecting Sn-3.0Ag-0.5Cu solder balls of φ0.76 mm to 1000 solder connection terminals on a semiconductor chip mounting substrate in a reflow furnace (peak temperature 252 ° C.), impact resistance Using a high-speed bond tester 4000HS (trade name, manufactured by Daisy Corporation), a shear (shear) test of the solder balls was performed under the condition of about 200 mm / sec (leaving time 0 h). In addition, after preparing a plurality of semiconductor chip mounting substrates to which solder balls are connected by reflow and leaving them at 150 ° C. for 100, 300, and 1000 hours, respectively, a solder ball shear (shear) test is similarly performed on these substrates. It was.

The evaluation criteria of solder connection reliability are as follows, and evaluation was performed for each terminal based on such criteria. The obtained results are shown in Table 1.
A: Breakage due to shearing in the solder balls was observed in all 1000 connection terminals for solder.
B: Fractures in modes other than shearing due to shear in the solder balls were observed at 1 to 10 locations.
C: Breakage in modes other than shearing due to shear in the solder balls was observed at 11 to 100 locations.
D: Breakage in modes other than shearing due to shear in the solder balls was observed at 101 or more locations.

(4) Diffusion of nickel to the gold layer surface In order to investigate the diffusion state of nickel to the gold layer 8 in the terminal portion of the semiconductor chip mounting substrate, the following test was performed. That is, after a plurality of semiconductor chip mounting substrates were heat-treated at 175 ° C. for 50, 100, and 200 hours, respectively, an X-ray photoelectron spectrometer AXIS 165 type (trade name, manufactured by Shimadzu Corporation) was used to form a gold layer Elemental analysis of the surface was performed to determine the types and proportions of elements present on the gold layer surface. The obtained results are shown in Table 2.

(5) Adhesiveness with solder resist The adhesiveness between the conductor circuit and the solder resist was evaluated by preparing a sample corresponding to Example 1 and evaluating the resistance to PCT (Pressure Cooker Test). That is, after the steps (1a) to (1j) described above are performed, instead of the step (1k), a solder ball connecting pad having a land diameter of 600 μm is covered so as to cover the conductor circuit in which 1000 places are formed. A sample in which the solder resist 7 having no opening diameter was formed was produced. This sample was subjected to a moisture absorption treatment for 96 hours under the conditions of 121 ° C./100%/2.3 atm, and then visually observed to see if swelling occurred at the top of the solder ball connection pad. It was. Based on the following criteria, the adhesiveness (SR adhesion) with the solder resist was evaluated. The obtained results are shown in Table 1.
A: No bulging B: Bulging occurs at 1 to 30 locations C: Bulging occurs at 31 to 100 locations D: Bulging occurs at 100 or more locations

(6) Crystal grain size on the surface of the nickel layer Further, the nickel layer 6 in contact with the first palladium layer 13 is subjected to a focused ion beam processing observation apparatus (FIB: Focused Ion Beam System, FB-manufactured by Hitachi, Ltd.). 2000A type) and observed using a transmission electron microscope (TEM), and the average particle diameter of the nickel layer 6 was determined from the cross-sectional observation image. The average particle diameter is obtained by measuring the cross section of the nickel layer 6 in contact with the first palladium layer 13 with a width of 10 μm, calculating the cross sectional area of each crystal grain, obtaining the average, and converting to a circle. The diameter was taken as the average particle size. The vicinity of the center part of the circuit conductor width of 35 μm was observed. Table 3 shows the average value of the crystal grain size of nickel on the surface of the nickel layer 6 on the palladium layer 13 side obtained by such observation.

[Example 2]
(Manufacture of semiconductor chip mounting substrates)
In the step (1g), using an electrolytic nickel plating solution having the following composition containing a brightening agent (primary brightening agent) having the following concentration, under conditions of a liquid temperature of 55 ° C. and a current density of 1.5 A / dm ² , Semiconductor chip in the same manner as in Example 1 except that electrolytic nickel plating is performed on the copper layer 5 of 2 so as to obtain a thickness of about 3 μm, and the nickel layer 6 is formed on the second copper layer 5. A mounting substrate was obtained.
Composition of electrolytic nickel plating solution Nickel sulfate: 240 g / L
Nickel chloride: 45g / L
Boric acid: 30 g / L
Surfactant: 3ml / L
(Nippon High Purity Chemical Co., Ltd., trade name: pit inhibitor # 62)
Saccharin (brightener): 3 g / L
pH: 4

(Characteristic evaluation)
The obtained semiconductor chip mounting substrate was evaluated in the same manner as in Example 1 for fine wiring formability, wire bonding properties, solder connection reliability, and adhesiveness with a solder resist (SR adhesion). The obtained results are shown in Table 1. Further, in the same manner as in Example 1, the diffusion state of nickel on the gold film surface was evaluated. The obtained results are shown in Table 2. Further, in the same manner as in Example 1, the crystal grain size of the surface of the nickel layer 6 in contact with the palladium layer 13 was measured by TEM. The obtained results are shown in Table 3.

[Example 3]
(Manufacture of semiconductor chip mounting substrates)
After the steps (1a) to (1g) in Example 1 were performed, the substrate in this state was converted into a pallet (trade name, manufactured by Kojima Chemical Co., Ltd.) which is a reduced palladium plating solution in the step (1h). Then, a step of forming a palladium layer 13 by immersing at 70 ° C. for 1 minute to deposit 0.1 μm of a reduced palladium plating film on the nickel layer 6 was performed. Subsequently, after performing the steps (1i) to (1k) in Example 1, the substrate in this state was placed on a pallet (trade name, manufactured by Kojima Chemical Co., Ltd.) which is a reduced palladium plating solution at 70 ° C. The second palladium layer was formed by depositing 0.1 μm of a reduced palladium plating film on the palladium layer 13 so that the total thickness of the palladium layer was 0.2 μm. At this time, a palladium layer of 0.1 μm was also deposited on the side surface of the conductor circuit 50 in which the first copper layer 32 and the second copper layer 5 were laminated. Then, the process of (1l) in Example 1 was performed, the electroless gold plating film was formed, and the semiconductor chip mounting substrate was obtained.

(Characteristic evaluation)
The obtained semiconductor chip mounting substrate was evaluated in the same manner as in Example 1 for fine wiring formability, wire bonding properties, solder connection reliability, and adhesiveness with a solder resist (SR adhesion). The obtained results are shown in Table 1. Further, in the same manner as in Example 1, the diffusion state of nickel on the gold film surface was evaluated. The obtained results are shown in Table 2. Further, in the same manner as in Example 1, the crystal grain size of the surface of the nickel layer 6 in contact with the palladium layer 13 was measured by TEM. The obtained results are shown in Table 3.
[Comparative Example 1]
(Manufacture of semiconductor chip mounting substrates)
In the step (1g), the second copper layer was used under the conditions of a liquid temperature of 55 ° C. and a current density of 1.5 A / dm ² by using an electrolytic nickel plating solution having the following composition not containing a brightener (primary brightener). A substrate for mounting a semiconductor chip was obtained in the same manner as in Example 1 except that electrolytic nickel plating was performed so that a thickness of about 3 μm was obtained and a nickel layer was formed on the second copper layer. At this time, the thickness of the palladium layer was set to 0.01 μm.
Composition of electrolytic nickel plating solution Nickel sulfate: 240 g / L
Nickel chloride: 45g / L
Boric acid: 30 g / L
Surfactant: 3ml / L
(Nippon High Purity Chemical Co., Ltd., trade name: pit inhibitor # 62)
pH: 4

(Characteristic evaluation)
The obtained semiconductor chip mounting substrate was evaluated in the same manner as in Example 1 for fine wiring formability, wire bonding properties, solder connection reliability, and adhesiveness with a solder resist (SR adhesion). The obtained results are shown in Table 1. Further, in the same manner as in Example 1, the diffusion state of nickel on the gold layer surface was evaluated. The obtained results are shown in Table 2. Further, in the same manner as in Example 1, the crystal grain size on the surface of the nickel layer in contact with the palladium layer was measured by TEM. The obtained results are shown in Table 3.

[Comparative Example 2]
(Manufacture of semiconductor chip mounting substrates)
After performing the steps (1a) to (1f) in Example 1, in the step (1g), using an electrolytic nickel plating solution having the following composition that does not contain a brightener (primary brightener), a liquid temperature of 55 ° C. Then, electrolytic nickel plating was performed on the second copper layer so as to obtain a thickness of about 3 μm under a current density of 1.5 A / dm ² , and a nickel layer was formed on the second copper layer.
Composition of electrolytic nickel plating solution Nickel sulfate: 240 g / L
Nickel chloride: 45g / L
Boric acid: 30 g / L
Surfactant: 3ml / L
(Nippon High Purity Chemical Co., Ltd., trade name: pit inhibitor # 62)
pH: 4

  Subsequently, in (1h) in Example 1, the substrate after electrolytic nickel plating was immersed in SA-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a substituted palladium plating solution having a liquid temperature of 25 ° C., for 2 minutes. , Washed with water for 1 minute, and further immersed in a palette (trade name, manufactured by Kojima Chemical Co., Ltd.), which is a reduced palladium plating solution, at 70 ° C. for 2 minutes to form a reduced palladium plating film (palladium on the nickel layer). Layer). At this time, the thickness of palladium was 0.05 μm. Subsequently, steps (1i) to (1l) in Example 1 were performed to obtain a semiconductor chip mounting substrate.

(Characteristic evaluation)
The obtained semiconductor chip mounting substrate was evaluated in the same manner as in Example 1 for fine wiring formability, wire bonding properties, solder connection reliability, and adhesiveness with a solder resist (SR adhesion). The obtained results are shown in Table 1. Further, in the same manner as in Example 1, the diffusion state of nickel on the gold layer surface was evaluated. The obtained results are shown in Table 2. Further, in the same manner as in Example 1, the crystal grain size on the surface of the nickel layer in contact with the palladium layer was measured by TEM. The obtained results are shown in Table 3.
[Comparative Example 3]
(Manufacture of semiconductor chip mounting substrates)
After performing the steps (1a) to (1f) in Example 1, in the step (1g), using an electrolytic nickel plating solution having the following composition that does not contain a brightener (primary brightener), a liquid temperature of 55 ° C. Then, electrolytic nickel plating was performed on the second copper layer so as to obtain a thickness of about 3 μm under a current density of 1.5 A / dm ² , and a nickel layer was formed on the second copper layer.
Composition of electrolytic nickel plating solution Nickel sulfate: 240 g / L
Nickel chloride: 45g / L
Boric acid: 30 g / L
Surfactant: 3ml / L
(Nippon High Purity Chemical Co., Ltd., trade name: pit inhibitor # 62)
pH: 4

  Subsequently, in (1h) in Example 1, the substrate after electrolytic nickel plating was immersed in SA-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a substituted palladium plating solution having a liquid temperature of 25 ° C., for 2 minutes. Then, a palladium plating film (palladium layer) was deposited on the nickel layer. The thickness of palladium at this time was 0.03 μm. Subsequently, steps (1i) to (1l) in Example 1 were performed to obtain a semiconductor chip mounting substrate.

(Characteristic evaluation)
The obtained semiconductor chip mounting substrate was evaluated in the same manner as in Example 1 for fine wiring formability, wire bonding properties, solder connection reliability, and adhesiveness with a solder resist (SR adhesion). The obtained results are shown in Table 1. Further, in the same manner as in Example 1, the diffusion state of nickel on the gold layer surface was evaluated. The obtained results are shown in Table 2. Further, in the same manner as in Example 1, the crystal grain size on the surface of the nickel layer in contact with the palladium layer was measured by TEM. The obtained results are shown in Table 3.
[Comparative Example 4]
(Manufacture of semiconductor chip mounting substrates)
In the step (1g), using the electrolytic nickel plating solution having the following composition containing a brightener (primary brightener), the second copper layer under the conditions of a liquid temperature of 55 ° C. and a current density of 1.5 A / dm ^2. A substrate for mounting a semiconductor chip was obtained in the same manner as in Example 1 except that electrolytic nickel plating was performed so that a thickness of about 3 μm was obtained and a nickel layer was formed on the second copper layer. At this time, the thickness of the palladium layer was set to 0.01 μm.
Composition of electrolytic nickel plating solution Nickel sulfate: 240 g / L
Nickel chloride: 45g / L
Boric acid: 30 g / L
Surfactant: 3ml / L
(Nippon High Purity Chemical Co., Ltd., trade name: pit inhibitor # 62)
Saccharin (brightener): 0.3 g / L
pH: 4

(Characteristic evaluation)
The obtained semiconductor chip mounting substrate was evaluated in the same manner as in Example 1 for fine wiring formability, wire bonding properties, solder connection reliability, and adhesiveness with a solder resist (SR adhesion). The obtained results are shown in Table 1. Further, in the same manner as in Example 1, the diffusion state of nickel on the gold layer surface was evaluated. The obtained results are shown in Table 2. In the same manner as in Example 1, the crystal grain size on the surface of the nickel layer in contact with the palladium layer was measured by TEM. The obtained results are shown in Table 3.
[Comparative Example 5]
(Manufacture of semiconductor chip mounting substrates)
In the step (1g), using the electrolytic nickel plating solution having the following composition containing a brightener (primary brightener), the second copper layer under the conditions of a liquid temperature of 55 ° C. and a current density of 1.5 A / dm ^2. A substrate for mounting a semiconductor chip was obtained in the same manner as in Example 1 except that electrolytic nickel plating was performed so that a thickness of about 3 μm was obtained and a nickel layer was formed on the second copper layer. At this time, the thickness of the palladium layer was set to 0.01 μm.
Composition of electrolytic nickel plating solution Nickel sulfate: 240 g / L
Nickel chloride: 45g / L
Boric acid: 30 g / L
Surfactant: 3ml / L
(Nippon High Purity Chemical Co., Ltd., trade name: pit inhibitor # 62)
Saccharin (brightener): 1.0 g / L
pH: 4

(Characteristic evaluation)
The obtained semiconductor chip mounting substrate was evaluated in the same manner as in Example 1 for fine wiring formability, wire bonding properties, solder connection reliability, and adhesiveness with a solder resist (SR adhesion). The obtained results are shown in Table 1. Further, in the same manner as in Example 1, the diffusion state of nickel on the gold layer surface was evaluated. The obtained results are shown in Table 2. Further, in the same manner as in Example 1, the crystal grain size on the surface of the nickel layer in contact with the palladium layer was measured by TEM. The obtained results are shown in Table 3.
[Comparative Example 6]
(Manufacture of semiconductor chip mounting substrates)
After performing the steps (1a) to (1f) in Example 1, in the step (1g), using an electrolytic nickel plating solution having the following composition containing a brightener (primary brightener), a liquid temperature of 55 ° C. Then, electrolytic nickel plating was performed on the second copper layer so as to obtain a thickness of about 3 μm under a current density of 1.5 A / dm ² , and a nickel layer was formed on the second copper layer.
Composition of electrolytic nickel plating solution Nickel sulfate: 240 g / L
Nickel chloride: 45g / L
Boric acid: 30 g / L
Surfactant: 3ml / L
(Nippon High Purity Chemical Co., Ltd., trade name: pit inhibitor # 62)
Saccharin (brightener): 1.0 g / L
pH: 4

  Subsequently, in (1h) in Example 1, the substrate after electrolytic nickel plating was immersed in SA-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a substituted palladium plating solution having a liquid temperature of 25 ° C., for 2 minutes. , Washed with water for 1 minute, and further immersed in a palette (trade name, manufactured by Kojima Chemical Co., Ltd.), which is a reduced palladium plating solution, at 70 ° C. for 2 minutes to form a reduced palladium plating film (palladium on the nickel layer). Layer). The thickness of the palladium layer at this time was 0.05 μm. Subsequently, the steps (1i) to (1l) in Example 1 were performed.

(Characteristic evaluation)
The obtained semiconductor chip mounting substrate was evaluated in the same manner as in Example 1 for fine wiring formability, wire bonding properties, solder connection reliability, and adhesiveness with a solder resist (SR adhesion). The obtained results are shown in Table 1. Further, in the same manner as in Example 1, the diffusion state of nickel on the gold layer surface was evaluated. The obtained results are shown in Table 2. In the same manner as in Example 1, the crystal grain size on the surface of the nickel layer in contact with the palladium layer was measured by TEM. The obtained results are shown in Table 3.
[Comparative Example 7]
(Manufacture of semiconductor chip mounting substrates)
After performing the steps (1a) to (1f) in Example 1, in the step (1g), using an electrolytic nickel plating solution having the following composition containing a brightener (primary brightener), a liquid temperature of 55 ° C. Then, electrolytic nickel plating was performed on the second copper layer so as to obtain a thickness of about 3 μm under a current density of 1.5 A / dm ² , and a nickel layer was formed on the second copper layer.
Composition of electrolytic nickel plating solution Nickel sulfate: 240 g / L
Nickel chloride: 45g / L
Boric acid: 30 g / L
Surfactant: 3ml / L
(Nippon High Purity Chemical Co., Ltd., trade name: pit inhibitor # 62)
Saccharin (brightener): 1.0 g / L
pH: 4
Subsequently, in (1h) in Example 1, the substrate after electrolytic nickel plating was immersed in SA-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a substituted palladium plating solution having a liquid temperature of 25 ° C., for 2 minutes. Then, a palladium plating film (palladium layer) was deposited on the nickel layer. The thickness of the palladium layer at this time was 0.04 μm. Subsequently, steps (1i) to (1l) in Example 1 were performed to obtain a semiconductor chip mounting substrate.

(Characteristic evaluation)
The obtained semiconductor chip mounting substrate was evaluated in the same manner as in Example 1 for fine wiring formability, wire bonding properties, solder connection reliability, and adhesiveness with a solder resist (SR adhesion). The obtained results are shown in Table 1. Further, in the same manner as in Example 1, the diffusion state of nickel on the gold layer surface was evaluated. The obtained results are shown in Table 2. Further, regarding the crystal grain sizes of nickel and gold in each of the nickel layer and the gold layer, the crystal grain size on the surface of the nickel layer in contact with the palladium layer was measured by TEM in the same manner as in Example 1. The obtained results are shown in Table 3.

[Comparative Example 8]
(Manufacture of semiconductor chip mounting substrates)
After performing steps (1a) to (1f) in Example 1, (1i) to (1k) without performing steps (1g) (electrolytic nickel plating) and (1h) (electroless palladium plating) The process was performed.

  Next, the substrate after the solder resist formation was immersed in SA-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a plating activation treatment solution, at 25 ° C. for 5 minutes, washed with water for 1 minute, It was immersed in nickel PS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is an electroless nickel plating solution, at 85 ° C. for 12 minutes and washed with water for 1 minute. Thereby, a 3 μm electroless nickel plating film was formed on the second copper layer.

  Thereafter, the substrate after the formation of the electroless nickel plating film was immersed in HGS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), a substitution gold plating solution, at 85 ° C. for 10 minutes, and then washed with water for 1 minute. Then, it was immersed in HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is a reduced gold plating solution for 45 minutes at 70 ° C. and washed with water for 5 minutes. Thus, a semiconductor chip mounting substrate was obtained. The total thickness of the gold layers obtained by displacement gold plating and reduction-type gold plating was 0.5 μm.

(Characteristic evaluation)
The obtained semiconductor chip mounting substrate was evaluated in the same manner as in Example 1 for fine wiring formability, wire bonding properties, solder connection reliability, and adhesiveness with a solder resist (SR adhesion). The obtained results are shown in Table 1. Further, in the same manner as in Example 1, the diffusion state of nickel on the gold layer surface was evaluated. The obtained results are shown in Table 2. Further, in the same manner as in Example 1, the crystal grain size on the surface of the nickel layer in contact with the palladium layer was measured by TEM. The obtained results are shown in Table 3.

[Comparative Example 9]
(Manufacture of semiconductor chip mounting substrates)
After performing steps (1a) to (1f) in Example 1, (1i) to (1k) without performing steps (1g) (electrolytic nickel plating) and (1h) (electroless palladium plating) The process was performed.

Subsequently, the substrate after forming the solder resist is immersed in a substituted palladium plating solution having the following composition, which is a plating activation treatment solution, for 5 minutes, then washed with water and dried to form a substituted palladium plating film on the second copper layer. Formed.
Composition of substituted palladium plating solution As palladium chloride (Pd): 100 mg / L
Ammonium chloride: 10 g / L
pH: 2 (adjusted with hydrochloric acid)

Next, the substrate after the treatment with the substituted palladium plating solution was immersed in a treatment solution having the following composition, then washed with water and dried.
Composition of treatment liquid Potassium thiosulfate: 50 g / L
pH adjuster: Sodium citrate pH: 6

  Then, the treated substrate was immersed in nickel PS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is an electroless nickel plating solution, at 85 ° C. for 12 minutes, and then washed with water for 1 minute. Thereby, a 3 μm electroless nickel plating film was formed on the palladium plating film. Subsequently, the substrate was immersed in HGS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), a substitution gold plating solution, at 85 ° C. for 10 minutes, washed with water for 1 minute, and then reduced gold plating solution. And immersed in HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.) at 70 ° C. for 45 minutes and washed with water for 5 minutes to form a gold layer on the electroless nickel plating film. Thus, a semiconductor chip mounting substrate was obtained. The total thickness of the gold layers obtained by displacement gold plating and reduction-type gold plating was 0.5 μm.

(Characteristic evaluation)
The obtained semiconductor chip mounting substrate was evaluated in the same manner as in Example 1 for fine wiring formability, wire bonding properties, solder connection reliability, and adhesiveness with a solder resist (SR adhesion). The obtained results are shown in Table 1.

[Comparative Example 10]
(Manufacture of semiconductor chip mounting substrates)
After performing steps (1a) to (1f) in Example 1, (1i) to (1k) without performing steps (1g) (electrolytic nickel plating) and (1h) (electroless palladium plating) The process was performed.

Subsequently, after immersing in a substituted palladium plating solution having the following composition as a plating activation treatment solution for 5 minutes, washing and drying were performed to form a substituted palladium plating film on the second copper layer.
Composition of substituted palladium plating solution Hydrochloric acid (35%): 70 ml / L
As palladium chloride (Pd): 50 mg / L
Hypophosphorous acid: 100 mg / L
Acidity: about 0.8N

  Next, the substrate after the treatment with the substituted palladium plating solution is immersed in nickel PS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is an electroless nickel plating solution at 85 ° C. for 12 minutes, and then for 1 minute. Washed with water. Thereby, a 3 μm electroless nickel plating film was formed on the palladium plating film. Subsequently, the substrate was immersed in HGS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a displacement gold plating solution, at 85 ° C. for 10 minutes, washed with water for 1 minute, and then reduced gold plating solution. And immersed in HGS-2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.) at 70 ° C. for 45 minutes and washed with water for 5 minutes to form a gold layer on the electroless nickel plating film. Thus, a semiconductor chip mounting substrate was obtained. The total thickness of the gold layers obtained by displacement gold plating and reduction-type gold plating was 0.5 μm.

(Characteristic evaluation)
The obtained semiconductor chip mounting substrate was evaluated in the same manner as in Example 1 for fine wiring formability, wire bonding properties, solder connection reliability, and adhesiveness with a solder resist (SR adhesion). The obtained results are shown in Table 1.

  From Table 1, according to Examples 1-3, compared with Comparative Examples 1-10, there is no formation of a bridge as fine wiring, and excellent fine wiring formability is obtained, as well as good wire bonding properties, It was confirmed that solder connection reliability and solder resist adhesion were obtained. Moreover, from Table 1 and Table 2, it was confirmed that wire bonding property falls as copper and nickel diffuse to a gold layer. Furthermore, from Table 3, in Examples 1 to 3, it was confirmed that the nickel crystal grain size on the surface of the nickel layer 6 on the palladium layer 13 side was small.

  From the above, it was confirmed that according to the method of the present invention, a semiconductor chip mounting substrate excellent in wire bonding property and solder connection reliability can be obtained without generating a bridge.

DESCRIPTION OF SYMBOLS 1 ... Inner layer board, 2 ... Copper foil with resin, 3 ... Copper plating layer, 4 ... Resist (plating resist), 5 ... 2nd copper layer, 6 ... Nickel layer, 7 ... Solder resist, 8 ... Gold layer, 9 DESCRIPTION OF SYMBOLS ... Reduction type gold plating film, 11 ... Replacement gold plating film, 13 ... Electroless palladium layer, 15 ... Insulating layer, 21 ... Insulating layer, 22 ... Copper foil, 30 ... IVH, 32 ... First copper layer, 50 ... Conductor circuit, 100 ... Inner layer substrate, 102 ... Inner layer circuit, 104 ... Inner layer via, 110 ... Laminated body, 120 ... Laminated body

Claims (10)

The first layer in the laminate comprising: an inner layer plate having an inner layer circuit on the surface; and a first copper layer provided on the inner layer plate with an insulating layer therebetween so as to be partially connected to the inner layer circuit. A resist forming step of forming a resist on the copper layer except for a portion to be a conductor circuit;
A second copper layer is formed by electrolytic copper plating on a portion to be the conductor circuit on the first copper layer, and the conductor circuit including the first copper layer and the second copper layer is formed. A conductor circuit forming step to obtain;
Wherein at least a part of the conductor circuit by electroless nickel plating, the conductor circuit nickel layer forming step of forming a nickel layer of an average value of the grain size of 0.07 to 0.15 micron m in a surface opposite to the When,
A first palladium layer forming step of forming a first palladium layer on at least a portion of the nickel layer by electroless palladium plating;
A resist removing step for removing the resist;
An etching step of removing the portion of the first copper layer covered with the resist by etching;
And a gold layer forming step of forming a gold layer by electroless gold plating on at least part of the conductor circuit on which the nickel layer and the first palladium layer are formed. .   After the etching step and before the gold layer forming step, a solder resist is formed on the surface so that at least a part of the conductor circuit on which the nickel layer and the first palladium layer are formed is exposed. The manufacturing method of the board | substrate for semiconductor chip mounting of Claim 1 which has a process. After the solder resist forming step and before the gold layer forming step, a second electroless palladium plating is performed on the conductor circuit on which the nickel layer and the first palladium layer exposed from the solder resist are formed. The manufacturing method of the board | substrate for semiconductor chip mounting of Claim 2 which has a 2nd palladium layer formation process which forms a palladium layer. In the resist forming step,
On the inner layer plate, a resin-coated copper foil in which an insulating layer mainly composed of a resin and a copper foil are laminated, the insulating layer is laminated so as to face the inner layer plate side,
A via hole is formed in the copper foil with resin laminated on the inner layer plate so that a part of the inner layer circuit is exposed,
Forming a copper plating layer by electroless copper plating so as to cover the inside of the copper foil and the via hole, the first copper layer comprising the copper foil and the copper plating layer and partially connected to the inner layer circuit After obtaining the laminate having
4. The method for manufacturing a semiconductor chip mounting substrate according to claim 1, wherein the resist is formed on the first copper layer in the multilayer body except for a portion to be the conductor circuit. 5. . The thickness of the said copper foil in the said copper foil with a resin is 5 micrometers or less, The manufacturing method of the board | substrate for semiconductor chip mounting of Claim 4 characterized by the above-mentioned. In the resist forming step,
On the inner layer plate having the inner layer circuit on the surface, a non-conductive film is laminated to form an insulating layer,
Forming a via hole in the insulating layer laminated on the inner layer plate so that a part of the inner layer circuit is exposed;
Forming the copper plating layer by electroless copper plating so as to cover the insulating layer and the via hole, and including the first copper layer made of the copper plating layer and partially connected to the inner layer circuit After getting the body
4. The method for manufacturing a semiconductor chip mounting substrate according to claim 1, wherein the resist is formed on the first copper layer in the multilayer body except for a portion to be the conductor circuit. 5. .   In the gold layer forming step, the electroless gold plating is performed using an electroless gold plating solution containing a reducing agent, and the reducing agent that does not generate hydrogen gas by oxidation is used. The manufacturing method of the semiconductor chip mounting substrate as described in any one of Claims.   The semiconductor chip mounting substrate according to claim 1, wherein in the gold layer forming step, the gold layer is formed by performing reduction gold plating after performing substitution gold plating. Manufacturing method.   The manufacturing method of the board | substrate for semiconductor chip mounting as described in any one of Claims 1-8 whose thickness of the said gold layer is 0.005 micrometer or more.   The method for manufacturing a semiconductor chip mounting substrate according to any one of claims 1 to 9, wherein at least a part of the conductor circuit is a solder connection terminal or a wire bonding terminal.

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