JP2011258597A - Base material with gold plated fine metal pattern, printed wiring board and semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a base material with a gold plated fine metal pattern obtained by a plated article manufacturing method which can suppress occurrence of abnormal deposition of metal on a ground resin surface when electroless nickel-palladium-gold plating is applied to the surface of a fine metal pattern supported on a resin base material.SOLUTION: The base material with a gold plated fine metal pattern comprises a base material having a support surface consisting of resin, on which a fine metal pattern and a solder resist layer to cover the fine metal pattern area are provided. The solder resist layer has an opening where at least part of the surface of the fine metal pattern is exposed but the support surface is not exposed, and a portion exposed in the opening is covered with a complex gold plated layer selected from a group consisting of a nickel-palladium-gold plated layer and a nickel-gold plated layer.

Description

  The present invention relates to a substrate with a gold-plated metal fine pattern, a printed wiring board, a semiconductor device, and a manufacturing method thereof.

  In recent years, with the demand for higher functionality, lighter weight, smaller size, and thinner electronic devices, high-density integration and high-density mounting of electronic components are progressing. The circuit wiring of printed wiring boards used in these electronic devices has a tendency to increase in density, and circuit patterns are becoming finer.

  Gold plating is performed as a final surface treatment of circuit mounting portions and terminal portions on the printed wiring board. One of the typical gold plating methods is an electroless nickel-gold plating method. In this method, a pretreatment is performed on an object to be plated by an appropriate method such as a cleaner, a palladium catalyst is applied, and then an electroless nickel plating process and an electroless gold plating process are sequentially performed. The ENIG method (Electroless Nickel Immersion Gold) is one of electroless nickel-gold plating methods, and is a method of performing substitution gold plating treatment (Immersion Gold) in the electroless gold plating treatment stage. In the electroless nickel-gold plating method, it is possible to prevent diffusion of the conductor material in the circuit and the terminal portion, improve corrosion resistance, and prevent nickel oxidation.

  As another gold plating method, application of an electroless nickel-palladium-gold plating method has begun to be studied. In this method, after the electroless nickel plating process of the electroless nickel-gold plating method, an electroless palladium plating process is performed, followed by an electroless gold plating process. The ENEPIG method (Electroless Nickel Electroless Palladium Immersion Gold) is a method of performing substitution gold plating treatment (Immersion Gold) in the electroless gold plating treatment stage of the electroless nickel-palladium-gold plating method (Patent Document 1). In the electroless nickel-palladium-gold plating method, it is possible to prevent the diffusion of the conductor material in the circuit and the terminal portion, improve the corrosion resistance, and prevent the nickel oxidation and the diffusion. In addition, since the electroless nickel-palladium-gold plating method can prevent nickel oxidation due to gold by providing an electroless palladium plating film, the reliability of lead-free solder bonding with a large thermal load is improved. Since nickel diffusion does not occur even if the gold film thickness is not increased, there is an advantage that the cost can be reduced as compared with the electroless nickel-gold plating method.

However, when the circuit of the printed wiring board is miniaturized, the metal deposits abnormally around the circuit of the insulating film supporting the conductor circuit or the resin surface of the substrate, reducing the quality of the plated surface, Cause short-circuiting between wirings or terminals.
The connection terminal of the outermost layer circuit on the semiconductor element connection side of the package substrate interposer has a narrow line-and-space (L / S) of about several tens of μm / several tens of μm, and thus is particularly prone to short circuit.

According to the study by the present inventors, it is considered that the above abnormal precipitation occurs due to the palladium catalyst applied in the process of electroless nickel-gold plating method or electroless nickel-palladium-gold plating method. The palladium catalyst is applied before electroless nickel plating in order to improve the electroless plating property of the circuit surface. However, the palladium catalyst applied at this stage may adhere not only to the circuit surface to be plated but also to the resin surface around the circuit.
It is considered that such a palladium catalyst or palladium catalyst residue existing on the resin surface serves as a nucleus and abnormal precipitation occurs on the resin surface around the circuit.

In addition, when the semi-additive method for forming a fine circuit and the electroless nickel-palladium-gold plating method are combined, a larger amount of abnormal precipitation is more likely to occur than when the subtractive method is performed. Turned out by. Therefore, when the electroless nickel-palladium-gold plating method is performed in combination with the semi-additive method, it is particularly necessary to prevent abnormal precipitation.

JP 2008-144188 A

The present invention has been made in order to solve the above-described problems, and includes a conductor circuit surface of a printed wiring board (especially a surface of a terminal portion), a conductor circuit surface of an electronic component other than the printed wiring board, and others When the surface of the metal fine pattern supported on the resin substrate is the target of plating treatment, and when electroless nickel-palladium-gold plating is performed on the surface to be plated, abnormal deposition of metal on the resin surface as the base It is an object of the present invention to provide a method for manufacturing a plated product that can prevent the occurrence of galvanic acid.
A further object of the present invention is to provide a substrate with a gold-plated metal fine pattern, a printed wiring board, and a semiconductor device having a plated surface excellent in quality.

The object is achieved by the following inventions (1) to (16).
(1) On the support surface of the base material having a support surface made of a resin, a solder resist layer is provided to cover the metal fine pattern and the region provided with the metal fine pattern,
The solder resist layer has an opening that exposes at least a part of the surface of the fine metal pattern, and the support surface is not exposed,
The exposed portion of the opening of the solder resist layer of the metal fine pattern is covered with a composite gold plating layer selected from the group consisting of a nickel-palladium-gold plating layer and a nickel-gold plating layer. Base material with metal fine pattern.
(2) The substrate with a metal fine pattern according to (1), wherein a line and space (L / S) of the region having the composite gold plating layer of the metal fine pattern is 5/5 to 100/100 μm.
(3) On the support surface of the printed wiring board substrate having a support surface made of a resin, a solder resist layer is provided to cover the conductor circuit and the region where the conductor circuit is provided,
The solder resist layer has an opening that exposes at least a part of the surface of the conductor circuit and does not expose the support surface;
The printed wiring, wherein the exposed portion of the opening of the solder resist layer of the conductor circuit is covered with a composite gold plating layer selected from the group consisting of a nickel-palladium-gold plating layer and a nickel-gold plating layer. Board.
(4) The printed wiring board according to (3) above, wherein the line and space (L / S) of the region having the composite gold plating layer of the conductor circuit is 5/5 to 100/100 μm.
(5) The printed wiring board according to (3) or (4), wherein the region having the composite gold plating layer of the conductor circuit is a region where a terminal is formed.
(6) A semiconductor device in which a semiconductor element is mounted on the printed wiring board according to (5), and a terminal of the printed wiring board and an input / output portion of the semiconductor element are connected by a peripheral arrangement.
(7) A step of preparing a substrate with a metal fine pattern having a metal fine pattern on a support surface made of a resin;
Performing a gold plating process selected from the group consisting of an electroless nickel-palladium-gold plating process and an electroless nickel-gold plating process on at least a part of the surface of the metal fine pattern, A method of manufacturing comprising:
The metal fine pattern forming surface of the substrate with the metal fine pattern is covered with a solder resist layer,
A solder resist layer existing on a predetermined region of the metal fine pattern is selectively removed to form an opening in which a part of the metal fine pattern is exposed and the support surface made of the resin is not exposed. ,
A method for producing a substrate with a gold-plated metal fine pattern, wherein the gold-plating process is performed on the metal fine pattern exposed in the opening.
(8) The solder resist layer is formed using a photosensitive solder resist, and the opening is formed by selectively removing a part of the solder resist layer by a photolithography process. Manufacturing method.
(9) The manufacturing method according to (7), wherein the opening is formed by selectively removing a part of the solder resist layer by irradiating the solder resist layer with a laser.
(10) The manufacturing method according to any one of (7) to (9), wherein a line and space (L / S) of a region in which the metal fine pattern is subjected to gold plating is 5/5 to 100/100 μm. .
(11) preparing a base material with a conductor circuit having a conductor circuit on a support surface made of a resin;
Performing a gold plating process selected from the group consisting of an electroless nickel-palladium-gold plating process and an electroless nickel-gold plating process on at least a part of the surface of the conductor circuit. And
The conductor circuit forming surface of the substrate with the conductor circuit is covered with a solder resist layer,
Selectively removing a solder resist layer present on a predetermined region of the conductor circuit to form an opening in which a part of the conductor circuit is exposed and the support surface made of the resin is not exposed;
A method of manufacturing a printed wiring board, wherein the gold plating process is performed on a conductor circuit exposed in the opening.
(12) The solder resist layer is formed using a photosensitive solder resist, and the opening is formed by selectively removing a part of the solder resist layer by a photolithography process. Manufacturing method.
(13) The manufacturing method according to (11), wherein the opening is formed by selectively removing a part of the solder resist layer by irradiating the solder resist layer with a laser.
(14) The manufacturing method according to any one of (11) to (13), wherein a line and space (L / S) of a region in which the conductor circuit is subjected to gold plating is 5/5 to 100/100 μm.
(15) The manufacturing method according to any one of (11) to (14), wherein the region having the composite gold plating layer of the conductor circuit is a region where a terminal is formed.
(16) A semiconductor element is mounted on a printed wiring board obtained by the manufacturing method according to any one of (11) to (15), and a terminal of the printed wiring board and an input / output portion of the semiconductor element are arranged as a peripheral. A manufacturing method of a semiconductor device, characterized in that the connection is made by

According to the present invention, the wiring between the conductor circuits of the printed wiring board is covered with the solder resist layer, the solder resist layer is opened so that only the terminal surface is exposed, and the opening is electroless nickel-palladium-gold plated. By coating a composite gold plating layer selected from the group consisting of a layer and an electroless nickel-gold plating layer, abnormalities in the metal around the conductor circuit of the printed wiring board, particularly between the fine circuit wiring and the resin surface between the terminals Precipitation can be prevented.
The present invention can also be suitably applied to the surface of a conductor circuit of an electronic component other than a printed wiring board. Furthermore, in various fields other than the electronic component, the metal supported on the resin base material It can be suitably applied to the case where a fine pattern is plated, and a high quality plated surface can be obtained.

It is a figure which shows typically the cross section of the printed wiring board which belongs to this invention. It is the top view which expanded a part of terminal area | region of a printed wiring board. It is AA sectional drawing of the terminal area | region of the printed wiring board shown to FIG. 2A. It is a figure which shows typically the cross section of only the single side | surface of the semiconductor device which belongs to this invention. It is a figure explaining the procedure (1st part) which manufactures a printed wiring board. It is a figure explaining the procedure (2nd part) which manufactures a printed wiring board. It is a figure explaining the procedure (3rd part) which manufactures a printed wiring board. It is a block diagram which shows the procedure of the electroless nickel-palladium-gold plating method. It is a block diagram which shows the procedure of the electroless nickel-gold plating method.

The inventor covers the printed circuit board between the conductor circuit wirings with a solder resist layer, opens the solder resist layer so that only the surface of the conductor circuit serving as the terminal portion is exposed, and electrolessly opens the opening. By coating the composite gold plating layer by the nickel-gold plating method or the electroless nickel-palladium-gold plating method, metal abnormalities around the conductor circuit of the printed wiring board, especially between the wiring of the fine circuit and between the terminals It was discovered that precipitation can be prevented.
In other words, by covering the region other than the surface of the conductor circuit serving as the terminal portion with the solder resist layer, it is possible to eliminate the occurrence of abnormal precipitation around the conductor circuit of the printed wiring board.

  The present invention can be suitably applied to the surface of a conductor circuit of an electronic component other than a printed wiring board, and further, a metal fine pattern supported on a resin substrate in various fields other than the electronic component. Can be suitably applied to the case of plating with a high quality plating surface.

Conventionally, in order to connect a semiconductor element to a printed wiring board by peripheral arrangement, a structure in which a conductor terminal is provided on the printed wiring board and connected to a connecting member such as a gold wire or solder may be used. Such peripheral-type terminals have been increasingly narrowed against the background of high performance of semiconductor devices in recent years, and the solder resist used as a surface protective layer for printed wiring boards includes a plurality of terminals. It is formed with the structure which opens.
The reason for opening a range including a plurality of terminals in this way is to prevent a decrease in yield due to the resolution performance of the applied solder resist and the positioning accuracy of the exposure process. The problem of short-circuiting due to abnormal deposition of plating on the resin surface has become apparent.

Based on the above findings, the following invention is provided.
The substrate with a gold-plated metal fine pattern of the present invention is
On the support surface of the base material having a support surface made of resin, a solder resist layer is provided to cover the metal fine pattern and the region provided with the metal fine pattern,
The solder resist layer has an opening that exposes at least a part of the surface of the fine metal pattern, and the support surface is not exposed,
The exposed portion of the opening of the solder resist layer of the fine metal pattern is covered with a composite gold plating layer selected from the group consisting of a nickel-palladium-gold plating layer and a nickel-gold plating layer.

The printed wiring board of the present invention is
On the support surface of the printed wiring board substrate having a support surface made of a resin, a solder resist layer is provided to cover the conductor circuit and the region where the conductor circuit is provided,
The solder resist layer has an opening that exposes at least a part of the surface of the conductor circuit and does not expose the support surface;
The exposed portion of the opening of the solder resist layer of the conductor circuit is covered with a composite gold plating layer selected from the group consisting of a nickel-palladium-gold plating layer and a nickel-gold plating layer.

  The semiconductor device of the present invention is characterized in that a semiconductor element is mounted on the printed wiring board of the present invention, and a terminal of the printed wiring board and an input / output portion of the semiconductor element are connected by a peripheral arrangement.

Moreover, the manufacturing method of the substrate with a gold-plated metal fine pattern of the present invention,
A step of preparing a substrate with a metal fine pattern having a metal fine pattern on a support surface made of a resin;
Performing a gold plating process selected from the group consisting of an electroless nickel-palladium-gold plating process and an electroless nickel-gold plating process on at least a part of the surface of the metal fine pattern, A method of manufacturing comprising:
The metal fine pattern forming surface of the substrate with the metal fine pattern is covered with a solder resist layer,
A solder resist layer existing on a predetermined region of the metal fine pattern is selectively removed to form an opening in which a part of the metal fine pattern is exposed and the support surface made of the resin is not exposed. ,
The gold plating process is performed on the metal fine pattern exposed in the opening.

Moreover, the method for producing the printed wiring board of the present invention is as follows.
Preparing a base material with a conductor circuit having a conductor circuit on a support surface made of a resin;
Performing a gold plating process selected from the group consisting of an electroless nickel-palladium-gold plating process and an electroless nickel-gold plating process on at least a part of the surface of the conductor circuit. And
The conductor circuit forming surface of the substrate with the conductor circuit is covered with a solder resist layer,
Selectively removing a solder resist layer present on a predetermined region of the conductor circuit to form an opening in which a part of the conductor circuit is exposed and the support surface made of the resin is not exposed;
The gold plating process is performed on the conductor circuit exposed in the opening.

In addition, a method for manufacturing a semiconductor device of the present invention includes:
A semiconductor element is mounted on the printed wiring board obtained by the manufacturing method of the present invention, and a terminal of the printed wiring board and an input / output portion of the semiconductor element are connected by peripheral arrangement.

First, the structure of the printed wiring board will be described.
FIG. 1 is a diagram schematically showing a cross section of a printed wiring board belonging to the present invention. The printed wiring board 1 has a core substrate 2 and conductor circuit layers on both sides thereof. Four conductor circuit layers 3a, 3b, 3c, 3d are sequentially stacked on the upper surface side of the core substrate 2 via interlayer insulating layers 4a, 4b, 4c, and four conductor circuit layers are disposed on the lower surface side. 5a, 5b, 5c, and 5d are sequentially stacked via interlayer insulating layers 4d, 4e, and 4f. The conductor circuit layers 3a to 3d and 5a to 5d are formed on a support surface made of a core substrate or an interlayer insulating layer. The conductor circuit layers on the upper and lower surfaces are connected to each other through via holes. Most of the outermost layer circuit 3d on the upper surface side of the core substrate is covered with the solder resist layer 6, but a part of the pad portion 7a included in the terminal region 7 (not shown) of the conductor circuit layer 3d is exposed. An opening 6 a is formed, and the exposed portion of the pad portion 7 a is covered with a nickel-palladium-gold plating layer 8. The solder resist layer 6 is coated so that there is no gap where the surface of the resin layer 4c is exposed. The outermost layer circuit 5d on the lower surface side of the core substrate is covered with a solder resist layer 6 so as to form an opening 6b for connection with a mother board or the like. The printed wiring board 1 can be connected to a mother board or the like by providing a contact member such as a solder ball on the pad portion 7c exposed from the opening 6b. The opening 6b may have a structure in which a gap is provided between the pad portion 7c and the solder resist 6, or may have a structure in which the periphery of the pad portion 7c is covered with the solder resist 6. FIG. 1 shows an opening 6 b having a structure in which a gap is provided between the pad portion 7 c and the solder resist 6. Since the opening 6b does not include a plurality of connection terminals like the terminal region 7 and short-circuit due to abnormal precipitation does not occur, the surface treatment (not shown) of the opening 6b is performed by electroless nickel-palladium. Mood gold plating or other known surface treatment methods may be used.
Although the printed wiring board 1 has a laminated structure of interlayer insulating layers on both surfaces of the core substrate, the printed wiring board of the present invention is not limited to this, and may have a structure having an interlayer insulating layer only on one side of the core substrate. A structure having only the core substrate may be used without the interlayer insulating layer.

  The terminal area 7 of the printed wiring board 1 is arranged by peripheral arrangement. In the present invention, the peripheral arrangement means that a large number of electrode terminals are arranged along the outer periphery of one main surface thereof. In the printed wiring board of the present invention, it is preferable that the terminal region has a peripheral arrangement, but there is no particular limitation, and a large number of electrode terminals are arranged in a grid pattern over substantially the entire main surface. An area array type may be used.

  FIG. 2A is an enlarged plan view of a part of the terminal region 7. The terminal region 7 has a pad portion 7a serving as an electrical connection point and a circuit 7b in the vicinity of the pad portion, and is covered with a solder resist layer 6 that is an insulating material, and a part of the pad portion 7a is exposed in the opening 6a. is doing. An exposed portion of the pad portion 7a and an electronic component (such as an element or a circuit) can be electrically connected. In FIG. 2A, the pad portion 7a present under the solder resist layer 6 and the circuit 7b in the vicinity of the pad portion are shown by dotted lines, although they are not visible because they are covered with the solder resist layer 6.

  2B is an AA cross-sectional view of the terminal region 7 of the printed wiring board shown in FIG. 2A. An exposed portion of the pad portion 7 a in the opening 6 a is covered with a nickel-palladium-gold plating layer 8.

  The printed wiring board 1 is excellent in the quality of the plated surface because there is no abnormal deposition of the resin surface around the terminal region 7, particularly the position sandwiched between adjacent circuits, and short-circuiting occurs. Absent. Abnormal precipitation due to nickel-palladium-gold plating is more likely to occur as the conductor circuit becomes finer and the distance between the conductor circuits becomes smaller. According to the present invention, however, a composite gold plating layer such as a nickel-palladium-gold plating layer of the conductor circuit is provided. Metal precipitation can be effectively prevented when the line and space of the region is in the range of 5/5 to 100/100 μm.

  FIG. 3 is a diagram schematically showing a cross section of only one side of a semiconductor device using the printed wiring board 1. The semiconductor device 10 is formed by mounting a semiconductor element 11 on a printed wiring board 1 by wire bonding. Although FIG. 3 shows an example in which semiconductor elements are connected by wire bonding, in the present invention, the connection method between the printed wiring board and the semiconductor elements is not particularly limited, and connection is made by a known method such as wire bonding or flip chip. be able to.

The outermost layer circuit 3d on the upper surface side of the printed wiring board 1 is covered with the solder resist layer 6, but a part of the pad portion 7a is exposed from the opening 6a of the solder resist layer 6, and the pad portion 7a. The exposed portion is covered with a nickel-palladium-gold plating layer 8. The solder resist layer 6 is coated so that there is no gap where the surface of the resin layer 4c is exposed.
The semiconductor element 11 is fixed on the solder resist layer 6 of the printed wiring board 1 via a die bond material cured layer 13 such as an epoxy resin. The semiconductor element 11 has an electrode pad 12 on the upper surface, and the electrode pad 12 and a connection terminal formed so as to cover the opening 6 a of the outermost layer circuit of the printed wiring board 1 are connected by a gold wire 14. is doing.
The semiconductor element mounting side of the semiconductor device 10 is sealed with a sealing material 15 such as epoxy resin.
Although FIG. 3 shows an example in which semiconductor elements are connected by wire bonding, the present invention is also applied to the case where the terminal portion of another connection method such as an area array type package is plated with gold.

Next, a method for manufacturing the printed wiring board 1 of FIG. 1 will be described.
First, a printed wiring board substrate having a support surface made of resin is prepared.
In the case of the printed wiring board 1, the printed wiring board substrate lacks the solder resist layer 6, the outermost layer circuit 3 d, and the nickel-palladium-gold plating layer 8 from the printed wiring board shown in FIG. A stacked body having the third interlayer insulating layer 4c is prepared.
In the present invention, the printed wiring board base material includes the core substrate 2 and one or more conductor circuit layers on the core substrate 2, the uppermost layer being an interlayer insulating layer, and a conductor circuit layer further thereon Is an intermediate product of a multilayer printed wiring board in a state where it can be formed.
In addition, the “substrate having a support surface made of resin” in the case of manufacturing a substrate with a gold-plated metal fine pattern other than a printed wiring board is not particularly limited, but by a semi-additive or subtractive method, etc. Any base material having a resin surface capable of forming a metal fine pattern may be used, and a deep portion of the base material may be made of a material other than resin.
Next, a conductor circuit is formed on the substrate for a printed wiring board to obtain a substrate with a conductor circuit. The formation method of the said conductor circuit is not specifically limited, It can carry out by well-known methods, such as a semi-additive method, an additive method, and a subtractive method. Among these, it is preferable to form the conductor circuit by a semi-additive method that enables particularly fine wiring processing.
In the case of the printed wiring board 1, the substrate with a conductor circuit is a laminate having a structure in which the solder resist layer 6 and the nickel-palladium-gold plating layer 8 are missing from the printed wiring board 1 shown in FIG.
Next, the conductor circuit forming surface of the substrate with the conductor circuit is covered with a solder resist layer, the solder resist layer existing on a predetermined region of the conductor circuit is selectively removed, and a part of the conductor circuit is An opening that is exposed and the support surface made of the resin is not exposed is formed.
Next, printed wiring by performing gold plating selected from the group consisting of electroless nickel-palladium-gold plating and electroless nickel-gold plating on at least a part of the surface of the conductor circuit included in the substrate with the conductor circuit. Get a board. In the case of the printed wiring board 1, the gold plating process is performed on the conductor circuit exposed at the opening of the solder resist layer.

Hereinafter, a method for manufacturing the printed wiring board 1 will be described in detail with reference to the drawings.
(A)-(k) as described in FIG. 4A, FIG. 4B, and FIG. 4C is a figure explaining the procedure which manufactures a printed wiring board. 4A, 4B, and 4C are schematic views showing only one side of the printed wiring board.
First, in the procedure (a), three conductor circuit layers (3a, 3b, 3c) are laminated on the upper surface side of the core substrate 2 via interlayer insulating layers (4a, 4b), and on the lower surface side of the core substrate 2. A conductor circuit layer 5 is formed, and a laminate in which the conductor circuit layers are connected in layers is prepared.
As the core substrate, a known substrate such as a glass epoxy substrate can be used. The conductive circuit layer can be built up on the core substrate using a known material, and the circuit can be formed by the known method.
Further, a resin sheet in which the insulating layer 4c ″ is laminated on the carrier film 16 is prepared. As the resin sheet, a known sheet that can transfer the interlayer insulating layer can be used.

  The resin sheet carrier film 16 has releasability so that the insulating layer 4c '' can be transferred onto the conductor circuit layer. The carrier film is not particularly limited, but a polymer film or a metal foil can be used. As the polymer film, for example, a thermoplastic resin film having heat resistance such as a polyester resin such as polyethylene terephthalate or polybutylene terephthalate, a fluorine-based resin, or a polyimide resin can be used. Examples of the metal foil include copper and / or copper-based alloy, aluminum and / or aluminum-based alloy, iron and / or iron-based alloy, silver and / or silver-based alloy, gold and gold-based alloy, zinc and zinc-based alloy. Further, metal foils such as nickel and nickel alloys, tin and tin alloys can be used.

The thickness of the carrier film is not particularly limited, but it is preferable to use a carrier film having a thickness of 10 to 70 μm because the handleability when producing the resin sheet is good.
Although the thickness of the insulating layer on a carrier film is not specifically limited, 1-60 micrometers is preferable and 5-40 micrometers is especially preferable. The thickness of the resin layer is preferably equal to or greater than the lower limit for improving insulation reliability, and is preferably equal to or less than the upper limit for achieving thinning of the multilayer printed wiring board.

The resin composition constituting the insulating layer 4c ″ is preferably composed of a resin composition containing a thermosetting resin. Thereby, the heat resistance of the resin layer can be improved.
The insulating layer 4c '' may include a base material such as a glass fiber base material.
Examples of thermosetting resins include novolak type phenolic resins such as phenol novolak resin, cresol novolak resin, bisphenol A novolak resin, unmodified resol phenol resin, oil-modified resol phenol resin modified with tung oil, linseed oil, walnut oil, and the like. Phenol resin such as resol type phenol resin, bisphenol A epoxy resin, bisphenol F epoxy resin, bisphenol E type epoxy resin, bisphenol S type epoxy resin, bisphenol Z type epoxy resin, bisphenol P type epoxy resin, bisphenol M type epoxy resin Bisphenol epoxy resin, phenol novolac epoxy resin, cresol novolac epoxy resin novolac epoxy resin, biphenyl epoxy resin, bif Nylaralkyl type epoxy resin, aryl alkylene type epoxy resin, naphthalene type epoxy resin, anthracene type epoxy resin, phenoxy type epoxy resin, dicyclopentadiene type epoxy resin, norbornene type epoxy resin, adamantane type epoxy resin, fluorene type epoxy resin, etc. Resin having triazine ring such as epoxy resin, urea (urea) resin, melamine resin, unsaturated polyester resin, bismaleimide resin, polyimide resin, polyamideimide resin, polyurethane resin, diallyl phthalate resin, silicone resin, benzoxazine ring Examples thereof include resins, triazine resins, benzocyclobutene resins, and cyanate resins.
Among these, one or more resins selected from epoxy resins, phenol resins, cyanate resins, and benzocyclobutene resins are preferable, and cyanate resins are particularly preferable. Thereby, the thermal expansion coefficient of the resin layer can be reduced. Further, the resin layer is excellent in electrical characteristics (low dielectric constant, low dielectric loss tangent), mechanical strength and the like.

  Specific examples of the cyanate resin include novolak-type cyanate resins, bisphenol A-type cyanate resins, bisphenol E-type cyanate resins, and bisphenol-type cyanate resins such as tetramethylbisphenol F-type cyanate resins. Among these, novolac type cyanate resin is preferable. The novolac-type cyanate resin can reduce the thermal expansion coefficient of the resin layer, and is excellent in the mechanical strength and electrical characteristics (low dielectric constant, low dielectric loss tangent) of the resin layer.

  The weight average molecular weight of the cyanate resin is not particularly limited, but a weight average molecular weight of 500 to 4,500 is preferable, and 600 to 3,000 is particularly preferable. If the weight average molecular weight is less than the lower limit, the mechanical strength of the cured product of the resin layer may be reduced, and further, tackiness may occur when the resin layer is produced, and the resin may be transferred. . Further, when the weight average molecular weight exceeds the above upper limit, the curing reaction is accelerated, and when a substrate (particularly, a circuit substrate) is formed, molding defects may occur or the interlayer peel strength may be reduced. In addition, weight average molecular weights, such as cyanate resin, can be measured by GPC (gel permeation chromatography, standard substance: polystyrene conversion), for example.

  Although content of a thermosetting resin is not specifically limited, 5 to 50 weight% of the whole resin composition is preferable, and 10 to 40 weight% is especially preferable. If the content is less than the lower limit, it may be difficult to form the resin layer, and if the content exceeds the upper limit, the strength of the resin layer may be reduced.

When a cyanate resin (especially a novolac-type cyanate resin) is used as the thermosetting resin, it is preferable to use an epoxy resin (substantially free of halogen atoms) in combination.
Examples of the epoxy resin include bisphenol A epoxy resin, bisphenol F epoxy resin, bisphenol E type epoxy resin, bisphenol S type epoxy resin, bisphenol Z type epoxy resin, bisphenol P type epoxy resin, bisphenol M type epoxy resin and the like. Resins, phenol novolac epoxy resins, cresol novolac epoxy resins and other novolac epoxy resins, biphenyl epoxy resins, xylylene epoxy resins, biphenyl aralkyl epoxy resins and other aryl alkylene epoxy resins, naphthalene epoxy resins, anthracene epoxy Resin, phenoxy type epoxy resin, dicyclopentadiene type epoxy resin, norbornene type epoxy resin, adamantane type epoxy Resins, fluorene type epoxy resins and the like.
As the epoxy resin, one of these can be used alone, or two or more having different weight average molecular weights are used in combination, or one or two or more thereof and a prepolymer thereof are used in combination. You can also

  Although content of an epoxy resin is not specifically limited, 1 to 55 weight% of the whole resin composition is preferable, and 5 to 40 weight% is especially preferable. If the content is less than the lower limit, the reactivity of the cyanate resin may decrease, or the moisture resistance of the resulting product may decrease. If the content exceeds the upper limit, the low thermal expansion and heat resistance will decrease. There is a case.

  The weight average molecular weight of the epoxy resin is not particularly limited, but a weight average molecular weight of 500 to 20,000 is preferable, and 800 to 15,000 is particularly preferable. If the weight average molecular weight is less than the lower limit, tackiness may occur on the surface of the resin layer, and if it exceeds the upper limit, solder heat resistance may be reduced. By setting the weight average molecular weight within the above range, it is possible to achieve an excellent balance of these characteristics. The weight average molecular weight of an epoxy resin can be measured by GPC, for example.

  Further, the resin composition constituting the insulating layer 4 c ″ can include an inorganic filler. Thereby, low thermal expansibility and mechanical strength can be provided. The inorganic filler is not particularly limited. For example, talc, fired clay, unfired clay, mica, silicates such as glass, oxides such as titanium oxide, alumina, silica, and fused silica, carbonic acid Carbonates such as calcium, magnesium carbonate, hydrotalcite, hydroxides such as aluminum hydroxide, magnesium hydroxide, calcium hydroxide, sulfates or sulfites such as barium sulfate, calcium sulfate, calcium sulfite, zinc borate, Borates such as barium metaborate, aluminum borate, calcium borate and sodium borate, nitrides such as aluminum nitride, boron nitride, silicon nitride and carbon nitride, titanates such as strontium titanate and barium titanate Can be mentioned. As the inorganic filler, one of these can be used alone, or two or more can be used in combination. Among these, silica is preferable and fused silica is more preferable in terms of excellent low thermal expansion, flame retardancy, and elastic modulus. Among these, the shape is preferably spherical silica. Moreover, it is more preferable to use glass fiber because it is further excellent in low thermal expansion, flame retardancy, and elastic modulus.

  The average particle diameter of the inorganic filler can be measured, for example, by a laser diffraction scattering method. The inorganic filler is dispersed in water by ultrasonic waves, and the particle size distribution of the inorganic filler is created on a volume basis by a laser diffraction type particle size distribution measuring device (HORIBA, LA-500), and the median diameter (D50) is averaged. It can measure by setting it as a particle diameter.

  The method for producing the resin sheet is not particularly limited. For example, a resin varnish is prepared by dissolving and dispersing a resin composition in a solvent or the like, impregnated and applied to glass fibers, and dried using various coater devices. Examples thereof include a method of drying the varnish after coating on the carrier film and a method of drying the resin varnish after spray coating on the carrier film using a spray device. Among these, a method in which a resin varnish is coated on a carrier film using various coaters such as a comma coater and a die coater and then dried is preferable. Thereby, the resin sheet which does not have a void and has the thickness of the uniform resin layer can be manufactured efficiently.

Next, in the step (b), the insulating layer side of the resin sheet is faced and stacked on the upper surface side of the laminate prepared in the step (a), and then the carrier film 16 is peeled in the step (c). When the interlayer insulating layer 4c is formed, a printed wiring board substrate is obtained.
The surface 4c ′ on the side where the carrier film of the interlayer insulating layer 4c is peeled is preferably roughened. As the roughening treatment method, for example, (a) a carrier film having a roughened contact surface with the interlayer insulating layer 4c is used, and the roughened carrier film is peeled off, thereby peeling the interlayer insulating layer. A method of roughening the surface 4c ′ of 4c, and (a) a surface 4c of the interlayer insulating layer 4c obtained by peeling off the roughened carrier film using a carrier film having a roughened contact surface with the interlayer insulating layer 4c. ', A method of roughening by plasma treatment and / or desmear treatment, (c) using a non-roughened carrier film, the surface 4c' of the interlayer insulating layer 4c from which the non-roughened carrier film was peeled off, Examples of the method include roughening by plasma treatment and / or desmear treatment.

  Next, in step (d), electroless plating is performed to form the electroless plating layer 18 on the surface of the interlayer insulating layer 4c. The type of metal of the electroless plating layer 18 is not particularly limited, but copper, nickel and the like are preferable.

  Next, in the procedure (e), the non-circuit forming portion is masked on the electroless plating layer 18 by the plating resist 19, and the electrolytic plating is performed in the procedure (f) to form the electrolytic plating layer 20. For the electrolytic plating, copper sulfate electrolytic plating can be used.

  Next, in step (g), the plating resist 19 is removed, and in step (h), the electroless plating layer 18 in the non-circuit forming portion is removed by flash etching, whereby the outermost layer circuit 3d is formed on the interlayer insulating layer 4c. When formed, a substrate with a conductor circuit is obtained.

  Next, the solder resist layer 6 is coated in the procedure (i), and in the procedure (j), a part of the solder resist layer 6 is selectively removed by a photolithography process or laser irradiation, and the opening 6a is removed. Form. A part of the pad portion 7a of the terminal region 7 is exposed in the opening 6a.

When the step (j) is performed by a photolithography process, the solder resist layer 6 is formed using a photosensitive solder resist.
When the step (j) is performed by a photolithography process, specifically, for example, a solder resist layer 6 is formed using a negative resist as the photosensitive solder resist, and active energy rays are formed in a region other than the opening 6a. Is selectively irradiated, cured, and developed to remove the solder-resist layer 6 covering the opening 6a and form the opening 6a.

When a part of the solder resist layer 6 is selectively removed by laser irradiation, a thermosetting or thermoplastic resist can be used.
The laser light is preferably a UV-YAG laser or an excimer laser. By using these lasers, the opening of the solder resist layer can be formed with high accuracy and shape. Although not particularly limited, the wavelength of the UV-YAG laser is preferably 355 nm, and the laser wavelength of the excimer laser can be 193 nm, 248 nm, 308 nm, or the like.

Next, in the step (k), the electroless nickel-palladium-gold plating is selectively performed on a part of the pad portion 7a exposed from the opening 6a of the base material with a conductor circuit. Is obtained.
In the base material with a conductor circuit, only a part of the pad portion 7a of the terminal region 7 in the outermost layer circuit is exposed from the opening 6a of the solder resist layer 6, so that the exposed portion of the pad portion 7a is nickel. -Palladium-gold plating can be selectively performed.
In the present invention, when it is desired to perform nickel-palladium-gold plating only on a partial area of a conductor circuit or a metal fine pattern, in addition to a permanent resist such as a solder resist layer, there are other resists such as a soluble resist and a molded product mask. Alternatively, a plating mask may be used.

  In the present invention, a gold plating process selected from the group consisting of an electroless nickel-palladium-gold plating process and an electroless nickel-gold plating process is performed. By performing the gold plating process, a composite gold plating layer selected from the group consisting of a nickel-palladium-gold plating layer (Ni-Pd-Au layer) and a nickel-gold plating layer (Ni-Au layer) is formed on the conductor circuit. To do. Among the gold plating processes, the ENEPIG method which is an example of an electroless nickel-palladium-gold plating process is particularly preferable. This is because it is more excellent in preventing oxidation and diffusion of nickel, has high heat resistance, and can reduce the thickness of the gold film.

FIG. 5 is a block diagram showing the procedure of the ENEPIG method as an example of the electroless nickel-palladium-gold plating process, and FIG. 6 is a block diagram showing the procedure of the ENIG method as an example of the electroless nickel-gold plating process.
When performing the ENEPIG method or the ENIG method in the present invention, as a pretreatment prior to the palladium catalyst application step, the terminal portion can be subjected to a surface treatment by one or more methods as necessary. In these figures, cleaner (S1a), soft etching (S1b), acid treatment (S1c), and pre-dip (S1d) are shown as pretreatments, but other treatments may be performed.
After the pretreatment, a composite gold plating layer (Ni—Pd—Au layer or Ni—Au layer) is formed by applying a palladium catalyst and performing the ENEPIG method or the ENIG method.

Hereinafter, the procedure of the ENEPIG method will be described unless otherwise specified, but the ENIG method can be considered in the same manner as the procedure of the ENEPIG method.
In the ENEPIG method, the pretreatment (S1), the palladium catalyst application step (S2), the electroless nickel plating treatment (S3), the electroless palladium plating treatment (S4), and the electroless gold plating treatment (S5) are the same as before. You can go to

Hereinafter, each processing stage of S1 to S5 will be described sequentially.
<Preprocessing (S1)>
(1) Cleaner treatment (S1a)
Cleaner treatment (S1a), which is one of the pre-treatments, removes the organic coating from the terminal surface, activates the metal on the terminal surface, and wets the terminal surface by bringing an acidic or alkaline type cleaner solution into contact with the terminal surface. This is done to improve the performance.
The acid type cleaner mainly activates the surface by etching a very thin portion of the terminal surface. As an effective material for the copper terminal, a liquid containing oxycarboxylic acid, ammonia, salt, and a surfactant is used. (For example, ACL-007 of Uemura Kogyo Co., Ltd.) is used.
As another acidic type cleaner effective for copper terminals, a solution containing sulfuric acid, a surfactant, and sodium chloride (for example, ACL-738 of Uemura Kogyo Co., Ltd.) may be used. high.
The alkaline type cleaner mainly removes the organic coating, and as a material effective for the copper terminal, a liquid containing nonionic surfactant, 2-ethanolamine, diethylenetriamine (for example, ACL of Uemura Kogyo Co., Ltd.) -009) is used.
In order to perform the cleaner treatment, any one of the above-mentioned cleaner liquids is brought into contact with the terminal portion by a method such as immersion or spraying, and then washed with water.

(2) Soft etching process (S1b)
The soft etching process (S1b), which is another pretreatment, is performed in order to remove the oxide film by etching a very thin portion of the terminal surface. As a soft etching solution effective for the copper terminal, an acidic solution containing sodium persulfate and sulfuric acid is used.
In order to perform the soft etching process, the terminal portion is brought into contact with the soft etching solution by a method such as immersion or spraying, and then washed with water.

(3) Pickling treatment (S1c)
The pickling treatment (S1c), which is another pretreatment, is performed to remove smut (copper fine particles) from the terminal surface or the resin surface in the vicinity thereof.
As the pickling solution effective for the copper terminal, sulfuric acid is used.
In order to perform the pickling treatment, the pickling solution may be brought into contact with the terminal portion by a method such as immersion or spraying and then washed with water.

(4) Pre-dip process (S1d)
The pre-dip treatment (S1d), which is another pretreatment, is a treatment that is immersed in sulfuric acid having substantially the same concentration as the catalyst application liquid prior to the palladium catalyst application process, and is included in the catalyst application liquid by increasing the hydrophilicity of the terminal surface. This is performed to improve the adhesion to Pd ions, to avoid repeated inflow of the washing water into the catalyst application liquid, and to allow repeated reuse of the catalyst application liquid, or to remove the oxide film. As the pre-dip solution, sulfuric acid is used.
In order to perform the pre-dip treatment, the terminal portion is immersed in the pre-dip solution. In addition, water washing is not performed after the pre-dip treatment.

<Palladium catalyst application step (S2)>
An acidic liquid (catalyst imparting liquid) containing Pd ²⁺ ions is brought into contact with the terminal surface, and the Pd ²⁺ ions are replaced with metal Pd on the terminal surface by an ionization tendency (Cu + Pd ²⁺ → Cu ²⁺ + Pd). Pd adhering to the terminal surface acts as a catalyst for electroless plating. Palladium sulfate or palladium chloride can be used as a palladium salt which is a Pd ²⁺ ion supply source.
Palladium sulfate has a lower adsorption power than palladium chloride and is easy to remove Pd, so it is suitable for forming fine wires. As the palladium sulfate-based catalyst imparting solution effective for the copper terminal, sulfuric acid, palladium salt, and strong acid solution containing copper salt (for example, KAT-450 of Uemura Kogyo Co., Ltd.), oxycarboxylic acid, sulfuric acid, and A strong acid solution containing a palladium salt (for example, MNK-4 from Uemura Kogyo Co., Ltd.) is used.
On the other hand, palladium chloride has a strong adsorptive power and displaceability, and is difficult to remove Pd. Therefore, when electroless plating is performed under conditions where plating non-deposition is likely to occur, the effect of preventing non-plating is obtained.
In order to perform the palladium catalyst application step, the catalyst application solution may be brought into contact with the terminal portion by a method such as immersion or spraying, and then washed with water.

<Electroless nickel plating treatment (S3)>
As the electroless nickel plating bath, for example, a plating bath containing a water-soluble nickel salt, a reducing agent and a complexing agent can be used. Details of the electroless nickel plating bath are described, for example, in JP-A-8-269726.
As the water-soluble nickel salt, nickel sulfate, nickel chloride or the like is used, and its concentration is set to about 0.01 to 1 mol / liter.
As the reducing agent, hypophosphite such as hypophosphorous acid and sodium hypophosphite, dimethylamine borane, trimethylamine borane, hydrazine and the like are used, and the concentration is set to about 0.01 to 1 mol / liter.
As the complexing agent, carboxylic acids such as malic acid, succinic acid, lactic acid, citric acid, and sodium salts thereof, and amino acids such as glycine, alanine, iminodiacetic acid, arginine, and glutamic acid are used, and the concentration is 0.01 to About 2 mol / liter.
The plating bath is adjusted to pH 4-7 and used at a bath temperature of about 40-90 ° C. When hypophosphorous acid is used as a reducing agent in this plating bath, the next main reaction proceeds on the copper terminal surface by the Pd catalyst, and a Ni plating film is formed.
Ni ²⁺ + H ₂ PO ₂ ⁻ + H ₂ O + 2e ⁻ → Ni + H ₂ PO ₃ ⁻ + H ₂

<Electroless palladium plating treatment (S4)>
As the electroless palladium plating bath, for example, a plating bath containing a palladium compound, a complexing agent, a reducing agent, and an unsaturated carboxylic acid compound can be used.
As the palladium compound, for example, palladium chloride, palladium sulfate, palladium acetate, palladium nitrate, tetraammine palladium hydrochloride and the like are used, and the concentration is about 0.001 to 0.5 mol / liter based on palladium.
As the complexing agent, ammonia or an amine compound such as methylamine, dimethylamine, methylenediamine, EDTA or the like is used, and the concentration is set to about 0.001 to 10 mol / liter.
As the reducing agent, hypophosphorous acid or hypophosphite such as sodium hypophosphite or ammonium hypophosphite is used, and its concentration is set to about 0.001 to 5 mol / liter.
Examples of unsaturated carboxylic acid compounds include unsaturated carboxylic acids such as acrylic acid, methacrylic acid, and maleic acid, anhydrides thereof, salts such as sodium salts and ammonium salts thereof, derivatives such as ethyl esters and phenyl esters thereof, and the like. The concentration is about 0.001 to 10 mol / liter.
The plating bath is adjusted to pH 4 to 10 and used at a bath temperature of about 40 to 90 ° C. When hypophosphorous acid is used as a reducing agent in this plating bath, the following main reaction proceeds on the copper terminal surface (actually the nickel surface), and a Pd plating film is formed.
Pd ²⁺ + H ₂ PO ₂ ⁻ + H ₂ O → Pd + H ₂ PO ₃ ⁻ + 2H ⁺

<Electroless gold plating treatment (S5)>
As the electroless gold plating bath, for example, a plating bath containing a water-soluble gold compound, a complexing agent, and an aldehyde compound can be used. Details of the electroless gold plating bath are described in, for example, JP-A-2008-144188.
As the water-soluble gold compound, for example, a gold cyanide salt such as gold cyanide, potassium gold cyanide, sodium gold cyanide, ammonium gold cyanide is used, and the concentration thereof is 0.0001 to 1 mol / liter based on gold. To the extent.
As the complexing agent, for example, phosphoric acid, boric acid, citric acid, gluconic acid, tartaric acid, lactic acid, malic acid, ethylenediamine, triethanolamine, ethylenediaminetetraacetic acid and the like are used, and the concentration is 0.001-1 mol / Use about liters.
Examples of aldehyde compounds (reducing agents) include aliphatic saturated aldehydes such as formaldehyde and acetaldehyde, aliphatic dialdehydes such as glyoxal and succindialdehyde, aliphatic unsaturated aldehydes such as crotonaldehyde, benzaldehyde, o-, m- Alternatively, an aromatic aldehyde such as p-nitrobenzaldehyde, a saccharide having an aldehyde group (—CHO) such as glucose or galactose is used, and the concentration is set to about 0.0001 to 0.5 mol / liter.
The plating bath is adjusted to pH 5 to 10 and used at a bath temperature of about 40 to 90 ° C. When this plating bath is used, the following two substitution reactions proceed on the copper terminal surface (actually the palladium surface), and an Au plating film is formed.
Pd + Au ⁺ → Pd ²⁺ + Au + e ⁻
e ⁻ (Acquired by oxidizing the components in the plating bath by the action of the Au autocatalyst) + Au ⁺ → Au

Through the above procedure, a high quality Ni-Pd-Au plating film is formed on the terminal portion of the outermost circuit of the printed wiring board, and there is no abnormal precipitation on the resin surface of the terminal region 7. Is secured.
By mounting a semiconductor element on the printed wiring board of the present invention manufactured by the above method, a semiconductor device with high connection reliability can be manufactured.

Hereinafter, the present invention will be described in more detail with reference to examples, but the present invention is not limited thereto.
(Create test piece)
A test piece (a substrate with a copper circuit) used in common in Examples and Comparative Examples to be described later was prepared by the following procedure.
(1) A surface treatment is performed with 5% hydrochloric acid on a 0.1 mm thick copper-clad laminate (MCL-E-679FG manufactured by Hitachi Chemical Co., Ltd.) with a 3 μm copper foil.
(2) A semi-additive dry film (UFG-255 manufactured by Asahi Kasei) is laminated on the copper foil surface of the copper clad laminate by a roll laminator.
(3) Exposure of the dry film in a predetermined pattern (parallel light exposure machine: EV-0800 manufactured by Ono Sokki, exposure condition: exposure amount 140 mJ), development (spray type apparatus, developer: 1% aqueous sodium carbonate solution, development (Time: 40 seconds). An electrolytic copper plating process is performed on the pattern-like exposed portion to form an electrolytic copper plating film having a thickness of 20 μm, and the dry film is peeled off (stripping solution: R-100, manufactured by Mitsubishi Gas Chemical, stripping time: 240 seconds).
(4) After peeling, the 3 μm copper foil seed layer is removed by flash etching (SAC process manufactured by Ebara Densan).
(5) Thereafter, circuit roughening treatment (roughening solution: CZ8101, manufactured by MEC Co., Ltd., 1 μm roughening condition) is performed, and a test piece having a copper circuit of line / space (L / S) = 70/30 μm It was created.

<Example 1>
After applying a solder resist (Taiyo Ink AUS703) to the copper circuit forming surface of the test piece obtained above by screen printing and drying, only the terminal forming part that is plated by the ENEPIG method is opened, and the copper-clad Exposure (parallel light exposure machine: EV-0800 manufactured by Ono Sokki, exposure condition: exposure amount 235 mJ), development (spray type device, developer: 1% sodium carbonate aqueous solution, development time so as not to expose the resin part of the laminate : 120 seconds), post-cure (150 ° C., 1 hour), post-exposure (EV-0800 manufactured by Ono Sokki, exposure condition: exposure 1000 mJ). Thereby, a circular opening having a diameter of 60 μm was formed at a predetermined position on the copper circuit.

The ENEPIG process common to Example 2 and Comparative Example 1 described later was performed on the opening by the following procedure.
(1) Cleaner treatment ACL-007 manufactured by Uemura Kogyo Co., Ltd. was used as a cleaner liquid, and the test piece was immersed in a cleaner liquid at a liquid temperature of 50 ° C. for 5 minutes and then washed with water three times.
(2) Soft Etching Treatment After the cleaner treatment, a mixed solution of sodium persulfate and sulfuric acid was used as a soft etching solution, the test piece was immersed in a soft etching solution at a liquid temperature of 25 ° C. for 1 minute, and then washed with water three times.
(3) Pickling treatment After the soft etching treatment, the test piece was immersed in sulfuric acid having a liquid temperature of 25 ° C. for 1 minute, and then washed with water three times.
(4) Pre-dip treatment After the pickling treatment, the test piece was immersed in sulfuric acid having a liquid temperature of 25 ° C. for 1 minute.
(5) Palladium catalyst provision process After pre-dip treatment, in order to provide a palladium catalyst to a terminal part, KAT-450 by Uemura Kogyo Co., Ltd. was used as a palladium catalyst provision liquid. The test piece was immersed in the palladium catalyst application solution at a liquid temperature of 25 ° C. for 2 minutes and then washed with water three times.
(6) Electroless Ni plating treatment After the palladium catalyst application step, the test piece was immersed in an electroless Ni plating bath (NPR-4 manufactured by Uemura Kogyo Co., Ltd.) at a liquid temperature of 80 ° C. for 35 minutes, and then washed three times with water. did.
(7) Electroless Pd plating treatment After the electroless Ni plating treatment, the test piece was immersed in an electroless Pd plating bath (TPD-30 manufactured by Uemura Kogyo Co., Ltd.) at a liquid temperature of 50 ° C. for 5 minutes, and then washed with water three times. did.
(8) Electroless Au plating treatment After the electroless Pd plating treatment, the test piece was immersed in an electroless Au plating bath (TWX-40 manufactured by Uemura Kogyo Co., Ltd.) at a liquid temperature of 80 ° C. for 30 minutes, and then washed with water three times. did.

<Example 2>
A thermosetting insulating layer (BLα3700GS manufactured by Sumitomo Bakelite Co., Ltd.) was laminated on the copper circuit formation surface of the test piece obtained above, and a thermosetting treatment (conditions 200 ° C., 1 hour) was performed. Only a terminal forming portion to be plated by the ENEPIG method is opened, and a UV-YAG laser having a wavelength of 355 nm (ML605LDX manufactured by Mitsubishi Electric, processing conditions: 40 μJ, 50 so that the resin portion of the copper-clad laminate is not exposed) Shot), a hole was formed in the thermosetting insulating layer, and desmear processing (Atotech Swelling Dip Securigant P process) was performed to form a circular opening with a diameter of 60 μm at a predetermined position on the copper circuit. . An ENEPIG process was performed on the opening in the same manner as in Example 1.

<Comparative Example 1>
Solder resist (Taiyo Ink AUS703) is applied on the copper circuit forming surface of the test piece by screen printing, dried, and then opened to include at least two terminal forming portions that are plated by the ENEPIG method. It processed like Example 1 except having exposed so that the resin part of a tension laminated board might be exposed.

  The following evaluation was performed about the test piece after the ENEPIG process obtained by each Example and the comparative example.

<Existence of abnormal precipitation>
The presence or absence of abnormal precipitation was confirmed by observing the terminals of the test pieces with a stereomicroscope.

<Presence / absence of short circuit>
The insulation check pad provided on the outer periphery of the test piece was checked for the presence or absence of short-circuit defects by a continuity tester (Hightester 1116 manufactured by HIOKI).

  The obtained results are shown in Table 1.

DESCRIPTION OF SYMBOLS 1 Printed wiring board 2 Core board | substrate 3 (3a, 3b, 3c, 3d) The upper surface side conductor circuit layer 4 (4a, 4b, 4c, 4d, 4e, 4f) Interlayer insulating layer 4c 'Support surface 4c''Insulating layer 5 (5a, 5b, 5c, 5d) Conductor layer 6 on the lower surface side Solder resist layer 6a Opening 6b Opening 7 Terminal area 7a Pad 7b Circuit in the vicinity of the pad 7c Pad 8 Nickel-palladium-gold plating layer 10 Semiconductor device DESCRIPTION OF SYMBOLS 11 Semiconductor element 12 Electrode pad 13 Die bond material hardening layer 14 Gold wire 15 Sealing material 16 Carrier film 17 Via hole 18 Electroless plating layer 19 Plating resist 20 Electrolytic plating layer

Claims (16)

A substrate with a gold-plated metal fine pattern,
On the support surface of the base material having a support surface made of resin, a solder resist layer is provided to cover the metal fine pattern and the region provided with the metal fine pattern,
The solder resist layer has an opening that exposes at least a part of the surface of the fine metal pattern, and the support surface is not exposed,
The exposed portion of the opening of the solder resist layer of the metal fine pattern is covered with a composite gold plating layer selected from the group consisting of a nickel-palladium-gold plating layer and a nickel-gold plating layer. Base material with metal fine pattern.   The substrate with a metal fine pattern according to claim 1, wherein a line and space (L / S) of a region having the composite gold plating layer of the metal fine pattern is 5/5 to 100/100 μm. A printed wiring board,
On the support surface of the printed wiring board substrate having a support surface made of a resin, a solder resist layer is provided to cover the conductor circuit and the region where the conductor circuit is provided,
The solder resist layer has an opening that exposes at least a part of the surface of the conductor circuit and does not expose the support surface;
The printed wiring, wherein the exposed portion of the opening of the solder resist layer of the conductor circuit is covered with a composite gold plating layer selected from the group consisting of a nickel-palladium-gold plating layer and a nickel-gold plating layer. Board.   The printed wiring board of Claim 3 whose line and space (L / S) of the area | region which has the composite gold plating layer of the said conductor circuit is 5 / 5-100 / 100 micrometers.   The printed wiring board according to claim 3 or 4, wherein the region having the composite gold plating layer of the conductor circuit is a region for forming a terminal.   6. A semiconductor device, wherein a semiconductor element is mounted on the printed wiring board according to claim 5, and a terminal of the printed wiring board and an input / output portion of the semiconductor element are connected by a peripheral arrangement. A method of manufacturing a substrate with a gold-plated metal fine pattern,
A step of preparing a substrate with a metal fine pattern having a metal fine pattern on a support surface made of a resin;
Performing a gold plating process selected from the group consisting of an electroless nickel-palladium-gold plating process and an electroless nickel-gold plating process on at least a part of the surface of the metal fine pattern, A method of manufacturing comprising:
The metal fine pattern forming surface of the substrate with the metal fine pattern is covered with a solder resist layer,
A solder resist layer existing on a predetermined region of the metal fine pattern is selectively removed to form an opening in which a part of the metal fine pattern is exposed and the support surface made of the resin is not exposed. ,
A method for producing a substrate with a gold-plated metal fine pattern, wherein the gold-plating process is performed on the metal fine pattern exposed in the opening.   The manufacturing method according to claim 7, wherein the solder resist layer is formed using a photosensitive solder resist, and the opening is formed by selectively removing a part of the solder resist layer by a photolithography process.   The manufacturing method of Claim 7 which forms the said opening part by irradiating a laser to the said soldering resist layer and selectively removing a part of soldering resist layer.   The manufacturing method according to any one of claims 7 to 9, wherein a line and space (L / S) of a region in which the metal fine pattern is subjected to gold plating is 5/5 to 100/100 µm. A method of manufacturing a printed wiring board,
Preparing a base material with a conductor circuit having a conductor circuit on a support surface made of a resin;
Performing a gold plating process selected from the group consisting of an electroless nickel-palladium-gold plating process and an electroless nickel-gold plating process on at least a part of the surface of the conductor circuit. And
The conductor circuit forming surface of the substrate with the conductor circuit is covered with a solder resist layer,
Selectively removing a solder resist layer present on a predetermined region of the conductor circuit to form an opening in which a part of the conductor circuit is exposed and the support surface made of the resin is not exposed;
A method of manufacturing a printed wiring board, wherein the gold plating process is performed on a conductor circuit exposed in the opening.   The manufacturing method according to claim 11, wherein the solder resist layer is formed using a photosensitive solder resist, and the openings are formed by selectively removing a part of the solder resist layer by a photolithography process.   The manufacturing method of Claim 11 which forms the said opening part by irradiating a laser to the said soldering resist layer and selectively removing a part of soldering resist layer.   The manufacturing method according to any one of claims 11 to 13, wherein a line and space (L / S) of a region in which the gold plating treatment of the conductor circuit is performed is 5/5 to 100/100 µm.   The manufacturing method according to claim 11, wherein the region having the composite gold plating layer of the conductor circuit is a region in which a terminal is formed.   A semiconductor element is mounted on the printed wiring board obtained by the manufacturing method according to any one of claims 11 to 15, and a terminal of the printed wiring board and an input / output portion of the semiconductor element are connected by a peripheral arrangement. A method for manufacturing a semiconductor device.

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