CN114190012A - Manufacturing method of chip carrier and chip carrier - Google Patents
Manufacturing method of chip carrier and chip carrier Download PDFInfo
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- CN114190012A CN114190012A CN202111476962.0A CN202111476962A CN114190012A CN 114190012 A CN114190012 A CN 114190012A CN 202111476962 A CN202111476962 A CN 202111476962A CN 114190012 A CN114190012 A CN 114190012A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/064—Photoresists
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
- H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/282—Applying non-metallic protective coatings for inhibiting the corrosion of the circuit, e.g. for preserving the solderability
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
The invention relates to a manufacturing method of a chip carrier plate and the chip carrier plate, comprising cutting a substrate; manufacturing an inner layer circuit, namely manufacturing the inner layer circuit on the substrate; the inner layer circuit manufacturing comprises the following steps: the grinding plate is used for roughening the surface of the substrate through brushing and micro-etching; sticking a film, namely sticking a dry film of 15-20 mu m on the substrate; exposing, namely exposing the substrate attached with the dry film, wherein the exposure energy is 80-90 mJ; developing, namely performing developing treatment on the exposed substrate through a developing solution to obtain an inner layer circuit pattern; etching, namely etching and removing a copper layer except the inner layer circuit pattern on the substrate, and removing the film to obtain the required inner layer circuit board, wherein the etching speed is 4-5 m/min; laminating, namely vacuumizing and pressing the inner layer circuit board and the single-side copper-clad plate of the prepreg into an integral circuit board; copper deposition, wherein copper deposition treatment is carried out on the integral circuit board; and manufacturing an outer layer circuit, namely manufacturing the outer layer circuit on the integral circuit board. The chip carrier plate manufactured by the method is thinner and has higher quality.
Description
Technical Field
The invention relates to the technical field of chip carrier board manufacturing, in particular to a chip carrier board manufacturing method and a chip carrier board.
Background
With the rapid growth of consumer electronics market and the wide application of very large scale integrated circuits, people have higher and higher requirements for the quality of visual hardware products and more comprehensive functions, and the size and the functions of modules become indexes which are primarily considered when consumers purchase electronic equipment. With the continuous development of mobile information technology, portable electronic devices are also being developed in the direction of light and thin, and meanwhile, there is a demand for light and thin chip carrier boards mounted on portable electronic devices, and some problems of corresponding manufacturing processes are also generated in the manufacturing process around the light and thin carrier boards.
Disclosure of Invention
In order to solve the problems associated with the manufacturing process of the light and thin chip carrier, the present invention provides a method for manufacturing a chip carrier for manufacturing a light and thin chip carrier, and a chip carrier, and provides corresponding solutions to some problems in the manufacturing process of the chip carrier, such as the black disc problem of the nickel layer, the improvement of the oxidation resistance and the conductive wire, the plating performance of the electroless palladium plating, and the stability of the plating solution.
According to an aspect of the present invention, there is provided a method for manufacturing a chip carrier, the method comprising:
cutting, namely cutting the substrate;
manufacturing an inner layer circuit, namely manufacturing the inner layer circuit on the substrate; the inner layer circuit manufacturing comprises the following steps:
grinding the surface of the substrate to coarsen by brushing and micro-etching;
sticking a film, namely sticking a dry film of 15-20 mu m on the substrate;
exposing, namely exposing the substrate attached with the dry film, wherein the exposure energy is 80-90 mJ;
developing, namely performing developing treatment on the exposed substrate through a developing solution to obtain an inner layer circuit pattern;
etching, namely etching and removing a copper layer except the inner layer circuit pattern on the substrate, and removing the film to obtain the required inner layer circuit board, wherein the etching speed is 4-5 m/min;
laminating, namely vacuumizing and pressing the inner layer circuit board and the single-side copper-clad plate of the prepreg into an integral circuit board;
copper deposition, wherein copper deposition treatment is carried out on the integral circuit board;
manufacturing an outer layer circuit, namely manufacturing the outer layer circuit on the integral circuit board; the outer layer circuit manufacturing comprises the following steps:
grinding the board, and roughening the surface of the whole circuit board;
sticking a film, namely sticking a dry film of 15-20 mu m on the integrated circuit board;
exposing, namely exposing the whole circuit board attached with the dry film, wherein the exposure energy is 80-90 millijoules;
developing, namely developing the exposed integral circuit board by using a developing solution to obtain an outer-layer circuit pattern;
performing outer layer solder mask, and performing solder mask treatment on the whole circuit board;
and (4) surface treatment, namely performing surface treatment on the whole circuit board.
As an embodiment of the present invention, the outer layer solder resist includes:
a first solder mask is attached to the integral circuit board;
arranging a first gold layer on the first solder mask;
a first metal palladium layer is arranged on the first gold layer in an attaching mode;
a first nickel layer is arranged on the first metal palladium layer;
a plurality of copper circuit layers and a plurality of dielectric layers are alternately attached to the first nickel layer;
arranging a second nickel layer on the copper circuit layer;
a second metal palladium layer is arranged on the second nickel layer;
a second gold layer is arranged on the second metal palladium layer;
and a second solder mask layer is arranged on the second gold layer.
As an embodiment of the present invention, the alternately attaching a plurality of copper circuit layers and a plurality of dielectric layers on the first nickel layer includes:
attaching a first copper circuit layer on the first nickel layer;
attaching a first dielectric layer on the first copper circuit layer;
attaching a second copper circuit layer on the first dielectric layer;
attaching a third dielectric layer on the second copper circuit layer;
and a fourth copper circuit layer is attached to the third dielectric layer.
As an embodiment of the present invention, an electroless gold plating process is used to dispose the first gold layer on the first solder resist, wherein a formula of the electroless gold plating solution is: HDQ-71 electroless gold plating solution 100mL/L, KAu (CN)21.5g/L, pH of the plating solution in the electroless gold plating process is 4.8, the temperature of the electroless gold plating process is 84 ℃, and the time of the electroless gold plating process is 20 min;
the method is characterized in that a first metal palladium layer is pasted on the first gold layer by using a chemical palladium plating process, wherein the chemical palladium plating solution comprises the following formula: tetraamminepalladium sulfate (Pd (NH)3)4SO4)0.005mol/L of reducing agent sodium hypophosphite (NaH)2PO2·H2O)0.01mol/L, complexing agent organic amine 0.1mol/L, glycine 0.08mol/L, stabilizer B0.3mol/L and stabilizer C1ppm, wherein the pH value of a plating solution in the chemical palladium plating process is 6.0 or 6.6 or 7.2 or 7.8, the temperature of the chemical palladium plating process is 45-60 ℃, and the time of the chemical palladium plating process is 15 min;
the first metal palladium layer is provided with a first nickel layer by using a chemical nickel plating process, wherein the chemical nickel plating solution comprises the following formula: 120mL/L, HDQ-209A of HDQ-209M electroless nickel plating solution, 45mL/L, HDQ-209D of electroless nickel plating solution, and 3mL/L of electroless nickel plating solution, wherein the pH value of the plating solution in the electroless nickel plating process is 4.7, the temperature of the electroless nickel plating process is 84 ℃, and the time of the electroless nickel plating process is 25 min.
As an embodiment of the present invention, the step of disposing the second nickel layer on the copper circuit layer uses an electroless nickel plating process, wherein the electroless nickel plating solution has a formula of: 120mL/L, HDQ-209A of HDQ-209M chemical nickel plating solution, 45mL/L, HDQ-209D of chemical nickel plating solution, and 3mL/L of chemical nickel plating solution, wherein the pH value of the plating solution in the chemical nickel plating process is 4.7, the temperature of the chemical nickel plating process is 84 ℃, and the time of the chemical nickel plating process is 25 min;
and arranging a second metal palladium layer on the second nickel layer by using a chemical palladium plating process, wherein the chemical palladium plating solution comprises the following formula: tetraamminepalladium sulfate (Pd (NH)3)4SO4)0.005mol/L of reducing agent sodium hypophosphite (NaH)2PO2·H2O)0.01mol/L, complexing agent organic amine 0.1mol/L, glycine 0.08mol/L, stabilizer B0.3mol/L and stabilizer C1ppm, wherein the pH value of a plating solution in the chemical palladium plating process is 6.0 or 6.6 or 7.2 or 7.8, the temperature of the chemical palladium plating process is 45-60 ℃, and the time of the chemical palladium plating process is 15 min;
and arranging a second gold layer on the second metal palladium layer by using an electroless gold plating process, wherein the formula of the electroless gold plating solution is as follows: the HDQ-71 electroless gold plating solution is 100mL/L, KAu (CN)21.5g/L, the pH of the solution in the electroless gold plating process is 4.8, the temperature in the electroless gold plating process is 84 ℃, and the time of the electroless gold plating process is 20 min.
As an embodiment of the present invention, in the step of manufacturing the outer layer circuit, the board grinding process includes:
aluminum powder grinding plate, in the aluminum powder grinding plate process, AL2O3Content of 15-25%, AL2O3The spraying pressure is 20-30PSI, and the plate grinding speed is as follows: 1.9-2 m/min.
As an embodiment of the present invention, the method for manufacturing a chip carrier further includes:
manufacturing characters, namely manufacturing characters on the integral circuit board; the step of character making is positioned between the step of outer layer circuit making and the step of surface treatment;
and (3) forming, namely putting a routing machine on the integral circuit board, routing a finished product according to the designed overall dimension, wherein the forming step is positioned after the surface treatment step.
As an embodiment of the invention, the substrate is a copper-clad plate.
As an embodiment of the present invention, the step of depositing copper includes the following steps performed in sequence: bulking, removing glue residues, pickling, pore-finishing, micro-etching, presoaking, activating, copper-depositing and drying.
According to another aspect of the present invention, a chip carrier is provided, wherein the chip carrier is manufactured by the method for manufacturing a chip carrier according to any one of the above embodiments.
The embodiment of the invention has the following beneficial effects:
1. in the manufacturing method of the chip carrier in this embodiment, since the thickness of the dry film is 15-20 μm in the inner layer circuit manufacturing process, after the subsequent exposure process and the development process, not only the conduction rate of the formed inner layer circuit pattern can be well ensured, but also the thickness of the formed inner layer circuit pattern can be made smaller, so that the thickness of the manufactured chip carrier can be made thinner. Since the thickness of the dry film is 15-20 μm, the exposure energy of the exposure machine needs to be adjusted to 80-90 mJ, and the dry film with the thickness of 15-20 μm can be fully exposed in this range without overexposure, so that the unexposed part of the dry film can be fully developed by the subsequent developing process. Setting the etching rate to 4-5m/min not only enables the etching process to be completed quickly, but also enables the portions to be removed completely. Finally, the quality of the manufactured chip carrier plate can be guaranteed on the premise of guaranteeing the production efficiency. Similarly, since the process steps and process parameters in the fabrication of the outer layer circuit are substantially the same as those in the fabrication of the inner layer circuit, the chip carrier manufactured by the method in this embodiment is thinner and has better quality.
2. Set up in this application, the dress facing of chip support plate is first resistance welding membrane to the face of weld in proper order, first gold layer, first metal palladium layer, first nickel layer, a plurality of copper line layers, a plurality of dielectric layers, the second nickel layer, second metal palladium layer, second gold layer and second resistance welding layer, not only the oxidation resistance is splendid through the chip support plate of making with above-mentioned technology, thereby electric conductive property has indirectly been improved, but also have many times welded performance and welded reliability, and have fine corrosion resisting property, can also prevent the problem of black dish from appearing in first nickel layer surface.
3. Through setting up three-layer dielectric layer and four layers of copper line layer in this application, press from both sides each dielectric layer respectively and establish between two copper line layers to can improve oxidation resistance and electric conductive property greatly.
4. The temperature of the chemical palladium plating process is in the range of 40-50 ℃, the surface of the chemical plating target presents a complete and defect-free state, the chemical palladium plating temperature is selected to be 40-50 ℃, the plating layer performance and the plating solution stability are guaranteed, the energy consumption is reduced, and meanwhile, when the pH value of the plating solution is in the range of 6.0-7.8, the surface of the plating layer presents a complete state and the corrosion to the plating layer is low.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic process flow diagram of a method for manufacturing a chip carrier according to an embodiment of the invention;
FIG. 2 is a schematic process flow diagram illustrating the fabrication of the inner layer circuit of FIG. 1;
FIG. 3 is a schematic process flow diagram for fabricating the outer layer circuit of FIG. 1;
fig. 4 is a process flow diagram of the outer layer solder resist of fig. 1.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1, an embodiment of the invention provides a method for manufacturing a chip carrier. The manufacturing method of the chip carrier in this embodiment includes:
and S110, cutting the substrate.
Specifically, the substrate is a copper-clad plate.
And S120, manufacturing an inner layer circuit, and manufacturing the inner layer circuit on the substrate.
Referring to fig. 2, in an embodiment, the step of fabricating the inner layer circuit includes the following steps:
and S121, grinding the plate, and roughening the surface of the substrate through brushing and micro-etching. After the surface of the substrate is roughened, the subsequent film pasting process can be conveniently carried out, and the success rate of the subsequent film pasting process can be improved.
Preferably, the oxide layer and the burrs on the surface of the substrate are removed by scrubbing with a scrubbing machine.
S122, pasting a film, namely pasting a dry film of 15-20 mu m on the substrate; when the thickness of the dry film is 15-20 μm, after the subsequent exposure process and the development process, the conductivity of the formed inner layer circuit pattern can be well ensured, and the circuit board with the line width and line distance in the range of 1.7/1.7-2.1/2.1mil can be met, so that the thickness of the formed inner layer circuit pattern can be smaller, and the thickness of the manufactured chip carrier plate can be thinner.
Preferably, the thickness of the dry film is 18 μm, and experiments prove that when the thickness of the dry film is 18 μm, the thickness of the chip carrier is smaller and the exposure effect is optimal under the condition that the conduction rate of the inner layer circuit pattern reaches the standard.
And S123, exposing, namely exposing the substrate attached with the dry film, wherein the exposure energy is 80-90 mJ. Since the thickness of the dry film is 15-20 μm, the exposure energy of the exposure machine needs to be adjusted to 80-90 mJ, and the dry film with the thickness of 15-20 μm can be fully exposed in this range without overexposure, so that the unexposed part of the dry film can be fully developed by the subsequent developing process.
Preferably, when the thickness of the dry film is 18 μm, the exposure energy of the exposure machine is adjusted to 85 mJ, at which time the exposure effect is optimal.
The optimum range of dry film thickness in the present application can be clearly understood by reference to the experimental data in the following table.
From the above table, when the thickness of the dry film is 15-20 μm, the line width and line distance are smaller, the thickness of the manufactured chip carrier is relatively thinner, and in this range, overexposure is not caused, so that the subsequent process steps are not affected, and the performance of the manufactured chip carrier is not affected.
S124, developing, namely performing developing treatment on the exposed substrate through a developing solution to obtain an inner layer circuit pattern; the unexposed portion of the dry film can be removed by a developing solution to obtain an inner layer circuit pattern.
Preferably, the developer is an aqueous sodium carbonate solution.
S125, etching, namely etching and removing the copper layer except the inner layer circuit pattern on the substrate, and removing the film to obtain the required inner layer circuit board, wherein the etching speed is 4-5 m/min; setting the etching rate to 4-5m/min not only enables the etching process to be completed quickly, but also enables the portions to be removed completely. Finally, the quality of the manufactured chip carrier plate can be guaranteed on the premise of guaranteeing the production efficiency.
Preferably, in the etching process, the concentration of Cu2 in the etching solution is controlled to be 135 +/-15 g/1, the concentration of C1 is controlled to be 5.3 +/-0.5N, the temperature is 50 +/-2 ℃, the pH value is 8.3 +/-0.4, the specific gravity is 1.185 +/-0.02, the etching speed is 4-5m/min, the etching frequency is 3 times, and the plate surface is overturned once after each etching.
In other embodiments, the etching may be performed by using a mixed solution of hydrochloric acid and hydrogen peroxide as an etching solution.
S130, laminating, namely vacuumizing and laminating the inner-layer circuit board and the one-side copper-clad plate of the prepreg to form an integral circuit board; the thickness of the manufactured chip carrier plate can be further reduced through lamination, so that the chip carrier plate is thinner and thinner.
And S140, copper deposition, wherein copper deposition treatment is carried out on the whole circuit board.
In one embodiment, the step of depositing copper S130 includes: the following steps are carried out in sequence: bulking, removing glue residues, pickling, pore-finishing, micro-etching, presoaking, activating, copper-depositing and drying.
S150, manufacturing an outer layer circuit, and manufacturing the outer layer circuit on the whole circuit board.
Referring to fig. 3, in an embodiment, the step of fabricating the outer layer circuit includes the following steps:
and S151, grinding the board, and roughening the surface of the whole circuit board. After the surface of the substrate is roughened, the subsequent film pasting process can be conveniently carried out, and the success rate of the subsequent film pasting process can be improved.
Preferably, the plate grinding process S151 is aluminum powder plate grinding, in which AL is2O3Content of 15-25%, AL2O3The spraying pressure is 20-30PSI, and the plate grinding speed is as follows: 1.9-2 m/min. The plate grinding process S151 is set as aluminum powder plate grinding, so that the brushing and grinding effect on the corners and burrs of the whole circuit board is better, and the subsequent film pasting is facilitated.
S152, sticking a film, namely sticking a dry film of 15-20 mu m on the integrated circuit board; when the thickness of the dry film is 15-20 μm, after the subsequent exposure process and the development process, the conductivity of the formed outer layer circuit pattern can be well ensured, and the thickness of the formed outer layer circuit pattern can be smaller, so that the thickness of the manufactured chip carrier plate can be thinner.
Preferably, the thickness of the dry film is 18 μm, and experiments prove that, when the thickness of the dry film is 18 μm, the thickness of the outer layer circuit pattern is also at a minimum under the condition that the conduction rate of the outer layer circuit pattern reaches the standard.
And S153, exposing, namely exposing the whole circuit board attached with the dry film, wherein the exposure energy is 80-90 mJ. Since the thickness of the dry film is 15-20 μm, the exposure energy of the exposure machine needs to be adjusted to 80-90 mJ, and the dry film with the thickness of 15-20 μm can be fully exposed in this range without overexposure, so that the unexposed part of the dry film can be fully developed by the subsequent developing process.
Preferably, when the thickness of the dry film is 18 μm, the exposure energy of the exposure machine is adjusted to 52 mJ, at which time the exposure effect is optimal.
S154, developing, namely performing developing treatment on the exposed substrate through a developing solution to obtain an outer layer circuit pattern; specifically, the unexposed portion of the dry film can be removed by a developer to obtain an outer layer circuit pattern.
Preferably, the developer is an aqueous sodium carbonate solution.
S160, outer layer resistance welding, wherein resistance welding treatment is carried out on the whole circuit board; the whole circuit board can be prevented from being oxidized before welding through the outer layer resistance welding.
Specifically, the outer layer solder resist may use an oxidation resistant material.
Referring to fig. 4, in an embodiment, the step S160 of outer layer solder mask includes the following steps:
s161, pasting a first solder mask layer on the integral circuit board;
s162, arranging a first gold layer on the first solder mask;
s163, attaching a first metal palladium layer on the first gold layer;
s164, arranging a first nickel layer on the first metal palladium layer;
s165, alternately attaching a plurality of copper circuit layers and a plurality of dielectric layers on the first nickel layer;
s166, arranging a second nickel layer on the copper circuit layer;
s167, arranging a second metal palladium layer on the second nickel layer;
s168, arranging a second gold layer on the second metal palladium layer;
and S169, a second solder mask layer is arranged on the second gold layer.
The chip carrier manufactured in step S160 by the outer layer solder mask sequentially includes a first solder mask, a first gold layer, a first palladium metal layer, a first nickel layer, a plurality of copper circuit layers, a plurality of dielectric layers, a second nickel layer, a second palladium metal layer, a second gold layer, and a second solder mask layer from the mounting surface to the soldering surface of the chip carrier. The chip carrier plate manufactured by the process has excellent oxidation resistance, indirectly improves the conductivity, has the performance of repeated welding and the reliability of welding, has good corrosion resistance, and can prevent the problem of black discs on the surface of the first nickel layer.
Further, the step S165 of alternately attaching the plurality of copper line layers and the plurality of dielectric layers on the first nickel layer includes:
attaching a first copper circuit layer on the first nickel layer;
attaching a first dielectric layer on the first copper circuit layer;
attaching a second copper circuit layer on the first dielectric layer;
attaching a third dielectric layer on the second copper circuit layer;
a fourth copper wiring layer is attached to the third dielectric layer.
In this embodiment, by providing three dielectric layers and four copper circuit layers, each dielectric layer is respectively sandwiched between two copper circuit layers, so that the oxidation resistance and the conductivity can be greatly improved.
Under the optimal process condition, the palladium layer has good performance, the influence on the nickel layer in gold plating can be reduced, and meanwhile, the palladium layer has the advantage of good corrosion resistance process and can be applied to the process production of the nickel-palladium-gold of the circuit board.
In a specific embodiment, the step S162 of disposing the first gold layer on the first solder resist uses an electroless gold plating process, wherein the formula of the electroless gold plating solution is as follows: the HDQ-71 electroless gold plating solution is 100mL/L, KAu (CN)21.5g/L, the pH of the solution in the electroless gold plating process is 4.8, the temperature in the electroless gold plating process is 84 ℃, and the time of the electroless gold plating process is 20 min. Because the pH of the plating solution of the electroless gold plating process is 4.8 and the temperature of the electroless gold plating process is 84 ℃, the electroless gold plating rate is highest, and the time of the electroless gold plating process is set to be 20min, the gold can be fully plated in the shortest time.
Step S163 of disposing a first palladium metal layer on the first gold layer uses a chemical palladium plating process, wherein the chemical palladium plating solution has a formula: tetraamminepalladium sulfate (Pd (NH)3)4SO4)0.005mol/L of reducing agent sodium hypophosphite (NaH)2PO2·H2O)0.01mol/L, complexing agent organic amine 0.1mol/L, glycine 0.08mol/L, stabilizer B0.3mol/L and stabilizer C1ppm, wherein the pH value of the plating solution of the chemical palladium plating process is 6.0 or 6.6 or 7.2 or 7.8, the temperature of the chemical palladium plating process is 45-60 ℃, and the time of the chemical palladium plating process is 15 min. When the pH value of the plating solution is in the range of 6.0-7.8, the surface of the plating layer presents a complete state, and meanwhile, the corrosion to the plating layer is low.
Preferably, the electroless palladium plating process has a temperature in the range of 40-50 ℃ and the surface of the electroless plating target exhibits a complete, defect-free state. The chemical palladium plating temperature is selected to be 40-50 ℃, thereby not only ensuring the plating layer performance and the plating solution stability, but also reducing the energy consumption.
Step S164 of providing a first nickel layer on the first palladium metal layer uses a chemical nickel plating process, wherein the chemical nickel plating solution has the following formula: 120mL/L, HDQ-209A of HDQ-209M electroless nickel plating solution, 45mL/L, HDQ-209D of electroless nickel plating solution, and 3mL/L of electroless nickel plating solution, wherein the pH value of the plating solution in the electroless nickel plating process is 4.7, the temperature of the electroless nickel plating process is 84 ℃, and the time of the electroless nickel plating process is 25 min.
In the embodiment, under the above process conditions, the palladium layer has good performance, and the influence on the nickel layer in gold plating can be reduced, and meanwhile, the method has the advantage of good corrosion resistance process.
In a specific embodiment, the step S166 of disposing a second nickel layer on the copper circuit layer uses an electroless nickel plating process, wherein the electroless nickel plating solution has a formula: 120mL/L, HDQ-209A of HDQ-209M electroless nickel plating solution, 45mL/L, HDQ-209D of electroless nickel plating solution, and 3mL/L of electroless nickel plating solution, wherein the pH value of the plating solution in the electroless nickel plating process is 4.7, the temperature of the electroless nickel plating process is 84 ℃, and the time of the electroless nickel plating process is 25 min.
Step S167 of disposing a second palladium layer on the second nickel layer uses an electroless palladium plating process, wherein the electroless palladium plating solution formula: tetraamminepalladium sulfate (Pd (NH)3)4SO4)0.005mol/L of reducing agent sodium hypophosphite (NaH)2PO2·H2O)0.01mol/L, complexing agent organic amine 0.1mol/L, glycine 0.08mol/L, stabilizer B0.3mol/L and stabilizer C1ppm, wherein the pH value of a plating solution in the chemical palladium plating process is 6.0 or 6.6 or 7.2 or 7.8, the temperature of the chemical palladium plating process is 45-60 ℃, and the time of the chemical palladium plating process is 15 min; when the pH value of the plating solution is in the range of 6.0-7.8, the surface of the plating layer presents a complete state, and meanwhile, the corrosion to the plating layer is low.
Preferably, the electroless palladium plating process has a temperature in the range of 40-50 ℃ and the surface of the electroless plating target exhibits a complete, defect-free state. The chemical palladium plating temperature is selected to be 40-50 ℃, thereby not only ensuring the plating layer performance and the plating solution stability, but also reducing the energy consumption.
In a specific embodiment, the step S168 of disposing a second gold layer on the second pd layer uses an electroless gold plating process, wherein the electroless gold plating solution has a formula: the HDQ-71 electroless gold plating solution is 100mL/L, KAu (CN)21.5g/L, the pH of the solution in the electroless gold plating process is 4.8, the temperature in the electroless gold plating process is 84 ℃, and the time of the electroless gold plating process is 20 min. Because the pH of the plating solution of the electroless gold plating process is 4.8 and the temperature of the electroless gold plating process is 84 ℃, the electroless gold plating rate is highest, and the time of the electroless gold plating process is set to be 20min, the gold can be fully plated in the shortest time.
In the embodiment, under the above process conditions, the palladium layer has good performance, and the influence on the nickel layer in gold plating can be reduced, and meanwhile, the method has the advantage of good corrosion resistance process.
S170, character manufacturing, and manufacturing characters on the whole circuit board.
And S180, surface treatment, namely, surface treatment is carried out on the whole circuit board.
And S190, forming, namely putting the integrated circuit board into a routing machine, and routing a finished product according to the designed overall dimension.
The invention also provides a chip carrier plate, which is manufactured by the manufacturing method of the chip carrier plate in any embodiment. The chip carrier manufactured by the manufacturing method of the chip carrier has thinner thickness and higher stability.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for manufacturing a chip carrier is characterized by comprising the following steps:
cutting, namely cutting the substrate;
manufacturing an inner layer circuit, namely manufacturing the inner layer circuit on the substrate; the inner layer circuit manufacturing comprises the following steps:
grinding the surface of the substrate to coarsen by brushing and micro-etching;
sticking a film, namely sticking a dry film of 15-20 mu m on the substrate;
exposing, namely exposing the substrate attached with the dry film, wherein the exposure energy is 80-90 mJ;
developing, namely performing developing treatment on the exposed substrate through a developing solution to obtain an inner layer circuit pattern;
etching, namely etching and removing a copper layer except the inner layer circuit pattern on the substrate, and removing the film to obtain the required inner layer circuit board, wherein the etching speed is 4-5 m/min;
laminating, namely vacuumizing and pressing the inner layer circuit board and the single-side copper-clad plate of the prepreg into an integral circuit board;
copper deposition, wherein copper deposition treatment is carried out on the integral circuit board;
manufacturing an outer layer circuit, namely manufacturing the outer layer circuit on the integral circuit board; the outer layer circuit manufacturing comprises the following steps:
grinding the board, and roughening the surface of the whole circuit board;
sticking a film, namely sticking a dry film of 15-20 mu m on the integrated circuit board;
exposing, namely exposing the whole circuit board attached with the dry film, wherein the exposure energy is 80-90 millijoules;
developing, namely developing the exposed integral circuit board by using a developing solution to obtain an outer-layer circuit pattern; performing outer layer solder mask, and performing solder mask treatment on the whole circuit board;
and (4) surface treatment, namely performing surface treatment on the whole circuit board.
2. The method for manufacturing a chip carrier board according to claim 1, wherein the outer layer solder mask comprises:
a first solder mask is attached to the integral circuit board;
arranging a first gold layer on the first solder mask;
a first metal palladium layer is arranged on the first gold layer in an attaching mode;
a first nickel layer is arranged on the first metal palladium layer;
a plurality of copper circuit layers and a plurality of dielectric layers are alternately attached to the first nickel layer;
arranging a second nickel layer on the copper circuit layer;
a second metal palladium layer is arranged on the second nickel layer;
a second gold layer is arranged on the second metal palladium layer;
and a second solder mask layer is arranged on the second gold layer.
3. The method of claim 2, wherein the alternately attaching a plurality of copper circuit layers and a plurality of dielectric layers on the first nickel layer comprises:
attaching a first copper circuit layer on the first nickel layer;
attaching a first dielectric layer on the first copper circuit layer;
attaching a second copper circuit layer on the first dielectric layer;
attaching a third dielectric layer on the second copper circuit layer;
and a fourth copper circuit layer is attached to the third dielectric layer.
4. The method for manufacturing a chip carrier according to claim 2, wherein the step of providing the first gold layer on the first solder mask uses an electroless gold plating process, wherein the electroless gold plating solution has a formula of: HDQ-71 electroless gold plating solution 100mL/L, KAu (CN)21.5g/L, pH of the plating solution in the electroless gold plating process is 4.8, the temperature of the electroless gold plating process is 84 ℃, and the time of the electroless gold plating process is 20 min;
the method is characterized in that a first metal palladium layer is pasted on the first gold layer by using a chemical palladium plating process, wherein the chemical palladium plating solution comprises the following formula: tetraamminepalladium sulfate (Pd (NH)3)4SO4)0.005mol/L of reducing agent sodium hypophosphite (NaH)2PO2·H2O)0.01mol/L, complexing agent organic amine 0.1mol/L, glycine 0.08mol/L, stabilizer B0.3mol/L and stabilizer C1ppm, wherein the pH value of a plating solution in the chemical palladium plating process is 6.0 or 6.6 or 7.2 or 7.8, the temperature of the chemical palladium plating process is 45-60 ℃, and the time of the chemical palladium plating process is 15 min;
the first metal palladium layer is provided with a first nickel layer by using a chemical nickel plating process, wherein the chemical nickel plating solution comprises the following formula: 120mL/L, HDQ-209A of HDQ-209M electroless nickel plating solution, 45mL/L, HDQ-209D of electroless nickel plating solution, and 3mL/L of electroless nickel plating solution, wherein the pH value of the plating solution in the electroless nickel plating process is 4.7, the temperature of the electroless nickel plating process is 84 ℃, and the time of the electroless nickel plating process is 25 min.
5. The method for manufacturing a chip carrier according to claim 2, wherein the step of providing the second nickel layer on the copper circuit layer uses an electroless nickel plating process, wherein the electroless nickel plating solution comprises the following formula: 120mL/L, HDQ-209A of HDQ-209M chemical nickel plating solution, 45mL/L, HDQ-209D of chemical nickel plating solution, and 3mL/L of chemical nickel plating solution, wherein the pH value of the plating solution in the chemical nickel plating process is 4.7, the temperature of the chemical nickel plating process is 84 ℃, and the time of the chemical nickel plating process is 25 min;
and arranging a second metal palladium layer on the second nickel layer by using a chemical palladium plating process, wherein the chemical palladium plating solution comprises the following formula: tetraamminepalladium sulfate (Pd (NH)3)4SO4)0.005mol/L of reducing agent sodium hypophosphite (NaH)2PO2·H2O)0.01mol/L, complexing agent organic amine 0.1mol/L, glycine 0.08mol/L, stabilizer B0.3mol/L and stabilizer C1ppm, wherein the pH value of a plating solution in the chemical palladium plating process is 6.0 or 6.6 or 7.2 or 7.8, the temperature of the chemical palladium plating process is 45-60 ℃, and the time of the chemical palladium plating process is 15 min;
and arranging a second gold layer on the second metal palladium layer by using an electroless gold plating process, wherein the formula of the electroless gold plating solution is as follows: the HDQ-71 electroless gold plating solution is 100mL/L, KAu (CN)21.5g/L, the pH of the solution in the electroless gold plating process is 4.8, the temperature in the electroless gold plating process is 84 ℃, and the time of the electroless gold plating process is 20 min.
6. The method for manufacturing a chip carrier according to claim 2, wherein in the step of fabricating the outer layer circuit, the board grinding process comprises:
aluminum powder grinding plate, in the aluminum powder grinding plate process, AL2O3Content of 15-25%, AL2O3The spraying pressure is 20-30PSI, and the plate grinding speed is as follows: 1.9-2 m/min.
7. The method of manufacturing a chip carrier according to claim 2, wherein the method further comprises:
manufacturing characters, namely manufacturing characters on the integral circuit board; the step of character making is positioned between the step of outer layer circuit making and the step of surface treatment;
and (3) forming, namely putting a routing machine on the integral circuit board, routing a finished product according to the designed overall dimension, wherein the forming step is positioned after the surface treatment step.
8. The method of claim 2, wherein the substrate is a copper-clad plate.
9. The method for manufacturing a chip carrier according to claim 2, wherein the step of copper deposition comprises the following steps performed in sequence: bulking, removing glue residues, pickling, pore-finishing, micro-etching, presoaking, activating, copper-depositing and drying.
10. A chip carrier, wherein the chip carrier is manufactured by the method for manufacturing a chip carrier according to any one of claims 1 to 9.
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