JP2000036662A - Manufacture of build-up multilayer interconnection board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a fine circuit conductor, by performing elimination until the circuit conductor of the circuit board of the inside is exposed at a place that becomes the via hole of a metal layer with a roughened surface, by eliminating the metal layer by etching, and by performing electroless plating onto the inner wall of a hole that becomes the via hole and the surface of the circuit board. SOLUTION: At a place that becomes a nickel layer 204 and a via hole 4 of an epoxy bonding layer 301, a circuit conductor 19 that is placed at a place being connected by the via hole 4 of a circuit board 1 of an inner layer is eliminated by carbon dioxide gas until the circuit conductor 19 is exposed. A smearing treatment is applied, and the nickel layer 204 on the surface of the first board is completely eliminated by etching. Catalyzation treatment is made onto the surface of the first board, and electroless copper plating is performed for forming a first plating copper 51, thus efficiently and economically manufacturing a multilayer interconnection board with a superior circuit formation property and excellent interlayer connection reliability without any problems.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for efficiently manufacturing a build-up multilayer wiring board having fine via holes and fine circuit conductors.

[0002]

2. Description of the Related Art In recent years, as electronic devices have become smaller, lighter, and more multifunctional, large-scale integrated circuits (hereinafter, referred to as LSIs) and chip components have been highly integrated. In order to increase the mounting density of electronic components on multilayer wiring boards,
There has been a growing demand for higher density wiring patterns. In order to meet this demand, thinning between layers, miniaturization of wiring, and reduction in diameter of interlayer connection holes have been performed, and interstitial via holes (hereinafter, referred to as “layers”) connecting only adjacent layers.
Called IVH. ) And buried via holes (hereinafter B
VH. ) Have been used, and the IVH and BVH have been further reduced in diameter.

[0003] In a multilayer wiring board, a plurality of circuit conductor layers and an insulating layer between the circuit conductor layers are usually piled together, laminated by heating and pressing, and holes are drilled at necessary places, and the inner walls of the holes are made of metal. An insulating layer is formed on a multilayer wiring board to be connected and formed, and a circuit conductor is formed on a substrate, holes are drilled at necessary places, inner walls of the holes are metallized, and circuit conductors are formed on the insulating layer, and so on. There is a build-up multilayer wiring board in which a circuit conductor layer and an insulating layer are sequentially formed.

[0004] As a method of manufacturing this build-up multilayer wiring board, an insulating layer of a thermosetting resin is formed on the surface of an inner layer circuit board having an inner layer circuit conductor and plated through holes formed therein, and a via hole is formed. The insulating layer is pierced by irradiating a laser beam, and the inside of the hole to be a via hole and the surface of the insulating layer are roughened with a roughening agent in order to enhance the adhesion with the plating performed in the next step, and the entire surface is plated. After that, a first method is known in which an etching resist is formed in a portion where plating is to be left, and a portion not covered with the etching resist is removed by etching to form a circuit conductor.

Further, an insulating layer of a thermosetting resin is formed on the surface of the inner layer circuit board having the inner layer circuit conductor and the plated through hole formed therein, and a laser beam is applied to a portion to be a via hole to form a hole in the insulating layer. Then, after roughening the inside of the hole serving as the via hole and the surface of the insulating layer with a roughening agent in order to increase the adhesion with plating performed in the next step, a plating resist is formed in a place where plating is not performed, A second method of forming a circuit conductor by plating is known.

Further, an insulating layer of a photocurable resin is formed on the surface of the inner layer circuit board having the inner layer circuit conductor and the plated through hole formed therein, and the portions other than the via holes are photocured, developed, and insulated. Drilling the layer, roughening the inside of the hole that will be the via hole and the surface of the insulating layer with a roughening agent to improve the adhesion with the plating performed in the next step, plating over the entire surface, and leaving the plating A third method is known in which an etching resist is formed on a substrate, and a portion not covered with the etching resist is removed by etching to form a circuit conductor.

Further, a metal foil with an insulating layer, which has been semi-cured by applying a resin to the roughened surface of the metal foil, is overlaid on the surface of the inner circuit board on which the inner circuit conductors and plated through holes are formed, and heated.・ After pressurizing and laminating and integrating, only the portions that will become via holes in the metal foil are etched and removed to form openings, and the openings are irradiated with laser light to make holes in the insulating layer and plated. A fourth method is known in which after the inside of a via hole is metallized, unnecessary metal is removed by etching to form a circuit conductor. According to this method, the adhesive strength between the resin insulating layer and the metal foil serving as the conductor circuit can be ensured without roughening the resin insulating layer with a roughening agent.

[0008]

Among the above conventional methods, the second method requires electroless plating performed in a high-temperature, high-alkaline atmosphere for forming a circuit, and the plating resist cannot withstand this. However, there is a problem that such a resin for a plating resist is not known at present.

In the first method, the second method, and the third method, the insulating layer needs to have a property of being roughened by a roughening agent to such an extent that the adhesion to plating performed in a subsequent step is enhanced. In addition, the degree of roughening must be controlled by a generally available chemical roughening agent. However, since there is no known resin composition in which both insulating properties and easy control of roughening are known, there is a resin composition in which a filler that is easily roughened is added and dispersed, and the insulating layer has insulating properties. It is necessary to use a method in which a layer and a layer that is easily roughened are used in combination, and when a resin composition in which a filler that is easily roughened is added and dispersed is used, in order to obtain high adhesion strength, When the particle diameter is increased, there is a problem that the interval between circuit conductors to be formed cannot be reduced, and when a layer having an insulating property and a layer that is easily roughened are used together as an insulating layer, the surface has a low insulating property. It is necessary to use a layer that is easily roughened, and in this case also, there is a problem that the interval between circuit conductors to be formed cannot be reduced.

In the fourth method, usually, in order to secure connection reliability, the plating thickness for connecting the inner layer circuit conductor and the surface circuit conductor needs to be 10 μm or more. By doing so, plating of the same thickness is also performed on the metal foil on the surface, and in order to form the circuit conductor formed on the surface, the thickness of the metal foil plus the plating thickness must be etched away. Therefore, there is a problem that it is difficult to form finer circuit conductors.

An object of the present invention is to provide a method of manufacturing a build-up multilayer wiring board which allows formation of fine circuit conductors and is excellent in insulation and connection reliability.

[0012]

A method of manufacturing a build-up multilayer wiring board according to the present invention includes the following steps. a. On a circuit board, a semi-cured insulating layer, an ultra-thin metal layer having a roughened surface, and a multilayer material including a copper layer as a carrier layer and a metal layer having different etching removal conditions from copper. A semi-cured insulation in contact with an ultra-thin metal layer of a multilayer material consisting of a copper layer as a carrier layer and an ultra-thin metal layer having a roughened surface and having different etching removal conditions from copper. A step of laminating the layers so that the semi-cured insulating layers are in contact with each other, and applying heat and pressure to laminate and integrate the layers. b. Removing only the carrier layer from the first substrate; d. A step of irradiating a portion of the ultrathin metal layer having a roughened surface to be a via hole with a laser beam until the circuit conductor of the internal circuit board is exposed. e. A step of etching and removing an extremely thin metal layer having a roughened surface. f. A step of performing electroless plating on the inner wall of the hole to be a via hole and the substrate surface. g. A step of forming a plating resist except for a portion to be a via hole and a portion to be a circuit conductor on the substrate surface. h. A step of electroplating a portion not covered with a plating resist. i. A step of removing the plating resist; j. A step of etching and removing the electroless plating under the removed plating resist.

The thickness of the metal layer having a roughened surface is 0.1 to
The thickness is preferably in the range of 10 μm, and copper is preferably used as the type of the metal layer.

Further, by using the build-up multilayer wiring board produced in the step j as a circuit board and repeating the steps a to j, further multilayering can be performed.

A material that does not contain reinforcing fibers, such as glass cloth, can be used for the semi-cured insulating layer.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Step a) In step a, any resin that can be drilled by a laser beam can be used for the semi-cured insulating layer. Glass cloth is used
A prepreg coated with a semi-curable resin can be used, and as the resin of the prepreg, an epoxy resin, a modified polyimide resin, a polyimide resin, a phenol resin, a bismaleimide triazine resin, or the like can be used. It is also possible to use a film-like insulating layer that does not contain such reinforcing fibers, such as the resin of the insulating layer,
Epoxy resin, modified polyimide resin, polyimide resin,
A phenol resin, a bismaleimide triazine resin, or the like can be used, and it is preferable because drilling with a laser beam becomes easy.

[0017] In the multilayer material comprising a metal layer having a roughened surface and a carrier layer used in the present invention, the carrier layer comprises:
Use copper.

Examples of the ultrathin metal layer having a rough surface, which is different from copper in etching removal conditions, include, for example, Ni, Sn, P
In addition to b, alloys such as Ni-P, Ni-B, and solder can be used, and more preferably those that can withstand roughening treatment. When Ni, Ni-P, Ni-
B or the like can be used.

This metal layer needs to have a certain thickness, and if it is too thick, the efficiency in the subsequent removal step may deteriorate or the material cost may increase. Since the roughened shape transferred to the resin insulating layer described later is easily damaged by the impact at the time, it is necessary to select a thickness in an optimal range by obtaining conditions in advance according to processing conditions, etc. Specifically, as an extremely thin metal layer, N
When i is used, the thickness is preferably 0.1 to 5 μm, and more preferably about 1 to 3 μm.

(Step b) The carrier layer can be removed from the multilayer material using a copper etchant, for example, copper chloride, iron chloride, alkaline etchant, ammonium persulfate, sulfuric acid-hydrogen peroxide, etc. General etching solution can be used, and commercially available etching solution SE
-07 (manufactured by Mitsubishi Gas Chemical Co., Ltd.) can be used. Etching methods include immersion in an etching solution,
This can be performed by spraying an etching solution.

(Step d) In order to remove the extremely thin metal layer having a roughened surface and the cured insulating layer thereunder by irradiating a laser beam until a circuit conductor to be connected to a circuit board is exposed, a CO2 laser is used. , An excimer laser, a UV laser, or the like can be used, and then the inside of the hole is preferably cleaned with an oxidizing roughening liquid such as permanganate.

(Step e) To remove a metal layer having a roughened surface, an example in which an extremely thin metal layer is made of Ni is shown below. Commercial products such as Merstrip N-950 (trade name, manufactured by Meltex Co., Ltd.) and nickel stripper BR (trade name, manufactured by McDermit Japan Co., Ltd.) can be used. In this case, when Ni has a thickness of 2 μm, the temperature is 20 μm.
The immersion time is 5 to 30 minutes at 80 ° C., and if the shower method is used, it can be removed more efficiently.

When the metal layer is removed, copper is not removed by etching, so that the conductor circuit on the circuit board at the bottom of the hole serving as the via hole is hardly damaged.

(Step f) The electroless plating which is performed on the inside of the hole serving as the via hole and on the surface of the insulating layer usually includes the electroless plating used as a pretreatment for the electroplating used in the manufacture of a printed wiring board. CUST201 (manufactured by Hitachi Chemical Co., Ltd., trade name), CUST2000
Commercial products such as (trade name, manufactured by Hitachi Chemical Co., Ltd.) can be used. The thickness of the plating may be a thickness that enables electroplating in the next step, and is preferably 0.01 μm or more, and 1 μm is sufficient for copper plating.

(Step g) of the surface subjected to the electroless plating,
In the step of forming a plating resist at a location other than a location of a hole to be a via hole and a location of a conductor circuit, the thickness of the plating resist to be formed is equal to or greater than the thickness of the conductor to be subsequently plated, and Is preferred.
Resins that can be used for the plating resist include, as photosensitive resins, liquid resists such as PMER P-LA900PM (trade name, manufactured by Tokyo Ohka Kogyo Co., Ltd.) and HW
425 (trade name, manufactured by Hitachi Chemical Co., Ltd.), RY-3
025 (trade name, manufactured by Hitachi Chemical Co., Ltd.) can be used.

(Step h) For the electroplating to be performed on the portion where the plating resist is not formed, copper sulfate electroplating or copper pyrophosphate electroplating usually used for a printed wiring board can be used. After plating the circuit conductor, the surface of the circuit conductor can be polished with a belt sander in order to make the circuit conductor uniform with the thickness of the resist because of the stabilization of characteristics and the ease of peeling of the resist. In this case, the thickness of the plating may be thicker than the plating resist.

(Step i) The plating resist can be removed by using an alkaline stripping solution, sulfuric acid or a commercially available resist stripping solution.

(Step j) To remove the electroless plating from the portion where the plating resist has been removed by etching, copper chloride,
The etching is performed in a short time with an etching solution such as iron chloride, an alkaline etching solution, ammonium persulfate, and sulfuric acid-hydrogen peroxide.

(Function) As described above, according to the present invention, since a conductor circuit is formed by copper electroplating after patterning with a photosensitive resin, fine wiring can be formed. Is used, when the metal layer is removed by etching, there is almost no etch-back of the inner layer copper, so that there is no problem in the inner layer connection reliability. Then, since the roughened shape of the metal layer is transferred to the insulating layer, it is not necessary to use a resin insulating layer having a special roughening property, and excellent circuit adhesion and insulating properties can be obtained. Further, since an extremely thin metal layer is present on the surface when drilling with a laser, a fine circuit can be formed without damaging the roughened surface during operation.

[0030]

Example 1 Step 1 Step a: A copper foil having a thickness of 18 μm is bonded on both sides to a thickness of 0.2 m.
MCL-E, an epoxy copper-clad laminate with a glass cloth base
Unnecessary copper foil of -679 (trade name, manufactured by Hitachi Chemical Co., Ltd.) was removed by etching, and the circuit conductor 19 was processed to produce the inner layer circuit board 1. An ultra-thin metal layer having a roughened surface and having a thickness of 30 μm as a multilayer material including a metal layer having different etching removal conditions from copper and a copper layer as a carrier layer.
m, electrolytic plating is performed on the electrolytic copper foil to deposit a bump-like plating, and further, electrolytic plating is performed to grow the bump-like plating, thereby forming a roughened surface, and forming the roughened surface on the roughened surface. ,
It was produced by performing electrolytic nickel plating. The thickness of the nickel was 2 μm, and the surface roughness of the rough nickel surface was a ten-point average roughness of 7.5 μm and a standard length of 2.5 mm. FIG. 1 (a)
As shown in the above, an epoxy resin in which a filler aluminum borate whisker used for MCF6000E (trade name, manufactured by Hitachi Chemical Co., Ltd.) is dispersed as a semi-cured insulating layer on the surface of the nickel layer of the multilayer material. An epoxy adhesive sheet with a multi-layer metal foil, in which a varnish is applied and dried to form a semi-cured epoxy adhesive layer 31, is applied to the adhesive layer 31.
Were laminated so as to be in contact with the circuit board 1, and were heated and pressed under a laminating condition of a temperature of 170 ° C., a time of 60 minutes and a molding pressure of 2.5 MPa to be laminated and integrated to form a first substrate 11. Step b As shown in FIG. 1 (b), an A process (manufactured by Meltex Co., Ltd.)
The carrier 203 of the first substrate 11 was removed by etching using (trade name) to leave a nickel layer 204 of 2 μm. Step d As shown in FIG. 1 (d), a portion of the nickel layer 204 and the cured epoxy adhesive layer 301 therebelow serving as the via hole 4 was subjected to a carbon dioxide gas laser at a frequency of 300 Hz, an output of 0.75 W, and pulse energy. Under the conditions of 2.5 mj and six shots, the circuit conductor 19 was removed until the circuit conductor 19 connected to the via hole 4 of the inner circuit board 1 was exposed. Step e Then, as shown in FIG. 1 (e), after performing a smear treatment with an aqueous solution of potassium permanganate, Melstrip N-950 (trade name, manufactured by Meltex Co., Ltd.) which is an etching solution for nickel was applied. The nickel layer 204 on the surface of the first substrate 11 was completely removed by etching. Step f As shown in FIG. 1 (f), the surface of the first substrate 11 is catalyzed, and CUST-201 (trade name, manufactured by Hitachi Chemical Co., Ltd.) is used. Under the condition of 30 minutes, electroless copper plating was performed to form first plated copper 51 having a thickness of 1 μm. Step g Next, as shown in FIG. 1 (g), a dry film for photoresist, Photek H-W425 (trade name, manufactured by Hitachi Chemical Co., Ltd.) was applied to the first plating of the first substrate 11. Laminated on the surface of the copper 51, and exposed to ultraviolet light through a photomask masking the portion to be electroplated,
By developing, a plating resist 6 was formed. Step h Next, as shown in FIG.
m, circuit conductor width / circuit conductor interval (L / S) = 5
The thickness of the second plated copper 71 is set to be 0 μm / 50 μm.
Was formed in the shape of a circuit. Step i As shown in FIG. 1 (i), 3% by weight of plating resist 6
And dissolved with sodium hydrogen carbonate solution. Step j Next, as shown in FIG. 1 (j), the plating resist 6 is immersed in an A process solution (trade name, manufactured by Meltex Co., Ltd.) which is an ammonium-based alkali copper etching solution at room temperature for 1 minute. The first plated copper 51 formed below was removed by etching.

Example 2 Step a: A copper foil having a thickness of 18 μm is bonded on both sides to a thickness of 0.2 m.
MCL-E, an epoxy copper-clad laminate with a glass cloth base
Unnecessary copper foil of -679 (trade name, manufactured by Hitachi Chemical Co., Ltd.) was removed by etching to process the circuit conductor 19, thereby producing the inner layer circuit board 1. Next, as shown in FIG. 2A, AS3000 which is an epoxy film 32 having a thickness of 40 μm as a semi-cured insulating layer is formed on both sides of the circuit board.
(Hitachi Kasei Kogyo Co., Ltd., trade name) and a very thin metal layer with a roughened surface, which has different etching removal conditions from copper, and a multilayer material consisting of a copper layer as a carrier layer, Copper foil Ni with roughened nickel comprising a nickel layer 204 having a thickness of 1 μm and a copper foil carrier 203 having a thickness of 35 μm
MT-CF35 (trade name, manufactured by Fukuda Metal Foil & Powder Industry Co., Ltd.) is superposed so that the roughened surface of the nickel layer 204 is in contact with the epoxy film 32, at a temperature of 170 ° C., for a time of 60 minutes, and at a molding pressure of 4.0 MPa. The first substrate 11 was formed by laminating and integrating by heating and pressing. Step b As shown in FIG. 2 (b), after lamination and integration, the first substrate 11 is processed using an A-process (trade name, manufactured by Meltex Co., Ltd.) which is an ammonium-based alkali etching solution.
Was removed by etching to leave a 1 μm nickel layer 204. Step d As shown in FIG. 2 (d), a portion of the nickel layer 204 and the cured epoxy film 302 under the nickel layer 204, which becomes the via hole 4, was subjected to a carbon dioxide gas laser at a frequency of 300 Hz, an output of 0.75 W, and a pulse energy of 2. Under the conditions of 0.5 mj and six shots, the circuit conductor 19 was removed until the circuit conductor 19 connected to the via hole 4 of the inner circuit board 1 was exposed.
Thereafter, the same procedure as in Example 1 was performed.

Example 3 Step a: A copper foil having a thickness of 18 μm is bonded on both sides to a thickness of 0.2 m.
MCL-E, an epoxy copper-clad laminate with a glass cloth base
Unnecessary portions of -679 (trade name, manufactured by Hitachi Chemical Co., Ltd.) were etched away to remove the copper foil, and the circuit conductor 19 was processed to produce the inner layer circuit board 1. Next, as shown in FIG. 3A, on both sides of the circuit board 1, as a semi-cured insulating layer, GEA-679 (Hitachi, a prepreg 33 made of glass cloth epoxy resin having a thickness of 0.1 mm) is used. 1 μm thick as a multi-layered material consisting of a metal layer having a roughened surface and having a different etching removal condition from copper, and a copper layer serving as a carrier layer. Nickel layer 204, 35 μm thick copper foil carrier 203
Copper foil NiMT-CF35 (trade name, manufactured by Fukuda Metal Foil & Powder Co., Ltd.) made of
The first substrate 11 was laminated by laminating the roughened surface of No. 04 such that the roughened surface was in contact with the prepreg 33, and heated and pressed under the conditions of a temperature of 170 ° C., a time of 60 minutes and a molding pressure of 4.0 MPa. Step b As shown in FIG. 3 (b), after laminating and integrating, the first substrate 11 is processed using an A-process (trade name, manufactured by Meltex Co., Ltd.) which is an ammonium-based alkali etching solution.
Was removed by etching to leave a 1 μm nickel layer 204. Step d As shown in FIG. 3D, a portion of the nickel layer 204 and the hardened prepreg 303 under the nickel layer 204 that becomes the via hole 4 was subjected to a carbon dioxide gas laser at a frequency of 300 Hz and an output of 0.1 mm.
Under the conditions of 75 W, pulse energy of 2.5 mj, and six shots, the circuit conductor 19 at the portion connected by the via hole 4 of the inner circuit board 1 was removed until the circuit conductor 19 was exposed. Thereafter, the same procedure as in Example 1 was performed.

COMPARATIVE EXAMPLE 1 Step a: A copper foil having a thickness of 18 μm is bonded on both sides to a thickness of 0.2 m.
MCL-E, an epoxy copper-clad laminate with a glass cloth base
-679 (trade name, manufactured by Hitachi Chemical Co., Ltd.), unnecessary copper foil was removed by etching, and the circuit conductor 19 was processed to produce the inner layer circuit board 1. As shown in FIG. NDGR-18, which is a copper foil 21 having a thickness of 18 μm roughened by oxidizing one surface as a metal layer having a textured surface.
(Trade name, manufactured by Nippon Electrolysis Co., Ltd.)
As a semi-cured insulating layer, AS3000 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is an epoxy film 32 having a thickness of 40 μm, is used as a semi-cured insulating layer.
Were laminated so as to be in contact with the circuit board 1, and were heated and pressed under a laminating condition of a temperature of 170 ° C., a time of 60 minutes and a molding pressure of 4.0 MPa to be laminated and integrated to form a first substrate 11. Step B1 As shown in FIG. 4 (B1), after lamination and integration, the copper foil 21 was entirely removed by etching using a copper chloride etching solution. Step D1 As shown in FIG. 4 (D1), the cured epoxy film 302 at the portion to be the via hole 4 of the first substrate 11 from which all the copper foil 21 has been removed by etching is subjected to carbon dioxide gas laser at a frequency of 300 Hz and an output of 0 Under the conditions of 0.75 W, pulse energy of 2.5 mj, and six shots, the circuit conductor 19 at a location connected by the via hole 4 of the inner circuit board 1
Was removed until exposed. Step F1 As shown in FIG. 4 (F1), the first substrate 11 from which the copper foil 21 has been entirely removed by etching is immersed in an aqueous solution of potassium permanganate to perform a smearing treatment, and then a catalyzing treatment is performed. Using CUST-201 (trade name, manufactured by Hitachi Chemical Co., Ltd.), electroless copper plating was performed at a liquid temperature of 25 ° C. for 30 minutes to form third plated copper 52 having a thickness of 1 μm. Step g Next, as shown in FIG. 4G, phototech H-W425 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a dry film for photoresist, is laminated on the first substrate 11, and UV light is exposed and developed through a photomask that masks a portion where plating is to be performed.
Was formed. Step h Next, as shown in FIG.
m, circuit conductor width / circuit conductor interval (L / S) = 5
The circuit conductor was formed so as to be 0 μm / 50 μm. Step i As shown in FIG. 4 (i), the plating resist 6 is 3% by weight.
And dissolved with sodium hydrogen carbonate solution. Step j Next, as shown in FIG. 4 (j), the plating resist 6 was immersed in an A process solution (trade name, manufactured by Meltex Co., Ltd.) which is an ammonium-based alkali copper etching solution at room temperature for 1 minute. The third plated copper 52 formed below was removed by etching.

Comparative Example 2 Step a: A copper foil having a thickness of 18 μm is bonded to both sides and has a thickness of 0.2 m.
MCL-E, an epoxy copper-clad laminate with a glass cloth base
Unnecessary portions of -679 (trade name, manufactured by Hitachi Chemical Co., Ltd.) were etched away to remove the copper foil, and the circuit conductor 19 was processed to produce the inner layer circuit board 1. Next, as shown in FIG. 5A, a 40 μm-thick epoxy film 32 is formed on both sides of the circuit board 1 as a semi-cured insulating layer.
Using S3000 (trade name, manufactured by Hitachi Chemical Co., Ltd.), as an epoxy film 32 and a metal layer having a roughened surface, NDGR which is an 18 μm thick copper foil 21 roughened by oxidizing one surface. -18 (manufactured by Nippon Electrolysis Co., Ltd.
(Trade name) in this order and with the roughened surface of the copper foil 21 in contact with the epoxy film 32 at a temperature of 170 ° C.
Heating for 60 minutes at a molding pressure of 4.0 MPa
The first substrate 11 was formed by pressing and laminating and integrating. Step C2 Next, as shown in FIG. 5 (C2), phototech H-W425 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a dry film for a photoresist, is laminated on the first substrate 11, and the vias are formed. UV light is exposed through a photomask in which a mask pattern is formed in a portion to be the hole 4 and developed to form an etching resist, and an ammonium-based alkali copper etching solution, A process (trade name, manufactured by Meltex Co., Ltd.) Was sprayed, and the copper foil 21 was removed by etching only in the portion to be the via hole 4 to form the opening 41. Step D2 As shown in FIG. 5 (D2), after the etching resist is removed by dissolving with a 3% by weight sodium hydrogen carbonate solution, the cured epoxy film 302 which is a cured insulating layer exposed to the opening 41 is removed. , CO2 laser, frequency 300Hz, output 0.75W, pulse energy 2.
Under the conditions of 5 mj and six shots, the circuit conductor 19 was removed until the circuit conductor 19 connected to the via hole 4 of the inner circuit board 1 was exposed. Step E2 Thereafter, as shown in FIG. 5 (E2), after performing a smear treatment with an aqueous solution of potassium permanganate, the copper foil 21 on the surface of the first substrate 11 is entirely etched using a copper chloride etching solution. Removed. Step f As shown in FIG. 5 (f), the surface of the first substrate 11 is catalyzed, and CUST-201 (trade name, manufactured by Hitachi Chemical Co., Ltd.) is used. Under the condition of 30 minutes, electroless copper plating was performed to form third plated copper 52 having a thickness of 1 μm. Step g Next, as shown in FIG. 5 (g), phototech H-W425 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a dry film for photoresist, is laminated on the first substrate 11, and UV light is exposed and developed through a photomask that masks a portion where plating is to be performed.
Was formed. Step h Next, as shown in FIG.
m, circuit conductor width / circuit conductor interval (L / S) = 5
The fourth plated copper 72 was formed in a circuit shape so as to be 0 μm / 50 μm. Step i As shown in FIG. 5 (i), 3% by weight of plating resist 6
And dissolved with sodium hydrogen carbonate solution. Step j Next, as shown in FIG. 5 (j), the plating resist 6 is immersed in an A process solution (trade name, manufactured by Meltex Co., Ltd.) which is an ammonium-based alkali copper etching solution at room temperature for 1 minute. The fourth plated copper 72 formed below was removed by etching.

(Hot Oil Test) As described above,
After producing the build-up multilayer wiring board, a hot oil test was performed to evaluate the connection reliability between layers. In this hot oil test, 260 ° C. for 10 seconds / room temperature
As a cycle, the resistance increase rate was measured every 10 cycles, and the number of cycles at which the resistance increase rate was 10% or more was examined. Table 1 shows the results. (Circuit defect occurrence rate) In addition, L / S
= 50/50 μm to check the formation state of the conductor circuit,
Using an automatic inspection device, the occurrence rate of circuit defects such as disconnection, short circuit, and dent was determined. A circuit defect is defined as a defect in which a portion where the width of the conductor is reduced to 2/3 or less of the design value is longer than the length of the conductor width.
Defects are those where the portion narrowed to 3 or less is longer than the length of the conductor width, and the sum of the area of the defective portion to the circuit area of the design value was calculated as a ratio. Table 1 shows the results.

In the case of Comparative Example 1, the hot oil test was 5
Although there was no problem even with 0 cycles or more, the incidence of surface circuit defects was 5%, and there was a problem in circuit formability. In the case of Comparative Example 2, in the hot oil test, the resistance increase rate reached 10% in 10 cycles, and the connection reliability was insufficient.
When the cross section of the via hole was observed, negative etchback was observed in the inner layer copper. From the above results, it was found that the multilayer wiring board according to the present invention was excellent in circuit formability and also had sufficient interlayer connection reliability.

[0037]

[Table 1]

[0038]

As described above, the present invention makes it possible to efficiently and economically manufacture a multilayer wiring board which is excellent in circuit formability and has no problem in the reliability of interlayer connection as compared with the conventional method. Can provide a way to

[Brief description of the drawings]

1 (a), 1 (b), 1 (d) to 1 (j) are cross-sectional views in respective steps showing one embodiment of the present invention.

2 (a), 2 (b) and 2 (d) are cross-sectional views in a process showing another embodiment of the present invention.

FIGS. 3 (a), (b) and (d) are cross-sectional views in a process showing still another embodiment of the present invention.

FIG. 4 (a), (B1), (D1), (F1),
(G)-(j) is sectional drawing in each process which shows a prior art example.

FIG. 5 (a), (C2), (D2), (E2),
(F)-(j) is sectional drawing in each process which shows another conventional example.

[Explanation of symbols]

 1. Circuit board 11. First substrate 19. Circuit conductor 21. Copper foil 203. Carrier 204. Nickel layer 31. Epoxy adhesive layer 301. Cured epoxy adhesive layer 32. Epoxy film 302. Cured epoxy film 33. Prepreg 303. 3. cured prepreg Via hole 41. Opening 51. First plated copper 52. Third plated copper 6. Plating resist 71. Second plated copper 72. Fourth plated copper

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor, Toyoki Ito, 1500 Ogawa, Oji, Shimodate, Ibaraki Prefecture Inside Shimodate Research Laboratory, Hitachi Chemical Co., Ltd. (72) Masao Sugano, 1500 Ogawa, Oji, Shimodate, Ibaraki Hitachi, Ltd. Inside Shimodate Research Laboratory (72) Inventor Eita Shinada 1500 Oji Ogawa, Shimodate City, Ibaraki Pref.Hitachi Chemical Industry Co., Ltd. In-house (72) Inventor Akishi Nakaso 48 Wadai, Tsukuba-shi, Ibaraki Pref.Hitachi Chemical Industry Co., Ltd.Tsukuba Development Laboratory Co., Ltd. Terms (reference) 5E346 AA02 AA06 AA12 AA15 AA43 BB01 CC08 CC09 CC10 CC13 CC31 CC32 CC58 CC60 DD02 DD23 DD24 DD25 DD33 DD47 EE02 EE06 EE07 EE33 EE38 EE39 FF13 FF14 FF15 GG01 GG15 GG17 GG22 GG23 GG28 HH07 HH08 HH26

Claims (5)

[Claims] 1. A method for manufacturing a build-up multilayer wiring board, comprising the following steps. a. On a circuit board, a semi-cured insulating layer, an ultra-thin metal layer having a roughened surface, and a multilayer material including a copper layer as a carrier layer and a metal layer having different etching removal conditions from copper. A semi-cured insulation in contact with an ultra-thin metal layer of a multilayer material consisting of a copper layer as a carrier layer and an ultra-thin metal layer having a roughened surface and having different etching removal conditions from copper. A step of laminating the layers so that the semi-cured insulating layers are in contact with each other, and applying heat and pressure to laminate and integrate the layers. b. Removing only the carrier layer from the first substrate; d. A step of irradiating a portion of the via hole with a laser beam until the circuit conductor of the internal circuit board is exposed. e. A step of etching and removing an extremely thin metal layer having a roughened surface. f. A step of performing electroless plating on the inner wall of the hole to be a via hole and the substrate surface. g. A step of forming a plating resist except for a portion to be a via hole and a portion to be a circuit conductor on the substrate surface. h. A step of electroplating a portion not covered with a plating resist. i. A step of removing the plating resist; j. A step of etching and removing the electroless plating under the removed plating resist. 2. The metal layer having a roughened surface has a thickness of 0.1 to
2. The method according to claim 1, wherein a metal layer having a thickness of 5 [mu] m is used. 3. The method for producing a build-up multilayer wiring board according to claim 1, wherein copper is used for the metal layer having a roughened surface. 4. The build-up according to claim 1, wherein the build-up multilayer wiring board produced in the step j is used as a circuit board, and the steps a to j are repeated. A method for manufacturing a multilayer wiring board. 5. The method according to claim 1, wherein a material containing no reinforcing fibers such as glass cloth is used as the semi-cured insulating layer. .