JP4593009B2 - Method for manufacturing printed circuit board - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a built-up type printed circuit board, and more particularly to a method for manufacturing a printed circuit board suitable for forming a thin film capacitor having good characteristics.
[0002]
[Prior art]
In recent years, in response to the miniaturization of electronic devices, built-up type printed circuit boards are generally used in the area of the mother board among the printed circuit boards built in the devices. In these printed circuit boards, it is required to reduce the mounting area in order to achieve higher density, and as a result, a technique for embedding the mounted parts in the printed circuit board has been developed. Thin film resistors and thin film capacitors have been used instead of the chip resistors and chip capacitors.
[0003]
A method of forming a thin film capacitor (hereinafter also referred to as a capacitor) having a good capacitance value is disclosed in, for example, Japanese Patent Application Laid-Open No. 2001-15928, and the outline thereof will be described below.
[0004]
FIG. 3 is a diagram showing a part of the process of the conventional printed circuit board manufacturing method.
First, as shown in FIG. 3 (1), a copper foil on a substrate 1 made of an insulating resin is processed to form a circuit pattern 2 having a predetermined shape, and this circuit pattern 2 is covered, for example, by screen printing. Thus, the insulating layer 3 made of an epoxy resin is formed, or a sheet material having a predetermined thickness mainly composed of an epoxy resin or a polyolefin resin is thermocompression bonded by a vacuum laminating method to form the insulating layer 3.
[0005]
Next, as shown in (2) of FIG. 3, a via hole 4 having a predetermined shape is formed by irradiating, for example, carbon dioxide laser light or YAG laser light on the insulating layer 3 where the capacitor on the circuit pattern 2 is to be formed. Form.
Next, as shown in FIG. 3 (3), the paste material 5 obtained by dispersing a filler made of, for example, barium titanate having a high dielectric constant in an epoxy resin is sufficiently embedded in the via hole 4 by screen printing. Alternatively, a predetermined amount is sufficiently injected into the via hole 4 with a dispenser, and then dried and cured at about 150 ° C. to 180 ° C.
[0006]
Next, as shown in (4) of FIG. 3, the paste material 5 protruding from the via hole 4 is removed by polishing, and the thickness of the paste material 5 is set to a predetermined thickness. At this time, the polishing surface 5a of the insulating layer 5 and the polishing surface 3a of the paste material 5 have a predetermined roughness.
Next, as shown in (5) of FIG. 3, a copper plating layer 6 having a predetermined thickness and shape is formed, whereby the paste material 5 sandwiched between the circuit pattern 2 and the plating layer 6 becomes a capacitor (capacitor). ).
[0007]
[Problems to be solved by the invention]
Incidentally, as described above, to accurately set Teisu because the capacitance value of the capacitor, it is necessary to precisely control the thickness of the paste material. However, unnecessary parts of the paste material are removed by polishing, but the insulating layer around the paste material is composed of the same resin as the paste material, and is polished in the same manner as the paste material. Since there is no means for detecting the end point of polishing, the paste material and the insulating layer are excessively polished, and as a result, it is difficult to precisely control the thickness of the paste material, and the capacitance value of the capacitor There was a problem that could not be set correctly.
[0008]
Therefore, the present invention solves the above-described problem, and in the method of manufacturing a printed circuit board, allows the thickness of the paste material constituting the thin film capacitor to be easily controlled, and thereby the printed circuit board having a thin film capacitor having an accurate capacitance value. It aims at providing the manufacturing method which manufactures.
[0009]
[Means for Solving the Problems]
As means for achieving the above object, the present invention includes an insulating substrate (11) a circuit pattern on a (12a, 22a) and the resin insulating layer (13) laminated alternately, the circuit pattern (12a, 22a) Forming a first circuit pattern ( 12a ) on the insulating substrate ( 11 ) in a manufacturing method of a printed circuit board in which build-up wiring is formed with via holes ( 17 ) connected therebetween; and the first circuit covering the pattern (12a), the activity forming a predetermined thickness of the resin insulating layer (13), the resin insulating layer by reactive ion etching or reverse sputtering using Ar gas the surface of (13) And a metal layer (stopper layer) ( 1) formed on the surface of the resin insulation layer ( 13 ) after the activation treatment step by sputtering. 6 ) and a via hole ( 14 ) reaching the first circuit pattern ( 12a ) from the surface of the metal layer ( 16 ) in the metal layer ( 16 ) and the resin insulating layer ( 13 ). And filling the via hole ( 14 ) with a paste material ( 15 ) made of a resin containing a filler having a high dielectric constant so as to protrude from the via hole ( 14 ) so as to form a protruding portion ( 15b ) , as a stopper layer for polishing a metal layer (16), removing by polishing the protruding portion (15b), after removing the metal layer (16), the second covering the paste material to (15a) And a step of forming a circuit pattern ( 22b ) . Reference numerals in parentheses are given for the sake of clarity of correspondence with the description of embodiments of the invention described later.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings by way of preferred examples.
[0011]
<Example>
FIG. 1 is a diagram showing a part of a process of a printed circuit board manufacturing method according to an embodiment of the present invention.
FIG. 2 is a diagram showing a part of the process of the printed circuit board manufacturing method according to the embodiment of the present invention.
[0012]
First, as shown in FIG. 1 (1), a copper foil is processed into a predetermined shape using a so-called copper-clad laminate in which copper foil is formed on both surfaces of a substrate 11 made of an insulating resin. The circuit patterns 12a and 12c are formed on the upper surface of the circuit 11, and the circuit pattern 12b is formed on the lower surface. If necessary, a through hole 18 is formed in the substrate 11, a copper electroless plating layer 20 and an electrolytic plating layer 20 ′ are formed on the inner wall of the through hole 18, and a non-conductive filler 19 is filled in the through hole 18. For example, the circuit pattern 12c and the circuit pattern 12b are electrically connected.
[0013]
Next, as shown in (2) of FIG. 1, the printing ink (for example, Taiyo Ink Co., Ltd.) which has an epoxy resin as a main component is coated on the substrate 11 by a screen printing method so as to cover the circuit patterns 12a and 12c. An insulating layer 13 made of L1 ink) or a sheet material mainly composed of an epoxy resin (for example, an SH material sheet manufactured by Ajinomoto Co., Inc.) is thermocompression bonded by a vacuum laminating method to form the insulating layer 13 Form. Thereafter, the insulating layer 13 is dried and cured by holding in a heat drying oven set at 150 ° C. to 170 ° C. for 30 minutes to 1 hour. Next, after activating the surface of the insulating layer 13 by RIE (reactive ion etching) using Ar gas or by reverse sputtering, a thickness of 0.1 μm or more is obtained by DC sputtering. A stopper film 16 made of a Cr or Ni film is formed.
[0014]
The RIE conditions are, for example, an Ar gas pressure of 30 mTorr to 100 mTorr, an RF power of 100 W, a parallel plate distance of 30 mm to 50 mm, and a processing time of 5 minutes to 10 minutes. The conditions for reverse sputtering are, for example, that the Ar gas pressure is 30 mTorr to 100 mTorr, the RF power is 100 W, and the processing time is 5 minutes to 10 minutes. The DC sputtering conditions are, for example, an Ar gas pressure of 20 mTorr to 30 mTorr, a DC power of 200 W to 400 W, a substrate-electrode distance of 30 mm to 50 mm, and a deposition rate of 5 angstrom / second to 10 angstrom / second. .
[0015]
Next, as shown in (3) of FIG. 1, a via hole 14 having a predetermined size reaching the circuit pattern 12a through the stopper film 16 and the insulating layer 13 at the position where the capacitor is to be formed is formed by a carbon dioxide laser or It is formed using a YAG laser.
Next, as shown in FIG. 1 (4), a dielectric paste material 15 (for example, manufactured by Asahi Kaken Co., Ltd.) made of an epoxy resin containing barium titanate having a high dielectric constant as a filler in the via hole 14 is used. CX-16) is embedded by a screen printing method, or a predetermined amount is injected by a dispenser, and then placed in a heat drying oven and cured and dried at 150 ° C. to 170 ° C. for 1 hour to 2 hours.
[0016]
Next, as shown in FIG. 1 (5), the protruding portion 15b of the paste material 15 protruding from the via hole 14 is removed by buffing using a nylon buff impregnated with # 320 to # 800 diamond slurry, Or it removes by rotary grinding | polishing and the paste material 15a which has a flat surface is obtained. At this time, the polishing rate of the paste material mainly composed of resin is extremely higher than the polishing rate of the stopper film made of Cr or Ni. Therefore, when the protruding portion 15b is removed by polishing and the stopper film 16 is exposed, the polishing rate is almost the same. Since polishing is not performed, the amount of polishing can be accurately managed according to the polishing time.
[0017]
Next, as shown in FIG. 2A, the stopper film 16 is dissolved and removed by wet etching. As the etchant, when the stopper film 16 is a Cr film, cerium ammonium nitrate (for example, Tw-20 solution manufactured by Wako Chemical Co., Ltd.) is used. When the stopper film 16 is a Ni film, a cupric chloride aqueous solution (5 wt%) is used. -10 wt%).
Next, as shown in FIG. 2 (2), via holes 17 for extracting capacitor electrodes are formed at predetermined positions on the insulating layer 13 by using a carbon dioxide gas laser or a YAG laser, and the circuit pattern 12a (bottom of the via holes 17) is formed. ) To expose a part of it.
[0018]
Next, as shown in FIG. 3 (3), the exposed insulating layer 13 and paste material 15a are activated by the RIE method using Ar gas or the reverse sputtering method, and the circuit pattern 12a (the bottom of the via hole 17). ) Desmear (remove trace contaminants). The conditions for using RIE are, for example, an Ar gas pressure of 30 mTorr to 100 mTorr, an RF power of 100 W, a parallel plate distance of 30 mm to 50 mm, and a processing time of 5 minutes to 10 minutes. The conditions for using reverse sputtering are, for example, that the Ar gas pressure is 30 mTorr to 100 mTorr, the RF power is 100 W, and the processing time is 5 minutes to 10 minutes.
[0019]
Following this activation, a Cr film, a Ni film, and a Cu film are successively formed to a thickness of 0.1 μm or more by the DC sputtering method to obtain the contact layer 21. The DC sputtering conditions are, for example, Ar gas pressure of 20 mTorr to 30 mTorr, DC power of 200 W to 400 W, substrate-electrode distance of 30 mm to 50 mm, and film formation rate of 510 angstrom / second to 10 angstrom / second. .
Next, as shown in (4) of FIG. 2, a plating layer having a thickness of 20 to 25 μm made of Cu is formed by a chemical plating method.
[0020]
Next, as shown in FIG. 2 (5), the composite layer of the plating layer 22 and the contact layer 21 is patterned into a predetermined shape to form capacitor electrodes. In the figure, the circuit pattern 22b is connected to the upper surface of the paste material 15a through the contact layer 21b, and the lower surface of the paste material 15a is connected to the circuit pattern 22a through the circuit pattern 12a and the contact layer 21a. The paste material 15a forms a capacitor.
[0021]
The paste material 15a is filled in the via hole 17 formed in a predetermined shape accurately by a carbon dioxide laser or the like, and the thickness thereof is provided with the stopper layer 16 when the protruding portion 15b is polished. Since it is possible to obtain an accurate thickness without being excessively polished, the capacitance value of the capacitor formed thereby is accurate with little variation.
[0022]
The stopper film 16 is formed by sputtering after the surface of the insulating layer 13 and the surface of the paste material 15a are activated by RIE or reverse sputtering. Therefore, the stopper film 16 has high adhesion and is not scraped off during polishing. , Stable polishing can be performed.
The method for manufacturing the printed circuit board in which the first circuit pattern (conductor layer), the insulating layer, and the second circuit pattern (conductor layer) are sequentially laminated on the substrate has been described above, but the present invention is not limited to this. Instead, it goes without saying that the present invention can be applied to a method of manufacturing a printed circuit board having a build-up wiring layer by alternately laminating a plurality of conductor layers and insulating layers.
[0023]
【The invention's effect】
As described above, the printed circuit board manufacturing method of the present invention includes a step of forming a first circuit pattern on an insulating substrate and a resin insulating layer having a predetermined thickness covering the first circuit pattern. A step of activating the surface of the resin insulating layer by a reactive ion etching method or a reverse sputtering method using Ar gas, and sputtering on the surface of the resin insulating layer after the activation processing step. Forming a metal layer by a method, and forming a via hole reaching the first circuit pattern from the surface of the metal layer in the metal layer and the resin insulating layer, and the via hole contains a filler having a high dielectric constant A step of filling the paste material made of resin to protrude from the via hole to form a protruding portion, and the metal layer as a polishing stopper layer, A step of polishing and removing the protruding portion, and a step of forming a second circuit pattern by covering the paste material after removing the metal layer. It is possible to easily control the thickness, thereby providing a method for manufacturing a printed circuit board having a thin film capacitor having an accurate capacitance value.
[Brief description of the drawings]
FIG. 1 is a diagram showing a part of a process of a printed circuit board manufacturing method according to an embodiment of the present invention.
FIG. 2 is a diagram showing a part of a process of a printed circuit board manufacturing method according to an embodiment of the present invention.
FIG. 3 is a diagram showing a part of a process of a conventional printed circuit board manufacturing method.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Board | substrate, 2 ... Circuit pattern, 3 ... Insulating layer, 3a ... Polishing surface, 4 ... Via hole, 5 ... Paste material, 5a ... Polishing surface, 6 ... Plating layer, 11 ... Board | substrate, 12a, 12b, 12c ... Circuit pattern , 13 ... insulating layer, 14 ... via hole, 15, 15a ... paste material, 15b ... protruding portion, 16 ... stopper film, 17 ... via hole, 18 ... via hole, 19 ... filler, 20 ... electroless plating layer, 20 '... Plated layer, 21, 21a, 21b ... contact layer, 22, 22a, 22b ... plated layer.

Claims (1)

In the manufacturing method of the printed circuit board in which the circuit pattern and the resin insulating layer are alternately laminated on the insulating substrate, and the build-up wiring in which the circuit pattern is connected by the via hole is formed,
Forming a first circuit pattern on the insulating substrate;
Covering the first circuit pattern and forming a resin insulating layer having a predetermined thickness;
An activation step of activating the surface of the resin insulating layer by reactive ion etching or reverse sputtering using Ar gas,
Forming a metal layer by sputtering on the surface of the resin insulation layer after the activation treatment step;
A via hole reaching the first circuit pattern from the surface of the metal layer is formed in the metal layer and the resin insulating layer, and a paste material made of a resin containing a filler having a high dielectric constant is formed from the via hole. A step of filling so as to form a protruding portion;
Polishing and removing the protruding portion using the metal layer as a polishing stopper layer;
And a step of forming a second circuit pattern covering the paste material after removing the metal layer.

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