JP4772586B2 - Circuit board manufacturing method - Google Patents

Description

  The present invention relates to a method for manufacturing a circuit board, and more particularly to a method for manufacturing a circuit board having a built-in capacitor structure.

  In recent years, printed wiring boards are required to be lighter, and are equipped with BGA (ball grid array), PGA (pin grid array), CSP (chip size package), etc., which are small and multi-pinned. Therefore, miniaturization and high density of wiring are required. However, as the wiring density increases, the wiring patterns are close to each other, causing problems such as crosstalk noise between the wirings and potential fluctuations in the power supply line, ground line, etc. Can happen. In particular, when mounting semiconductor elements or electronic components that require high-speed switching operation, crosstalk noise is likely to occur as the frequency increases, and switching noise is caused by the switching elements turning on and off at high speed. As a result, the potential of the power supply line or the like is likely to fluctuate. This leads to a decrease in the operational reliability of the mounted semiconductor element or the like, which is not preferable.

  Therefore, for the purpose of stabilizing the power supply voltage and reducing switching noise and the like, conventionally, a capacitor element such as a chip capacitor has been attached to a semiconductor package on which a semiconductor element is mounted to “decouple” the power line and the like. Has been done. As a typical method, there is a method in which a chip capacitor is surface-mounted by soldering or the like on the same surface as the side on which a semiconductor element or the like of a semiconductor package is mounted or on the opposite side.

In addition, the space in a device or the area on a board that is allowed for mounting a mobile device such as a mobile phone or a PDA that requires high functionality and high speed is becoming smaller. For example, a capacitor can be cited as one of electronic components for mobile phones that are being miniaturized. Typical small capacitors for mobile phones include 0603 (0.6 × 0.3 × 0.3 mm) and 1005 (1.0 × 0.5 × 0.5 mm). Problems with the prior art include that it is difficult to reduce the size to the above-mentioned size, and that about 250 capacitors are mounted per mobile phone, so that component costs and mounting costs are incurred. It is done. For this reason, a component-embedded substrate has been developed that allows a three-dimensional mounting by securing a new mounting area and space by incorporating a component into the substrate as a new mounting form. Up to now, as circuit boards with built-in components, technological development has been carried out in which passive elements such as resistors, capacitors, and inductances are built in a base material or substrate such as glass epoxy resin or ceramics, and some of them have been put into practical use.
The capacitor-embedded substrate described in Patent Document 1 (P4 paragraph number 0031) and Patent Document 2 (P5 paragraph number 0031) uses a resin such as polyimide by electrodeposition as a dielectric. Since the relative dielectric constant of polyimide is about 3.3, it is possible to make a high-capacity 0.1-1 pF of high-frequency small-capacity capacitors at a high density, but the process is complicated, and decoupling capacitors are used. In order to obtain the required capacity of about 0.005-0.1 μF , a large area is required, so it is not suitable for high density. Moreover, in a multilayer substrate, the place where a dielectric can be formed by electrodeposition is limited.
Further, since the capacitor-embedded substrate described in Patent Document 3 (P2 Paragraph No. 0008) has a hole filled with a dielectric, it requires a large area and is suitable for high density. Absent.

For these reasons, there has been a demand for a method of manufacturing a substrate in which a high-frequency small-sized capacitor of about 0.1-1 pF and a decoupling capacitor of about 0.005-0.1 μF are embedded at a high density at the same time. In order to increase the capacitance, it is important to narrow the distance between the two electrodes, that is, to make the dielectric thin. Further, the larger the relative dielectric constant of the dielectric, the larger the capacitance can be obtained with a smaller area.

  FIG. 3 is a process diagram showing a conventional method for manufacturing a capacitor-embedded substrate described in Patent Document 2. First, as shown in FIG. 3A, both surfaces of a flexible insulating base material 61 such as polyimide are shown. A so-called double-sided copper-clad laminate 64 having a first conductor layer 62 such as copper foil and a second conductor layer 63 is prepared, and an opening 65 is formed at a required position of the conductor layer 62 to form a mask layer. .

  Next, as shown in FIG. 2 (2), the flexible insulating base material 61 exposed through the opening 65 is subjected to laser processing, plasma etching processing, and wet etching processing to form a hole 67 for forming a capacitor. Then, a hole 68 for forming a via hole is formed.

  Next, as shown in FIG. 3C, in order to form a capacitor by forming a protective layer with a mask tape to prevent electrodeposition of polyimide on the bottom surface of the hole 68 for forming a via hole. The electrodeposition resin 69 is selectively electrodeposited only on the bottom of the hole 67.

  Next, as shown in FIG. 4 (4), the bottom surface and wall surface of the hole 68 of the via hole forming portion 70, the bottom surface and wall surface of the hole 67 forming the capacitor forming portion 71, and the top surface of the mask layer are made conductive. The plating film 72 is formed by performing the treatment and the plating treatment.

Next, as shown in FIG. 5 (5), the plating film 72, the conductor layer 62, and the conductor layer 63 are subjected to wiring formation processing by an etching method to obtain a double-sided flexible circuit board 74 in which the capacitor structure 73 is built.
JP 2004-235490 A JP 2004-39908 A JP 2003-304060 A Japanese Patent No. 3251515 JP 2002-353629 A JP 2000-68640 A

It is an object of the present invention to provide a method for manufacturing a substrate in which a small capacitor for high frequency of about 0.1-1 pF and a decoupling capacitor of about 0.005-0.1 μF are built in a high density by the same method. And

  In order to achieve the above object, the present application provides the following invention.

According to the present invention, in a method of manufacturing a circuit board incorporating a capacitor,
a) providing a laminate having a first conductor layer and second conductor layer on both surfaces of the insulating base material, forming a metal mask on the first conductive layer, the second as the first electrode forming a bottomed hole having a tapered wall the following 45 ° to the insulating base material laminated to a conductive layer
b) A process of selectively applying a dielectric material from the bottom surface of the hole to the wall surface by an ink-jet method, followed by thermosetting.
c) Conducting treatment and plating treatment to form second electrode and circuit pattern
A method of manufacturing a circuit board having a built-in capacitor, including a) to c) is employed.

  Due to these features, the present invention has the following effects.

According to the present invention, in a method of manufacturing a circuit board incorporating a capacitor,
a) providing a laminate having a first conductor layer and second conductor layer on both surfaces of the insulating base material, forming a metal mask on the first conductive layer, the second as the first electrode forming a bottomed hole having a tapered wall the following 45 ° to the insulating base material laminated to a conductive layer
b) A process of selectively applying a dielectric material from the bottom surface of the hole to the wall surface by an ink-jet method, followed by thermosetting.
c) Conducting treatment and plating treatment to form second electrode and circuit pattern
In the method of manufacturing a circuit board containing a capacitor comprising a) to c), the wall surface of the hole formed in a) has a taper of 45 ° or less, and the dielectric applied in b) is formed in the hole. By reaching the wall surface, a short circuit in the capacitor structure can be more reliably prevented. In addition, since the high dielectric is applied to the bottom of the hole using an inkjet method, capacitors of various capacitances can be formed in a small area at an arbitrary place.

As a result, it is possible to manufacture a circuit board in which a small-sized high frequency capacitor of about 0.1-1 pF and a decoupling capacitor of about 0.005-0.1 μF are built in a high density by the same method.

  Hereinafter, the present invention will be further described with reference to the illustrated embodiments.

FIG. 1 is a manufacturing process diagram showing a method of manufacturing a circuit board incorporating a capacitor structure according to an embodiment of the present invention. First, as shown in FIG. A so-called double-sided copper clad laminate 4 having a first conductor layer 2 such as a copper foil and a second conductor layer 3 on both sides of the material 1 is prepared, and a normal photo is placed at a required position of the first conductor layer 2. The resist layer 5 for forming a metal mask having an opening at a portion where a hole or a groove is formed is formed by using an etching method by a fabrication method. In this step, it is preferable to bond a dry film resist or the like with a laminator or the like. The base material was polyimide having a thickness of 25 μm .

Next, as shown in FIG. 2 (2), a metal mask 7 having an opening 6 is formed in a portion where a hole or a groove is to be formed by using the resist layer 5 and an etching method based on a normal photofabrication method. .
Next, as shown in FIG. 3 (3), a laser processing technique is used to form a hole 8 for forming a capacitor and a hole 9 for forming a via hole in the flexible insulating base material 1 exposed through the opening 6. In addition, the plasma etching method, the resin etching method, and the like are etched and removed alone and in combination to form a hole 8 for forming a bottomed capacitor reaching the conductor layer 3 on the other side and a hole 9 for forming a via hole. . Here, in order to form holes of various shapes at the same time and to taper the wall surfaces of the holes to 45 ° or less, the resin etching technique by chemical treatment described in Patent Document 4 (P4 paragraph number 0025 to P5 paragraph number 0036) Formed. In this case, since the resin etching rate differs depending on the type of polyimide film, the flexible insulating base material 1 may be a polyimide film obtained by polycondensation of pyromellitic dianhydride and an aromatic diamine (for example, the United States). DuPont Kapton, Kaneka Chemical Co., Ltd.'s apical), or a thermoplastic polyimide having a similar structure is preferred.

The reason for processing the hole wall into a taper of 45 ° or less is that when applying the dielectric in the next process, the paste reaches the taper wall to ensure a short circuit in the capacitor structure. This is to prevent it. Since the base material is made of polyimide with a thickness of 25 μm, the tolerance of misalignment when applying dielectric is ± 10 μm by making the wall of the hole into a taper of 45 ° or less. Therefore, the ink jet method can sufficiently cope with this. Here, the difference between the upper hole diameter and the lower hole diameter was designed to be 40 μm .
Next, as shown in FIG. 4 (4), the dielectric 10 is applied onto the second conductor layer exposed through the holes 8 by using an ink jet method and thermally cured. Here, in order to prevent a short circuit in the capacitor structure portion, it is necessary to draw a dielectric on the second conductor layer 3 without a gap. Therefore, as shown in FIG. 4 (4), a dielectric was drawn so as to reach the wall surface of the hole formed in the flexible insulating base material 1. The decoupling capacitor is 100 mm ^{2 in} this method.
Since a certain area is required, it is also effective to use screen printing for the bottom surface and an ink jet method for the wall surface. When electrodeposited polyimide is used for the dielectric as in Patent Document 1 (P4 paragraph number 0031) and Patent Document 2 (P5 paragraph number 0031), the portion where the polyimide is not deposited must be protected with a mask tape or the like. If a high dielectric paste is used, it can be applied only to an arbitrary place by an ink jet method or screen printing, so that the process can be simplified and the relative permittivity of the dielectric, the film thickness and the coating area are changed. Any capacitance can be obtained. Ink-jet inks have more solvent than screen printing pastes, so there is a lot of film loss after thermosetting. For this reason, even when ink having the same dielectric constant is used, the dielectric formed by inkjet is thinner than the dielectric formed by screen printing, so that a capacitor having a high capacity can be formed. At the time of dielectric drawing by the inkjet method, unevenness of about 1.5 μm can be formed on the surface by one drawing, but the unevenness of the surface is about 3.5 μm and the surface unevenness is about 0.3 μm by drawing three times. Smaller to about 2 μm . Here, in order to surely prevent a short circuit due to a pinhole, a film thickness of 5 μm was formed by drawing five times.

  Next, as shown in FIG. 5 (5), the dielectric 10 applied on the first conductor layer 2 and the second conductor layer 3 exposed by the hole 8, and the wall surface of the hole 8 and the hole 9 exposed by the hole 9 are used. Conductive treatment is performed on the second conductor layer 3 and the wall surface of the hole 9 to form a plating film 11.

  Next, as shown in FIG. 6 (6), circuit patterns 12 and 13 are formed on the first conductor layer 2, the second conductor layer 3 and the plating film 11 by using an etching technique based on a photofabrication technique. Thus, the double-sided flexible circuit board 14 incorporating the capacitor structure is obtained.

As a design example of the capacitor of the above embodiment, the capacitance when the dielectric film having a thickness of 5 μm and a thickness of 100 mm ² is left on the second conductor layer from the formula (1) is approximately 0.005 μF. .

ここで、Ｃ：静電容量（Ｆ）、ε０：真空の誘電率８．８５×１０−１２（Ｆ/ｍ）、ε：比誘電率、特許文献５（Ｐ３段落番号００１５）に記載の誘電ペーストの場合約６０、ｓ：面積（ｍ^２）、ｄ：厚さ（ｍ）。

Here, C: capacitance (F), ε0: dielectric constant of vacuum 8.85 × 10-12 (F / m), ε: relative dielectric constant, dielectric described in Patent Document 5 (P3 paragraph number 0015) In the case of paste, about 60, s: area (m ² ), d: thickness (m).

If it is this size, since it can be built under a chip component such as QFP mounted on the substrate, it does not hinder density increase. In addition, the capacitance value on the substrate can be arbitrarily controlled by changing the thickness and area of the dielectric. For example, the capacitance of a high-frequency small capacitor used for a mobile phone or the like is about 0.1-1 pF, so that it can be manufactured to a size of 0402 (0.4 × 0.2 × 0.2 mm) or less. It is. Actually, it is possible to obtain a capacitance of 0.2 pF with the thickness of the dielectric paste being 5 μm and φ50 μm . Therefore, the mounting area can be greatly reduced.

  Moreover, in this invention, not only a capacitor structure but a resistive element can be incorporated together by using a carbon containing ink for the ink to apply | coat.

  In addition, it is possible to manufacture a multi-layer board using a double-sided circuit board incorporating the capacitor structure according to the present invention as a core board. Of course, since it can also be formed in the build layer, a double-sided circuit board incorporating the capacitor structure according to the present invention can be used for both the core substrate and the build layer.

FIG. 2 is a manufacturing process diagram showing a method of manufacturing a circuit board incorporating a capacitor structure according to another embodiment of the present invention. First, as shown in FIG. A so-called double-sided copper-clad laminate 44 having a first conductor layer 42 such as a copper foil and a second conductor layer 43 on both sides of the base material 41 is prepared. A resist layer 45 for forming a metal mask having an opening at a portion where a hole or a groove is formed is formed by using an etching method by a photofabrication method. In this step, it is preferable to bond a dry film resist or the like with a laminator or the like. The base material was polyimide having a thickness of 25 μm .

Next, as shown in FIG. 2B, using the resist layer 45, a metal mask 47 having an opening 46 in a portion where a hole or groove is to be formed is formed using an etching method based on a normal photofabrication method. .
Next, as shown in FIG. 3 (3), the flexible insulating base material 41 exposed through the opening 46 is etched and removed by a laser processing method, a plasma etching method, a resin etching method, etc. alone or in combination. A hole 48 for forming a bottomed capacitor reaching the conductor layer 43 in the direction and a hole 49 for forming a via hole are formed. Here, in order to form holes of various shapes at the same time and to taper the wall surfaces of the holes to 45 ° or less, the resin etching technique by chemical treatment described in Patent Document 4 (P4 paragraph number 0025 to P5 paragraph number 0036) Formed. In this case, since the resin etching rate differs depending on the type of polyimide film, the flexible insulating base material 1 may be a polyimide film obtained by polycondensation of pyromellitic dianhydride and an aromatic diamine (for example, the United States). DuPont Kapton, Kaneka Chemical Co., Ltd.'s apical), or a thermoplastic polyimide having a similar structure is preferred.

The reason for processing the hole wall into a taper of 45 ° or less is that when applying the dielectric in the next process, the paste reaches the taper wall to ensure a short circuit in the capacitor structure. This is to prevent it.
Since the base material is made of polyimide with a thickness of 25 μm, the tolerance of misalignment when applying dielectric is ± 10 μm by making the wall of the hole into a taper of 45 ° or less. Therefore, the ink jet method can sufficiently cope with this. Here, the difference between the upper hole diameter and the lower hole diameter was designed to be 40 μm .

Next, as shown in FIG. 4 (4), the dielectric 50 is applied on the second conductor layer exposed through the holes 48 using an ink jet method, and is thermally cured. Here, in order to prevent a short circuit in the capacitor structure portion, it is necessary to draw a dielectric on the second conductor layer 3 without a gap.
Therefore, as shown in FIG. 4 (4), the dielectric is drawn so as to reach the wall surface of the hole formed in the flexible insulating base material 41. The decoupling capacitor is 100 mm ^{2 in} this method.
Since a certain area is required, it is also effective to use screen printing for the bottom surface and an ink jet method for the wall surface. When electrodeposited polyimide is used for the dielectric as in Patent Document 1 (P4 paragraph number 0031) and Patent Document 2 (P5 paragraph number 0031), the portion where the polyimide is not deposited must be protected with a mask tape or the like. If a high dielectric paste is used, it can be applied only to an arbitrary place by an ink jet method or screen printing, so that the process can be simplified and the relative permittivity of the dielectric, the film thickness and the coating area are changed. Any capacitance can be obtained. Ink-jet inks have more solvent than screen printing pastes, so there is a lot of film loss after thermosetting.
For this reason, even when ink having the same dielectric constant is used, the dielectric formed by inkjet is thinner than the dielectric formed by screen printing, so that a capacitor having a high capacity can be formed. At the time of dielectric drawing by the inkjet method, unevenness of about 1.5 μm can be formed on the surface by one drawing, but the unevenness of the surface is about 3.5 μm and the surface unevenness is about 0.3 μm by drawing three times. Smaller to about 2 μm . Here, in order to surely prevent a short circuit due to a pinhole, a film thickness of 5 μm was formed by drawing five times.
Next, as shown in FIG. 5 (5), the conductive paste 51 is filled in all the holes using the method described in Patent Document 6 (P4 paragraph number 0013, FIG. 3), and is thermally cured.
Next, as shown in FIG. 6 (6), the conductive paste is planarized together with the first conductor layer by polishing.

  Next, as shown in FIG. 7 (7), the first conductor layer 42 and the conductive paste 51 are subjected to a conductive treatment to form a plating film 52.

  Next, as shown in FIG. 8 (8), circuit patterns 53 and 54 are formed on the first conductor layer 42, the second conductor layer 43, and the plating film 52 by using an etching technique based on a photofabrication technique. Thus, the double-sided flexible circuit board 55 incorporating the capacitor structure is obtained.

  Capacitors and interlayer connections can be formed at the same time by filling all holes and grooves with conductive paste after the dielectric is thermally cured in this way, and the plating process is performed after the surface is thermally cured and the surface is polished. Can ensure connection reliability. In the case where the conduction between the layers is performed only by plating, there is a limit to increasing the density because there is a portion where the via stack structure cannot be obtained in manufacturing the multilayer substrate using the capacitor built-in substrate as the core substrate, and Since the via portion must be filled together with the one wiring portion, it is necessary to increase the thickness of the interlayer adhesive. However, if a multilayer board is manufactured by filling all holes and grooves with conductive paste as in this structure and using the plated capacitor built-in board as the core board, vias can be formed at any location in the build area. This also contributes to higher density, and since only the wiring portion is filled, the interlayer adhesive can be made thinner. By optimizing the polishing amount and the plating thickness after heat curing of the conductive paste, there is a possibility of reducing the thickness of the interlayer adhesive, which greatly contributes to improving connection reliability.

The manufacturing process figure of the double-sided flexible circuit board which incorporates the capacitor structure in one Example of this invention. The manufacturing process figure of the double-sided flexible circuit board which incorporates the capacitor structure in the other Example of this invention. The manufacturing process figure of the double-sided flexible circuit board which incorporates the capacitor structure by a conventional construction method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flexible insulating base material 2 1st conductor layer 3 2nd conductor layer 4 Double-sided copper clad laminated board 5 Resist layer 6 Opening 7 Metal mask 8 Hole 9 Hole 10 Dielectric 11 Plating film 12 Circuit pattern 13 Circuit pattern 14 Double-sided flexible circuit board

Claims (3)

In a method for manufacturing a circuit board with a built-in capacitor,
a) providing a laminate having a first conductor layer and second conductor layer on both surfaces of the insulating base material, forming a metal mask on the first conductive layer, the second as the first electrode forming a bottomed hole having a tapered wall the following 45 ° to the insulating base material laminated to a conductive layer
b) A process of selectively applying a dielectric material from the bottom surface of the hole to the wall surface by an ink-jet method, followed by thermosetting.
c) Conducting treatment and plating treatment to form second electrode and circuit pattern
A method of manufacturing a circuit board containing a capacitor, comprising: a) to c). A method of manufacturing a circuit board with a built-in capacitor, wherein in the step c), the conductive paste is filled in the holes, thermally cured, and flattened before conducting the conductive treatment. The method of manufacturing a circuit board with a built-in capacitor according to claim 1, wherein the circuit board is a double-sided flexible circuit board.

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