WO2018038094A1

WO2018038094A1 - Method for manufacturing capacitor, method for manufacturing substrate with built-in capacitor, substrate with built-in capacitor, and semiconductor device mounting component

Info

Publication number: WO2018038094A1
Application number: PCT/JP2017/029906
Authority: WO
Inventors: 重信三浦
Original assignee: 重信三浦
Priority date: 2016-08-22
Filing date: 2017-08-22
Publication date: 2018-03-01
Also published as: JP6967005B2; JPWO2018038094A1

Abstract

Provided are: a step (1) for forming a first electrode 3A; a step (2) for forming a high dielectric thin film 5 on the first electrode 3A; a step (3) in which a solder-containing resin composition 6 that contains a resin component and a melting temperature transition-type solder is provided on the high dielectric thin film 5, degassing is performed, and the resin is filled into pinholes in the high dielectric thin film 5; a step (4) in which the melting temperature transition-type solder 6 is allowed to settle and a melting temperature transition-type solder layer 7 is formed on the high dielectric thin film 5; a step (5) for melting the melting temperature transition-type solder layer 7, and prompting the formation of an alloy to yield a conductor layer 8 for which the re-melting temperature is MP; a step (6) in which the resin component is hardened at a temperature lower than the melting temperature MP of the conductor layer 8 to make a resin hardened layer 9; and a step (7) for forming a through hole in the resin hardened layer 9 and exposing the conductor layer, and also forming a second electrode connected to the conductor layer.

Description

Capacitor manufacturing method, capacitor built-in substrate manufacturing method, capacitor built-in substrate, and semiconductor device mounting component

The present invention relates to a capacitor manufacturing method, a capacitor built-in substrate manufacturing method, a capacitor built-in substrate, and a semiconductor device mounting component.

A voltage drop occurs as the speed of a semiconductor device typified by LSI or WLP (Wafer Level Package) increases, but there is a technique of providing a capacitor that compensates for the voltage drop in order to ensure the stability of the device. As a capacitor for preventing such a voltage drop, a technique for providing a capacitor having a relatively large capacity is generally used. However, in order to ensure the reliability of a high-speed device, the voltage drop can be prevented. The time until the voltage is compensated is important, and a device has been devised to shorten the time by arranging it near a component such as an LSI using a package substrate incorporating a capacitor (see Patent Documents 1 and 2).

However, the substrate with a built-in capacitor has a problem that the manufacturing process is complicated because the capacitor is built around the LSI mounting portion.

Also, in order to cope with further higher speeds in the future, even if the capacitance of the capacitor is small, it is necessary to incorporate the capacitor as close as possible. In view of this, a technique has been proposed in which a via wiring and a capacitor built-in via wiring in which a capacitor is incorporated are provided adjacent to each other in an LSI mounting portion, and the LSI is mounted on the via wiring (see Patent Document 3).

In order to manufacture a capacitor-embedded substrate having such a capacitor-embedded via, a sheet in which a high dielectric layer is sandwiched between conductive layers is used. However, since the dielectric layer is provided on the entire surface of the substrate, There is a problem that it is expensive. Another problem is that the manufacturing yield is very low due to the problem of pinholes generated in the high dielectric layer.

Although a technology for manufacturing such a capacitor built-in substrate at low cost is desired, there is currently no technology capable of manufacturing such a capacitor built-in substrate at low cost.

In some cases, it is not always necessary to provide a capacitor built-in via wiring to all of the via wiring connected to the power supply terminal and signal terminal of the LSI. In this case, a sheet provided with a high dielectric layer on the entire substrate is used. If provided, there is a problem that waste is further increased.

Therefore, it is conceivable to provide an inorganic high-dielectric film or an organic thin film only in necessary places by a sputtering method or a plating method in the manufacturing process of the capacitor built-in substrate. Therefore, there is a problem that the possibility of dielectric breakdown due to pinholes further increases.

Triazine disulfide polymer has been proposed as a material suitable for a thin film capacitor (see Patent Document 4). However, there is a problem of pinholes as in the case of an inorganic thin film, and the chemical resistance of the film is low. There is also a problem that it is difficult to form the upper electrode.

JP 2005-101075 A JP 2014-127716 A Special table 2008-529309 JP 2005-251932 A

In view of the above-described circumstances, the present invention provides a capacitor manufacturing method, a capacitor built-in substrate manufacturing method, a capacitor built-in substrate, and a semiconductor device mounting component capable of manufacturing a capacitor built-in substrate that can cope with the above-described high speed at a relatively low cost. The purpose is to provide.

A first mode for achieving the object includes a step (1) of forming a first electrode, a step (2) of forming a high dielectric thin film on the first electrode, and a resin on the high dielectric thin film. A step (3) of providing a solder-containing resin composition containing a component and a melting temperature transition type solder, defoaming and filling the resin into the pinhole of the high dielectric thin film, and settling the melting temperature transition type solder A step (4) of forming a melting temperature transition type solder layer on the high dielectric thin film, and a step of melting and alloying the melting temperature transition type solder layer to form a conductor layer having a remelting temperature of MP ( 5), a step (6) of curing the resin component at a temperature lower than the melting temperature MP of the conductor layer to form a resin cured layer, and forming the through hole in the resin cured layer to form the conductor layer. Forming a second electrode that is exposed and connected to the conductor layer ( ) And, in the manufacturing method of the capacitor, characterized by comprising.

The second aspect of the present invention includes a step (1) of forming a first electrode, a step (2) of forming a high dielectric thin film on the first electrode, and a first resin on the high dielectric thin film. A step (3-1) of providing a resin composition layer containing a component and degassing to fill the pinhole of the high dielectric thin film with the first resin component; a second resin component and a melting temperature transition type solder; A step (3-2) of providing a solder-containing resin composition containing the resin composition layer on the resin composition layer, and the melting temperature transition type solder is allowed to settle into the resin composition layer to melt the high temperature dielectric film on the high dielectric thin film. A step (4) of forming a transitional solder layer, a step (5) of melting and alloying the transitional solder layer to form a conductor layer having a remelting temperature of MP, and a melting temperature of the conductor layer Curing the first resin component and the second resin component at a temperature lower than MP to cure the resin And a step (8) of forming a through hole in the cured resin layer to expose the conductor layer and forming a second electrode connected to the conductor layer. It is in the manufacturing method of the capacitor characterized.

According to a third aspect of the present invention, in the first or second aspect, the defoaming is performed at a temperature of room temperature to 160 ° C.

According to a fourth aspect of the present invention, there is provided a step (11) of forming a plurality of via conductors provided penetrating through a first layer made of an insulator, and a via for providing a capacitor among the plurality of via conductors. A step (12) of forming a high dielectric thin film on the first electrode by covering another via conductor with a second layer made of an insulator using the conductor as the first electrode, and a resin on the high dielectric thin film; A step (13) of providing a solder-containing resin composition containing a component and a melting temperature transition type solder and defoaming; and a melting temperature transition type solder layer on the high dielectric thin film by allowing the melting temperature transition type solder to settle. A step (15) of forming a melting temperature transition-type solder layer and alloying to form a conductor layer having a remelting temperature of MP, and a temperature lower than the melting temperature MP of the conductor layer Step of curing the resin component to form a cured resin layer ( 6) and a step (17) of forming a through hole in the cured resin layer to expose the conductor layer and forming a second electrode made of a second via conductor connected to the conductor layer; Forming a through hole in the second layer to expose the via conductor and providing a third via conductor connected to the via conductor (18). Is in the way.

According to a fifth aspect of the present invention, there is provided a step (11) of forming a plurality of via conductors provided penetrating through a first layer made of an insulator, and a via for providing a capacitor among the plurality of via conductors. A step (12) of forming a high dielectric thin film on the first electrode, covering the other via conductor with a second layer made of an insulator with the conductor as the first electrode, and a second layer on the high dielectric thin film; A step (13-1) of defoaming by providing a resin composition layer containing one resin component and a solder-containing resin composition containing a second resin component and a melting temperature transition type solder are provided on the resin composition layer A step (13-2), a step (14) of causing the melting temperature transition type solder to settle into the resin composition layer to form a melting temperature transition type solder layer on the high dielectric thin film, and the melting temperature. Conductor with melting and alloying transitional solder layer and remelting temperature MP The step (15), the step (16) of curing the first resin component and the second resin component at a temperature lower than the melting temperature MP of the conductor layer to form a resin cured layer, and the resin cured layer Forming a through hole in the second layer to expose the conductor layer and forming a second electrode made of a second via conductor connected to the conductor layer; and forming a through hole in the second layer And a step (18) of providing a third via conductor that exposes the via conductor and connects to the via conductor.

A sixth aspect of the present invention is the method for manufacturing a capacitor built-in substrate according to the fourth or fifth aspect, wherein the defoaming is performed at a temperature of room temperature to 160 ° C.

According to a seventh aspect of the present invention, there is provided a step (21) of forming a plurality of wiring terminals by etching the first metal layer of the laminated metal sheet in which a plurality of metal layers are laminated, and an insulating layer for embedding the wiring terminals. And a step of removing a wiring terminal at a location where a capacitor terminal for providing a capacitor from among the plurality of wiring terminals is formed and exposing a second metal layer below the wiring terminal as a first electrode. A step (23) of forming, a step (24) of forming a high dielectric thin film covering at least the first electrode in the recess, and a resin component and a melting temperature transition type solder on the high dielectric thin film. A step (25) of providing a solder-containing resin composition and defoaming, a step (26) of forming a melting temperature transition type solder layer on the high dielectric thin film by precipitating the melting temperature transition type solder, Melting temperature transition A step (27) of melting and alloying a solder layer to form a conductor layer having a remelting temperature of MP, and a step of curing the resin component at a temperature lower than the melting temperature MP of the conductor layer to obtain a cured resin layer (28) and a step (29) of forming a through hole in the cured resin layer to expose the conductor layer and forming a second electrode made of a second conductor connected to the conductor layer. A method for manufacturing a capacitor-embedded substrate is provided.

According to an eighth aspect of the present invention, a second metal layer under the first metal layer is etched by etching the first metal layer at a location where a capacitor terminal for providing a capacitor of a laminated metal sheet in which a plurality of metal layers are laminated. Forming a recess exposing the first electrode as a first electrode, forming a high dielectric thin film covering at least the first electrode in the recess (32), and a resin component on the high dielectric thin film And a defoaming step (33) of providing a solder-containing resin composition containing a melting temperature transition type solder and a melting temperature transition type solder layer on the high dielectric thin film by settling the melting temperature transition type solder A step (34) of forming, a step (35) of melting and alloying the melting temperature transition type solder layer to form a conductor layer having a remelting temperature MP, and a temperature lower than the melting temperature MP of the conductor layer. Curing the resin component A step (36) of forming a cured resin layer, a step (37) of etching the first metal layer leaving the conductive layer and the cured resin layer in the recess, and a wiring terminal other than the capacitor terminal; A step (38) of forming an insulating layer for embedding the conductor layer and the resin cured layer and the wiring terminal; and forming a through hole in the resin cured layer to expose the conductor layer and the conductor layer And a step (38) of forming a second electrode made of a second conductor connected to the capacitor.

According to a ninth aspect of the present invention, in the seventh or eighth aspect, the defoaming is performed at a temperature of room temperature to 160 ° C.

According to a tenth aspect of the present invention, there is provided a capacitor built-in substrate provided between a semiconductor package and a substrate on which the semiconductor package is mounted, a plurality of via terminals connecting the semiconductor package and the substrate, and the via A capacitor built-in terminal provided adjacent to the terminal and having a built-in capacitor, wherein the capacitor built-in terminal includes a first electrode, a high-dielectric thin film provided on the first electrode, and the high-dielectric A conductive layer made of molten transition type solder provided on the body thin film, a cured resin layer provided on the conductive layer, and penetrated until the conductive layer provided on the cured resin layer is exposed. And a second electrode made of a second via conductor provided in the through hole.

According to an eleventh aspect of the present invention, in the tenth aspect, the via terminal includes a via conductor penetrating the first layer made of an insulator and the cured resin layer provided on the first layer. A capacitor-embedded substrate comprising a second via conductor connected to the via conductor through a second layer.

A twelfth aspect of the present invention is the capacitor according to the tenth or eleventh aspect, wherein the first electrode includes the via conductor provided through the first layer made of an insulator. Located on the built-in board.

According to a thirteenth aspect of the present invention, in the tenth or eleventh aspect, the first electrode includes the via conductor provided through the resin cured layer provided on the first layer made of an insulator. A capacitor-embedded substrate comprising a body.

According to a fourteenth aspect of the present invention, in any one of the tenth to thirteenth aspects, the conductor layer is formed of a melt transition formed by sedimenting a solder-containing resin composition containing a resin component and a melting temperature transition type solder. The resin cured layer is a cured product of the resin component of the solder-containing resin composition, and the pin holes of the high dielectric thin film are filled with the resin component of the solder-containing resin composition. A capacitor-embedded substrate.

A fifteenth aspect of the present invention is a capacitor built-in substrate having a signal wiring terminal and a capacitor built-in terminal provided adjacent to the signal wiring terminal, wherein the capacitor built-in terminal includes the first electrode, A melt transition type formed by sedimenting a high dielectric thin film provided on the first electrode, and a solder-containing resin composition provided on the high dielectric thin film and including a resin component and a melting temperature transition type solder A conductive layer made of solder, a cured resin layer provided on the conductive layer and cured by the resin component of the solder-containing resin composition, and until the conductive layer provided on the cured resin layer is exposed A second electrode made of a second via conductor provided in the penetrating through hole, and the pinhole of the high dielectric thin film is filled with the resin component of the solder-containing resin composition Features In the capacitor built-in substrate.

According to a sixteenth aspect of the present invention, there is provided a semiconductor mounting component comprising the capacitor built-in substrate according to any one of the tenth to fifteenth aspects, and the semiconductor package mounted on the capacitor built-in substrate. It is in.

According to a seventeenth aspect of the present invention, there is provided the semiconductor mounting component according to the sixteenth aspect, wherein the capacitor-embedded substrate is mounted on the substrate.

FIG. 3 is a cross-sectional view schematically showing the manufacturing method according to the first embodiment. 5 is a cross-sectional view schematically showing a manufacturing method according to Embodiment 2. FIG. It is sectional drawing which shows typically the modification of the capacitor of embodiment. It is sectional drawing which shows the effect of this invention typically. It is sectional drawing which shows typically an example of the semiconductor mounting component of this invention. It is sectional drawing which compares the capacitor of embodiment with a comparative example. It is the top view and sectional drawing which show the other example of the basic composition of the board | substrate with a built-in capacitor of this invention. It is sectional drawing which shows typically the manufacturing method which concerns on another example. It is sectional drawing which shows typically the manufacturing method which concerns on another example.

Hereinafter, the present invention will be described in more detail.
(Embodiment 1)
In the present embodiment, an example of a method for manufacturing a capacitor that can be applied to the capacitor-embedded substrate of the present invention will be described.

As shown in FIG. 1A, a via 2a, which is a through hole, is formed in the insulator layer 2 of the printed circuit board including the conductor layer 1 and the insulator layer 2 by laser processing or the like, and the via 2a is plated. The via conductor 3 is formed by embedding with a via conductor such as copper by the method.

Here, as the printed board, a rigid board such as a glass epoxy board, a glass composite board, a ceramic board, and a Teflon (registered trademark) board, or a flexible board can be used. Further, a substrate on which the via conductor 3 is formed may be used.

Next, as shown in FIG. 1B, an insulator layer 4 is formed, a via 4a is formed at a site where a capacitor is to be formed, and the via conductor 3 is exposed to form the first electrode 3A.

Here, the insulator layer 4 may be formed using a resin composition (prepreg) containing a resin component and an inorganic filler such as silica or a filler such as acrylic rubber particles, and has a low thermal expansion coefficient (CTE) as much as possible. Coefficient of thermal expansion) is preferable.

As the resin composition forming the insulator layer 4, a commercially available prepreg may be used, but a resin component and a filler may be appropriately blended. The resin component contains a thermosetting resin, a curing agent, and, if necessary, a solvent. As the thermosetting resin, typically, various epoxy resins can be used. Polyfunctional cyanate resin, polyfunctional maleimide-cyanate resin, polyfunctional maleimide resin, unsaturated polyphenylene ether resin, vinyl ester resin, urea resin, diallyl phthalate resin, melanin resin, guanamine resin, unsaturated polyester resin, A melamine-urea cocondensation resin or the like may be blended.

The method for forming the via 4a in the insulator layer 4 is not particularly limited, but may be performed by laser processing or the like.

Next, as shown in FIG. 1C, a high dielectric thin film 5 is provided so as to cover the first electrode 3A in the via 4a.

The high dielectric thin film 5 is composed of an inorganic high dielectric thin film such as barium titanate (BTO) or strontium titanate (BST), or an organic high dielectric thin film such as hydrazine, a hydrazine derivative, or a triazine thiol derivative.

Such a high dielectric thin film 5 can be formed by a vapor phase method such as sputtering, CVD, or ion plating, a liquid phase method such as a solution coating method, a printing method, a plating method, or the like. The film thickness of the high dielectric thin film 5 is appropriately selected depending on the relative dielectric constant of the material and the application, but may be a thickness in the range of 0.5 μm to 1.0 μm, for example.

Examples of such a capacitor include a capacitor having a capacity of 30 pF to 80 pF, preferably 50 pF to 80 pF.

For example, when the effective high dielectric thin film 5 has a diameter of 100 μm to 200 μm, inorganic high dielectric thin films such as barium titanate (BTO), strontium titanate (BST), and tantalum pentoxide (Ta ₂ O ₅ ) In the case of organic high dielectric thin films such as 0.5 μm to 1.0 μm, hydrazine, hydrazine derivatives, and triazine thiol derivatives, the thickness may be 120 nm to 150 nm. An inorganic high dielectric thin film such as BTO can be formed by a vapor phase method such as sputtering, a liquid phase method such as a solution coating method, or a printing method. A tantalum pentoxide film or the like can also be formed by an anodic oxidation film formation method. The organic high dielectric thin film can be formed by a liquid phase method such as a solution coating method or a printing method. In the vapor phase method and the liquid phase method, a high temperature environment may be supplied in some cases. However, the printing method and the anodic oxidation film forming method have an advantage that the film formation can be performed in a low temperature environment.

In the present embodiment, a barium titanate thin film having a thickness of 0.6 μm is formed by a sputtering method to obtain a high dielectric thin film 5.

The high dielectric thin film 5 may be provided only in the via 4a through a mask such as a resist.

Next, as shown in FIG. 1 (d), after filling the high dielectric thin film 5 in the via 4 a with the solder-containing resin composition 6 containing the resin component and the melting temperature transition type solder, defoaming, Resin is filled into pinholes existing in the high dielectric thin film 5.

Here, the melting temperature transition type solder contained in the solder-containing resin composition 6 is made of an alloy or metal fine particles, and is, for example, 160 to 260 ° C., preferably 160 to 200 ° C., more preferably 160 to 180 ° C. It becomes what becomes a conductor by sintering or metallization at the temperature of, and the subsequent remelting temperature (MP) becomes 260 degreeC or more, Preferably it becomes 400 degreeC or more.

The melting temperature transition type solder contains, for example, a low melting point metal powder and a high melting point metal powder. The low metal metal powder is made of one or more alloys such as indium, tin, lead, indium, and bismuth, and has a melting point of 180 ° C. or lower, for example. The high melting point metal powder is silver, copper, silver-coated copper or the like, and has a melting point of 800 ° C. or higher. The shape of the metal powder is not particularly limited as long as it has an average particle size of about 1 μm to 25 μm, but it is preferable not to include metal powder having a size that can enter the pinhole.

A melting temperature transition type solder composed of such a low melting point metal powder and a high melting point metal powder is melted, alloyed by sintering or metallization, and becomes a conductor whose remelting temperature has transitioned to a high temperature. Such alloying (hereinafter also simply referred to as metallization) is promoted by the presence of flux. Therefore, it is preferable to contain a flux.

As flux, zinc chloride, lactic acid, citric acid, oleic acid, stearic acid, glutamic acid, benzoic acid, oxalic acid, glutamic acid hydrochloride, aniline hydrochloride, cetylpyridine bromide, urea, hydroxyethyllaurylamine, polyethylene glycol laurylamine Oleylpropylenediamine, triethanolamine, glycerin, hydrazine, rosin and the like.

The resin component contained in the solder-containing resin composition 6 includes a thermosetting resin and a curing agent.
Examples of the thermosetting resin include various epoxy resins and other resins.

Epoxy resins include naphthalene type epoxy resin, cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, alicyclic epoxy resin, aliphatic chain epoxy resin, cresol novolak type Epoxy resins, phenol novolac type epoxy resins, alkylphenol novolac type epoxy resins, aralkyl type epoxy resins, biphenol type epoxy resins, dicyclopentadiene type epoxy resins, trishydroxyphenylmethane type epoxy compounds, aromatics having phenols and phenolic hydroxyl groups Epoxidized products of condensates with aldehydes, diglycidyl etherified products of bisphenol, diglycidyl etherified products of naphthalenediol, phenolic groups Glycidyl etherified product, diglycidyl ethers of alcohols, triglycidyl isocyanurate.

Other resins include polyfunctional cyanate resin, polyfunctional maleimide-cyanate resin, polyfunctional maleimide resin, unsaturated polyphenylene ether resin, vinyl ester resin, urea resin, diallyl phthalate resin, melanin resin, Examples thereof include guanamine resin, unsaturated polyester resin, melamine-urea cocondensation resin, and the like.

Particularly preferred thermosetting resins include, for example, 20 parts by weight or more of an epoxy resin having an epoxy equivalent in the range of 200 to 600 and a hydrolyzable chlorine concentration of less than 200 ppm, and 80 weight of a resin other than this epoxy resin. And a resin having an ethylene glycol-modified epoxy resin and an overall hydrolyzable chlorine concentration of less than 1000 ppm.

Examples of the epoxy resin having an epoxy equivalent in the range of 200 to 600 and having a hydrolyzable chlorine concentration of less than 200 ppm include bisphenol A type epoxy resin, brominated epoxy resin, bisphenol F type epoxy resin, novolac type epoxy resin, Examples thereof include alicyclic epoxy resins, glycidyl amine type epoxy resins, glycidyl ether type epoxy resins, and heterocyclic epoxy resins.

Preferred examples of resin components other than epoxy resins that satisfy the requirements for the epoxy equivalent and hydrolyzable chlorine concentration include epoxy resins, alkyd resins, melamine resins, xylene resins, and the like that do not satisfy the requirements.

In any case, the curing agent is appropriately selected so as to obtain desired characteristics, and examples of usable curing agents include imidazole curing agents, phenol novolac curing agents, and naphthol curing agents, but are not limited thereto. Is not to be done.

The imidazole-based curing agent is one that can be used as a curing agent among imidazole and its derivatives. Examples of derivatives include 2-undecylimidazole, 2-heptadecylimidazole, 2-ethylimidazole, 2-phenylimidazole, Examples include 2-ethyl-4-methylimidazole, 1-cyanoethyl-2-undecylimidazole, 1-cyanoethyl-2-undecylimidazolium trimellitate and the like.

The phenol novolac-based curing agent is a phenol novolak and derivatives thereof usable as a curing agent, and the naphthol-based curing agent is a naphthol and derivatives thereof usable as a curing agent.

In the present invention, the solder-containing resin composition 6 is filled and then defoamed.
Here, defoaming refers to a reduced pressure environment in which bubbles in pinholes existing in the high dielectric thin film 5 are detached and filled with resin instead. This defoaming step is performed under a vacuum of −30 kPa to −100 kPa and a temperature of room temperature to 160 ° C. As a result, the bubbles in the pinholes present in the high dielectric thin film 5 are detached and filled with the resin component instead.

Next, as shown in FIG. 1 (e), the temperature is raised to, for example, 50 ° C. to 160 ° C., and ultrasonic vibrations are applied as necessary to remove the metal powder in the solder-containing resin composition 6. A melting temperature transition type solder layer 7 is formed on the high dielectric thin film 5 by sedimentation.

Then, in this state, as shown in FIG. 1 (f), the melting temperature transition type solder layer 7 is metallized to form a conductor layer 8.

Here, the metallization of the melting temperature transition type solder layer 7 may be performed at a temperature corresponding to the component of the melting temperature transition type solder layer 7, for example, at a temperature of 160 ° C. to 260 ° C. The remelting temperature MP of the conductor layer 8 formed thereby is, for example, 260 ° C. or higher, preferably 400 ° C. or higher.

As described above, in this embodiment, after the solder-containing resin composition 6 is provided and the defoaming process is performed, the sedimentation process is performed to form the molten transition type solder layer 7, which is metallized to form the conductor layer 8. Therefore, it is necessary to select the composition of the solder-containing resin composition 6 so that the contained melting temperature transition type solder can settle. Further, the content of the melting temperature transition type solder should be settled to form the melting temperature transition type solder layer 7 and to be contained in an amount sufficient to form the conductor layer 8.

The content of the melting temperature transition type solder in the solder-containing resin composition 6 is, for example, preferably 40 vol% or less, and more preferably 20 to 40 vol%.

In addition, although the resin component is mixed in the melt transition type solder layer 7 formed after settling, the content of the melt transition type solder layer 7 is 60 vol% or more, for example, 60 vol%. It may be ˜80 vol%.

Thereby, the volume resistivity of the conductor layer 8 can be set to 1 × 10 ⁻⁵ or more, preferably 1 × 10 ⁻⁶ to 1 × 10 ⁻⁷ .

Further, the resin component of the solder-containing resin composition 6 needs to be prepared so that the melting temperature transition type solder can be settled. At the temperature of the sedimentation step, for example, a temperature of 50 ° C. to 160 ° C. Although it is premised on not to harden | cure, what has the property to reduce viscosity is preferable. Further, the resin component preferably does not contain a solvent.

Further, it is preferable that the resin component of the solder-containing resin composition 6 is not cured when the melting temperature transition type solder layer 7 is metallized. Here, “not cured” means substantially not cured. For example, when metallized at 160 to 260 ° C., there is a problem even if a resin component having a curing temperature (process temperature) of 130 to 230 ° C. is used. Absent.

Thus, it is preferable that the curing of the resin component is not started as much as possible in the sedimentation step, but there is no problem even if the curing reaction is started simultaneously in the metallization step.

In this embodiment, after filling with such a solder-containing resin composition 6, defoaming, but since there is a possibility of sedimentation until the defoaming step, after filling the solder-containing resin composition 6, It is preferable to defoam without taking time.

The conductor layer 8 formed by sintering or metallization in this way has a melting temperature MP of, for example, 260 ° C. or higher.

Therefore, after that, the resin component is cured at a temperature lower than the melting temperature MP of the conductor layer 8 to form the resin cured layer 9, and the high dielectric thin film 5 on the surface of the insulator layer 4 is removed and the resin cured layer is removed. 9 is flattened (FIG. 1G).

Next, as shown in FIG. 1 (h), an insulator layer 10 is provided on the surface, and as shown in FIG. 1 (i), vias 9a are formed in the insulator layer 10 and the cured resin layer 9 by laser processing or the like. Thus, the conductor layer 8 is exposed. At the same time, a via 4 b is formed in the insulator layer 10 and the insulator layer 4 to expose the via conductor 3.

Then, as shown in FIG. 1 (j), a via conductor 11 is embedded in the via 9a and the via 4b by plating or the like. Thereby, the second electrode 11A and the via terminal 11B are formed.

Next, as shown in FIG. 1 (k), the conductor layer 1 on the back surface side is patterned by etching or the like to form an external terminal, and the first electrode 3A and the via terminal 3B are separated.

Thereby, a capacitor terminal including a capacitor in which the high dielectric thin film 5 is sandwiched between the first electrode 3A and the second electrode 11A, and a via terminal having no capacitor including the via terminal 3B and the via terminal 11B are formed. The

Here, for example, a via terminal including the via terminal 3B and the via terminal 11B is used for a signal line, and a capacitor terminal including a capacitor in which the high dielectric thin film 5 is sandwiched between the first electrode 3A and the second electrode 11A is used. Used as a ground connected to the power supply.

(Embodiment 2)
The present embodiment is the same as the first embodiment except that the resin composition not containing solder is filled before the solder-containing resin composition 6 is filled, and the defoaming step is performed in that state. Description is omitted.

In the present embodiment, FIGS. 2A to 2C are the same as those in the first embodiment. In the process shown in FIG. 2D, the high dielectric thin film 5 in the via 4a is covered. The resin composition 12 is provided, a defoaming step is performed, bubbles in the pinholes present in the high dielectric thin film 5 are removed, and a resin component that forms the resin composition 12 is filled in the pinholes.

Thereafter, the solder-containing resin composition 6 is filled in the via 4a in the same manner as in the first embodiment, and a sedimentation process is performed (FIG. 2 (e)). In this sedimentation step, the melting temperature transition type solder in the solder-containing resin composition 6 settles down to the resin composition 12 and forms the melting temperature transition type solder layer 7 directly on the high dielectric thin film 5. (FIG. 2 (f)). Then, the melting temperature transition type solder layer 7 is metallized to form a conductor layer 8 (FIG. 2G).

Here, the resin composition 12 contains a thermosetting resin and a curing agent. As the thermosetting resin, the same resin component as that of the solder-containing resin composition 6 described in the first embodiment can be used.

The resin component of the resin composition 12 and the resin component of the solder-containing resin composition 6 may be the same or different, but the melting temperature transition type solder is allowed to settle in the same manner as the resin component of the solder-containing resin composition 6. However, it is premised that it does not substantially harden at the temperature of the sedimentation step, for example, a temperature of 50 ° C. to 160 ° C., but preferably has a property of reducing the viscosity. Moreover, the resin composition 12 desirably does not contain a solvent.

Also, it is preferable that the resin composition 12 does not harden when the melting temperature transition type solder layer 7 is metallized similarly to the resin component of the solder-containing resin composition 6. Here, “not cured” means substantially not cured. For example, when metallized at 160 to 260 ° C., there is a problem even if a resin component having a curing temperature (process temperature) of 130 to 230 ° C. is used. Absent.

The conductor layer 8 formed by metallization in this way has a melting temperature MP of, for example, 260 ° C. or higher.

Therefore, after that, the resin components of the resin composition 12 and the solder-containing resin composition 6 are cured at a temperature lower than the melting temperature MP of the conductor layer 8 to form the cured resin layer 9, and further, the insulator layer The high dielectric thin film 5 on the surface 4 is removed and the cured resin layer 9 is flattened (FIG. 2H).

Similarly, as shown in FIGS. 2 (i) and 2 (j), an insulator layer 10 is provided on the surface, and vias 9a are formed in the insulator layer 10 and the cured resin layer 9 by laser processing or the like. The body layer 8 is exposed. At the same time, a via 4 b is formed in the insulator layer 10 and the insulator layer 4 to expose the via conductor 3.

Then, as shown in FIG. 2 (k), the via conductor 11 is embedded in the via 9a and the via 4b by plating or the like. Thereby, the second electrode 11A and the via terminal 11B are formed.

Next, the conductor layer 1 on the back surface side is patterned by etching or the like to form external terminals, and the first electrode 3A and the via terminal 3B are separated (FIG. 2 (l)).

Thereby, a capacitor terminal including a capacitor in which the high dielectric thin film 5 is sandwiched between the first electrode 3A and the second electrode 11B and a via terminal having no capacitor including the via terminal 3B and the via terminal 11B are formed. The

(Modification)
In FIG. 3, the principal part enlarged view of a some modification is shown.
In the first and second embodiments, since the high dielectric thin film is formed by the sputtering method, as shown in FIG. 3A, the high dielectric thin film 5 is formed so as to cover the side wall in the via 4a. For example, it may be provided only at the bottom of the via 4a by a solution coating method or a printing method. In this case, as shown in FIG. 3B, the high dielectric thin film 5A only needs to be provided to cover the first electrode 3A.

In the first and second embodiments, the capacitor of the present invention is provided adjacent to the via conductor penetrating the substrate, and the first electrode and the second electrode of the capacitor are provided on the front surface and the back surface of the substrate. As shown in FIG. 3C, the first electrode 3A of the capacitor may be provided on the surface side adjacent to the second electrode 11A, and various modifications can be considered.

(Effects of the invention)
The operational effects of the invention will be described with reference to FIG.
The essence of the present invention is that the yield of low-capacitance but small capacitors is dramatically improved, and high yield and low-capacity but small capacitors can be freely provided adjacent to the wiring. is there.

In order to realize this, it is in the point of preventing dielectric breakdown due to pinholes in the high dielectric thin film. That is, as shown in FIG. 4A, even if the pinhole 51 exists in the high dielectric thin film 5, the resin composition 12 is provided on the high dielectric thin film 5 as shown in FIG. Then, by performing a defoaming process, the resin component is filled in the pinhole 51 and cured later, thereby preventing dielectric breakdown due to the pinhole 51.

Examples of the high dielectric thin film 5 include inorganic high dielectric thin films such as barium titanate (BTO) and strontium titanate (BST), and organic high dielectric thin films such as hydrazine, hydrazine derivatives, and triazine thiol derivatives. it can.

Even if the dielectric breakdown is prevented by the resin composition 12 as described above, the second electrode must be provided immediately above the high dielectric thin film 5, but in the present invention, the conductor layer formed by metallizing the second electrode is provided in the first layer. This is solved by using a part of two electrodes.

That is, as shown in FIG. 4 (c), a solder-containing resin composition 6 containing a resin component and a melting temperature transition type solder is used, and after this is provided on the resin composition 12, the melting temperature transition type solder is used. The resin composition 12 is allowed to settle and the melting temperature transition type solder layer 7 is provided directly on the high dielectric thin film 5 (FIG. 4D), which is metallized and alloyed to increase the remelting temperature. It is set as the body layer 8 (FIG.4 (e)). Thereby, the conductor layer 8 which becomes a 2nd electrode in close contact with the high dielectric material thin film 5 can be provided. In addition, since the remelting temperature MP is increased, the conductive layer 8 is a step in which the resin component of the resin composition 12 or the solder-containing resin composition 6 is subsequently cured without being remelted. The point that 8 can be held is important.

This technique also solves the problem that electrodes have not been effectively provided on organic high dielectric thin films such as hydrazine, hydrazine derivatives, and triazine thiol derivatives. That is, the organic high-dielectric thin film has a problem that the plating resistance is low and the upper electrode cannot be effectively provided, but this problem is caused by metallizing the precipitated melting point transition type thin film to form the upper electrode. Has solved.

The above description has been made based on the above-described second embodiment. However, as shown in the first embodiment, the solder-containing resin composition 6 is provided on the high dielectric thin film 5 without providing the resin composition 12. Even if defoaming is performed, insulation breakdown due to pinholes can be similarly prevented.

(Embodiment of semiconductor mounting component)
The capacitor built-in substrate manufactured in the above-described embodiment is provided, for example, between a semiconductor package and a substrate on which the semiconductor package is mounted.

An example of such a semiconductor mounting component is shown in FIG. As shown in FIG. 5, the capacitor built-in substrate 50 is disposed between a package substrate 200 provided on the mother board 100 and an LSI 300 which is a semiconductor package to be mounted. FIG. 5A is a schematic diagram of a semiconductor mounting component, and FIG. 5B is an enlarged view showing a capacitor built-in substrate and an LSI.

By using such a capacitor-embedded substrate 50, it is possible to dispose a capacitor immediately below the high-speed signal terminal of the LSI 300. Thus, the function of the capacitor provided immediately below is not required to have a high capacity, and the time required to compensate for the voltage drop is important, that is, it is important to be provided directly below as much as possible.

As such a capacitor, for example, a capacitance of 30 pF to 80 pF, preferably 50 pF to 80 pF is sufficient.

An enlarged view of such a capacitor is shown in FIG. As shown in FIG. 6A, the diameter φ1 of the via 4a provided in the insulator layer 4 is, for example, 150 μm to 250 μm, for example, 200 μm, and the diameter φ2 of the second electrode 11A is, for example, 100 μm to 150 μm. As an example, the diameter φ3 of the first electrode 3A was set to 100 μm to 200 μm, and as an example 150 μm.

The thickness d1 of the insulator layer 4 is, for example, 0.04 mm to 0.10 mm, for example, 0.05 mm, and the thickness d2 of the insulator layer 2 is, for example, 0.06 mm to 0.30 mm, for example. As 0.06 mm.

In such a capacitor, when a BTO thin film having a thickness of 0.06 μm to 1.0 μm is used as the high dielectric thin film 5, a capacitor of 50 to 80 pF can be realized with a yield of about 70%. Here again, the yield is the yield that did not break down due to 5 V or less. In this example, breakdown due to pinholes is eliminated, but the yield is 70% due to other process factors.

On the other hand, as a comparative example, a conventional capacitor is shown in FIG. Similarly, this capacitor has a similar high dielectric thin film 02 provided by sputtering on a first electrode 01 having a diameter of 150 μm, and a copper seed layer provided thereon by sputtering, followed by copper plating and patterning. The second electrode 03 having a diameter of 200 μm is provided.

In this case, the yield when 5V is applied is 30%. About 40% of the breakdown is due to pinhole breakdown.

(Modification 2)
In the capacitor-embedded substrates of

Embodiments

1 and 2 described above, a normal via terminal that uses a capacitor terminal containing a capacitor for compensating for a voltage drop for wiring of a mounted component in order to ensure the stability of the device. The semiconductor mounting component shown in FIG. 5 schematically shows an example of the semiconductor mounting component using the above-described capacitor-embedded substrate, and the structure shown in FIG. It cannot be said that the actual terminal structure is accurately shown.

For example, the basic configuration of the capacitor-embedded substrate may be the structure shown in FIG.
The structure shown in FIG. 7 includes a capacitor terminal 21 having the same structure as in the first and second embodiments. The capacitor terminal 21 includes a first electrode 21A, a high dielectric thin film 5, a melting temperature transition type solder layer 7, and a second electrode 21B, and a via terminal 22 serving as a ground wiring adjacent thereto. And a via terminal 23 serving as a power supply wiring. The via terminal 22 serving as the ground wiring is composed of a first via terminal 22A and a second via terminal 22B, and the first via terminal 22A is connected to the first electrode 21A of the capacitor terminal 21. The via terminal 23 serving as a power supply wiring is composed of a first via terminal 23A and a second via terminal 23B, and the second via terminal 23B is connected to the second electrode 21B of the capacitor terminal 21. .
Also, the via terminal 25 serving as a signal wiring is provided adjacent to the ground wiring, and includes a first via terminal 25A and a second via terminal 25B.

By adopting such a configuration, even when a voltage drop occurs, the voltage drop can be instantaneously compensated by the presence of the capacitor terminal 21, and a semiconductor device represented by LSI, WLP (Wafer Level Package), or the like can be used. It can cope with high speed.

This is because the high dielectric thin film can be reduced in size and thinned by using the capacitor built-in substrate incorporating the capacitor terminal of the present invention described in the first and second embodiments. This is because dielectric breakdown due to thin film pinholes can be prevented, and a capacitor can be built in a position adjacent to the signal wiring as much as possible. Therefore, as long as the capacitor built-in substrate of the present invention is such a capacitor built-in substrate incorporating the capacitor of the present invention, the arrangement of capacitors and the connection structure of capacitor terminals are not particularly limited.

Also, the terminal structure is not particularly limited, and a terminal having a built-in multilayer ceramic capacitor may be used. For example, the capacitor built-in substrate shown in FIG. 7 may have a structure in which a via terminal 25 serving as a signal wiring and a via terminal 23 serving as a power wiring are terminals incorporating a multilayer ceramic capacitor.

In the embodiment described above, the cross section of the via is displayed in a taper shape, but it may be formed in a shape close to a vertical shape instead of the taper shape, and the present invention is not limited to this. Further, the capacitor built-in substrate described above can be manufactured from the upper surface side to the lower surface side by changing the process, and the capacitor built-in substrate manufactured in this way is also the capacitor built-in substrate of the present invention. In this case, for example, the cross section of the via terminal in FIG. 7 looks like a taper in the opposite direction.

(Modification 3)
In the embodiment described above, an example in which the via terminal is formed by laminating at least two layers of conductors has been described. However, the via terminal structure may be formed using a laminated metal sheet in which a plurality of metal layers are laminated. Is possible.
Hereinafter, the manufacture example using a laminated metal sheet is shown. Although there are structural differences due to different starting materials, the basic configuration is the same as that of the above-described embodiment, and therefore, the same portions are denoted by the same reference numerals and redundant description is omitted.

FIG. 8 shows an example of a production example using a laminated metal sheet.
As shown in FIG. 8A, a laminated metal layer 60 comprising a first metal layer 61 made of copper, a second metal layer 62 made of nickel, and a third metal layer 63 made of copper is prepared. In this case, the first metal layer 61 is thicker than the third metal layer 63, but is not limited thereto. The second metal layer 62 made of nickel is not limited to nickel as long as it is a conductor having etching characteristics different from those of copper.

First, as shown in FIG. 8B, the first metal layer 61 is etched to form a plurality of wiring terminals. In this case, a capacitor forming terminal 61A and a ground wiring 61B are formed. A terminal 61C serving as a power wiring and a wiring terminal 61D serving as a signal wiring are illustrated.

Next, the terminal 31 and the wiring terminals 32A to 34A are embedded with the insulator layer 41 (FIG. 8C). Here, the insulator layer 41 is not particularly limited. For example, the insulator layer 41 may be formed using a resin composition (prepreg) containing a resin component and an inorganic filler such as silica or a filler such as acrylic rubber particles. A material having a coefficient of thermal expansion (CTE) as low as possible is preferable.

Next, the terminal 31 is removed by etching to form a recess 42 exposing the second metal layer 62 (FIG. 8D).

Thereafter, the high dielectric thin film 5 is provided so as to cover the second metal layer 62 in the recess 42 (FIG. 8E), and the resin composition 12 is applied so as to cover the high dielectric thin film 5 in the recess 42. Providing a defoaming step, detaching bubbles in the pinholes present in the high dielectric thin film 5, and filling the resin components to form the resin composition 12 in the pinholes (FIG. 8 (f)), Thereafter, the solder-containing resin composition 6 is filled in the recesses 42, a sedimentation process is performed to form a melting temperature transition type solder layer 7 (FIG. 8G), and the melting temperature transition type solder layer 7 is metallized. Then, the resin component of the resin composition 12 and the solder-containing resin composition 6 is cured at a temperature lower than the melting temperature MP of the conductor layer 8 to form the cured resin layer 9 (see FIG. 8 (h)) and the high dielectric thin film 5 on the surface of the insulator layer 4 is further removed. Both to planarize the cured resin layer 9 (FIG. 8 (i)) point is the same as in Embodiment 2.

Next, as shown in FIG. 8 (j), vias 9a are formed in the cured resin layer 9 in the recess 42 by laser processing or the like to expose the conductor layer 8. Then, as shown in FIG. 8K, via conductors 11 are embedded in the vias 9a by plating or the like, and wirings are formed at the same time. As a result, the first electrode 31A and the wiring terminals 32A to 34A to be the upper wiring are formed.

Next, as shown in FIG. 8L, the second metal layer 62 and the third metal layer 63 on the back surface side are patterned, and the conductor layer 1 is patterned by etching or the like to form external terminals. An electrode 31B and wiring terminals 32B to 34B are formed.

As a result, the capacitor terminal 31 containing the capacitor sandwiching the high dielectric thin film 5 between the first electrode 31A and the second electrode 31B and the wiring terminals 32 to 34 including the wiring terminal 32A and the wiring terminal 32B are formed. . Here, the wiring terminal 32 is a ground wiring, the wiring terminal 33 is a power supply wiring, and the wiring terminal 34 is a signal wiring.

FIG. 9 shows another example of a production example using a laminated metal sheet.
As shown in FIG. 9A, a laminated metal layer 60 comprising a first metal layer 61 made of copper, a second metal layer 62 made of nickel, and a third metal layer 63 made of copper is prepared. As shown in FIG. 9B, the first metal layer 61 is etched to form a recess 42 for forming a capacitor.

Thereafter, the high dielectric thin film 5 is provided so as to cover the second metal layer 62 in the recess 42 (FIG. 9C), and the resin composition 12 is applied so as to cover the high dielectric thin film 5 in the recess 42. Providing a defoaming step, detaching bubbles in the pinholes present in the high dielectric thin film 5, and filling the resin components forming the resin composition 12 in the pinholes (FIG. 9 (d)), Thereafter, the solder-containing resin composition 6 is filled in the recesses 42, a sedimentation process is performed to form the melting temperature transition type solder layer 7 (FIG. 9E), and the melting temperature transition type solder layer 7 is metallized. Then, the resin component of the resin composition 12 and the solder-containing resin composition 6 is cured at a temperature lower than the melting temperature MP of the conductor layer 8 to form the cured resin layer 9 (see FIG. 9 (f)), and when the high dielectric thin film 5 on the surface of the insulator layer 4 is removed, Moni cured resin layer 9 is planarized (FIG. 9 (g)) point is the same as the method of Embodiment 2, and FIG.
In this method, since only the laminated metal sheet 60 exists in the process of providing the high dielectric thin film 5, for example, there is an advantage that sputtering at a high temperature process of about 400 ° C. can be easily used.

Next, as shown in FIG. 9 (h), the first metal layer 61 is etched to leave the structure in the recess 42 and form terminals other than the terminals for capacitor formation. In this case, a terminal 61B serving as a ground wiring, a terminal 61C serving as a power wiring, and a wiring terminal 61D serving as a signal wiring are illustrated.

Next, the portion removed by the etching is embedded with an insulator layer 41 (FIG. 9 (i)). Next, as shown in FIG. 9 (j), a via 9a is laser-processed in the cured resin layer 9 in the recess 42. Etc. to expose the conductor layer 8. Then, as shown in FIG. 9K, via conductors 31 are embedded in the vias 9a by plating or the like, and wirings are formed at the same time. As a result, the first electrode 31A and the wiring terminals 32A to 34A to be the upper wiring are formed.

Next, as shown in FIG. 9L, the second metal layer 62 and the third metal layer 63 on the back surface side are patterned, and the conductor layer 1 is patterned by etching or the like to form external terminals. An electrode 31B and wiring terminals 32B to 34B are formed.

In the embodiment described with reference to FIG. 8 and FIG. 9, it is possible to manufacture from the upper surface side to the lower surface side by changing the process, and the capacitor-embedded substrate thus manufactured is also the capacitor-embedded substrate of the present invention. .

DESCRIPTION OF SYMBOLS 1 Conductor layer 2 Insulator layer 3 Via conductor 3A 1st electrode 3B Via terminal 4

Insulator layer

5, 5A, 5B High dielectric thin film 6 Solder containing resin composition 7 Melting temperature transition type solder layer 8 Conductor layer 9 Hardened resin layer 10 Insulator layer 11 Via conductor

11A Second electrode

11B Via terminal 12 Resin composition 50 Substrate with built-in capacitor 51 Pinhole 100 Motherboard 200 Package substrate 300 LSI (semiconductor mounting component)

Claims

Forming a first electrode (1);
Forming a high dielectric thin film on the first electrode (2);
A step (3) of providing a solder-containing resin composition containing a resin component and a melting temperature transition type solder on the high dielectric thin film and defoaming to fill the pinhole of the high dielectric thin film with the resin;
(4) forming a melting temperature transition type solder layer on the high dielectric thin film by precipitating the melting temperature transition type solder;
A step (5) of melting and alloying the melting temperature transition type solder layer to form a conductor layer having a remelting temperature of MP;
A step (6) of curing the resin component at a temperature lower than the melting temperature MP of the conductor layer to form a cured resin layer;
Forming a through hole in the cured resin layer to expose the conductor layer and forming a second electrode connected to the conductor layer (7). .
Forming a first electrode (1);
Forming a high dielectric thin film on the first electrode (2);
Providing a resin composition layer containing a first resin component on the high dielectric thin film and degassing to fill the pin hole of the high dielectric thin film with the first resin component (3-1);
Providing a solder-containing resin composition containing a second resin component and a melting temperature transition type solder on the resin composition layer (3-2);
(4) forming the melting temperature transition type solder layer on the high dielectric thin film by allowing the melting temperature transition type solder to settle into the resin composition layer;
A step (5) of melting and alloying the melting temperature transition type solder layer to form a conductor layer having a remelting temperature of MP;
A step (7) of curing the first resin component and the second resin component at a temperature lower than the melting temperature MP of the conductor layer to form a resin cured layer;
Forming a through hole in the cured resin layer to expose the conductor layer and forming a second electrode connected to the conductor layer (8). .
In claim 1 or 2,
A method for producing a capacitor, wherein the defoaming is performed at a temperature of room temperature to 160 ° C.
A step (11) of forming a plurality of via conductors provided penetrating through the first layer made of an insulator;
A step of forming a high dielectric thin film on the first electrode by covering a via conductor provided with a capacitor among the plurality of via conductors as a first electrode and covering another via conductor with a second layer made of an insulator. (12)
Providing a solder-containing resin composition containing a resin component and a melting temperature transition type solder on the high dielectric thin film and defoaming (13);
A step (14) of forming a melting temperature transition type solder layer on the high dielectric thin film by precipitating the melting temperature transition type solder;
A step (15) of melting and alloying the melting temperature transition type solder layer to form a conductor layer having a remelting temperature of MP;
A step (16) of curing the resin component at a temperature lower than the melting temperature MP of the conductor layer to form a cured resin layer;
Forming a through hole in the cured resin layer to expose the conductor layer and forming a second electrode made of a second via conductor connected to the conductor layer;
Forming a through hole in the second layer to expose the via conductor and providing a third via conductor connected to the via conductor (18). Production method.
A step (11) of forming a plurality of via conductors provided penetrating through the first layer made of an insulator;
A step of forming a high dielectric thin film on the first electrode by covering a via conductor provided with a capacitor among the plurality of via conductors as a first electrode and covering another via conductor with a second layer made of an insulator. (12)
Providing a resin composition layer containing a first resin component on the high dielectric thin film and defoaming (13-1);
Providing a solder-containing resin composition containing a second resin component and a melting temperature transition type solder on the resin composition layer (13-2);
A step (14) of forming the melting temperature transition type solder layer on the high dielectric thin film by allowing the melting temperature transition type solder to settle into the resin composition layer;
A step (15) of melting and alloying the melting temperature transition type solder layer to form a conductor layer having a remelting temperature of MP;
A step (16) of curing the first resin component and the second resin component at a temperature lower than the melting temperature MP of the conductor layer to form a resin cured layer;
Forming a through hole in the cured resin layer to expose the conductor layer and forming a second electrode made of a second via conductor connected to the conductor layer;
Forming a through hole in the second layer to expose the via conductor and providing a third via conductor connected to the via conductor (18). Production method.
In claim 4 or 5,
A method for producing a capacitor-embedded substrate, wherein the defoaming is performed at a temperature of room temperature to 160 ° C.
Etching the first metal layer of the laminated metal sheet in which a plurality of metal layers are laminated to form a plurality of wiring terminals;
Forming an insulating layer for embedding the wiring terminals (22);
A step (23) of removing a wiring terminal where a capacitor terminal for forming a capacitor from among the plurality of wiring terminals is to be formed and exposing a second metal layer under the wiring terminal as a first electrode; ,
Forming a high dielectric thin film covering at least the first electrode in the recess;
Providing a solder-containing resin composition containing a resin component and a melting temperature transition type solder on the high dielectric thin film and defoaming (25);
(26) a step of sinking the melting temperature transition type solder to form a melting temperature transition type solder layer on the high dielectric thin film;
A step (27) of melting and alloying the melting temperature transition type solder layer to form a conductor layer having a remelting temperature of MP;
A step (28) of curing the resin component at a temperature lower than the melting temperature MP of the conductor layer to form a cured resin layer;
Forming a through hole in the cured resin layer to expose the conductor layer and forming a second electrode made of a second conductor connected to the conductor layer (29). A method of manufacturing a capacitor built-in substrate.
A recess that exposes a second metal layer under the first metal layer as a first electrode by etching a first metal layer at a location where a capacitor terminal for providing a capacitor of a laminated metal sheet in which a plurality of metal layers are laminated is provided. Forming (31);
Forming a high dielectric thin film covering at least the first electrode in the recess;
Providing a solder-containing resin composition containing a resin component and a melting temperature transition type solder on the high dielectric thin film and defoaming (33);
A step (34) of forming a melting temperature transition type solder layer on the high dielectric thin film by precipitating the melting temperature transition type solder;
A step (35) of melting and alloying the melting temperature transition type solder layer to form a conductor layer having a remelting temperature of MP;
Curing the resin component at a temperature lower than the melting temperature MP of the conductor layer to form a resin cured layer (36);
Etching the first metal layer leaving the wiring layer other than the capacitor layer and the conductor layer and the resin cured layer in the recess; and
Forming the conductive layer and the cured resin layer, and an insulating layer for embedding the wiring terminal (38);
Forming a through hole in the cured resin layer to expose the conductor layer and forming a second electrode made of a second conductor connected to the conductor layer (38). A method of manufacturing a capacitor built-in substrate.
In claim 7 or 8,
A method for producing a capacitor-embedded substrate, wherein the defoaming is performed at a temperature of room temperature to 160 ° C.
A substrate with a built-in capacitor provided between a semiconductor package and a substrate on which the semiconductor package is mounted, a plurality of via terminals connecting the semiconductor package and the substrate, provided adjacent to the via terminals, and a capacitor And a built-in capacitor terminal.
The capacitor built-in terminal includes a first electrode, a high-dielectric thin film provided on the first electrode, a conductor layer made of molten transition type solder provided on the high-dielectric thin film, and the conductor A cured resin layer provided on the layer, and a second electrode made of a second via conductor provided in the through hole provided in the cured resin layer and penetrating until the conductive layer is exposed. A capacitor-embedded substrate.
In claim 10,
The via terminal is connected to the via conductor passing through the first layer made of an insulator and the second layer made of the cured resin layer provided on the first layer. A capacitor built-in substrate comprising a second via conductor.
In claim 10 or 11,
The capacitor-embedded substrate, wherein the first electrode includes the via conductor provided through a first layer made of an insulator.
In claim 10 or 11,
The substrate with a built-in capacitor, wherein the first electrode includes the via conductor provided through the resin cured layer provided on the first layer made of an insulator.
In any one of claims 10 to 13,
The conductor layer is made of a melt transition type solder formed by precipitating a solder-containing resin composition containing a resin component and a melting temperature transition type solder, and the cured resin layer is a resin component of the solder-containing resin composition A capacitor-embedded substrate, wherein a pinhole of the high dielectric thin film is filled with a resin component of the solder-containing resin composition.
A capacitor built-in substrate having a signal wiring terminal and a capacitor built-in terminal provided adjacent to the signal wiring terminal,
The capacitor built-in terminal includes a first electrode, a high dielectric thin film provided on the first electrode, a solder-containing resin provided on the high dielectric thin film and including a resin component and a melting temperature transition type solder. A conductor layer made of a molten transition type solder formed by settling the composition, a resin cured layer provided on the conductor layer and cured with a resin component of the solder-containing resin composition, and the resin cured layer And a second electrode made of a second via conductor provided in a through-hole penetrating until the conductor layer is exposed, and the solder-containing resin is provided in the pinhole of the high dielectric thin film A capacitor-embedded substrate, wherein the resin component of the composition is filled.
A semiconductor device mounting component comprising the capacitor built-in substrate according to any one of claims 10 to 15 and the semiconductor package mounted on the capacitor built-in substrate.
The semiconductor device mounting component according to claim 16, wherein the capacitor built-in substrate is mounted on the substrate.