KR101300318B1 - Printed circuit board and method of manufacturing a printed circuit board - Google Patents

Abstract

The present invention relates to a printed circuit board and a method of manufacturing a printed circuit board.
According to an embodiment of the present invention, an inner circuit layer is formed on a base substrate on which an inner circuit layer is formed, a base substrate and an inner circuit layer, and is formed on an outer circuit layer and an outer circuit layer including an outer connection pad and an outer circuit pattern, and an outer layer connection. A printed circuit board including a solder resist including an opening exposing the pad, a metal pad formed on the upper and outer layer connection pads, a surface treatment layer formed on the metal pad, and a bump formed on the surface treatment layer and the solder resist This is provided.

Description

Printed circuit board and printed circuit board manufacturing method {PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING A PRINTED CIRCUIT BOARD}

The present invention relates to a printed circuit board and a method of manufacturing a printed circuit board.

An external device such as a semiconductor chip may be mounted on the printed circuit board. As described above, in order to mount the external device on the printed circuit board, a solder resist formed to expose the connection pad and the connection pad upper part for mounting the external device may be formed on the outermost layer of the printed circuit board. Bumps are formed on the exposed connection pads, and external devices are mounted on the printed circuit board by the bumps, and electrically connected to each other. (Japanese Patent Laid-Open No. 2004-345904)

At this time, when the depth of the opening in which the bump is formed is deep, pores may be introduced when printing the solder paste for forming the bump. Thereafter, the pores introduced during the high temperature reflow process to expand the bumps are expanded between the connection pads and the bumps of the openings. As the pores expand, bumps may be separated from the connection pads. In particular, when the surface treatment layer is formed on the connection pad by the electroless tin plating and the organic film coating method, which is a low cost surface treatment method, the thickness of the surface treatment layer is about 0.1 to 2 um. On the other hand, the surface treatment layer by the expensive nickel or gold plating is formed thick to about 5 ~ 20um. That is, since the surface treatment layer by the low cost electroless tin plating and the organic film coating is thinner than the surface treatment layer by the expensive nickel or gold plating, it is necessary to form relatively thicker bumps. Therefore, when the inexpensive surface treatment layer is formed, the bump separation problem may be serious compared to the expensive surface treatment layer.

The present invention is to provide a printed circuit board and a printed circuit board manufacturing method that can prevent the separation of the bump by forming a thick metal pad.

The present invention is to provide a printed circuit board and a printed circuit board manufacturing method capable of supplying a high capacity current by selectively forming a thick circuit pattern.

The present invention is to provide a printed circuit board and a printed circuit board manufacturing method that can ensure the flatness of the solder resist by forming a thick solder resist.

The present invention is to provide a printed circuit board and a printed circuit board manufacturing method that can prevent the mounting failure of the external device by ensuring the flatness of the solder resist.

According to an aspect of the present invention, an inner circuit layer is formed on the base substrate, the base substrate and the inner circuit layer formed on the outer circuit layer, the outer circuit layer including an outer connection pad and the outer circuit pattern, the outer circuit layer is formed on the outer layer connection A printed circuit board including a solder resist including an opening exposing the pad, a metal pad formed on the upper and outer layer connection pads, a surface treatment layer formed on the metal pad, and a bump formed on the surface treatment layer and the solder resist This is provided.

The upper portion of the metal pad may be formed inside the opening.

The metal pad may be formed of copper.

The surface treatment layer may be formed of Organic Solder ability Preservative (OSP) or Immersion Tin or Immersion Sn (OSN).

According to another aspect of the present invention, an inner circuit layer is formed on a base substrate on which an inner circuit layer is formed, a base substrate and an inner circuit layer, and is formed on an outer circuit layer, an outer circuit layer including an outer connection pad and an outer circuit pattern, and an outer layer connection. A first solder resist having a first opening for exposing the pad, an upper surface of the outer layer connection pad and a first opening, and a first metal pad formed to protrude from the top of the first solder resist, and a surface treatment formed on the first metal pad A printed circuit board comprising a layer, a second solder resist formed on the first solder resist and having a second opening to expose the surface treatment layer, and a bump formed on the surface treatment layer and the second solder resist are provided.

The first metal pad may be formed of copper.

The surface treatment layer may be formed of Organic Solder ability Preservative (OSP) or Immersion Tin or Immersion Sn (OSN).

The semiconductor device may further include a second metal pad formed on the outer circuit pattern.

The second metal pad may be formed of copper.

According to another aspect of the invention, preparing a base substrate having an inner circuit layer, forming an outer circuit layer including an outer layer connection pad and an outer layer circuit pattern on the inner layer circuit layer, solder on the outer layer circuit layer Forming a resist, forming an opening in the solder resist so that the top of the outer layer connection pad is exposed, forming a metal pad on the exposed outer layer connection pad, forming a surface treatment layer on the metal pad and the surface Provided is a method of manufacturing a printed circuit board including forming a bump on an upper portion of a processing layer.

In the step of forming the metal pad, the metal pad may be formed of copper.

In the step of forming the surface treatment layer, the surface treatment layer may be formed of Organic Solder ability Preservative (OSP) or Immersion Tin or Immersion Sn (OSN).

According to another aspect of the invention, preparing a base substrate having an inner circuit layer, forming an outer circuit layer including an outer layer connection pad and an outer circuit pattern on the inner circuit layer, the upper layer circuit layer 1 forming a solder resist, forming a first opening in the first solder resist to expose the top of the outer layer connection pad, forming a first metal pad formed on the exposed outer layer connection pad and protruding from the first solder resist Forming a second solder resist on top of the first solder resist, forming a second opening in the second solder resist to expose the top of the first metal pad, surface treatment on the exposed first metal pad Provided is a method of manufacturing a printed circuit board comprising forming a layer and forming a bump on the surface treatment layer.

In the step of forming the first metal pad, the first metal pad may be formed of copper.

In the step of forming the surface treatment layer, the surface treatment layer may be formed of Organic Solder ability Preservative (OSP) or Immersion Tin or Immersion Sn (OSN).

After forming the first solder resist sheet, the method may further include forming a second opening in the first solder resist to expose the upper portion of the outer circuit pattern.

After forming the second opening, the method may further include forming a second metal pad formed on the exposed outer circuit pattern and protruding from the first solder resist.

The features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings.

Prior to that, terms and words used in the present specification and claims should not be construed in a conventional and dictionary sense, and the inventor may properly define the concept of the term in order to best explain its invention It should be construed as meaning and concept consistent with the technical idea of the present invention.

The printed circuit board and the method of manufacturing the printed circuit board according to the embodiment of the present invention can prevent the bump from leaving.

In addition, the printed circuit board and the method of manufacturing the printed circuit board according to the embodiment of the present invention can selectively conduct a high capacity current by forming a thick circuit pattern.

In addition, the printed circuit board and the method of manufacturing the printed circuit board according to the embodiment of the present invention can ensure the flatness of the solder resist by forming a thick solder resist.

In addition, the printed circuit board and the method of manufacturing the printed circuit board according to the embodiment of the present invention can prevent the mounting failure of the external device by ensuring the flatness of the solder resist.

1 is an exemplary view showing a printed circuit board according to an embodiment of the present invention.
2 to 8 are exemplary views showing a printed circuit board manufacturing method according to an embodiment of the present invention.
9 is an exemplary view illustrating a printed circuit board according to another exemplary embodiment of the present invention.
10 to 18 are diagrams illustrating a method of manufacturing a printed circuit board according to another exemplary embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The objectives, specific advantages and novel features of the present invention will become more apparent from the following detailed description and examples taken in conjunction with the accompanying drawings. It should be noted that, in the present specification, the reference numerals are added to the constituent elements of the drawings, and the same constituent elements are assigned the same number as much as possible even if they are displayed on different drawings.

In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. In this specification, the terms first, second, etc. are used to distinguish one element from another, and the element is not limited by the terms.

Hereinafter, a printed circuit board and a method of manufacturing the printed circuit board according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is an exemplary view showing a printed circuit board according to an embodiment of the present invention.

The printed circuit board according to the embodiment of the present invention includes a base substrate 110, a first inner circuit layer 123, a second inner circuit layer 126, a first insulating layer 131, and a second insulating layer 132. The first outer circuit layer 143, the second outer circuit layer 146, the first solder resist 151, the second solder resist 152, the first metal pad 161, the second metal pad 162, The first surface treatment layer 171, the second surface treatment layer 172, and the bump 180 may be included.

The base substrate 110 may be formed of a rigid material capable of supporting the printed circuit board on which the base substrate 110 is built up. For example, the base substrate 110 may be a metal plate or an insulating material. Here, the metal plate may be a copper foil, and the insulating material may be made of a composite polymer resin. Alternatively, the base substrate 110 can easily implement a microcircuit using an ABF (Ajinomoto Build up Film) or a printed circuit board can be made thin by employing a prepreg. However, the present invention is not limited thereto, and the base substrate 110 may be formed of a hard insulating material including an epoxy resin or a modified epoxy resin, a bisphenol A resin, an epoxy-novolak resin, an aramid reinforced glass fiber reinforced or paper reinforced epoxy resin. Can be formed.

The base substrate 110 may include through vias 111. The through via 111 may be formed to perform electrical connection between the first inner layer circuit layer 123 and the second inner layer circuit layer 126 formed on both sides of the base substrate 110. The through via 111 may be formed by plating with electrolytic plating. Alternatively, the through via 111 may be formed by filling with a conventional conductive paste.

The first inner circuit layer 123 may be formed on the base substrate 110. The first inner layer circuit layer 123 may be formed of a conductive metal, and may include, for example, at least one of gold, silver, nickel, aluminum, copper, and alloys thereof. The first inner layer circuit layer 123 may include a first inner layer circuit pattern 121 and a first inner layer connection pad 122. Here, the first inner layer connection pad 122 may be formed on the through via 111 and electrically connected to the through via 111.

The second inner circuit layer 126 may be formed under the base substrate 110. The second inner circuit layer 126 may be formed of a conductive metal like the first inner circuit layer 123. The second inner layer circuit layer 126 may include a second inner layer circuit pattern 124 and a second inner layer connection pad 125. Here, the second inner layer connection pad 125 may be formed under the through via 111 to be electrically connected to the through via 111.

 The first insulating layer 131 may be formed on the first inner layer circuit layer 123. The first insulating layer 131 may be formed to include an opening formed on the first inner layer connection pad 122 to expose the first inner layer connection pad 122. The first insulating layer 131 may be formed of a conventional composite polymer resin. That is, the first insulating layer 131 may be formed of a conventional epoxy resin or fluorine resin.

The second insulating layer 132 may be formed on the second inner circuit layer 126. The second insulating layer 132 may be formed to include an opening formed on the second inner layer connection pad 125 to expose the second inner layer connection pad 125. The second insulating layer 132 may be formed of a conventional composite polymer resin. That is, the second insulating layer 132 may be formed of a conventional epoxy resin or fluorine resin.

The first outer circuit layer 143 may be formed on the first insulating layer 131. The first outer circuit layer 143 may include a first outer circuit pattern 141 and a first outer layer via 142. Here, the first outer layer via 142 may be formed for electrical connection between the first inner layer circuit layer 123 and the first outer layer circuit layer 143. That is, the first outer layer via 142 may be formed in the opening formed in the first insulating layer 131, and thus may be formed on the first inner layer connection pad 122. The first outer circuit layer 143 may be formed by performing electroplating. The first outer layer circuit layer 143 may include a conductive metal. For example, the first outer circuit layer 143 may include at least one of gold, silver, nickel, aluminum, copper, and alloys thereof.

The second outer circuit layer 146 may be formed on the second insulating layer 132. The second outer layer circuit layer 146 may include a second outer layer circuit pattern 144 and a second outer layer connection pad 145. The second outer circuit layer 146 may be formed by performing electroplating. The second outer layer circuit layer 146 may be formed including a conductive metal.

The first solder resist 151 may be formed on the first outer circuit layer 143.

The first solder resist 151 may be formed to protect the first outer circuit layer 143 from an external material such as solder or the like and to prevent oxidation. The first solder resist 151 may be formed to expose the first outer layer via 142 on which solder is to be performed. That is, the first solder resist 151 may be formed to cover the first outer circuit layer 143 and include an opening formed on the first outer via 142.

The second solder resist 152 may be formed on the second outer circuit layer 146.

The second solder resist 152 may be formed to protect the second outer circuit layer 146 from an external material such as solder or the like and to prevent oxidation. The second solder resist 152 may be formed to expose the second outer connection pad 145. That is, the second solder resist 152 may be formed to cover the second outer layer circuit layer 146, and include an opening formed on the second outer layer connection pad 145.

The first metal pad 161 may be formed on the first outer layer via 142. The first metal pad 161 may be formed including a conductive metal. For example, the first metal pad 161 may be formed to include at least one of gold, silver, nickel, aluminum, copper, and alloys thereof. In an embodiment of the present invention, the first metal pad 161 may be formed of copper. For example, the first metal pad 161 may be formed to have a thickness of 1 to 20 μm through electrolytic plating. As such, the first metal pad 161 having a thickness of about 1 μm to about 20 μm may be formed so as not to protrude out of the first solder resist 151.

The second metal pad 162 may be formed on the second outer layer connection pad 145. The second metal pad 162 may include a conductive metal. In addition, the second metal pad 162 may be formed to have a thickness of about 1 μm to about 20 μm, for example, through electrolytic plating. As such, the second metal pad 162 having a thickness of about 1 μm to about 20 μm may be formed so as not to protrude out of the second solder resist 152.

The first surface treatment layer 171 may be formed on the first metal pad 161. The first surface treatment layer 171 may be formed to prevent the first metal pad 161 from being oxidized. The first surface treatment layer 171 may be formed of Immersion Tin or Immersion Sn. In this case, the first surface treatment layer 171 may be formed by an electroless plating method. In addition, the first surface treatment layer 171 may be formed by an organic solder ability preservative (OSP) method. The organic film coating method is a method of forming an organic compound in the form of alkyl imidazole (Alkyl Imidazole) on the first metal pad 161.

The second surface treatment layer 172 may be formed on the second metal pad 162. The second surface treatment layer 172 may be formed to prevent the second metal pad 162 from being oxidized. The second surface treatment layer 172 may be formed of Immersion Tin or Immersion Sn. In this case, the second surface treatment layer 172 may be formed by an electroless tin plating method. In addition, the second surface treatment layer 172 may be formed by an organic solder ability preservative (OSP) method.

The bump 180 may be formed on the first surface treatment layer 171. The bump 180 may be formed to mount or electrically connect an external device such as a semiconductor chip to a printed circuit board. The bump 180 may be formed by performing a high temperature reflow process after the solder paste is applied.

2 to 8 are exemplary views showing a printed circuit board manufacturing method according to an embodiment of the present invention.

Referring to FIG. 2, a base substrate 110 on which inner circuit layers 123 and 126 are formed is provided.

The base substrate 110 may be made of a hard material that can support the printed circuit board to be built up. For example, the base substrate 110 may be a metal plate or an insulating material. Here, the metal plate may be a copper foil, and the insulating material may be made of a composite polymer resin. Alternatively, the base substrate 110 can easily implement a microcircuit using an ABF (Ajinomoto Build up Film) or a printed circuit board can be made thin by employing a prepreg. However, the present invention is not limited thereto, and the base substrate 110 may be formed of a hard insulating material including an epoxy resin or a modified epoxy resin, a bisphenol A resin, an epoxy-novolak resin, an aramid reinforced glass fiber reinforced or paper reinforced epoxy resin. Can be formed.

The base substrate 110 may include through vias 111. The through vias 111 may be formed to perform electrical connection between the inner circuit layers 123 and 126 formed on both sides of the base substrate 110. The through via 111 may be formed by plating with electrolytic plating. Alternatively, the through via 111 may be formed by filling with a conventional conductive paste.

The first inner layer circuit layer 123 may be formed on the base substrate 110. The first inner layer circuit layer 123 may be formed by performing electroplating. The first inner layer circuit layer 123 may be formed of a conductive metal, and may include, for example, at least one of gold, silver, nickel, aluminum, copper, and alloys thereof. The first inner layer circuit layer 123 may include a first inner layer circuit pattern 121 and a first inner layer connection pad 122. Here, the first inner layer connection pad 122 may be formed on the through via 111 and electrically connected to the through via 111.

In addition, a second inner layer circuit layer 126 may be formed under the base substrate 110. The second inner layer circuit layer 126 may include a second inner layer circuit pattern 124 and a second inner layer connection pad 125. The second inner layer connection pad 125 may be formed under the through via 111 and electrically connected to the through via 111. The second inner circuit layer 126 may be formed in the same manner as the first inner circuit layer 123.

As described above, the first inner layer circuit layer 123 is formed on the base substrate 110, and the second inner layer circuit layer 126 is formed on the lower portion of the base substrate 110, and then the first insulating layer 131 and the second insulating layer 132 are formed. This can be formed.

That is, the first insulating layer 131 may be formed on the first inner circuit layer 123, and the second insulating layer 132 may be formed on the second inner circuit layer 126.

The first insulating layer 131 and the second insulating layer 132 may be formed of a conventional composite polymer resin. That is, the first insulating layer 131 and the second insulating layer 132 may be formed of a conventional epoxy resin or fluorine resin.

Referring to FIG. 3, the outer circuit layers 143 and 146 may be formed on the insulating layers 131 and 132.

The first outer circuit layer 143 may be formed on the first insulating layer 131. The first outer circuit layer 143 may include a first outer circuit pattern 141 and a first outer layer via 142. Here, the first outer layer via 142 may be formed for electrical connection between the first inner layer circuit layer 123 and the first outer layer circuit layer 143. That is, the first outer layer via 142 may be formed on the first inner layer connection pad 122 through the first insulating layer 131. The first outer circuit layer 143 may be formed by performing electroplating. The first outer layer circuit layer 143 may include a conductive metal. For example, the first outer circuit layer 143 may include at least one of gold, silver, nickel, aluminum, copper, and alloys thereof.

The second outer circuit layer 146 may be formed on the second insulating layer 132. The second outer layer circuit layer 146 may include a second outer layer circuit pattern 144 and a second outer layer connection pad 145. The second outer circuit layer 146 may be formed in the same manner as the first outer circuit layer 143.

Referring to FIG. 4, solder resists 151 and 152 may be formed on the outer circuit layers 143 and 146. The first solder resist 151 may be formed on the first outer circuit layer 143 to surround the first outer circuit layer 143. In addition, a second solder resist 152 may be formed on the second outer circuit layer 146 to surround the second outer circuit layer 146.

Referring to FIG. 5, openings 153 and 154 may be formed in the solder resists 151 and 152.

The first opening 153 may be formed in the first solder resist 151 formed on the first outer circuit layer 143. The first opening 153 may be formed to expose an upper portion of the first outer via 142 of the first outer circuit layer 143. The first opening 153 may be formed using a mechanical drill or a laser drill.

In addition, a second opening 154 may be formed in the second solder resist 152 formed on the second outer circuit layer 146. The second opening 154 may be formed to expose the upper portion of the second outer layer connection pad 145 of the second outer layer circuit layer 146. Like the first opening 153, the second opening 154 may be formed using a mechanical drill or a laser drill.

Referring to FIG. 6, metal pads 161 and 162 may be formed on the outer circuit layers 143 and 146.

The first metal pad 161 may be formed on the first outer layer via 142 exposed by the first opening 153. The first metal pad 161 may be formed including a conductive metal. For example, the first metal pad 161 may be formed to include at least one of gold, silver, nickel, aluminum, copper, and alloys thereof. In an embodiment of the present invention, the first metal pad 161 may be formed of copper. Here, the first metal pad 161 may be formed by electroplating. In addition, the first metal pad 161 may be formed to have, for example, a thickness of about 1 μm to about 20 μm. As described above, the first metal pad 161 having a thickness of 1 μm to 20 μm is formed in the first opening 153 and does not protrude to the outside of the first solder resist 151.

The second metal pad 162 may be formed on the second outer layer connection pad 145 exposed by the second opening 154. The second metal pad 162 may also be formed in the same manner as the first metal pad 161.

Referring to FIG. 7, surface treatment layers 171 and 172 may be formed on the metal pads 161 and 162. The surface treatment layers 171 and 172 are formed to prevent the metal pads 161 and 162 from being oxidized.

The first surface treatment layer 171 may be formed on the first metal pad 161. The first surface treatment layer 171 may be formed of Immersion Tin or Immersion Sn. In this case, the first surface treatment layer 171 may be formed by an electroless plating method. In addition, the first surface treatment layer 171 may be formed by an organic solder ability preservative (OSP) method. The organic film coating method is a method of forming an organic compound in the form of alkyl imidazole (Alkyl Imidazole) on the first metal pad 161.

The second surface treatment layer 172 may be formed on the second metal pad 162. Similarly to the first surface treatment layer 171, the second surface treatment layer 172 may be formed using an electroless plating method using tin or an organic film coating method.

Referring to FIG. 8, bumps 180 may be formed on the metal pads 161 and 162. The bump 180 may be formed by applying a solder paste on the first metal pad 161 and then performing a reflow process. The bump 180 may be formed to mount or electrically connect an external device such as a semiconductor chip to a printed circuit board.

According to an exemplary embodiment of the present invention, a bump dropout phenomenon may be prevented by forming a thick metal pad on the connection pad or the outer layer via. In addition, according to an embodiment of the present invention, even when the surface treatment layer formed on the connection pad or the outer layer via is thinly formed, bump dropout may be prevented.

9 is an exemplary view illustrating a printed circuit board according to another exemplary embodiment of the present invention.

According to another exemplary embodiment of the present invention, a printed circuit board may include a base substrate 210, a first inner circuit layer 223, a second inner circuit layer 225, a first insulation layer 231, and a second insulation layer 232. ), The first outer circuit layer 243, the second outer circuit layer 246, the first solder resist 251, the second solder resist 252, the first metal pad 261, and the second metal pad 262. , The third metal pad 263, the first surface treatment layer 281, the second surface treatment layer 282, the third solder resist 271, the fourth solder resist 272, the first bump 291 and the first It may include two bumps 292.

The base substrate 210 may be formed of a rigid material capable of supporting the printed circuit board on which the base substrate 210 is built up. For example, the base substrate 210 may be a metal plate or an insulating material. Here, the metal plate may be a copper foil, and the insulating material may be made of a composite polymer resin. Alternatively, the base substrate 210 may adopt an Ajinomoto Build up Film (ABF) to easily implement a fine circuit or may employ a prepreg to manufacture a printed circuit board thinly. However, the present invention is not limited thereto, and the base substrate 210 may be formed of a hard insulating material including an epoxy resin or a modified epoxy resin, a bisphenol A resin, an epoxy-novolak resin, an aramid reinforced glass fiber reinforced or paper reinforced epoxy resin. Can be formed.

The base substrate 210 may include through vias 211. The through via 211 may be formed to perform electrical connection between the first inner circuit layer 223 and the second inner circuit layer 225 formed on both sides of the base substrate 210. The through via 211 may be plated by electroplating. Alternatively, the through via 211 may be formed by filling with a conventional conductive paste.

The first inner circuit layer 223 may be formed on the base substrate 210. The first inner layer circuit layer 223 may be formed of a conductive metal, and may include, for example, at least one of gold, silver, nickel, aluminum, copper, and alloys thereof. The first inner layer circuit layer 223 may include a first inner layer circuit pattern 221 and a first inner layer connection pad 222. Here, the first inner layer connection pad 222 may be formed on the through via 211 and electrically connected to the through via 211.

The second inner circuit layer 225 may be formed under the base substrate 210. The second inner circuit layer 225 may be formed of a conductive metal like the first inner circuit layer 223. The second inner layer circuit layer 225 may include a second inner layer circuit pattern 224 and a second inner layer connection pad 225. Here, the second inner layer connection pad 225 may be formed under the through via 211 to be electrically connected to the through via 211.

 The first insulating layer 231 may be formed on the first inner circuit layer 223. The first insulating layer 231 may be formed to include an opening formed on the first inner layer connection pad 222 so that the first inner layer connection pad 222 is exposed. The first insulating layer 231 may be formed of a conventional composite polymer resin. That is, the first insulating layer 231 may be formed of a conventional epoxy resin or fluorine resin.

The second insulating layer 232 may be formed on the second inner layer circuit layer 225. The second insulating layer 232 may be formed to include an opening formed on the second inner layer connection pad 225 so that the second inner layer connection pad 225 is exposed. The second insulating layer 232 may be formed of a conventional composite polymer resin. That is, the second insulating layer 232 may be formed of a conventional epoxy resin or fluorine resin.

The first outer circuit layer 243 may be formed on the first insulating layer 231. The first outer circuit layer 243 may include a first outer circuit pattern 241 and a second outer layer via 242. Here, the second outer layer via 242 may be formed for electrical connection between the first inner layer circuit layer 223 and the first outer layer circuit layer 243. That is, the second outer layer via 242 may be formed in the opening formed in the first insulating layer 231, and thus may be formed on the first inner layer connection pad 222. The first outer circuit layer 243 may be formed by performing electroplating. The first outer circuit layer 243 may be formed of a conductive metal. For example, the first outer layer circuit layer 243 may be formed to include at least one of gold, silver, nickel, aluminum, copper, and alloys thereof.

The second outer circuit layer 246 may be formed on the second insulating layer 232. The second outer layer circuit layer 246 may include a second outer layer circuit pattern 244 and a second outer layer connection pad 245. The second outer circuit layer 246 may be formed by performing electroplating. The second outer circuit layer 246 may be formed of a conductive metal.

The first solder resist 251 may be formed on the first outer circuit layer 243.

The first solder resist 251 may be formed to expose the second outer layer via 242. That is, the first solder resist 251 may be formed to cover the first outer circuit layer 243, and may include an opening formed on the second outer via via 242.

The second solder resist 252 may be formed on the second outer circuit layer 246.

The second solder resist 252 may be formed to expose the second outer layer connection pad 245. In addition, the second solder resist 252 may be formed to expose the second outer circuit pattern 244. Here, the second outer layer circuit pattern 244 may be a circuit pattern through which a large capacity electric signal is energized.

The first metal pad 261 may be formed on the second outer layer via 242. The first metal pad 261 may be formed including a conductive metal. For example, the first metal pad 261 may be formed to include at least one of gold, silver, nickel, aluminum, copper, and alloys thereof. In an embodiment of the present invention, the first metal pad 261 may be formed of copper. For example, the first metal pad 261 may be formed to have a thickness of 1 to 100 μm through electrolytic plating. As such, the first metal pad 261 having a thickness of about 1 μm to about 100 μm may be formed to protrude out of the first solder resist 251.

The second metal pad 262 may be formed on the second outer layer connection pad 245. The second metal pad 262 may include a conductive metal. For example, the second metal pad 262 may be formed to have a thickness of 1 to 100 μm through electrolytic plating. As such, the second metal pad 262 having a thickness of about 1 μm to about 100 μm may be formed to protrude out of the second solder resist 252.

The third metal pad 263 may be formed on the second outer layer circuit pattern 244. The third metal pad 263 may be formed including a conductive metal. For example, the third metal pad 263 may be formed to have a thickness of 1 to 100 μm through electrolytic plating. As such, the third metal pad 263 having a thickness of about 1 μm to about 100 μm may be formed to protrude out of the third solder resist 271.

The first surface treatment layer 281 may be formed on the first metal pad 261. The first surface treatment layer 281 may be formed to prevent the first metal pad 261 from being oxidized. The first surface treatment layer 281 may be formed of Immersion Tin or Immersion Sn. In this case, the first surface treatment layer 281 may be formed by an electroless plating method. In addition, the first surface treatment layer 281 may be formed by an organic solder ability preservative (OSP) method. The organic film coating method is a method of forming an organic compound in the form of alkyl imidazole (Alkyl Imidazole) on the first metal pad 261.

The second surface treatment layer 282 may be formed on the second metal pad 262. The second surface treatment layer 282 may be formed to prevent the second metal pad 262 from being oxidized. The second surface treatment layer 282 may be formed of electroless tin (Immersion Tin or Immersion Sn). In this case, the second surface treatment layer 282 may be formed by an electroless tin plating method. In addition, the second surface treatment layer 282 may be formed by an organic solder ability preservative (OSP) method.

The third solder resist 271 may be formed on the first solder resist 251 and the first surface treatment layer 281.

By forming the third solder resist 271 on the first solder resist 251, a thick solder resist can be formed. As described above, the first bump 291 formed later by the thick solder resist may be stably formed. In addition, by forming the third solder resist 271 on the first solder resist 251, which may become uneven depending on the conductor area of the first outer circuit layer 243, the flatness of the solder resist may be secured. . As a result, mounting failure of an external device such as a semiconductor chip can be minimized.

The fourth solder resist 272 may be formed on the second solder resist 252 and the second surface treatment layer 282.

By forming the fourth solder resist 272 on the second solder resist 252, a thick solder resist may be formed. As described above, the second bump 292 formed later by the thick solder resist may be stably formed. In addition, by forming the fourth solder resist 272 on the second solder resist 252, which may become uneven depending on the conductor area of the second outer circuit layer 246, the flatness of the solder resist may be secured. . As a result, mounting defects of an external device such as a semiconductor chip can be minimized. In addition, the fourth solder resist 272 is formed on the third metal pad 263, so that the third metal pad 263 is formed to protrude out of the second solder resist 252 from an external material such as solder or the like. Protects and prevents oxidation.

The first bump 291 may be formed on the first surface treatment layer 281. The first bump 291 may be formed to mount or electrically connect an external device such as a semiconductor chip to a printed circuit board. The first bump 291 may be formed by performing a high temperature reflow process after the solder paste is applied.

The second bump 292 may be formed on the second surface treatment layer 282. The second bump 292 may be formed to mount or electrically connect an external device such as a semiconductor chip to a printed circuit board. The second bump 292 may be formed by performing a high temperature reflow process after the solder paste is applied.

10 to 18 are diagrams illustrating a method of manufacturing a printed circuit board according to another exemplary embodiment of the present invention.

Referring to FIG. 10, a base substrate 210 on which inner circuit layers 223 and 226 are formed is provided.

The base substrate 210 may be made of a hard material that can support the printed circuit board to be built up. For example, the base substrate 210 may be a metal plate or an insulating material. Here, the metal plate may be a copper foil, and the insulating material may be made of a composite polymer resin. Alternatively, the base substrate 210 may adopt an Ajinomoto Build up Film (ABF) to easily implement a fine circuit or may employ a prepreg to manufacture a printed circuit board thinly. However, the present invention is not limited thereto, and the base substrate 210 may be formed of a hard insulating material including an epoxy resin or a modified epoxy resin, a bisphenol A resin, an epoxy-novolak resin, an aramid reinforced glass fiber reinforced or paper reinforced epoxy resin. Can be formed.

The base substrate 210 may include through vias 211. The through via 211 may be formed to perform electrical connection between the inner circuit layers 223 and 226 formed on both sides of the base substrate 210. The through via 211 may be plated by electroplating. Alternatively, the through via 211 may be formed by filling with a conventional conductive paste.

The first inner layer circuit layer 223 may be formed on the base substrate 210. The first inner layer circuit layer 223 may be formed by performing electroplating. The first inner layer circuit layer 223 may be formed of a conductive metal, and may include, for example, at least one of gold, silver, nickel, aluminum, copper, and alloys thereof. The first inner layer circuit layer 223 may include a first inner layer circuit pattern 221 and a first inner layer connection pad 222. Here, the first inner layer connection pad 222 may be formed on the through via 211 and electrically connected to the through via 211.

In addition, a second inner circuit layer 225 may be formed under the base substrate 210. The second inner layer circuit layer 225 may include a second inner layer circuit pattern 224 and a second inner layer connection pad 225. The second inner layer connection pad 225 may be formed under the through via 211 to be electrically connected to the through via 211. The second inner circuit layer 225 may be formed in the same manner as the first inner circuit layer 223.

As such, after the first inner circuit layer 223 is formed on the base substrate 210 and the second inner circuit layer 225 is formed on the lower portion of the base substrate 210, the first insulating layer 231 and the second insulating layer 232 are formed. This can be formed.

That is, the first insulating layer 231 may be formed on the first inner circuit layer 223, and the second insulating layer 232 may be formed on the second inner circuit layer 225.

The first insulating layer 231 and the second insulating layer 232 may be formed of a conventional composite polymer resin. That is, the first insulating layer 231 and the second insulating layer 232 may be formed of a conventional epoxy resin or fluorine resin.

Referring to FIG. 11, outer circuit layers 243 and 246 may be formed on the insulating layers 231 and 232.

The first outer circuit layer 243 may be formed on the first insulating layer 231. The first outer circuit layer 243 may include a first outer circuit pattern 241 and a second outer layer via 242. Here, the second outer layer via 242 may be formed for electrical connection between the first inner layer circuit layer 223 and the first outer layer circuit layer 243. That is, the second outer layer via 242 may be formed on the first inner layer connection pad 222 through the first insulating layer 231. The first outer circuit layer 243 may be formed by performing electroplating. The first outer circuit layer 243 may be formed of a conductive metal. For example, the first outer layer circuit layer 243 may be formed to include at least one of gold, silver, nickel, aluminum, copper, and alloys thereof.

The second outer circuit layer 246 may be formed on the second insulating layer 232. The second outer layer circuit layer 246 may include a second outer layer circuit pattern 244 and a second outer layer connection pad 245. The second outer circuit layer 246 may be formed in the same manner as the first outer circuit layer 243.

Referring to FIG. 12, a first solder resist 251 may be formed on the first outer circuit layer 243 to surround the first outer circuit layer 243. In addition, a second solder resist 252 may be formed on the second outer circuit layer 246 to surround the second outer circuit layer 246.

Referring to FIG. 13, a first opening 253 may be formed in the first solder resist 251 formed on the first outer circuit layer 243. The first opening 253 may be formed to expose the upper portion of the second outer via via 242 of the first outer circuit layer 243. The first opening 253 may be formed using a mechanical drill or a laser drill.

In addition, a second opening 254 and a third opening 255 may be formed in the second solder resist 252 formed on the second outer circuit layer 246. The second opening 254 may be formed to expose the upper portion of the second outer layer connection pad 245 of the second outer layer circuit layer 246. In addition, the third opening 255 may be formed to expose the upper portion of the second outer circuit pattern 244. Like the first opening 253, the second opening 254 and the third opening 255 may be formed using a mechanical drill or a laser drill.

Referring to FIG. 14, metal pads 261, 262, and 263 may be formed on the outer circuit layers 243 and 246.

The first metal pad 261 may be formed on the second outer layer via 242 exposed by the first opening 253. The first metal pad 261 may be formed including a conductive metal. For example, the first metal pad 261 may be formed to include at least one of gold, silver, nickel, aluminum, copper, and alloys thereof. In an embodiment of the present invention, the first metal pad 261 may be formed of copper. Here, the first metal pad 261 may be formed by electroplating. In addition, the first metal pad 261 may be formed to have a thickness of, for example, 1 to 100 μm. As such, the first metal pad 261 having a thickness of about 1 μm to about 100 μm may be formed to protrude out of the first solder resist 251.

The second metal pad 262 may be formed on the second outer layer connection pad 245 exposed by the second opening 254. The second metal pad 262 may also be formed in the same manner as the first metal pad 261. In addition, the second metal pad 262 may have a thickness of, for example, about 1 μm to about 100 μm and may protrude to the outside of the second solder resist 252.

The third metal pad 263 may be formed on the second outer layer circuit pattern 244 exposed by the third opening 255. The third metal pad 263 may also be formed in the same manner as the first metal pad 261. In addition, the third metal pad 263 may have a thickness of, for example, about 1 μm to about 100 μm and may protrude to the outside of the second solder resist 252.

Referring to FIG. 15, a third solder resist 271 may be formed on the first metal pad 261 and the first solder resist 251. In addition, a fourth solder resist 272 may be formed on the second metal pad 262, the third metal pad 263, and the second solder resist 252.

Referring to FIG. 16, a fourth opening 273 may be formed in the first solder resist 251. The fourth opening 273 may be formed on the first metal pad 261 to expose the first metal pad 261. In addition, a fifth opening 274 may be formed in the second solder resist 252. The fifth opening 274 may be formed on the second metal pad 262 to expose the second metal pad 262. The fourth opening 273 and the fifth opening 274 may be formed by a mechanical drill or a laser drill.

Referring to FIG. 17, a first surface treatment layer 281 may be formed on the first metal pad 261. The first surface treatment layer 281 may be formed of Immersion Tin or Immersion Sn. In this case, the first surface treatment layer 281 may be formed by an electroless plating method. In addition, the first surface treatment layer 281 may be formed by an organic solder ability preservative (OSP) method. The organic film coating method is a method of forming an organic compound in the form of alkyl imidazole (Alkyl Imidazole) on the first metal pad 261.

The second surface treatment layer 282 may be formed on the second metal pad 262. Similarly to the first surface treatment layer 281, the second surface treatment layer 282 may be formed using an electroless plating method using tin or an organic film coating method.

Referring to FIG. 18, a first bump 291 may be formed on the first metal pad 261. The first bump 291 may be formed by applying a solder paste on the first metal pad 261 on which the first surface treatment layer 281 is formed, and then performing a reflow process. In addition, a second bump 292 may be formed on the second metal pad 262 on which the second surface treatment layer 281 is formed. The second bump 292 may also be formed by applying a solder paste on the second metal pad 262 and then performing a reflow process.

The first bump 291 and the second bump 292 may be formed for mounting or electrically connecting an external device such as a semiconductor chip to a printed circuit board.

According to the embodiment of the present invention, by forming a thick metal pad on the outer layer connection pad or the outer layer via, it is possible to prevent the bump dropout phenomenon. In addition, according to an embodiment of the present invention, even when the surface treatment layer formed on the connection pad or the outer layer via is thinly formed, bump dropout may be prevented. In addition, by forming a thick metal pad on the upper portion of the outer circuit pattern, a high capacity electric signal can be supplied with electricity. In addition, since the solder resist is formed thick, the planarization of the solder resist can be ensured. Thereby, external devices, such as a semiconductor chip, can be mounted stably.

That is, according to the printed circuit board and the method of manufacturing the printed circuit according to the embodiment of the present invention, by forming a thick metal pad formed bump, it is not necessary to form a relatively thick bump, it is possible to prevent the bump dropout phenomenon. In addition, by selecting a circuit pattern to which the high capacity electric signal is to be energized to form a thick metal pad, the high capacity electric signal can be energized. In addition, when the solder resist is formed thick, it is possible to secure the planarization of the solder resist, thereby stably mounting an external device on the printed circuit board.

Although the present invention has been described in detail through the embodiments, this is to specifically describe the present invention, and the printed circuit board and the method of manufacturing the printed circuit board according to the present invention are not limited thereto. Those skilled in the art will appreciate that various modifications and changes can be made in the present invention without departing from the spirit and scope of the invention as set forth in the claims below.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

110, 210: base substrates 111, 211: through vias
121, 221: First inner layer circuit pattern 122, 222: First inner layer connection pad
123 and 223: first inner layer circuit layer 124 and 224: second inner layer circuit pattern
125, 225: second inner layer connection pads 126, 226: second inner layer circuit layer
131 and 231: first insulating layer 132 and 232: second insulating layer
141 and 241: first outer layer connection pads 142 and 242: first outer layer vias
143 and 243: first outer layer circuit layer 144.244: second outer layer circuit pattern
145 and 245: second outer layer connection pads 146 and 246: second outer layer circuit layer
151 and 251: first solder resist 152 and 252: second solder resist
153, 253: first opening 154, 254: second opening
255: third openings 161, 261: first metal pad
162 and 262: second metal pad 263: third metal pad
171 and 281: first surface treatment layer 172, 282: second surface treatment layer
180: bump 271: third solder resist
272: fourth solder resist 273: fourth opening
274: fifth opening 291: first bump
292: second bump

Claims (17)

delete delete delete delete A base substrate on which an inner circuit layer is formed;
An outer circuit layer formed on the base substrate and the inner circuit layer and including an outer connection pad and an outer circuit pattern;
A first solder resist formed on the outer circuit layer and having a first opening exposing the outer connection pad;
A first metal pad formed on an upper portion of the outer layer connection pad and the first opening and protruding from an upper portion of the first solder resist;
A surface treatment layer formed on the first metal pad;
A second solder resist formed on the first solder resist and having a second opening exposing the surface treatment layer; And
A bump formed on the surface treatment layer and the second solder resist;
And a printed circuit board.
The method of claim 5,
The first metal pad is a printed circuit board formed of copper.
The method of claim 5,
The surface treatment layer is a printed circuit board formed of OSP (Organic Solder ability Preservative) or electroless tin (Immersion Tin or Immersion Sn).
The method of claim 5,
The printed circuit board further comprises a second metal pad formed on the outer circuit pattern.
9. The method of claim 8,
The second metal pad is a printed circuit board formed of copper.
delete delete delete Preparing a base substrate on which an inner circuit layer is formed;
Forming an outer circuit layer including an outer layer connection pad and an outer circuit pattern on the inner circuit layer;
Forming a first solder resist on the outer circuit layer;
Forming a first opening in the first solder resist such that an upper portion of the outer layer connection pad is exposed;
Forming a first metal pad formed on the exposed outer layer connection pad and protruding from the first solder resist;
Forming a second solder resist on the first solder resist;
Forming a second opening in the second solder resist such that an upper portion of the first metal pad is exposed;
Forming a surface treatment layer on the exposed first metal pads; And
Forming a bump on the surface treatment layer;
≪ / RTI >
14. The method of claim 13,
In the forming of the first metal pad,
The first metal pad is a copper printed circuit board manufacturing method.
14. The method of claim 13,
In the step of forming the surface treatment layer,
The surface treatment layer is a printed circuit board manufacturing method is formed of Organic Solder ability Preservative (OSP) or Immersion Tin (Immersion Tin).
The method according to claim 13,
After the step of forming the first solder resist sheet,
And forming a second opening in the first solder resist to expose the upper portion of the outer circuit pattern.
18. The method of claim 16,
After forming the second opening,
And forming a second metal pad formed on the exposed outer circuit pattern and protruding from the first solder resist.

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