JP5599860B2 - Manufacturing method of semiconductor package substrate - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor package substrate.

  In recent years, the electronic industry has been adopting mounting technology that uses printed circuit boards that can achieve higher density, higher accuracy, and higher integration when mounting components, as electronic devices become smaller and thinner. is there.

  Fields using such printed circuit boards include many fields such as factory automation (FA) equipment, office automation (OA) equipment, communication equipment, broadcasting equipment, and portable computers.

  In particular, as electronic products become smaller, lighter, and smaller due to miniaturization, high density, packaging, and personal portability, printed circuit boards are simultaneously becoming smaller and higher density. For this reason, many processes for forming bumps on the substrate are currently being developed and mass-produced.

  The most frequently used bump forming method is a solder paste printing method using a metal mask.

  However, the metal mask printing method has a tendency that it is difficult to catch up with the quality level such as the height and shape of the bump in the fine pitch bump, and as a method for solving this, a metal post (metal post) is formed. Many studies have been conducted on methods for ensuring reliability even at fine pitches by ensuring the height of the bumps.

  Hereinafter, a method for manufacturing a semiconductor package substrate according to an embodiment of the prior art will be described with reference to FIGS.

  First, referring to FIG. 1, a base substrate 10 having a circuit pattern including a first wiring 12, a flip chip bonding connection pad 13, a second wiring 14 and a solder pad 15 on both surfaces of an insulating layer 11 is prepared. .

  Next, referring to FIG. 2, first and second solder resist layers 16 and 17 are formed on both surfaces of the base substrate 10. Referring to FIG. 3, the first and second solder resist layers 16 and 17 are open. The portions 18 and 19 are formed to expose the connection pad 13 and the solder pad 15.

  Next, referring to FIG. 4, a seed layer 20 is formed on the first solder resist layer 16 including the exposed connection pads 13.

  Thereafter, referring to FIG. 5, first and second dry films 21 and 22 are applied to both surfaces of the base substrate 10, and referring to FIG. 6, patterning is performed and openings 23 are formed at portions where posts are to be formed. Form.

  Next, referring to FIG. 7, the opening 23 is filled with electrolytic copper plating (24).

  Next, referring to FIG. 8, the first and second dry films 21 and 22 are peeled off. Referring to FIG. 9, after the seed layer 20 on the first solder resist layer 16 is removed by flash etching, the first and second dry films 21 and 22 are removed. The bump forming process is completed by removing the catalyst (for example, Pd) used in the electrolytic plating.

  However, in order to form a metal post by the above-described conventional technique, the metal must be plated, and in order to perform plating, a conductive sheet layer is required on the solder resist layer. As a typical seed layer forming method, there are a sputtering method and an electroless copper plating method using a Pd catalyst.

  In sputter method, even if plasma or ion beam pretreatment is performed, the formed sheet layer is easily separated due to low adhesive force, so that subsequent circuit steps are difficult to perform.

  The formation of the seed layer by chemical copper, that is, electroless plating, requires not only the problem of low adhesion with the solder resist layer, but also removal of Pd used as a catalyst after removal by an etching process after the formation of the metal post. There are also difficulties.

  Further, Pd remaining on the solder resist at a finer bump pitch that becomes increasingly finer can act as a substance that can cause a short circuit failure due to migration.

  The present invention is to solve the above-described problems of the conventional technology, and an object of the present invention is to provide a method of manufacturing a semiconductor package substrate that can cope with a high-density bump pitch.

  Another object of the present invention is to provide a method for manufacturing a semiconductor package substrate having post bumps with high density and high reliability.

  Another object of the present invention is to provide a method for manufacturing a semiconductor package substrate capable of realizing an open portion with a fine pitch.

  To achieve the above object, according to an aspect of the present invention, a step of preparing a base substrate having connection pads, a step of laminating a protective layer and a metal layer containing polyimide on the base substrate, Manufacturing a semiconductor package substrate comprising: forming an open part in a metal layer and a protective layer to expose the connection pad; forming a post bump on the open part; and removing the metal layer Provide a method.

  The method may further include a step of removing a part of the metal layer in a thickness direction before the step of exposing the connection pad.

  The open portion may be formed by laser processing.

  The step of forming the post bump includes forming a seed layer on the inner wall and the metal layer of the open part including the exposed connection pad, and forming the seed layer on the metal layer on which the seed layer is formed. Forming a post-bump forming hole by laminating plating resist patterns having corresponding openings, filling the post-bump forming hole by electrolytic plating, and removing the plating resist pattern. But you can.

  The seed layer formed on the metal layer may be removed together when the metal layer is removed.

  The step of forming the seed layer may be performed by electroless plating or vapor deposition.

  The method may further include forming a surface treatment layer on the connection pad on which the seed layer is formed before the filling step.

  The metal layer may be a copper foil.

  The method may further include a step of planarizing a surface of the post bump after the step of forming the post bump.

  According to a preferred aspect of the present invention, the adhesion with the protective layer can be improved by further forming a metal layer on the protective layer containing polyimide.

  According to another aspect of the present invention, a thermoplastic polyimide that can be laminated at a high temperature for the formation of a seed layer is laminated at the same time as the metal layer, thereby improving adhesion and supporting a high density bump pitch. be able to.

  In addition, a separate catalyst removal step is omitted after etching the seed layer, and there is no fear of migration due to the remaining catalyst, so that a high-density and highly reliable metal post can be manufactured.

  According to another aspect of the present invention, the size of the fine pitch open portion can be realized by processing the open portion of the protective layer for forming the post by a laser method, which is advantageous for forming fine pitch bumps. It is.

It is process flowchart (1) shown roughly in order to demonstrate the manufacturing method of the semiconductor package board | substrate which concerns on one Example of a prior art. It is process flowchart (2) shown roughly in order to demonstrate the manufacturing method of the semiconductor package board | substrate which concerns on one Example of a prior art. It is process flowchart (3) shown schematically in order to demonstrate the manufacturing method of the semiconductor package board | substrate which concerns on one Example of a prior art. It is a process flow chart (4) shown roughly in order to explain the manufacturing method of the semiconductor package substrate concerning one example of conventional technology. It is process flowchart (5) shown schematically in order to demonstrate the manufacturing method of the semiconductor package board | substrate which concerns on one Example of a prior art. It is process flowchart (6) shown roughly in order to demonstrate the manufacturing method of the semiconductor package board | substrate which concerns on one Example of a prior art. It is process flowchart (7) shown roughly in order to demonstrate the manufacturing method of the semiconductor package board | substrate which concerns on one Example of a prior art. It is process flowchart (8) shown roughly in order to demonstrate the manufacturing method of the semiconductor package board | substrate which concerns on one Example of a prior art. It is process flowchart (9) shown schematically in order to demonstrate the manufacturing method of the semiconductor package board | substrate which concerns on one Example of a prior art. It is sectional drawing shown schematically in order to demonstrate the structure of a semiconductor package board | substrate. 5 is a process flow chart (1) schematically showing a method for manufacturing a semiconductor package substrate according to a preferred embodiment of the present invention. 5 is a process flowchart (2) schematically showing a method for manufacturing a semiconductor package substrate according to a preferred embodiment of the present invention. 5 is a process flowchart (3) schematically showing a method for manufacturing a semiconductor package substrate according to a preferred embodiment of the present invention. FIG. 5 is a process flowchart (4) schematically showing a method for manufacturing a semiconductor package substrate according to a preferred embodiment of the present invention. FIG. 10 is a process flow chart (5) schematically showing a method for manufacturing a semiconductor package substrate according to a preferred embodiment of the present invention. FIG. 10 is a process flowchart (6) schematically showing a method for manufacturing a semiconductor package substrate according to a preferred embodiment of the present invention; FIG. 10 is a process flowchart (7) schematically showing a method for manufacturing a semiconductor package substrate according to a preferred embodiment of the present invention; FIG. 10 is a process flowchart (8) schematically showing a method for manufacturing a semiconductor package substrate according to a preferred embodiment of the present invention; 10 is a process flowchart (9) schematically showing a method for manufacturing a semiconductor package substrate according to a preferred embodiment of the present invention; 10 is a process flowchart (10) schematically illustrating a method for manufacturing a semiconductor package substrate according to a preferred embodiment of the present invention;

  Objects, specific advantages and novel features of the present invention will become more apparent from the following detailed description and preferred embodiments when taken in conjunction with the accompanying drawings.

  Prior to this, terms or words used in the specification and claims should not be construed in a normal and lexical sense, so that the inventor best describes the invention. Based on the principle that the concept of terms can be appropriately defined, it must be interpreted with the meaning and concept consistent with the technical idea of the present invention.

  In the present invention, it is to be noted that when reference numerals are added to components in each drawing, the same components are given the same numbers as much as possible even if they are displayed on other drawings. . In the description of the present invention, detailed descriptions of known related technologies that may unnecessarily disturb the gist of the present invention are omitted. In the present specification, terms such as “first” and “second” are used to distinguish one component from other components, and do not limit the components.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(Semiconductor package substrate)
FIG. 10 is a cross-sectional view schematically showing the structure of the semiconductor package substrate.

  Referring to FIG. 10, the semiconductor package substrate includes a base substrate 100 having connection pads 103, a first open portion 108 formed on the base substrate 100 and exposing the connection pads 103, and includes polyimide. The protective layer 106 includes post bumps 115 formed on the first open portion 108 of the protective layer 106.

  In addition to the connection pads 103, the base substrate 100 may be provided with normal wirings 102 and 104 and solder pads 105.

  Further, a solder resist layer 107 having a second open portion 109 that exposes the solder pad 105 may be provided on the solder pad 105 as is well known in the art.

  The base substrate 100 is a circuit substrate in which at least one circuit including the connection pads 103 is formed on the insulating layer 101, and is preferably a printed circuit board. In this drawing, for the sake of convenience of explanation, a specific inner layer circuit configuration is omitted, but those skilled in the art will understand that a normal multilayer in which at least one circuit is formed on the insulating layer 101 as the base substrate 100. It will be appreciated that a circuit board can be applied.

  As the insulating layer, a resin insulating layer used as an insulating layer of a printed board can be used. As the resin insulating layer, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin impregnated with a reinforcing material such as glass fiber or inorganic filler, such as a prepreg, can be used. A curable resin and / or a photocurable resin can be used, but is not limited thereto.

  The connection pad 103 is preferably a flip chip bonding pad.

  The circuit including the connection pads 103 can be applied without limitation as long as it is used as a conductive metal for circuits in the circuit board field, and copper is typically used for printed boards.

  The protective layer 106 functions as a protective layer for protecting the outermost layer circuit, and is formed for electrical insulation, and an open portion 108 is formed to expose the outermost connection pad 103. Is done. The protective layer 106 includes polyimide, preferably made of thermoplastic polyimide.

  The post bump 115 serves to electrically connect the electronic component and the inner layer circuit, and may have a structure protruding outward from the protective layer 106.

  The post bump 115 may include a seed layer 110 and an electrolytic plating layer 114 formed on the seed layer 110. The seed layer 110 may be an electroless plating layer.

  The post bump 115 can be made of a metal selected from the group consisting of copper, nickel, tin, gold, alloys thereof, or combinations thereof, but is not particularly limited thereto.

  A surface treatment layer may be further provided on the connection pad 103 as necessary.

  The surface treatment layer is not particularly limited as long as it is known in the art. For example, electro gold plating, electroless gold plating, OSP (Organic Solderability Preservative), or electroless tin. Plating (Immersion Tin Plating), Electroless Silver Plating (EN) (Electroless Nickel and Immersion Gold, Electroless Nickel / Displacement Gold Plating), DIG Plating (Direct Immersion GoldPlatHolding) Such Can be formed.

  On the other hand, the solder resist layer 107 has a function of a protective layer for protecting the outermost layer circuit together with the protective layer 106, and is formed for electrical insulation, and exposes the outermost solder pad 105. For this purpose, an open portion 109 is formed. The solder resist layer 107 can be formed of, for example, a solder resist ink, a solder resist film, or an encapsulating agent as is well known in the art, but is not limited thereto. The solder resist layer 107 may be made of the same material as the protective layer 106.

  In addition, the above-described surface treatment layer may be further provided on the solder pad 105, and a solder bump such as a normal solder ball can be formed as known in the art.

  The semiconductor package substrate described above is provided with a protective layer containing polyimide, thereby improving the adhesive strength characteristics and realizing a fine bump pitch with high density and high reliability.

(Method for manufacturing semiconductor package substrate)
FIG. 11 to FIG. 20 are process flow diagrams schematically showing a method for manufacturing a semiconductor package substrate according to a preferred embodiment of the present invention.

  First, referring to FIG. 11, a base substrate 100 having connection pads 103 is prepared.

  In addition to the connection pads 103, the base substrate 100 may be provided with normal wirings 102 and 104 and solder pads 105.

  The base substrate 100 is a circuit substrate in which at least one circuit including the connection pads 103 is formed on the insulating layer 101, and is preferably a printed circuit board. In this drawing, for the sake of convenience, a specific inner layer circuit configuration is omitted. However, those skilled in the art will recognize that the base substrate 100 is a normal multilayer printed circuit board in which at least one circuit is formed on the insulating layer 101. Can be fully recognized.

  As the insulating layer, a resin insulating layer used as an insulating layer of a printed board can be used.

  As the resin insulating layer, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin impregnated with a reinforcing material such as glass fiber or inorganic filler, such as a prepreg, can be used. A curable resin and / or a photocurable resin can be used, but is not limited thereto.

  The connection pad 103 is preferably a flip chip bonding pad.

  The circuit including the connection pads 103 can be applied without limitation as long as it is used as a conductive metal for circuits in the circuit board field, and copper is typically used for printed boards.

  Next, referring to FIG. 12, a protective layer 106 containing polyimide and a metal layer 106 </ b> A are stacked on the base substrate 100.

  The protective layer 106 functions as a protective layer for protecting the outermost layer circuit and is formed for electrical insulation. The protective layer 106 includes polyimide, preferably made of thermoplastic polyimide.

  The metal layer 106A is preferably a copper foil.

  On the other hand, together with the step of laminating the protective layer 106 and the metal layer 106A, the lower surface of the base substrate 100 may be subjected to a step of laminating an ordinary solder resist layer 107 known in the art.

  The solder resist layer 107 functions as a protective layer for protecting the outermost layer circuit together with the protective layer 106, and is formed for electrical insulation. The solder resist layer 107 can be formed of, for example, a solder resist ink, a solder resist film, or an encapsulating agent as is well known in the art, but is not limited thereto. The solder resist layer 107 may be made of the same material as the protective layer 106.

  Referring to FIG. 13, a part of the metal layer 106A is selectively removed by a normal etching or polishing process, for example, in the thickness direction at 3 μm inside or outside, so that a seed metal layer 106a instead of a normal seed layer is formed. Can be formed.

  The above process can be selectively applied according to the thickness of the actually applied metal layer 106A.

  In the present invention, by laminating the metal layer 106A together with the protective layer 106 containing polyimide, the adhesive strength characteristics can be improved as compared with the existing one.

  In addition, compared to the conventional technique in which the seed layer is formed on the protective layer 106 by a separate process, the protective layer 106 and the metal layer 106A are bonded by a physical method, so that the adhesion characteristics can be improved. In addition, it is possible to omit a step of removing a separate catalyst after etching the seed layer in a subsequent step.

  As a result, the catalyst removal step is omitted, and there is no risk of migration due to the catalyst remaining after etching, so that a high-density, high-reliability post bump can be manufactured.

  In particular, when a thermoplastic polyimide that can be laminated at a high temperature is used as the protective layer, there is an advantage that the above-described effects can be further doubled.

  Next, referring to FIG. 14, a first open part 108 is formed in the seed metal layer 106 a and the protective layer 106 to expose the connection pad 103.

  The opening 108 is formed by ordinary laser processing such as a Yag laser. In this case, the size of the fine pitch open portion can be realized, which is advantageous for forming fine pitch bumps.

  Meanwhile, when the first open part 108 is formed, the solder pad 105 may be exposed by forming the second open part 109 together with the solder resist layer 107.

  Next, referring to FIG. 15, a seed layer 110 is formed on the inner wall of the first open part 108 including the exposed connection pad 103 and the seed metal layer 106a.

  The seed layer 110 can be formed by vapor deposition such as normal electroless plating or sputtering. In addition, as described above, the seed metal layer 106a is formed on the protective layer 106, and the adhesion property can be improved compared with the conventional technique in which the seed layer is directly formed on the protective layer 106, and the density is high. Highly reliable post formation is possible.

  Next, referring to FIG. 16, a first photosensitive plating resist 111 is stacked on the seed metal layer 106a on which the seed layer 110 is formed.

  The first photosensitive plating resist 111 can be formed by applying a resist ink or a dry film.

  On the other hand, when the first photosensitive plating resist 111 is applied, the second photosensitive plating resist 112 may be formed on the solder resist layer 107 on which the second open portion 109 on the lower surface is formed.

  Next, referring to FIG. 17, an opening corresponding to the first open portion 108 is formed in the first photosensitive plating resist 111 by a photolithography process including normal exposure / development to form a post bump forming groove. 113 is formed.

  Optionally, the method may further include forming a surface treatment layer on the connection pad 103 on which the seed layer 111 is formed.

  The surface treatment layer is not particularly limited as long as it is known in the art. For example, electro gold plating, electroless gold plating, OSP (Organic Solderability Preservative), or electroless tin. Plating (Immersion Tin Plating), Electroless Silver Plating (EN) (Electroless Nickel and Immersion Gold, Electroless Nickel / Displacement Gold Plating), DIG Plating (Direct Immersion GoldPlatHolding) Such Can be formed.

  Next, referring to FIG. 18, the post bump forming groove 113 is filled (114) by electrolytic plating.

  At this time, the seed layer 110 and the seed metal layer 106a can function as plating lead wires.

  Next, referring to FIG. 19, the first photosensitive plating resist 111 is removed. The removing process may be performed by normal peeling. At this time, when the first photosensitive plating resist 111 is removed, the second photosensitive plating resist 112 on the lower surface can be removed together.

  Referring to FIG. 20, the seed layer 110 and the seed metal layer 106 a formed on the protective layer 106 are removed to expose the protective layer 106, thereby forming a post bump 115.

  The removal of the seed layer 110 and the seed metal layer 106a may be performed by an ordinary etching process such as flash etching.

  The post bump 115 can be made of copper, nickel, tin, gold, alloys thereof, or combinations thereof.

  Further, a surface treatment layer known in the art can be further formed on the surface of the post bump 115 as required.

  Meanwhile, after the formation of the post bump 115, a step of planarizing the surface of the post bump 115 may be further performed as necessary in order to reduce height variation of the post bump 115, for example, plating variation. The flattening process is not particularly limited as long as it does not substantially damage the post bumps 115 formed, and any method known in the art can be applied.

  As described above, according to a preferred embodiment of the present invention, a seed layer is formed by simultaneously laminating a protective layer containing polyimide and a metal layer when forming post bumps to accommodate a high density bump pitch. In addition to the function of the layer, it is possible to improve the adhesive strength characteristics when forming a normal seed layer.

  According to another preferred embodiment of the present invention, as a protective layer, a thermoplastic polyimide that can be laminated at a high temperature is laminated at the same time as the metal layer, so that the protective layer and the metal layer are bonded by a physical method. Thus, the adhesive property can be further doubled and improved.

  In addition, as described above, a metal layer serving as a seed layer is introduced on the protective layer to improve the adhesion, so that the seed layer formed by ordinary electroless plating or the like is removed separately. There is no need to remove the catalyst.

  Thereby, since there is no fear of migration due to the catalyst remaining after the removal, a high-density, high-reliability post bump can be manufactured.

  According to another preferred embodiment of the present invention, by applying a laser method as a method of opening a protective layer to form a bump, it is possible to form a fine pitch open portion, and It is advantageous for formation.

  As described above, the present invention has been described in detail with reference to specific embodiments. However, this is only for specifically describing the present invention, and the method for manufacturing a semiconductor package substrate according to the present invention is not limited thereto. It is obvious that those having ordinary knowledge in the field can make modifications or improvements within the technical idea of the present invention.

  All simple modifications and variations of the present invention belong to the scope of the present invention, and the specific scope of protection of the present invention will be apparent from the claims.

  The present invention can be applied to a method for manufacturing a semiconductor package substrate that can cope with a high-density bump pitch.

DESCRIPTION OF SYMBOLS 100 Base substrate 101 Insulating layer 102,104 Wiring 103 Connection pad 105 Solder pad 106 Protective layer 106A Metal layer 106a Seed metal layer 107 Solder resist layer 108 1st open part 109 2nd open part 110 Seed layer 111 1st photosensitive plating resist 112 Second photosensitive plating resist 113 Post bump forming groove 114 Electrolytic plating filling 115 Post bump

Claims (14)

Providing a base substrate having connection pads;
Laminating a protective layer and a metal layer containing thermoplastic polyimide on the base substrate;
Forming an open part in the metal layer and the protective layer to expose the connection pad;
Forming a post bump in the open portion;
Removing the metal layer. A method for manufacturing a semiconductor package substrate, comprising: Before the step of exposing the connection pad,
The method of manufacturing a semiconductor package substrate according to claim 1, further comprising removing a part of the metal layer in a thickness direction.   The method of manufacturing a semiconductor package substrate according to claim 1, wherein the open portion is formed by laser processing. The step of forming the post bump includes
Forming a seed layer on the inner wall and the metal layer of the open part including the exposed connection pads;
A step of forming a post bump forming hole by laminating a plating resist pattern having an opening corresponding to the open portion on the metal layer on which the seed layer is formed;
Filling the post bump forming hole by electrolytic plating;
The method of manufacturing a semiconductor package substrate according to claim 1, further comprising: removing the plating resist pattern. 5. The method of manufacturing a semiconductor package substrate according to claim 4 , wherein the seed layer formed on the metal layer is removed together when the metal layer is removed. The method of manufacturing a semiconductor package substrate according to claim 4 , wherein the step of forming the seed layer is performed by electroless plating or vapor deposition. Before the filling step,
The method of manufacturing a semiconductor package substrate according to claim 4 , further comprising forming a surface treatment layer on the connection pad on which the seed layer is formed.   2. The method of manufacturing a semiconductor package substrate according to claim 1, wherein the post bumps are made of a metal selected from the group consisting of copper, nickel, tin, gold, alloys thereof, or combinations thereof.   The method of manufacturing a semiconductor package substrate according to claim 1, wherein the metal layer is a copper foil. After the step of forming the post bump,
The method of manufacturing a semiconductor package substrate according to claim 1, further comprising planarizing a surface of the post bump.   2. The method of manufacturing a semiconductor package substrate according to claim 1, wherein the connection pad is a flip-chip bonding connection pad. Providing a base substrate having connection pads;
Laminating a protective layer and a metal layer containing polyimide on the base substrate;
Forming an open part in the metal layer and the protective layer to expose the connection pad;
Forming a seed layer on the inner wall and the metal layer of the open part including the exposed connection pads;
A step of forming a post bump forming hole by laminating a plating resist pattern having an opening corresponding to the open portion on the metal layer on which the seed layer is formed;
Forming a post bump in the post bump forming hole;
Removing the plating resist pattern;
Removing the metal layer and the seed layer on the metal layer. A method for manufacturing a semiconductor package substrate, comprising: The step of forming the post bump includes
13. The method of manufacturing a semiconductor package substrate according to claim 12, wherein the post bump forming hole is filled by electrolytic plating. The method of manufacturing a semiconductor package substrate according to claim 12, wherein the polyimide is a thermoplastic polyimide.

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