KR20150135046A - Package board, method for manufacturing the same and package on packaage having the thereof - Google Patents

Package board, method for manufacturing the same and package on packaage having the thereof Download PDF

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Publication number
KR20150135046A
KR20150135046A KR1020140174195A KR20140174195A KR20150135046A KR 20150135046 A KR20150135046 A KR 20150135046A KR 1020140174195 A KR1020140174195 A KR 1020140174195A KR 20140174195 A KR20140174195 A KR 20140174195A KR 20150135046 A KR20150135046 A KR 20150135046A
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South Korea
Prior art keywords
insulating layer
connection pad
present
cavity
layer
Prior art date
Application number
KR1020140174195A
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Korean (ko)
Inventor
김혜진
정혜원
강명삼
봉강욱
고영관
성민재
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삼성전기주식회사
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Application filed by 삼성전기주식회사 filed Critical 삼성전기주식회사
Priority to KR1020140194133A priority Critical patent/KR20150135048A/en
Priority to TW104116329A priority patent/TW201603665A/en
Priority to US14/719,309 priority patent/US20150342046A1/en
Priority to CN201510271845.9A priority patent/CN105101636A/en
Publication of KR20150135046A publication Critical patent/KR20150135046A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)

Abstract

The present invention relates to a package board, a method for manufacturing a package board, and a stacked package including the same. According to an embodiment of the present invention, the package board comprises: an insulating layer; a cavity formed to have the depth to the inside of a lower surface of the insulating layer; and a connection pad formed inside the insulating layer, and formed in at least one side of the cavity.

Description

TECHNICAL FIELD [0001] The present invention relates to a package substrate, a method of manufacturing a package substrate, and a stacked package including the package substrate.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package substrate, a method of manufacturing a package substrate, and a stacked package including the package substrate.

Recently, the electronics industry adopts a mounting technique using a multi-layer printed circuit board (PCB) which enables high density and high integration in component mounting for miniaturization and thinning of electronic devices. Such multilayer printed circuit boards are being developed through the development of elemental technologies such as substrate microcircuits and bumps for high density and high integration. 2. Description of the Related Art Recently, semiconductor packages such as SIP (System In Package), CSP (Chip Sized Package), and FCP (Flip Chip Package) in which electronic devices are mounted on a printed circuit board in advance to form packages are being actively developed. There is also a package on package (POP) in which a control device and a memory device are implemented as a single package in order to miniaturize a high-performance smart phone and improve performance. The stacked package can be implemented by separately packaging the control device and the memory device, stacking them, and connecting them.

United States Patent No. 5986209

One aspect of the present invention is to provide a package substrate, a method of manufacturing a package substrate, and a stacked package including the package substrate, which facilitates reduction of bridge generation and fine pitch of external connection terminals.

Another aspect of the present invention is to provide a package substrate capable of reducing the overall thickness of the stacked package, a method of manufacturing the package substrate, and a stacked package including the same.

According to an embodiment of the present invention, there is provided a package substrate including an insulating layer, a cavity formed to have a depth inward from a lower surface of the insulating layer, and a connection pad formed in at least one side of the cavity.

The connection pad is formed to have the same or a thin thickness as the insulating layer.

The insulating layer is penetrated by the vias formed on the top surfaces of the connection pads and the connection pads.

According to another embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a connection pad and a cavity pattern on a carrier substrate; forming an insulating layer formed on the carrier substrate to fill the connection pad and the cavity pattern; And removing the step and the cavity pattern.

According to another embodiment of the present invention, there is provided a semiconductor device comprising: a lower package including a lower package substrate and a first electronic element disposed on a lower package substrate; an insulating layer; a cavity formed to have a depth from the lower surface of the insulating layer; And an upper package substrate including a connection pad formed on at least one side of the cavity, wherein the upper package and the lower package substrate are formed between the circuit pattern of the upper package substrate and the connection pads of the upper package substrate, Wherein at least a portion of the first electronic element is inserted into the cavity.

1 is an exemplary view showing a package substrate according to an embodiment of the present invention.
FIGS. 2 to 16 are illustrations showing a method of manufacturing a package substrate according to an embodiment of the present invention.
17 is an exemplary view showing a stacked package according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The objectives, specific advantages and novel features of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. It should be noted that, in the present specification, the reference numerals are added to the constituent elements of the drawings, and the same constituent elements are assigned the same number as much as possible even if they are displayed on different drawings. It will be further understood that terms such as " first, "" second," " one side, "" other," and the like are used to distinguish one element from another, no. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description of the present invention, detailed description of related arts which may unnecessarily obscure the gist of the present invention will be omitted.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an exemplary view showing a package substrate according to an embodiment of the present invention.

Referring to FIG. 1, a package substrate 100 according to an embodiment of the present invention includes an insulating layer 130, a connection pad 110, an inner layer circuit pattern 150, an outer layer circuit pattern 170, a first via 140 A second via 160, and a protective layer 180,

According to an embodiment of the present invention, the insulating layer 130 may be formed of a composite polymer resin, which is typically used as an interlayer insulating material. For example, the insulating layer 130 may be formed of an epoxy resin such as prepreg, ABF (Ajinomoto Build-up Film), FR-4, and BT (Bismaleimide Triazine). However, the material forming the insulating layer 130 in the embodiment of the present invention is not limited thereto. The insulating layer 130 according to embodiments of the present invention may be selected from those known in the field of circuit boards.

In the embodiment of the present invention, the insulating layer 130 is divided into a first insulating layer 131 and a second insulating layer 135. The second insulating layer 135 is formed on the first insulating layer 131.

In FIG. 1, the first insulating layer 131 and the second insulating layer 135 are formed of the same material. However, the first insulating layer 131 and the second insulating layer 135 are not limited to be formed of the same material in the embodiment of the present invention. For example, the first insulating layer 131 may be formed of an insulating material containing glass fibers, and the second insulating layer 135 may be formed of an insulating material containing no glass fibers. As such, the material of the first insulating layer 131 and the second insulating layer 135 can be changed according to the choice of a person skilled in the art.

According to the embodiment of the present invention, the first insulating layer 131 is formed with a cavity 121 having a predetermined depth from the bottom to the inside. When the stacked package is formed in the cavity 121 according to the embodiment of the present invention, the electronic device of the lower package is located. Therefore, the cavity 121 according to the embodiment of the present invention is formed to have a size such that at least a part of the electronic device can be inserted therein.

According to the embodiment of the present invention, the connection pad 110 is formed inside the first insulating layer 131 and formed on both sides of the cavity 121. Although the connection pad 110 is illustrated as being formed on the left and right sides of the cavity 121 in FIG. 1, the connection pad 110 may be formed to surround the side edge of the cavity 121.

According to the embodiment of the present invention, the connection pad 110 is formed to have the same or a thin thickness as the first insulation layer 131. [ Here, the connection pad 110 according to the embodiment of the present invention is formed to have a thickness corresponding to the depth of the cavity 121. For example, as shown in FIG. 1, the connection pad 110 is formed to have the same thickness as the depth of the cavity 121.

In the embodiment of the present invention, the connection pad 110 is formed to have a thicker thickness than other circuit patterns as shown in FIG.

A metal layer 520 may be formed under the connection pad 110 according to an embodiment of the present invention. The metal layer 520 is formed under the connection pad 110 and protrudes from the first insulating layer 131.

The connection pad 110 and the metal layer 520 according to the embodiment of the present invention are formed of copper (Cu). However, the material of the connection pad 110 and the metal layer 520 is not limited to copper, and may be conductive material used in the circuit board field.

According to the embodiment of the present invention, the inner layer circuit pattern 150 is formed inside the insulating layer 130. For example, the inner layer circuit pattern 150 may be formed on the first insulating layer 131 and may be formed to be embedded in the second insulating layer 135. In the embodiment of the present invention, the inner layer circuit pattern 150 is shown and described as being formed in one layer, but is not limited thereto. That is, the inner layer circuit pattern 150 according to the embodiment of the present invention may be formed as a multilayer of two or more layers according to the choice of a person skilled in the art.

According to the embodiment of the present invention, the outer layer circuit pattern 170 is formed on the upper portion of the second insulating layer 135.

The inner layer circuit pattern 150 and the outer layer circuit pattern 170 according to the embodiment of the present invention may be formed of copper (Cu). However, the material of the inner layer circuit pattern 150 and the outer layer circuit pattern 170 is not limited to copper, and may be one of conductive materials used in the circuit board field.

According to an embodiment of the present invention, the first via 140 is formed inside the first insulating layer 131. According to the embodiment of the present invention, the lower surface of the first via 140 is bonded to the connection pad 110, and the upper surface is bonded to the inner layer circuit pattern 150. The first via 140 thus formed electrically connects the connection pad 110 and the inner layer circuit pattern 150.

According to the embodiment of the present invention, the external component located outside the package substrate 100 and the inner layer circuit pattern 150 are electrically connected to each other by the connection pad 110, the first via 140 and the metal layer 520 do. Therefore, the sum of the thicknesses of the connection pad 110 and the first via 140 according to the embodiment of the present invention is such that the inner layer circuit pattern 150 and the metal layer 520 can be electrically connected to each other. Thus, the external component may be, for example, an electronic component, a package, a main board, or the like.

When the package substrate 100 according to the embodiment of the present invention is stacked on the lower package substrate (not shown), the lower package substrate 100 is bonded to the upper package substrate 100 by the cavity 121, the connection pad 110, Is narrowed. Therefore, the size of the external connection terminal (not shown) for connection with the lower package substrate can be reduced as the interval becomes narrower.

A second via 160 according to an embodiment of the present invention is formed within the second insulating layer 135. According to the embodiment of the present invention, the lower surface of the second via 160 is bonded to the inner layer circuit pattern 150, and the upper surface is bonded to the outer layer circuit pattern 170. The second via 160 thus formed electrically connects the inner layer circuit pattern 150 and the outer layer circuit pattern 170.

According to an embodiment of the present invention, the protective layer 180 is formed on the second insulating layer 135 and the outer layer circuit pattern 170. The protective layer 180 according to the embodiment of the present invention can prevent the solder from being applied when the outer layer circuit pattern 170 is soldered for mounting an electronic device (not shown). Further, the protective layer 180 can prevent the outer layer circuit layer from being oxidized and corroded.

The protective layer 180 according to an embodiment of the present invention is formed to expose a part of the outer layer circuit pattern 170. At this time, the outer layer circuit pattern 170 exposed by the protection layer 180 may be an area electrically connected to an external component such as an electronic device.

In addition, according to an embodiment of the present invention, the protective layer 180 is formed under the first insulating layer 131 to expose the metal layer 520. The metal layer 520 exposed by the passivation layer 180 may be a region electrically connected to the external component.

According to an embodiment of the present invention, the protective layer 180 is formed of a heat resistant coating material. For example, the protective layer 180 may be formed of a solder resist.

According to the embodiment of the present invention, the protective layer 180 can be formed by changing the area formed according to the selection of a person skilled in the art, and can be omitted.

According to an embodiment of the present invention, the surface treatment layer 190 is formed on the outer layer circuit pattern 170 exposed by the protective layer 180. In addition, the surface treatment layer 190 is formed on the metal layer 520 exposed by the protective layer 180. The surface treatment layer 190 is formed to prevent the outer layer circuit pattern 170 and the metal layer 520 exposed by the protective layer 180 from being corroded and oxidized. For example, the surface treatment layer 190 may be any surface treatment layer known in the circuit board art, such as plating nickel, tin, gold, palladium, or the like, or coating an Organic Solderability Preservative (OSP) .

The surface treatment layer 190 according to an embodiment of the present invention may be omitted according to the choice of a person skilled in the art.

Although not shown in FIG. 1, external connection terminals (not shown) may be formed under the package substrate 100. The external connection terminal may be a solder ball.

In the embodiment of the present invention, the thickness of the connection pad 110 is formed to have the depth of the cavity 121 so that the first via 140 is formed for electrical connection with the inner layer circuit pattern 150 But the present invention is not limited thereto. For example, if the connection pad 110 according to the embodiment of the present invention is formed to have a thickness that penetrates through the first insulating layer 131, the first via 140 is directly connected to the inner layer circuit pattern 150, .

The package substrate 100 according to the embodiment of the present invention includes a cavity 121 in which electronic elements of a lower package substrate are disposed and a connection pad 110 that narrows a gap between the cavity and the lower package. Therefore, when the stacked package is formed later, the thickness of the entire stacked package can be reduced by the package substrate 100 according to the embodiment of the present invention. A stacked package to which the package substrate 100 according to the embodiment of the present invention is applied will be described later with reference to FIG.

Referring to FIG. 2, a carrier substrate 500 is provided.

The carrier substrate 500 according to the embodiment of the present invention is a structure for supporting the insulating layer and the circuit layer for the package substrate when they are formed.

According to the embodiment of the present invention, the carrier substrate 500 is a structure in which the metal layer 520 is laminated on the carrier core 510.

For example, the carrier core 510 is formed of an insulating material. However, the material of the carrier core 510 is not limited to an insulating material, and may be a metal material or a structure in which one or more layers of an insulating layer and a metal layer are stacked.

For example, the metal layer 520 is formed of copper (Cu). However, the material of the metal layer 520 is not limited to copper, and any conductive material used in the field of circuit boards may be used without limitation.

In the embodiment of the present invention, the carrier substrate 500 is shown and described as a structure in which a single metal layer 520 is laminated on both sides of the carrier core 510, but the structure of the carrier substrate 500 is not limited thereto . That is, the carrier substrate 500 in the embodiment of the present invention is schematically shown for the convenience of explanation and understanding. For example, the carrier substrate 500 may be formed by stacking a plurality of metal layers on a carrier core and forming a release layer between the metal layers of the plurality of layers. Accordingly, the carrier layer can be separated from and removed from the package substrate with the exception of the metal layer formed on the outermost layer. The structure of the carrier substrate 500 is not limited to the structure shown and described in the embodiment of the present invention. That is, a carrier substrate of any structure used in the technical field is applicable to this embodiment.

Referring to FIG. 3, a plating resist 530 is formed on the carrier substrate 500.

According to an embodiment of the present invention, a plating resist 530 is formed on the metal layer 520 of the carrier substrate 500. The plating resist 530 according to the embodiment of the present invention has an opening 531 for exposing a connection pad (not shown) and a metal layer 520 in a region where a cavity pattern (not shown) is to be formed. Here, the region where the cavity pattern is to be formed is formed to have a size such that the electronic device can be mounted.

Referring to FIG. 4, a connection pad 110 and a cavity pattern 120 are formed on a carrier substrate 500.

According to an embodiment of the present invention, the connection pad 110 and the cavity pattern 120 are formed on the metal layer 520 of the carrier substrate 500.

According to the embodiment of the present invention, the connection pad 110 and the cavity pattern 120 are formed by performing electrolytic plating on the opening 531 of the plating resist 530. At this time, the metal layer 520 exposed through the opening 531 of the plating resist 530 may serve as a seed layer for electroplating.

The connection pad 110 according to the embodiment of the present invention is a circuit pattern electrically connected to an external component.

In addition, the cavity pattern 120 is formed in order to secure a space in which the electronic device mounted on the lower package substrate is located when the stacked package is formed. Accordingly, the cavity pattern 120 is formed to have a size such that the electronic device can be located inside the cavity (not shown).

In the embodiment of the present invention, the connection pad 110 is formed to have the same thickness because it is formed in the same process as the cavity pattern 120. However, the connection pad 110 is not necessarily formed to have the same thickness as the cavity pattern 120. Depending on the choice of those skilled in the art, the connection pad 110 may be formed thicker or thinner than the cavity pattern 120.

Referring to Fig. 5, the plating resist (530 in Fig. 4) is removed.

Referring to FIG. 6, a first insulating layer 131 is formed.

The first insulating layer 131 is formed on the metal layer 520 to cover the connection pad 110 and the cavity pattern 120. In this case, The upper surface of the first insulating layer 131 is formed to be positioned higher than the upper surface of the connection pad 110 and the upper surface of the cavity pattern 120. [ That is, the first insulating layer 131 may be formed to have a predetermined thickness also on the connection pad 110 and the cavity pattern 120.

According to an embodiment of the present invention, the first insulating layer 131 may be formed in a liquid state by applying the metal layer 520, the connection pad 110, and the cavity pattern 120 on top of each other. Or the first insulating layer 131 may be formed on the metal layer 520, the connection pad 110, and the cavity pattern 120 in the form of a film and then pressed. The first insulating layer 131 according to the embodiment of the present invention may be formed by any method of forming the insulating layer in the circuit substrate field as well as the above-described method.

The first insulating layer 131 according to the embodiment of the present invention may be formed of a composite polymer resin which is typically used as an interlayer insulating material. For example, the first insulating layer 131 may be formed of an epoxy resin such as prepreg, ABF (Ajinomoto Build-up Film), FR-4, and BT (Bismaleimide Triazine). However, the material forming the first insulating layer 131 in the embodiment of the present invention is not limited thereto. The first insulating layer 131 according to an embodiment of the present invention may be selected from insulating materials known in the circuit board field.

Referring to FIG. 7, an inner layer circuit pattern 150 and a first via 140 are formed.

The inner layer circuit pattern 150 is formed on the first insulating layer 131 and the first vias 140 are formed on the inner surface of the first insulating layer 131. In this embodiment,

The first via 140 according to the embodiment of the present invention is formed on the first insulating layer 131 formed on the connection pad 110. That is, the first via 140 passes through the first insulating layer 131 formed on the connection pad 110, the upper surface thereof is joined to the inner layer circuit pattern 150, and the lower surface thereof is connected to the connection pad 110 do. The inner layer circuit pattern 150 and the connection pads 110 are electrically connected by the first vias 140 thus formed.

The inner layer circuit pattern 150 and the first via 140 according to the embodiment of the present invention can be formed by processing a via hole (not shown), forming a patterned plating resist (not shown), and then performing plating . Alternatively, the inner layer circuit pattern 150 and the first via 140 according to the embodiment of the present invention may be formed by processing a via hole, performing plating, forming an etching resist, and performing an etching process. The inner layer circuit pattern 150 and the first via 140 may be formed by any method known in the circuit board art, for example, As shown in FIG.

In addition, the inner layer circuit pattern 150 and the first via 140 according to the embodiment of the present invention may be formed of any conductive material used in the circuit board field. For example, the innerlayer circuit pattern 150 and the first via 140 may be formed of copper (Cu).

In the embodiment of the present invention, the inner layer circuit pattern 150 is formed as one layer. However, the present invention is not limited to this structure. That is, the inner layer circuit pattern 150 according to the embodiment of the present invention may be formed in multiple layers according to the selection of a person skilled in the art. In this case, the first insulating layer 131 may be formed in multiple layers, and vias may be formed to connect the inner layer circuit patterns 150 of each layer to each other.

Referring to FIG. 8, a second insulating layer 135 is formed.

According to an embodiment of the present invention, the second insulating layer 135 is formed on the first insulating layer 131 to cover the inner layer circuit pattern 150.

According to an embodiment of the present invention, the second insulating layer 135 may be formed in a liquid form by applying the first insulating layer 131 and the inner layer circuit pattern 150 on top of each other. Or the second insulating layer 135 may be formed on the first insulating layer 131 and the inner layer circuit pattern 150 in the form of a film and then pressed. The second insulating layer 135 according to the embodiment of the present invention may be formed by any method of forming the insulating layer in the circuit substrate field as well as the method described above.

According to an embodiment of the present invention, the second insulating layer 135 may be formed of an insulating material that does not contain glass fibers among interlayer insulating materials that are commonly used. However, the material of the second insulating layer 135 is not limited thereto. That is, the second insulating layer 135 according to the embodiment of the present invention may be formed of the same material as that of the first insulating layer 131, and may be any of the conventional interlayer insulating materials used in the field of circuit boards.

Referring to FIG. 9, an outer layer circuit pattern 170 and a second via 160 are formed.

The outer layer circuit pattern 170 is formed on the top of the second insulating layer 135 and the second vias 160 are formed on the inside of the second insulating layer 135. [

The outer layer circuit pattern 170 according to the embodiment of the present invention is a circuit pattern formed on the outermost layer of the package substrate 100. [ Therefore, a part of the pattern of the outer layer circuit pattern 170 may be electrically connected to an external component such as an electronic device, a package, a substrate, or the like.

The second via 160 according to the embodiment of the present invention is formed so as to penetrate the second insulating layer 135 and to be bonded to the outer layer circuit pattern 170 on the upper surface and to the innerlayer circuit pattern 150 on the lower surface. The inner layer circuit pattern 150 and the outer layer circuit pattern 170 are electrically connected by the second vias 160 thus formed.

The method and material of forming the outer layer circuit pattern 170 and the second via 160 according to the embodiment of the present invention are the same as the method of forming the inner layer circuit pattern 150 and the first via 140 of FIG. References

Referring to FIG. 10, a protective layer 180 is formed.

According to an embodiment of the present invention, the protective layer 180 is formed on the second insulating layer 135 and the outer layer circuit pattern 170. The protective layer 180 according to the embodiment of the present invention can prevent the solder from being applied when the outer layer circuit pattern 170 is soldered for mounting an electronic device (not shown). Also, the protective layer 180 can prevent the outer layer circuit layer from being oxidized and corroded.

The protective layer 180 according to an embodiment of the present invention is formed to expose a part of the outer layer circuit pattern 170. At this time, the outer layer circuit pattern 170 exposed by the protection layer 180 may be an area electrically connected to an external component such as an electronic device.

According to an embodiment of the present invention, the protective layer 180 is formed of a heat resistant coating material. For example, the protective layer 180 may be formed of a solder resist.

Referring to FIG. 11, the carrier substrate 500 is removed.

According to an embodiment of the present invention, after the carrier core 510 and the metal layer 520 are separated, the carrier core 510 is removed. When the carrier core 510 is removed, the package substrate 100 formed on both sides of the carrier substrate 500 is separated.

Referring to FIG. 12, an etching resist 540 is formed.

The etching resist 540 according to the embodiment of the present invention is formed to prevent the connection pad 110 from being damaged when the cavity pattern 120 is etched in the future. Thus, the etching resist 540 is formed under the connection pad 110 to protect the connection pad 110 from the etching process. At this time, the etching resist 540 simultaneously protects a part of the metal layer 520 located in the region where the connection pad 110 is formed.

The etching resist 540 according to the embodiment of the present invention is formed with the opening 541 so as to expose an area other than the area where the connection pad 110 is formed.

In addition, the etching resist 540 according to the embodiment of the present invention should be formed of a material that does not react with the etching solution, if a subsequent etching process uses an etching solution.

Referring to Fig. 13, a cavity 121 is formed.

According to an embodiment of the present invention, an etching process is performed. The metal layer 520 and the cavity pattern 120 in the region exposed by the opening 541 of the etching resist 540 are removed by the etching process.

According to an embodiment of the present invention, the etching process may be performed with an etchant in which the cavity pattern 120 and the metal layer 520 react. At this time, the etching resist 540 should not react with the etching solution used.

According to the embodiment of the present invention, the cavity pattern 120 is removed by the etching process, and the cavity 121 is formed. An electronic device (not shown) may be located later in the cavity 121 thus formed.

In the embodiment of the present invention, although the etching liquid is used for removing the cavity pattern 120, the etching process for removing the cavity pattern 120 is not limited thereto. That is, the cavity pattern 120 can be removed by any of the etching methods known in the field of circuit boards.

According to the embodiment of the present invention, when the etching process is performed, the connection pad 110 and the metal layer 520 located between the connection pad 110 and the etching resist 540 are not etched by the etching resist 540 Protected.

Referring to Fig. 14, the etching resist (540 in Fig. 13) is removed.

According to an embodiment of the present invention, the metal layer 520 formed under the connection pad 110 by the etching resist (540 in Fig. 13) is protected from the etching process. Thus, when the etching resist (540 in FIG. 13) is removed, the protected metal layer 520 protrudes from the lower surface of the first insulating layer 131 as shown.

Referring to FIG. 15, a surface treatment layer 190 may be formed.

According to an embodiment of the present invention, a protective layer 180 is formed under the first insulating layer 131. The protective layer 180 formed under the first insulating layer 131 is formed to expose the metal layer 520 to the outside. At this time, the metal layer 520 exposed to the outside is a portion connected to an external connection terminal (not shown).

The protective layer 180 formed under the first insulating layer 131 according to the embodiment of the present invention is not necessarily formed at this stage. The protective layer 180 may be formed at any stage after the metal layer 520 is patterned. In addition, the protective layer 180 formed under the first insulating layer 131 according to the embodiment of the present invention may be omitted according to the selection of a person skilled in the art.

According to an embodiment of the present invention, the surface treatment layer 190 is formed on the outer layer circuit pattern 170 exposed by the protective layer 180. In addition, according to an embodiment of the present invention, the surface treatment layer 190 is formed on the metal layer 520 exposed by the protective layer 180.

The surface treatment layer 190 according to the embodiment of the present invention is formed to prevent the outer layer circuit pattern 170 and the metal layer 520 exposed by the protective layer 180 from being corroded and oxidized. For example, the surface treatment layer 190 may be formed by a known surface treatment method in the circuit board field, such as plating nickel, tin, gold, palladium, or the like, or coating an Organic Solder ability Preservative (OSP) have.

The step of forming the surface treatment layer 190 according to the embodiment of the present invention may be omitted according to the selection of a person skilled in the art or the forming step may be changed if the outer layer circuit pattern 170 is formed. In addition, the surface treatment layer 190 according to the embodiment of the present invention may be selectively formed only in a desired pattern among the outer layer circuit pattern 170 and the metal layer 520 according to a selection of a person skilled in the art.

16, an external connection terminal 195 is formed.

The external connection terminal 195 is formed on the lower surface of the surface treatment layer 190 exposed to the outside by the protective layer 180 among the surface treatment layer 190 formed under the metal layer 520 do. Or the surface treatment layer 190 and the protective layer 180 are omitted, the external connection terminal 195 is formed on the lower surface of the connection pad 110 exposed from the first insulation layer 131. The external connection terminal 195 according to the embodiment of the present invention is a component for electrically connecting an external component such as a substrate, a package, a main board and the like to the package substrate 100. For example, the external connection terminal 195 may be a solder ball. However, the shape of the external connection terminal 195 is not limited to a ball shape.

A package substrate 100 manufactured according to an embodiment of the present invention is formed with a cavity 121. When an electronic device (not shown) of a lower package (not shown) is placed in the cavity 121 . Therefore, the gap between the package substrate 100 and the lower package becomes narrower by the thickness of the cavity 121. [ Accordingly, the package substrate 100 and the lower package according to the embodiment of the present invention can be connected to the external connection terminal 195 having a small size. As the size of the external connection terminal 195 becomes smaller, the external connection terminal 195 can be disposed at a minute interval and the occurrence of a failure due to a bridge between the external connection terminals 195 can be prevented or reduced can do.

The manufacturing method of the package substrate 100 according to the embodiment of the present invention is not limited to the method shown in FIG. 2 to FIG. The method of FIGS. 2 to 16 is only an embodiment, and the carrier substrate, the circuit pattern forming method, the etching method, and the like can be changed to any of structures and methods known in the circuit board field depending on the choice of a person skilled in the art.

17 is an exemplary view showing a stacked package according to an embodiment of the present invention.

Referring to FIG. 17, the stacked package 300 according to the embodiment of the present invention has a structure in which the upper package 330 is stacked on the lower package 310.

According to an embodiment of the present invention, the lower package 310 includes a lower package substrate 210 and a first electronic component 220.

The lower package substrate 210 according to the embodiment of the present invention includes an insulating layer and a circuit pattern formed on the insulating layer. A first electronic device 220 is disposed on top of the lower package substrate 210.

The first electronic device 220 according to an embodiment of the present invention may be any type of electronic device that can be applied in the packaging field.

In addition, a first external connection terminal 320 may be formed under the lower package 310 according to an embodiment of the present invention. The first external connection terminal 320 according to the embodiment of the present invention may be a solder ball.

In accordance with an embodiment of the present invention, the top package 330 includes an upper package substrate 230, a second electronic component 240, and a molding portion 250.

The upper package substrate 230 according to the embodiment of the present invention is the package substrate 100 of FIG.

In accordance with an embodiment of the present invention, a second electronic component 240 is disposed on top of the top package substrate 230. At this time, the second electronic element 240 is electrically connected to the outer layer circuit pattern 170 of the upper package substrate 230 through a wire. The second electronic component 240 and the upper package substrate 230 are connected to each other by wires. However, the present invention is not limited thereto. That is, the second electronic component 240 and the top package 330 may be electrically connected through a conductive material such as a solder bump or a solder ball. Also, according to an embodiment of the present invention, the second electronic device 240 may be a memory device. However, the type of the second electronic device 240 is not limited to a memory device, and may be any type of electronic device applicable to the package field.

According to an embodiment of the present invention, the molding part 250 is formed on the upper package substrate 230 and is formed to cover the second electronic device 240. The molding part 250 according to the embodiment of the present invention is formed to protect the second electronic device 240 from the outside. For example, the molding part 250 may be formed of an epoxy molding compound (EMC). However, the material of the molding part 250 is not limited to EMC.

According to an embodiment of the present invention, a second external connection terminal 340 may be formed under the upper package 330. The second external connection terminal 340 according to the embodiment of the present invention is the external connection terminal 195 shown in Fig.

The first electronic component 220 is positioned within the cavity 121 of the upper package substrate 230 when the upper package 330 is laminated to the lower package 310. [ At this time, the gap between the upper package 330 and the lower package 310 is narrowed by the depth of the cavity 121 by the cavity 121. Connection pads 110 are formed on both sides of the cavity 121 to electrically connect the inside of the upper package 330 to the second external connection terminals 340. Accordingly, even though the second external connection terminal 340 is formed of a small-sized solder ball, the upper package 330 and the lower package 310 can be sufficiently connected. Since the second external connection terminals 340 are formed of small-sized solder balls, a plurality of the second external connection terminals 340 can be arranged at minute intervals. In addition, it is possible to prevent or reduce the occurrence of defects by the bridges between the second external connection terminals 340. Further, since the second external connection terminal 340 of a small size is used, the thickness of the stacked package 300 can also be reduced.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the same is by way of illustration and example only and is not to be construed as limiting the present invention. It is obvious that the modification or improvement is possible.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

100: Package substrate
110: connection pad
120: cavity pattern
121: cavity
130: insulating layer
131: first insulating layer
135: second insulating layer
140: 1st Via
150: Inner layer circuit pattern
160: Second Via
170: outer layer circuit pattern
180: protective layer
190: Surface treatment layer
195: External connection terminal
210: Lower package substrate
220: first electronic element
230: upper package substrate
240: second electronic element
250: Molding part
300: stacked package
310: Lower package
320: first external connection terminal
330: Upper package
340: second external connection terminal
500: carrier substrate
510: carrier core
520: metal layer
530: plating resist
531, 541:
540: etching resist

Claims (19)

Insulating layer;
A cavity formed to have a depth from the lower surface of the insulating layer; And
A connection pad formed in the insulating layer and formed on at least one side of the cavity;
≪ / RTI >
The method according to claim 1,
And the connection pad is formed to surround the side edge of the cavity.
The method according to claim 1,
Wherein the connection pad has a thickness equal to or thinner than the insulation layer.
The method according to claim 1,
And a via formed in the insulating layer and formed on an upper surface of the connection pad.
The method of claim 4,
And the insulating layer is penetrated by the via formed on the upper surface of the connection pad and the connection pad.
The method according to claim 1,
And a metal layer formed on a lower surface of the connection pad.
The method of claim 4,
And an inner layer circuit pattern formed on the insulating layer and bonded to an upper surface of the via.
Forming a connection pad and a cavity pattern on the carrier substrate;
Forming an insulating layer formed on the carrier substrate to fill the connection pads and the cavity pattern;
Removing the carrier substrate; And
Removing the cavity pattern;
Wherein the package substrate has a first surface and a second surface.
The method of claim 8,
In the step of forming the connection pad and the cavity pattern,
Wherein the carrier substrate comprises a metal layer on an upper portion or upper and lower portions of the carrier core.
The method of claim 8,
Wherein the step of removing the carrier substrate comprises:
Separating the carrier core and the metal layer to remove the carrier core;
Forming an etching resist which is formed on a lower portion of the metal layer and is formed at a position corresponding to the connection pad; And
Removing the exposed metal layer by the etching resist;
Wherein the package substrate has a first surface and a second surface.
The method of claim 8,
In the step of forming the connection pad and the cavity pattern,
Wherein the connection pad and the cavity pattern are formed by an electrolytic plating method.
The method of claim 8,
After the step of forming the insulating layer,
And forming a via formed on the upper surface of the connection pad so as to penetrate the insulating layer.
The method of claim 12,
The step of forming the vias, or thereafter,
And forming an inner layer circuit pattern formed on the insulating layer and bonded to an upper surface of the via.
A lower package comprising a lower package substrate and a first electronic component disposed over the lower package substrate;
An upper package including an insulating layer, a cavity formed so as to have a depth from the lower surface of the insulating layer, and a connection pad formed inside the insulating layer and formed on at least one side of the cavity. And
An external connection terminal formed between a circuit pattern of the lower package substrate and a connection pad of the upper package substrate to electrically connect the upper package and the lower package;
, ≪ / RTI &
Wherein at least a portion of the first electronic component is inserted into the cavity.
15. The method of claim 14,
Wherein the connection pad is configured to surround a side edge of the cavity.
15. The method of claim 14,
And a via formed in the insulating layer and formed on an upper surface of the connection pad.
18. The method of claim 16,
Wherein the insulating layer is penetrated by the connection pad and a via formed on the upper surface of the connection pad.
15. The method of claim 14,
And a metal layer formed on a lower surface of the connection pad and in contact with the external connection terminal.
18. The method of claim 16,
And an inner layer circuit pattern formed on the insulating layer and bonded to an upper surface of the via.
KR1020140174195A 2014-05-23 2014-12-05 Package board, method for manufacturing the same and package on packaage having the thereof KR20150135046A (en)

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TW104116329A TW201603665A (en) 2014-05-23 2015-05-21 Printed circuit board, method for manufacturing the same and package on package having the same
US14/719,309 US20150342046A1 (en) 2014-05-23 2015-05-21 Printed circuit board, method for maufacturing the same and package on package having the same
CN201510271845.9A CN105101636A (en) 2014-05-23 2015-05-25 Printed circuit board, method for manufacturing the same and package on package having the same

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CN107731698A (en) * 2017-10-26 2018-02-23 日月光半导体(上海)有限公司 Ic package, package substrate and its manufacture method

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US10163867B2 (en) 2015-11-12 2018-12-25 Amkor Technology, Inc. Semiconductor package and manufacturing method thereof
US10410999B2 (en) 2017-12-19 2019-09-10 Amkor Technology, Inc. Semiconductor device with integrated heat distribution and manufacturing method thereof
US10506712B1 (en) * 2018-07-31 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Printed circuit board
KR102238223B1 (en) * 2018-08-28 2021-04-09 성균관대학교산학협력단 A method for flip-chip bonding using anisotropic adhesive polymer

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Publication number Priority date Publication date Assignee Title
CN107731698A (en) * 2017-10-26 2018-02-23 日月光半导体(上海)有限公司 Ic package, package substrate and its manufacture method
CN107731698B (en) * 2017-10-26 2024-03-26 日月光半导体(上海)有限公司 Integrated circuit package, package substrate and manufacturing method thereof

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