KR20150135048A - Printed circuit board, method for manufacturing the same and package on packaage having the thereof - Google Patents

Printed circuit board, method for manufacturing the same and package on packaage having the thereof Download PDF

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Publication number
KR20150135048A
KR20150135048A KR1020140194133A KR20140194133A KR20150135048A KR 20150135048 A KR20150135048 A KR 20150135048A KR 1020140194133 A KR1020140194133 A KR 1020140194133A KR 20140194133 A KR20140194133 A KR 20140194133A KR 20150135048 A KR20150135048 A KR 20150135048A
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South Korea
Prior art keywords
cavity
insulating layer
layer
electronic component
present
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KR1020140194133A
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Korean (ko)
Inventor
김혜진
정혜원
강명삼
봉강욱
고영관
성민재
Original Assignee
삼성전기주식회사
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Application filed by 삼성전기주식회사 filed Critical 삼성전기주식회사
Priority to US14/719,309 priority Critical patent/US20150342046A1/en
Priority to TW104116329A priority patent/TW201603665A/en
Priority to CN201510271845.9A priority patent/CN105101636A/en
Publication of KR20150135048A publication Critical patent/KR20150135048A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

The present invention relates to a printed circuit board, a method for manufacturing the printed circuit board, and a stacked package including the same. According to one embodiment of the present invention, the printed circuit board includes one side connected to one side of a substrate on which a first electronic component is mounted, and at least one insulation layer. A cavity receiving at least a part of the first electronic component is formed on the insulation layer and an inner side of the cavity is made of an insulating material.

Description

TECHNICAL FIELD [0001] The present invention relates to a printed circuit board, a method of manufacturing a printed circuit board, and a stacked package including the printed circuit board,

The present invention relates to a printed circuit board, a method of manufacturing a printed circuit board, and a stacked package including the same.

Recently, the electronics industry adopts a mounting technique using a multi-layer printed circuit board (PCB) which enables high density and high integration in component mounting for miniaturization and thinning of electronic devices. Such multilayer printed circuit boards are being developed through the development of elemental technologies such as substrate microcircuits and bumps for high density and high integration. 2. Description of the Related Art Recently, semiconductor packages such as SIP (System In Package), CSP (Chip Sized Package), and FCP (Flip Chip Package) in which electronic components are mounted on a printed circuit board in advance to form packages are actively being developed. There is also a package on package (POP) in which a control device and a memory device are implemented as a single package in order to miniaturize a high-performance smart phone and improve performance. The stacked package can be implemented by separately packaging the control device and the memory device, stacking them, and connecting them.

United States Patent No. 5986209

An aspect of the present invention is to provide a printed circuit board, a method of manufacturing a printed circuit board, and a stacked package including the printed circuit board, which facilitates reduction in bridge generation and fine pitch of external connection terminals.

Another aspect of the present invention is to provide a printed circuit board, a method of manufacturing a printed circuit board, and a stacked package including the same, which can reduce the overall thickness of the stacked package.

According to an embodiment of the present invention, there is provided a printed circuit board connected to one surface of a substrate on which a first electronic component is mounted and having at least one insulating layer, wherein the insulating layer contains at least a portion of the first electronic component And the inner surface of the cavity is provided with a printed circuit board made of an insulating material.

The cavity is recessed on the lower surface of the insulating layer.

And a connection pad formed inside the insulating layer and spaced apart from the cavity and formed on at least one side thereof.

The connection pad is formed to have the same or a thin thickness as the insulating layer.

The entire inner surface of the cavity is made of the same insulating material as the insulating layer.

According to another embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a cavity pattern on a carrier substrate; forming an insulating layer formed on the carrier substrate to fill the cavity pattern; removing the carrier substrate; The method comprising the steps of:

In the step of forming the cavity pattern, a connection pad is further formed on the carrier substrate when the cavity pattern is formed.

According to another embodiment of the present invention, there is provided a package comprising: a lower package including a lower package substrate and a first electronic component disposed on the lower package substrate, at least one insulating layer, And an external connection terminal formed between the lower package substrate and the upper package substrate to electrically connect the upper package substrate and the lower package substrate, wherein the cavity is formed with a cavity A stacked package is provided in which at least a portion of one electronic component is housed in a cavity.

1 is an exemplary view illustrating a printed circuit board according to an embodiment of the present invention.
FIGS. 2 to 16 are views showing an example of a method of manufacturing a printed circuit board according to an embodiment of the present invention.
17 is an exemplary view showing a stacked package according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The objectives, specific advantages and novel features of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. It should be noted that, in the present specification, the reference numerals are added to the constituent elements of the drawings, and the same constituent elements are assigned the same number as much as possible even if they are displayed on different drawings. It will be further understood that terms such as " first, "" second," " one side, "" other," and the like are used to distinguish one element from another, no. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description of the present invention, detailed description of related arts which may unnecessarily obscure the gist of the present invention will be omitted.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an exemplary view illustrating a printed circuit board according to an embodiment of the present invention.

Although the printed circuit board 100 according to the embodiment of the present invention is not shown, it is connected to one surface of a substrate on which an electronic component is mounted on one surface. In the printed circuit board 100, at least one insulating layer 130 is formed. The insulating layer 130 is formed with a cavity 121 for accommodating at least a part of an electronic component (not shown), and the inner surface of the cavity 121 is made of an insulating material.

Referring to FIG. 1, a printed circuit board 100 according to an embodiment of the present invention includes an insulating layer 130, a connection pad 110, an inner layer circuit pattern 150, an outer layer circuit pattern 170, 140, a second via 160, and a protective layer 180.

According to an embodiment of the present invention, the insulating layer 130 may be formed of a composite polymer resin, which is typically used as an interlayer insulating material. For example, the insulating layer 130 may be formed of an epoxy resin such as prepreg, ABF (Ajinomoto Build-up Film), FR-4, and BT (Bismaleimide Triazine). However, the material forming the insulating layer 130 in the embodiment of the present invention is not limited thereto. The insulating layer 130 according to embodiments of the present invention may be selected from those known in the field of circuit boards.

In the embodiment of the present invention, the insulating layer 130 is divided into a first insulating layer 131 and a second insulating layer 135. The second insulating layer 135 is formed on the first insulating layer 131.

In FIG. 1, the first insulating layer 131 and the second insulating layer 135 are formed of the same material. However, the first insulating layer 131 and the second insulating layer 135 are not limited to be formed of the same material in the embodiment of the present invention. For example, the first insulating layer 131 may be formed of an insulating material containing glass fibers, and the second insulating layer 135 may be formed of an insulating material containing no glass fibers. As such, the material of the first insulating layer 131 and the second insulating layer 135 can be changed according to the choice of a person skilled in the art.

According to the embodiment of the present invention, the first insulating layer 131 is formed with a cavity 121 having a predetermined depth from the bottom to the inside. That is, according to the embodiment of the present invention, the cavity 121 is formed in a concave shape on the lower surface of the first insulating layer 131. In forming the stacked package in the cavity 121 according to the embodiment of the present invention, at least a part of the electronic component (not shown) of the lower package is accommodated. Therefore, the cavity 121 according to the embodiment of the present invention is formed to have a size such that at least a part of the electronic component can be inserted therein. At this time, although the cavity 121 is not shown, it accommodates the electronic components in a state spaced apart by a predetermined distance. In addition, according to the embodiment of the present invention, the cavity 121 is formed in the first insulating layer 131 so that the entire inner surface of the cavity 121 is made of an insulating material. That is, the inner surface of the cavity 121 may be formed of the first insulating layer 131.

1, the depth of the cavity 121 is formed to be smaller than the thickness of the first insulating layer 131. As shown in FIG.

According to an embodiment of the present invention, the connection pad 110 is formed to be embedded in the first insulating layer 131. Although the connection pad 110 is illustrated as being formed on the left and right sides of the cavity 121 in FIG. 1, the connection pad 110 may be formed to surround the side edge of the cavity 121.

According to the embodiment of the present invention, the connection pad 110 is formed to have the same or a thin thickness as the first insulation layer 131. [ Here, the connection pad 110 according to the embodiment of the present invention is formed to have a thickness corresponding to the depth of the cavity 121. For example, as shown in FIG. 1, the connection pad 110 is formed to have the same thickness as the depth of the cavity 121. Here, the same means substantially the same (Substantially same). That is, the same means the same in consideration of errors or deviations occurring in the manufacturing process.

In the embodiment of the present invention, the connection pad 110 is formed to have a thicker thickness than other circuit patterns as shown in FIG.

A metal layer 520 may be formed under the connection pad 110 according to an embodiment of the present invention. The metal layer 520 is formed under the connection pad 110 and protrudes from the first insulating layer 131.

The connection pad 110 and the metal layer 520 according to the embodiment of the present invention are formed of copper (Cu). However, the material of the connection pad 110 and the metal layer 520 is not limited to copper, and may be conductive material used in the circuit board field.

According to the embodiment of the present invention, the inner layer circuit pattern 150 is formed inside the insulating layer 130. For example, the inner layer circuit pattern 150 may be formed on the first insulating layer 131 and may be formed to be embedded in the second insulating layer 135. In the embodiment of the present invention, the inner layer circuit pattern 150 is shown and described as being formed in one layer, but is not limited thereto. That is, the inner layer circuit pattern 150 according to the embodiment of the present invention may be formed as a multilayer of two or more layers according to the choice of a person skilled in the art.

According to the embodiment of the present invention, the outer layer circuit pattern 170 is formed on the upper portion of the second insulating layer 135.

The inner layer circuit pattern 150 and the outer layer circuit pattern 170 according to the embodiment of the present invention may be formed of copper (Cu). However, the material of the inner layer circuit pattern 150 and the outer layer circuit pattern 170 is not limited to copper, and may be one of conductive materials used in the circuit board field.

According to an embodiment of the present invention, the first via 140 is formed inside the first insulating layer 131. According to the embodiment of the present invention, the lower surface of the first via 140 is bonded to the connection pad 110, and the upper surface is bonded to the inner layer circuit pattern 150. The first via 140 thus formed electrically connects the connection pad 110 and the inner layer circuit pattern 150.

According to an embodiment of the present invention, the outer layer circuit pattern 170 may include a mounting pattern that is electrically connected to an external component when the external component is mounted on the insulating layer 130. For example, the mounting pattern is a portion shown in FIG. 1 so that at least a part of the outer layer circuit pattern 170 is exposed to the outside by the protection layer 180.

According to an embodiment of the present invention, the vias 140 are formed such that the upper surface has a larger diameter than the lower surface.

According to the embodiment of the present invention, the external component portion located outside the printed circuit board 100 and the inner layer circuit pattern 150 are electrically connected to each other by the connection pad 110, the first via 140 and the metal layer 520 . Here, the external component may be, for example, an electronic component, a printed circuit board, a main board substrate, a package, or the like.

In addition, when the printed circuit board 100 according to the embodiment of the present invention is laminated on the lower printed circuit board (not shown), a part of the electronic parts mounted in the lower package is accommodated in the cavity 121. Therefore, the distance between the printed circuit board 100 and the lower printed circuit board is reduced by the height of the electronic component housed in the cavity 121. [ Accordingly, the amount of the solder for connection to the lower printed circuit board (see the second external connection terminal 340 shown in FIG. 17) can be reduced as the distance is reduced. Accordingly, the rate of bridge generation between the solder is also lowered, and the assembly yield and the fine pitch of the connection pad 11 can be realized.

A second via 160 according to an embodiment of the present invention is formed within the second insulating layer 135. According to the embodiment of the present invention, the lower surface of the second via 160 is bonded to the inner layer circuit pattern 150, and the upper surface is bonded to the outer layer circuit pattern 170. The second via 160 thus formed electrically connects the inner layer circuit pattern 150 and the outer layer circuit pattern 170.

According to an embodiment of the present invention, the protective layer 180 is formed on the second insulating layer 135 and the outer layer circuit pattern 170. The protective layer 180 according to the embodiment of the present invention can prevent the solder from being applied when the outer layer circuit pattern 170 is subjected to soldering for mounting an electronic component (not shown) , The protective layer 180 can prevent the outer layer circuit layer from being oxidized and corroded.

The protective layer 180 according to an embodiment of the present invention is formed to expose a part of the outer layer circuit pattern 170. At this time, the outer layer circuit pattern 170 exposed by the protective layer 180 may be a mounting pattern electrically connected to an external component such as an electronic component.

In addition, according to an embodiment of the present invention, the protective layer 180 is formed under the first insulating layer 131 to expose the metal layer 520. The metal layer 520 exposed by the passivation layer 180 may be a region electrically connected to the external component.

According to an embodiment of the present invention, the protective layer 180 is formed of a heat resistant coating material. For example, the protective layer 180 may be formed of a solder resist.

According to the embodiment of the present invention, the protective layer 180 can be formed by changing the area formed according to the selection of a person skilled in the art, and can be omitted.

According to an embodiment of the present invention, the surface treatment layer 190 is formed on the outer layer circuit pattern 170 exposed by the protective layer 180. In addition, the surface treatment layer 190 is formed on the metal layer 520 exposed by the protective layer 180. The surface treatment layer 190 is formed to prevent the outer layer circuit pattern 170 and the metal layer 520 exposed by the protective layer 180 from being corroded and oxidized. For example, the surface treatment layer 190 may be any surface treatment layer known in the circuit board art, such as plating nickel, tin, gold, palladium, or the like, or coating an Organic Solderability Preservative (OSP) .

The surface treatment layer 190 according to an embodiment of the present invention may be omitted according to the choice of a person skilled in the art.

Although not shown in FIG. 1, external connection terminals (not shown) may be formed under the printed circuit board 100. The external connection terminal may be formed of a solder material.

In the embodiment of the present invention, the thickness of the connection pad 110 is formed to have the depth of the cavity 121 so that the first via 140 is formed for electrical connection with the inner layer circuit pattern 150 But the present invention is not limited thereto. For example, if the connection pad 110 according to the embodiment of the present invention is formed to have a thickness that penetrates through the first insulating layer 131, the first via 140 is directly connected to the inner layer circuit pattern 150, .

The printed circuit board 100 according to the embodiment of the present invention includes a cavity 121 in which electronic components of a lower printed circuit board are disposed and a connection pad 110 that narrows a gap between the lower package and the lower package. Therefore, when the stacked package is formed later, the thickness of the entire stacked package can be reduced by the printed circuit board 100 according to the embodiment of the present invention. A stacked package to which the printed circuit board 100 according to the embodiment of the present invention is applied will be described later with reference to FIG.

Conventionally, a cavity is formed on an upper surface of a substrate, and an electronic part accommodated in the cavity is directly electrically connected to the substrate. Therefore, a protective layer and solder must be formed inside the cavity. However, the upper surface of the substrate has a stepped structure by the cavity, and forming the protective layer and solder on the upper surface of the substrate including the cavity has a complicated process and the like.

The printed circuit board 100 according to the embodiment of the present invention is not directly electrically connected to the electronic parts accommodated in the cavity 121. [ Here, direct electrical connection means that the electronic components are electrically connected to each other by the circuit pattern of the printed circuit board 100 and the solder (external connection terminal) inside the cavity 121. [ Therefore, the protective layer 180 and the solder are not formed in the cavity 121 of the printed circuit board 100.

FIGS. 2 to 16 are views showing an example of a method of manufacturing a printed circuit board according to an embodiment of the present invention.

Referring to FIG. 2, a carrier substrate 500 is provided.

The carrier substrate 500 according to the embodiment of the present invention is a structure for supporting an insulating layer and a circuit layer for a printed circuit board when they are formed.

According to the embodiment of the present invention, the carrier substrate 500 is a structure in which the metal layer 520 is laminated on the carrier core 510.

For example, the carrier core 510 is formed of an insulating material. However, the material of the carrier core 510 is not limited to an insulating material, and may be a metal material or a structure in which one or more layers of an insulating layer and a metal layer are stacked.

For example, the metal layer 520 is formed of copper (Cu). However, the material of the metal layer 520 is not limited to copper, and any conductive material used in the field of circuit boards may be used without limitation.

In the embodiment of the present invention, the carrier substrate 500 is shown and described as a structure in which a single metal layer 520 is laminated on both sides of the carrier core 510, but the structure of the carrier substrate 500 is not limited thereto . That is, the carrier substrate 500 in the embodiment of the present invention is schematically shown for the convenience of explanation and understanding. For example, the carrier substrate 500 may be formed by stacking a plurality of metal layers on a carrier core and forming a release layer between the metal layers of the plurality of layers. Accordingly, the carrier layer can be separated from and removed from the printed circuit board with the exception of the metal layer formed on the outermost layer, as the release layer is separated later. The structure of the carrier substrate 500 is not limited to the structure shown and described in the embodiment of the present invention. That is, a carrier substrate of any structure used in the technical field is applicable to this embodiment.

Referring to FIG. 3, a plating resist 530 is formed on the carrier substrate 500.

According to an embodiment of the present invention, a plating resist 530 is formed on the metal layer 520 of the carrier substrate 500. The plating resist 530 according to the embodiment of the present invention has an opening 531 for exposing a connection pad (not shown) and a metal layer 520 in a region where a cavity pattern (not shown) is to be formed. Here, the region where the cavity pattern is to be formed is formed to have a size such that the electronic component can be mounted.

Referring to FIG. 4, a connection pad 110 and a cavity pattern 120 are formed on a carrier substrate 500.

According to an embodiment of the present invention, the connection pad 110 and the cavity pattern 120 are formed on the metal layer 520 of the carrier substrate 500.

According to the embodiment of the present invention, the connection pad 110 and the cavity pattern 120 are formed by performing electrolytic plating on the opening 531 of the plating resist 530. At this time, the metal layer 520 exposed through the opening 531 of the plating resist 530 may serve as a seed layer for electroplating.

The connection pad 110 according to the embodiment of the present invention is a circuit pattern electrically connected to an external component.

Further, the cavity pattern 120 is formed in order to secure a space in which the electronic components mounted on the lower printed circuit board are located when the stacked package is formed. Thus, the cavity pattern 120 is formed to have a size such that the electronic component can be located inside the cavity (not shown).

In the embodiment of the present invention, the connection pad 110 is formed to have the same thickness because it is formed in the same process as the cavity pattern 120. Here, the same means substantially the same (Substantially same). That is, the same means the same in consideration of errors or deviations occurring in the manufacturing process. However, the connection pad 110 is not necessarily formed to have the same thickness as the cavity pattern 120. Depending on the choice of those skilled in the art, the connection pad 110 may be formed thicker or thinner than the cavity pattern 120.

Referring to Fig. 5, the plating resist (530 in Fig. 4) is removed.

Referring to FIG. 6, a first insulating layer 131 is formed.

The first insulating layer 131 is formed on the metal layer 520 to cover the connection pad 110 and the cavity pattern 120. In this case, The upper surface of the first insulating layer 131 is formed to be positioned higher than the upper surface of the connection pad 110 and the upper surface of the cavity pattern 120. [ That is, the first insulating layer 131 is formed to have a larger thickness than the cavity pattern 120.

According to an embodiment of the present invention, the first insulating layer 131 may be formed by stacking a metal layer 520, a connection pad 110, and a cavity pattern 120 on a film in a film form, followed by pressing. The first insulating layer 131 according to the embodiment of the present invention may be formed by any method of forming the insulating layer in the circuit substrate field as well as the above-described method.

The first insulating layer 131 according to the embodiment of the present invention may be formed of a composite polymer resin which is typically used as an interlayer insulating material. For example, the first insulating layer 131 may be formed of an epoxy resin such as prepreg, ABF (Ajinomoto Build-up Film), FR-4, and BT (Bismaleimide Triazine). However, the material forming the first insulating layer 131 in the embodiment of the present invention is not limited thereto. The first insulating layer 131 according to an embodiment of the present invention may be selected from insulating materials known in the circuit board field.

Referring to FIG. 7, an inner layer circuit pattern 150 and a first via 140 are formed.

The inner layer circuit pattern 150 is formed on the first insulating layer 131 and the first vias 140 are formed on the inner surface of the first insulating layer 131. In this embodiment,

The first via 140 according to the embodiment of the present invention is formed on the first insulating layer 131 formed on the connection pad 110. That is, the first via 140 passes through the first insulating layer 131 formed on the connection pad 110, the upper surface thereof is joined to the inner layer circuit pattern 150, and the lower surface thereof is connected to the connection pad 110 do. The inner layer circuit pattern 150 and the connection pads 110 are electrically connected by the first vias 140 thus formed. In addition, the first vias 140 are formed such that the upper surface has a larger diameter than the lower surface.

The inner layer circuit pattern 150 and the first via 140 according to the embodiment of the present invention can be formed by processing a via hole (not shown), forming a patterned plating resist (not shown), and then performing plating . Alternatively, the inner layer circuit pattern 150 and the first via 140 according to the embodiment of the present invention may be formed by processing a via hole, performing plating, forming an etching resist, and performing an etching process. The inner layer circuit pattern 150 and the first via 140 may be formed by any method known in the circuit board art, for example, As shown in FIG.

In addition, the inner layer circuit pattern 150 and the first via 140 according to the embodiment of the present invention may be formed of any conductive material used in the circuit board field. For example, the innerlayer circuit pattern 150 and the first via 140 are formed of copper (Cu).

In the embodiment of the present invention, the inner layer circuit pattern 150 is formed as one layer. However, the present invention is not limited to this structure. That is, the inner layer circuit pattern 150 according to the embodiment of the present invention may be formed in multiple layers according to the selection of a person skilled in the art. In this case, the first insulating layer 131 may be formed in multiple layers, and vias may be formed to connect the inner layer circuit patterns 150 of each layer to each other.

Referring to FIG. 8, a second insulating layer 135 is formed.

According to an embodiment of the present invention, the second insulating layer 135 is formed on the first insulating layer 131 to cover the inner layer circuit pattern 150.

According to an embodiment of the present invention, the second insulating layer 135 may be formed by depositing a film on the first insulating layer 131 and the inner layer circuit pattern 150, and then pressing the second insulating layer 135. The second insulating layer 135 according to the embodiment of the present invention may be formed by any method of forming the insulating layer in the circuit substrate field as well as the method described above.

According to an embodiment of the present invention, the second insulating layer 135 may be formed of an insulating material that does not contain glass fibers among interlayer insulating materials that are commonly used. However, the material of the second insulating layer 135 is not limited thereto. That is, the second insulating layer 135 according to the embodiment of the present invention may be formed of the same material as that of the first insulating layer 131, and may be any of the conventional interlayer insulating materials used in the field of circuit boards.

Referring to FIG. 9, an outer layer circuit pattern 170 and a second via 160 are formed.

The outer layer circuit pattern 170 is formed on the top of the second insulating layer 135 and the second vias 160 are formed on the inside of the second insulating layer 135. [

The outer layer circuit pattern 170 according to the embodiment of the present invention is a circuit pattern formed on the outermost layer of the printed circuit board 100. Therefore, a part of the pattern of the outer layer circuit pattern 170 may be electrically connected to an external component such as an electronic component, a package, a substrate, and the like. Here, some of the patterns may be a mounting pattern electrically connected to an electronic component mounted on the second insulating layer 135.

The second via 160 according to the embodiment of the present invention is formed so as to penetrate the second insulating layer 135 and to be bonded to the outer layer circuit pattern 170 on the upper surface and to the innerlayer circuit pattern 150 on the lower surface. The inner layer circuit pattern 150 and the outer layer circuit pattern 170 are electrically connected by the second vias 160 thus formed.

The method and material of forming the outer layer circuit pattern 170 and the second via 160 according to the embodiment of the present invention are the same as the method of forming the inner layer circuit pattern 150 and the first via 140 of FIG. References

Referring to FIG. 10, a protective layer 180 is formed.

According to an embodiment of the present invention, the protective layer 180 is formed on the second insulating layer 135 and the outer layer circuit pattern 170. The protective layer 180 according to the embodiment of the present invention can prevent the solder from being applied when the outer layer circuit pattern 170 is soldered for mounting of an electronic component (not shown). Further, the protective layer 180 can prevent the outer layer circuit layer from being oxidized and corroded.

The protective layer 180 according to an embodiment of the present invention is formed to expose a part of the outer layer circuit pattern 170. At this time, the outer layer circuit pattern 170 exposed by the protective layer 180 may be a mounting pattern electrically connected to an external component such as an electronic component.

According to an embodiment of the present invention, the protective layer 180 is formed of a heat resistant coating material. For example, the protective layer 180 may be formed of a solder resist.

Referring to FIG. 11, the carrier substrate 500 is removed.

According to an embodiment of the present invention, after the carrier core 510 and the metal layer 520 are separated, the carrier core 510 is removed. When the carrier core 510 is removed, the printed circuit board 100 formed on both sides of the carrier substrate 500 is separated.

Referring to FIG. 12, an etching resist 540 is formed.

The etching resist 540 according to the embodiment of the present invention is formed to prevent the connection pad 110 from being damaged when the cavity pattern 120 is etched in the future. Thus, the etching resist 540 is formed under the connection pad 110 to protect the connection pad 110 from the etching process. At this time, the etching resist 540 simultaneously protects a part of the metal layer 520 located in the region where the connection pad 110 is formed.

The etching resist 540 according to the embodiment of the present invention is formed with the opening 541 so as to expose an area other than the area where the connection pad 110 is formed.

In addition, the etching resist 540 according to the embodiment of the present invention should be formed of a material that does not react with the etching solution, if a subsequent etching process uses an etching solution.

Referring to Fig. 13, a cavity 121 is formed.

According to an embodiment of the present invention, an etching process is performed. The metal layer 520 and the cavity pattern 120 in the region exposed by the opening 541 of the etching resist 540 are removed by the etching process.

According to an embodiment of the present invention, the etching process may be performed with an etchant in which the cavity pattern (120 in FIG. 12) and the metal layer 520 react. At this time, the etching resist 540 should not react with the etching solution used.

According to the embodiment of the present invention, the cavity pattern (120 in FIG. 12) is removed by the etching process, and the cavity 121 is formed. In forming the stacked package in the cavity 121 according to the embodiment of the present invention, at least a part of the electronic component (not shown) of the lower package is accommodated. According to the embodiment of the present invention, the cavity 121 is formed by removing the cavity pattern (120 in FIG. 12) formed in the first insulating layer 131, so that the entire inner surface of the cavity 121 is made of an insulating material . That is, the inner surface of the cavity 121 may be formed of the first insulating layer 131.

According to the embodiment of the present invention, when the etching process is performed, the connection pad 110 and the metal layer 520 located between the connection pad 110 and the etching resist 540 are not etched by the etching resist 540 Protected.

As a method of forming the cavity 121, there is a method of removing the cavity portion with a laser after stacking the insulating film, but a laser starter layer which is expensive and can stop the progress of the laser during laser processing is separately required. As another method, there is a method of laminating the portion where the cavity of the insulating film is to be formed in advance, and then laminating it. However, the previously cut side is flowed to the high temperature in the process of forming the insulating layer, so that the cavity wall surface is not uniform. However, in the present invention, since the cavity 121 is formed by etching the cavity pattern 120 as described above, the cavity 121 having a low process cost and uniform wall surface can be formed.

The depth of the cavity 121 thus formed is smaller than the thickness of the first insulating layer 131.

Referring to Fig. 14, the etching resist (540 in Fig. 13) is removed.

According to an embodiment of the present invention, the metal layer 520 formed under the connection pad 110 by the etching resist (540 in Fig. 13) is protected from the etching process. Thus, when the etching resist (540 in FIG. 13) is removed, the protected metal layer 520 protrudes from the lower surface of the first insulating layer 131 as shown.

Referring to FIG. 15, a surface treatment layer 190 may be formed.

According to an embodiment of the present invention, a protective layer 180 is formed under the first insulating layer 131. The protective layer 180 formed under the first insulating layer 131 is formed to expose the metal layer 520 to the outside. At this time, the metal layer 520 exposed to the outside is a portion connected to an external connection terminal (not shown).

The protective layer 180 formed under the first insulating layer 131 according to the embodiment of the present invention is not necessarily formed at this stage. The protective layer 180 may be formed at any stage after the metal layer 520 is patterned. In addition, the protective layer 180 formed under the first insulating layer 131 according to the embodiment of the present invention may be omitted according to the selection of a person skilled in the art.

According to an embodiment of the present invention, the surface treatment layer 190 is formed on the outer layer circuit pattern 170 exposed by the protective layer 180. For example, the surface treatment layer 190 is formed in the mounting pattern in the outer layer circuit pattern 170. In addition, according to an embodiment of the present invention, the surface treatment layer 190 is formed on the metal layer 520 exposed by the protective layer 180.

The surface treatment layer 190 according to the embodiment of the present invention is formed to prevent the outer layer circuit pattern 170 and the metal layer 520 exposed by the protective layer 180 from being corroded and oxidized. For example, the surface treatment layer 190 may be formed by a known surface treatment method in the circuit board field, such as plating nickel, tin, gold, palladium, or the like, or coating an Organic Solder ability Preservative (OSP) have.

The step of forming the surface treatment layer 190 according to the embodiment of the present invention may be omitted according to the selection of a person skilled in the art or the forming step may be changed if the outer layer circuit pattern 170 is formed. In addition, the surface treatment layer 190 according to the embodiment of the present invention may be selectively formed only in a desired pattern among the outer layer circuit pattern 170 and the metal layer 520 according to a selection of a person skilled in the art.

16, an external connection terminal 195 is formed.

The external connection terminal 195 is formed on the lower surface of the surface treatment layer 190 exposed to the outside by the protective layer 180 among the surface treatment layer 190 formed under the metal layer 520 do. Or the surface treatment layer 190 and the protective layer 180 are omitted, the external connection terminal 195 is formed on the lower surface of the connection pad 110 exposed from the first insulation layer 131. The external connection terminal 195 according to the embodiment of the present invention is a component for electrically connecting an external component such as a substrate, a package, a main board and the like to the printed circuit board 100. For example, the external connection terminal 195 may be formed of a ball-shaped solder material. However, the shape of the external connection terminal 195 is not limited to a ball shape.

A cavity 121 is formed in the printed circuit board 100 manufactured according to the embodiment of the present invention. Further, when the stacked package is formed, the cavity 121 accommodates a part of the electronic component (not shown) mounted on the lower package (not shown). Therefore, the gap between the printed circuit board 100 and the lower package becomes narrower by the thickness of the electronic component housed in the cavity 121. [ Therefore, the printed circuit board 100 and the lower package according to the embodiment of the present invention can be connected to the external connection terminal 195 having a small size. As the size of the external connection terminal 195 becomes smaller, the external connection terminal 195 can be disposed at a minute interval and the occurrence of a failure due to a bridge between the external connection terminals 195 can be prevented or reduced can do.

The method of manufacturing the printed circuit board 100 according to the embodiment of the present invention is not limited to those shown in Figs. The method of FIGS. 2 to 16 is only an embodiment, and the carrier substrate, the circuit pattern forming method, the etching method, and the like can be changed to any of structures and methods known in the circuit board field depending on the choice of a person skilled in the art.

17 is an exemplary view showing a stacked package according to an embodiment of the present invention.

Referring to FIG. 17, the stacked package 300 according to the embodiment of the present invention has a structure in which the upper package 330 is stacked on the lower package 310.

According to an embodiment of the present invention, the lower package 310 includes a lower package substrate 210 and a first electronic component 220.

The lower package substrate 210 according to the embodiment of the present invention includes an insulating layer and a circuit pattern formed on the insulating layer. A first electronic component 220 is disposed on an upper portion of the lower package substrate 210.

The first electronic component 220 according to the embodiment of the present invention may be any kind of electronic component that can be applied to the package field.

In addition, a first external connection terminal 320 may be formed under the lower package 310 according to an embodiment of the present invention. The first external connection terminal 320 according to the embodiment of the present invention may be formed of a ball-shaped solder material.

According to an embodiment of the present invention, the top package 330 includes an upper package substrate 230, a second electronic component 240, and a first molding material 250.

The upper package substrate 230 according to the embodiment of the present invention is the printed circuit board 100 of FIG.

According to an embodiment of the present invention, the upper package substrate 230 is connected to one surface (upper surface) of the lower package substrate 210 on which the first electronic component 220 is mounted. The upper package substrate 230 includes at least one insulating layer. A cavity 121 for accommodating at least a part of the first electronic component 220 is formed in the insulating layer, and an inner surface of the cavity 121 is made of an insulating material.

According to an embodiment of the present invention, a second electronic component 240 is disposed on the upper package substrate 230. At this time, the second electronic component 240 is electrically connected to the outer layer circuit pattern 170 of the upper package substrate 230 through a wire. Here, the outer layer circuit pattern 170 electrically connected to the second electronic component 240 with a wire is a mounting pattern. In the embodiment of the present invention, the second electronic component 240 and the upper package substrate 230 are connected by wires. However, the present invention is not limited thereto. That is, the second electronic component 240 and the upper package 330 may be electrically connected through a conductive material. Further, according to the embodiment of the present invention, the second electronic component 240 may be a memory element. However, the type of the second electronic component 240 is not limited to the memory device, and may be any kind of electronic component that can be applied to the package field.

According to an embodiment of the present invention, the first molding material 250 is formed on the upper package substrate 230 to cover the second electronic component 240. The first molding material 250 according to the embodiment of the present invention is formed to protect the second electronic component 240 from the outside. For example, the first molding material 250 may be formed of an epoxy molding compound (EMC) or a silicone gel. However, the material of the first molding material 250 is not limited to the EMC and the silicone gel, and any molding material known in the known package art is also possible.

According to an embodiment of the present invention, a second external connection terminal 340 may be formed under the upper package 330. The second external connection terminal 340 according to the embodiment of the present invention is the external connection terminal 195 shown in Fig.

A portion of the first electronic component 220 is received in the cavity 121 of the upper package substrate 230. In this case, At this time, the cavity 121 accommodates the first electronic component 220 in a state of being spaced apart by a predetermined distance.

According to an embodiment of the present invention, a second molding material 260 may be formed between the inner surface of the cavity 121 and the first electronic component 220. That is, the second molding material 260 is formed to fill the space between the cavity 121 and the first electronic component 220. For example, the second molding material 260 may be formed of an epoxy molding compound (EMC). However, the material of the second molding material 260 is not limited to EMC, and any known molding material may be used in the known package field. 17, the second molding material 260 is also formed between the upper package 330 and the lower package 310, as well as between the cavity 121 and the first electronic component 220. However, if the second molding material 260 is formed between the cavity 121 and the first electronic component 220, whether or not the molding material is formed in other areas and the formation position can be changed.

The gap between the upper package 330 and the lower package 310 is narrowed by the cavity 121 by the thickness of the electronic component accommodated in the cavity 121. [ Connection pads 110 are formed on both sides of the cavity 121 to electrically connect the inside of the upper package 330 to the second external connection terminals 340. Therefore, even if the second external connection terminal 340 is formed of a small-sized solder, the upper package 330 and the lower package 310 can be sufficiently connected. Since the second external connection terminals 340 are formed of small-sized solder, a plurality of the second external connection terminals 340 can be arranged at minute intervals. In addition, it is possible to prevent or reduce the occurrence of defects by the bridges between the second external connection terminals 340. Further, since the second external connection terminal 340 of a small size is used, the thickness of the stacked package 300 can also be reduced.

Further, conventionally, a cavity for mounting electronic components is formed on the substrate of the lower package. When a cavity is formed in the lower package substrate as in the conventional art, the area in which a circuit can be formed is reduced by the area where the cavity is formed. In addition, a protective layer such as solder resist and a solder (external connection terminal) must be formed in the cavity for electrical connection with the electronic component. However, since the upper surface of the substrate by the cavity has a stepped structure, it is difficult to form the protective layer and the solder.

However, the printed circuit board (100 in FIG. 1) according to the embodiment of the present invention is applied to the upper package 330 in the stacked package 300. FIG. That is, the cavity 121 in which the electronic component is accommodated is formed on the lower surface of the upper package substrate 230. Also, the accommodated electronic component is not directly electrically connected to the upper package substrate 230 in the cavity 121. [ Therefore, it is not necessary to form the protective layer and the solder inside the cavity 121. [

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the same is by way of illustration and example only and is not to be construed as limiting the present invention. It is obvious that the modification or improvement is possible.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

100: printed circuit board
110: connection pad
120: cavity pattern
121: cavity
130: insulating layer
131: first insulating layer
135: second insulating layer
140: 1st Via
150: Inner layer circuit pattern
160: Second Via
170: outer layer circuit pattern
180: protective layer
190: Surface treatment layer
195: External connection terminal
210: Lower package substrate
220: first electronic component
230: upper package substrate
240: second electronic component
250: First molding material
260: second molding material
300: stacked package
310: Lower package
320: first external connection terminal
330: Upper package
340: second external connection terminal
500: carrier substrate
510: carrier core
520: metal layer
530: plating resist
531, 541:
540: etching resist

Claims (30)

1. A printed circuit board connected to one surface of a substrate on which a first electronic component is mounted and having at least one insulating layer,
Wherein a cavity for accommodating at least a part of the first electronic component is formed in the insulating layer, and an inner surface of the cavity is made of an insulating material.
The method according to claim 1,
Wherein a depth of the cavity is smaller than a thickness of the insulating layer.
The method according to claim 1,
And a mounting pattern formed on the insulating layer and electrically connected to a second electronic component mounted on the insulating layer.
The method according to claim 1,
And a connection pad formed so that at least a portion thereof is embedded in the insulating layer.
The method of claim 4,
And the connection pad is configured to surround a side edge of the cavity.
The method of claim 3,
And the thickness of the connection pad is equal to the depth of the cavity.
The method of claim 3,
And a via formed in the insulating layer and formed on an upper surface of the connection pad.
The method of claim 7,
Wherein the upper surface of the via has a larger diameter than a lower surface.
The method according to claim 1,
And the entire inner surface of the cavity is made of the same insulating material as the insulating layer.
The method of claim 3,
And a metal layer formed on a lower surface of the connection pad.
The method of claim 7,
And an inner layer circuit pattern formed on the insulating layer and joined to an upper surface of the via.
The method according to claim 1,
Wherein the cavity accommodates the first electronic component with a predetermined gap therebetween.
Forming a cavity pattern on the carrier substrate;
Forming an insulating layer formed on the carrier substrate so as to fill the cavity pattern;
Removing the carrier substrate; And
Removing the cavity pattern;
And a step of forming the printed circuit board.
14. The method of claim 13,
In the step of forming the cavity pattern,
Wherein a connection pad is further formed on the carrier substrate when the cavity pattern is formed.
15. The method of claim 14,
In the step of forming the insulating layer,
Wherein the insulating layer is formed to fill the cavity pattern and the connection pad.
15. The method of claim 14,
Wherein the carrier substrate comprises a metal layer on an upper portion or upper and lower portions of the carrier core.
15. The method of claim 14,
Wherein the step of removing the carrier substrate comprises:
Separating the carrier core and the metal layer to remove the carrier core;
Forming an etching resist which is formed on a lower portion of the metal layer and is formed at a position corresponding to the connection pad; And
Removing the exposed metal layer by the etching resist;
And a step of forming the printed circuit board.
14. The method of claim 13,
In the step of forming the cavity pattern,
Wherein the cavity pattern is formed by an electrolytic plating method.
16. The method of claim 15,
After the step of forming the insulating layer,
And forming a via formed on an upper surface of the connection pad so as to penetrate the insulating layer.
The method of claim 19,
The step of forming the vias, or thereafter,
And forming an inner layer circuit pattern formed on the insulating layer and joined to an upper surface of the via.
A lower package including a lower package substrate and a first electronic component disposed above the lower package substrate;
An upper package substrate comprising at least one insulating layer, wherein the insulating layer is formed with a cavity for accommodating at least a part of the first electronic component, and the inner surface of the cavity is made of an insulating material; And
An external connection terminal formed between the lower package substrate and the upper package substrate and electrically connecting the upper package substrate and the lower package substrate;
, ≪ / RTI &
And at least a portion of the first electronic component is received in the cavity.
23. The method of claim 21,
Wherein the inner surface of the cavity in the upper package substrate is made of the same insulating material as the insulating layer.
23. The method of claim 21,
Wherein the upper package substrate further comprises a metal layer formed under the upper package substrate and in contact with the external connection terminal.
23. The method of claim 21,
Wherein the upper package substrate further comprises an inner layer circuit pattern formed therein.
23. The method of claim 21,
And a second electronic component mounted on an upper portion of the upper package substrate.
26. The method of claim 25,
And the second electronic component is electrically connected to the upper package substrate by wire bonding.
27. The method of claim 26,
And a first molding material formed on the upper package substrate to cover the second electronic part.
23. The method of claim 21,
Wherein the cavity is recessed in the lower surface of the upper package substrate.
23. The method of claim 21,
Wherein the cavity accommodates the first electronic component in a state where the first electronic component is spaced apart from the first electronic component by a predetermined distance.
23. The method of claim 21,
And a second molding material is further formed between the inner surface of the cavity and the first electronic part.
KR1020140194133A 2014-05-23 2014-12-30 Printed circuit board, method for manufacturing the same and package on packaage having the thereof KR20150135048A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10163867B2 (en) 2015-11-12 2018-12-25 Amkor Technology, Inc. Semiconductor package and manufacturing method thereof
US10410999B2 (en) 2017-12-19 2019-09-10 Amkor Technology, Inc. Semiconductor device with integrated heat distribution and manufacturing method thereof
KR20200024713A (en) * 2018-08-28 2020-03-09 성균관대학교산학협력단 A method for flip-chip bonding using anisotropic adhesive polymer

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CN107731698B (en) * 2017-10-26 2024-03-26 日月光半导体(上海)有限公司 Integrated circuit package, package substrate and manufacturing method thereof
US10506712B1 (en) * 2018-07-31 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Printed circuit board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10163867B2 (en) 2015-11-12 2018-12-25 Amkor Technology, Inc. Semiconductor package and manufacturing method thereof
US10410999B2 (en) 2017-12-19 2019-09-10 Amkor Technology, Inc. Semiconductor device with integrated heat distribution and manufacturing method thereof
US10985146B2 (en) 2017-12-19 2021-04-20 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device with integrated heat distribution and manufacturing method thereof
US11901343B2 (en) 2017-12-19 2024-02-13 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device with integrated heat distribution and manufacturing method thereof
KR20200024713A (en) * 2018-08-28 2020-03-09 성균관대학교산학협력단 A method for flip-chip bonding using anisotropic adhesive polymer

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