KR101197783B1 - Embedded PCB and Manufacturing method of the same - Google Patents

Abstract

The present invention relates to a method for manufacturing a buried printed circuit board and a structure thereof, and in particular, a first step of forming a connection well of a partition structure capable of accommodating a metal paste on a first metal layer and the connection well. ) To provide a manufacturing process including a two-step of filling the metal paste and mounting the electronic device chip.
According to the present invention, it is possible to implement an SMT pad having a hollow well shape (Metla Well), and to mount a chip in a structure in which a solder is filled therein, so that the solder exposed to the upper portion of the connection well is Since the solder fillet is not formed by forming the interface with the electrode of the device chip, stress concentration due to the stiffness of the solder fillet can be prevented, and further, the insulating layer and the solder fillet Since the interface between the (Fillet) is not originally formed, there is an effect that can minimize the unnecessary stress.

Description

Embedded PCB and Manufacturing method of the same {Embedded PCB and Manufacturing method of the same}

The present invention is directed to a method for manufacturing an electronic device chip in a buried printed circuit board and a printed circuit board accordingly.

Printed circuit boards are solidifying their status as one of electronic components with the development of semiconductors and electronic devices, and all electric and electronic devices such as radios, televisions, PCS, and various other electrical and electronic products, as well as computers and high-tech electronic equipment. It is widely used as a component for implementing the circuit of. In recent years, as the technological progress in this field becomes remarkable, high quality is required in printed circuit boards, thereby rapidly increasing density. Particularly, in the manufacture of embedded PCB, a metal material such as Au is plated on the part where the component is to be surface-mounted, and for this purpose, masking treatment is performed using a dry film resist (hereinafter referred to as 'DFR'). This is achieved through a process.

The electronic device chip of the embedded PCB, particularly the passive device mounting technology, can be classified into three types. 1 illustrates examples of various structures of such a printed circuit board. The chip mounting method includes a circuit pattern 2 formed on the insulating layer 1 and an electronic device chip 4 embedded in the insulating layer, as shown in (a). The device chip may have a mounting structure in which via holes 5 are processed to be electrically connected through plating, or (b) an electronic device chip embedded in the insulating layer 1 may be mounted through an adhesive layer 6, and then an external circuit may be mounted. (2) and via holes (7), (c) and SMT Pad (Surface Mount Technology Pad) (6) is formed, and a chip mounting method using a solder and the like.

In general, however, due to differences in thermal expansion coefficients and material composition fractions of the materials constituting the substrate, the substrate undergoes local wrinkling around the chip and wide wrinkling on strip or panel scales as it passes through the heating process. (Global Warpage) will occur. In addition, the stress induced from such wrinkles may ultimately cause delamination or cracking at the interface between the materials.

In the case of the conventional chip mounting method using solder printing, the interface between the solder and the dissimilar material is different in the contact interface between the dissimilar materials as the solder material is added in addition to the existing substrate components, that is, the Cu, the insulating layer, and the outermost insulating layer. As a result, local warpage or global warpage occurs due to mismatch of thermal expansion coefficient, or delamination or crack occurs. It is getting bigger.

In particular, as shown in (c), a solder fillet 8 is formed as the periphery of the solder spreads when the chip is mounted on the printed solder on the pad 6. The solder fillet 8 is a factor of stress generation due to CTE mismatch between the insulating layers forming the interface. In addition, the solder fillet reacts stiffly to warpage caused by other factors due to the characteristics of the metal, which means that the function of stress absorption is very weak. It acts as a factor to make the chip mounting structure difficult.

The present invention has been made to solve the above-described problems, an object of the present invention is to implement a SMT Pad of the shape of the well (Metla Well) empty inside, and to mount the chip in a structure in which the solder is filled therein As the solder exposed to the upper part of the connection well forms the interface with the electrode of the electronic device chip, the solder fillet is not formed, so the stress concentration due to the stiffness of the solder fillet is reduced. The present invention provides a method of manufacturing a buried printed circuit board, which can prevent and further minimize the unnecessary stress since the interface between the insulating layer and the solder fillet is not formed at the source.

As a means for solving the above problems, the present invention comprises the steps of forming a connection well (well) of the barrier rib structure that can accommodate the metal paste on the first metal layer; Filling a metal paste in the connection well (well) and mounting an electronic device chip to provide a method of manufacturing a buried printed circuit board comprising a.

In addition, the connection wells of the first stage may be electroplated, screen printing, sputtering, and evaporation of the protrusion structure whose upper part is opened on the first metal layer and the side surface is sealed by the partition structure. It may be formed using any one of evaporation, inkjetting, dispensing, or a combination thereof.

In addition, the connection wells of the first step may be formed using any one of Cu, Ni, Pd, Au, Sn, Ag, Co, or a binary or raw alloy thereof.

In particular, the metal paste of the second step may be a paste formed of Cu, Ag, Au, Sn, Pb as the main component or an alloy thereof.

The above-described manufacturing process may further include three steps of forming an outer circuit pattern layer including an insulating layer and a second metal layer filling the periphery of the electronic device chip after the second step.

In addition, in the third step, at least one or more first insulating stacked groups having a structure surrounding the periphery of the electronic device chip and the second insulating stacked group and the outer circuit layer covering the upper portion of the insulating stacked group are arranged, The third insulating layer group including the internal circuit pattern may be arranged and stacked between the first insulating layer group and the second insulating layer group.

In particular, in this case, the three steps may include: a1) separating the carrier from the first metal layer; a2) forming a through hole electrically connecting the internal circuit pattern to the first and second metal layers; a3) filling the through hole with a metal material, and patterning the first and second metal layers to implement an outer layer circuit. In addition, after the step a3), the step of laminating an insulating layer and a metal layer on the upper surface of the outer layer circuit, and processing the metal layer to process a circuit pattern electrically connected to the outer layer circuit or the inner layer circuit at least once. The process may be implemented to be repeated. In addition, the buried printed circuit board may further include a process of coating and patterning a solder resist on the upper surface of the circuit pattern exposed to the outside or a process of performing a surface treatment on the exposed circuit pattern.

Unlike the above-described process, after the step 2, the step of forming an outer circuit pattern layer including an insulating layer and a second metal layer to embed the electronic device chip; Step 3, b1) separating the carrier from the first metal layer; b2) forming a through hole for electrically connecting the first and second metal layers; b3) plating the conductive hole and patterning the first and second metal layers to implement an outer layer circuit.

The buried printed circuit board according to the present invention manufactured by the above-described manufacturing process may be formed in the following structure.

Specifically, the buried printed circuit board according to the present invention includes a connection well having a partition structure for accommodating a metal paste formed on the upper surface of the outer circuit pattern, and an electronic device chip mounted on the connection well. ; It may be formed into a structure comprising a.

Further, the connection wells are formed in a protrusion structure in which an upper part is opened on an outer layer circuit pattern and a side surface is sealed by a barrier rib structure. A metal paste may be filled in the connection wells beyond the protrusion height of the connection wells. have. In this case, the connection wells may be formed using any one of Cu, Ni, Pd, Au, Sn, Ag, Co, or a binary or raw alloy thereof, and the metal paste may be formed of Cu, Ag, Au, Sn or Pb may be formed as a main component or an alloy thereof.

Particularly, in the printed circuit board according to the present invention, a third insulating laminated group having an internal circuit pattern is further formed in the insulating layer in which the electronic device chip is embedded, and electrically connecting the inner circuit pattern and the outer circuit pattern. The conductive hole may further include a structure, and further, on the upper portion of the outer circuit pattern, a circuit pattern electrically connected to the outer circuit pattern and a second outer circuit pattern including an insulating layer are stacked at least one. It can also be implemented.

The circuit pattern exposed to the outside in the buried printed circuit board according to the present invention, the solder resist layer covering a part of the exposed circuit pattern, Cu, Ni, Pd, Au, which is formed on the surface of the exposed circuit pattern, The plated layer may be provided in a single layer or multiple layers using any one of Sn, Ag, and Co, or a binary or raw alloy thereof.

In addition, the buried printed circuit board according to the present invention can be implemented in a structure without an internal circuit pattern inside the insulating layer, which is an insulating layer for embedding the electronic device chip; and an outer layer formed on the surface of the insulating layer It may be implemented in a structure having at least one conductive hole for electrically connecting the circuit patterns.

According to the present invention, it is possible to implement an SMT pad having a hollow well shape (Metla Well), and to mount a chip in a structure in which a solder is filled therein, so that the solder exposed to the upper portion of the connection well is Since the solder fillet is not formed by forming the interface with the electrode of the device chip, stress concentration due to the stiffness of the solder fillet can be prevented, and further, the insulating layer and the solder fillet Since the interface between the (Fillet) is not originally formed, there is an effect that can minimize the unnecessary stress.

In particular, the stress generated at the interface between the side wall of the connection well and the filled solder is weak enough not to affect the reliability, but it can also be absorbed by the metal material such as Cu, which is high in ductility surrounding the solder. It is more efficient, and the solder is inserted into the SMT Pad of the existing design without the surface treatment layer such as Ni / Au plating on the SMT Pad, so that the thickness of the lower part of the chip can be increased and the thickness can be realized. Filling by resin at the bottom is much easier (Filling) also has the effect of increasing the reliability.

1 illustrates a mounting structure of an electronic device chip according to the related art.
Figure 2a shows a flow chart of the manufacturing process of the buried printed circuit board according to the present invention.
2b to 2d show a manufacturing process of the buried printed circuit board according to the present invention.
3A and 3B show another application example of a buried printed circuit board according to the present invention.
4 is a conceptual diagram illustrating a structure of a connection well structure and an electronic device chip according to the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation according to the present invention. In the description with reference to the accompanying drawings, the same components are given the same reference numerals regardless of the reference numerals, and duplicate description thereof will be omitted. The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The present invention is to form a connection well of a barrier rib structure in which an electronic device chip can be mounted on a circuit pattern, and to fill the inside with metal paste such as solder paste so that the chip can be mounted. .

Figure 2a is a flow chart of the manufacturing process according to the invention, Figures 2b and 2c is a manufacturing process diagram.

In the manufacturing of the buried printed circuit board according to the present invention, a first step of forming a connection well of a partition structure capable of accommodating a metal paste on a first metal layer and filling the metal paste in the connection well is performed. It comprises two steps of mounting the device chip. In other words, a manufacturing process method of forming a structure having a hollow structure on the first metal layer and filling the inside with a metal paste to mount the electronic device chip will be included in the gist of the present invention.

The above-described process will be described in detail with reference to the flowcharts and process diagrams provided.

1. Formation process of connection well

The first step according to the present invention is a process of forming a structure of a partition structure having an empty inside on the first metal layer 110, in particular, the first metal layer 110 on the carrier 120 in accordance with the process shown in Figure 2b ) To perform the process by attaching the) will be described as an embodiment. Of course, the progress of the process can be carried out with only the first metal layer 110, but in general, in order to use a thin copper foil of 3 ~ 20㎛ in the process progress, it is easy to proceed by attaching on the carrier of the illustrated structure Therefore, the process using the carrier structure will be described below. The carrier structure may be applied to various structures, which will be removed during a later process. In the present embodiment, the structure of the copper composites 122, 123, and 124 adhered to the first metal layer 110 through the adhesive material 121 is used. This will be described as an example.

In the step S1, as shown, a structure in which the first metal layer 110 and the carrier 120 are stacked is prepared, and thereafter, a dry film resist D is coated and patterned on the top surface of the first metal layer 110. .

As in step S 2, the dry film resist D is patterned to have a developing region D1 and an undeveloped region D2 in order to form a connection well according to the present invention. Silver is subjected to a process such as exposure, development, peeling, etching, and then plating is performed. Plating is a structure protruding to the upper portion of the first metal layer 110 and the inside is preferably performed to form a connection well 130 of the empty structure. The connection well is not limited to the illustrated structure, and any structure may be any structure in which the outside is surrounded by a partition structure. That is, the side surface is a projecting structure that is closed by the partition structure. In particular, the cross-sectional shape of the inside may be formed in various structures such as a rectangle, a circle, a polygon as shown. In addition, the connection well may be formed using any one of Cu, Ni, Pd, Au, Sn, Ag, Co, or a binary or raw alloy thereof, and the forming method may have an upper portion opened on the first metal layer. The side surface is formed using any one or a combination of electroplating, screen printing, sputtering, evaporation, ink jetting, and dispensing the protrusion structure sealed by the partition structure. can do. In this embodiment, forming a connection well of Cu material by using the plating method will be described as an example.

Subsequently, the metal paste 140 is filled in the connection well 130 as in step S 3. The metal paste 140 may use a paste formed of Cu, Ag, Au, Sn, or Pb as a main component or an alloy thereof. In the preferred application example of the present invention, a solder paste is filled. Let's explain. As shown in the drawing, the inner space of the connection well 130 is filled by printing a solder paste using a metal mask (M). That is, the inside of the connection well is filled with solder paste 140, and the shape in which Cu 130 is wrapped around the solder is realized. In this case, the solder paste 140 is preferably filled to the same height or more than the interface of the upper surface of the connection well 130.

2. Mounting stage of electronic device chip

Thereafter, the electronic device chip 150 is mounted on the interface of the solder paste 140 of the connection well 130, and the upper surface of the solder paste 140 is connected to the electrode of the electronic device chip through reflow. (S step 4).

In the electronic device chip mounting method, the solder paste 140 is surrounded by Cu, which is a first metal layer, and the upper part forms an interface with an electrode of the electronic device chip. Therefore, since a solder fillet which is a problem of the conventional mounting method is not formed, concentration of stress due to stiffness of the solder fillet can be prevented. In addition, since the interface between the insulating layer and the solder fillet is not originally formed as in the conventional mounting structure, the stress can be minimized.

Furthermore, unlike the conventional mounting structure, the mounting method using the connection wells according to the present invention has a weak level at which the stress generated at the solder paste-Cu interface does not affect the reliability, but also has a high ductility around the solder. Can be absorbed by. In addition, since the solder is inserted into the SMT pad of the existing design without the surface treatment layer such as Ni / Au plating on the SMT Pad, which is essential in the conventional mounting method, the thickness of the lower part of the chip can be increased without increasing the height. . In addition, the filling of resin (Resin) at the lower end of the electronic device chip is much easier (filling) can be implemented to increase the reliability.

3. Complete process of embedded printed circuit board

After the process of mounting the electronic device chip in the connection well of the second step described above, the process of embedding the electronic device chip in the insulating layer, forming an external circuit pattern to complete the printed circuit board. The above process may be variously modified, and in general, the process may vary according to the order of the process and the number of layers of the circuit layer. Let's do it.

(1) Structure having inner circuit pattern

3A and 3B illustrate the process after step S4 described above.

After the step S 4 described above, at least one first insulating stacked group 160 having a structure surrounding the periphery of the electronic device chip 150 and the second insulating stacked group 180 covering an upper portion of the insulating stacked group. And an outer circuit layer 190, and in particular, the third insulation stack group 170 including an internal circuit pattern 171 between the first insulation stack group 160 and the second insulation stack group 180. It can be formed by arranging and laminating (P 1 step).

In this case, the first insulation layer group 160 and the second insulation layer group 180 may be implemented by laminating in a semi-cured state (B-stage). In addition, it is also possible to form a single layer, each formed of a plurality of layers can be formed in the above-described structure, epoxy, phenol resin, prepreg, polyimide film, ABF film is applied to form the same material May be In addition, the third insulation layer group 170 may be formed in a structure including a circuit pattern 171 formed on both surfaces of the insulation layer 173 and a conductive via 172 electrically connecting the circuit patterns on both sides. have.

After that, remove the carrier board 120 (P 2 step). The process after removing the carrier board 120 may apply a general manufacturing process of a printed circuit board. That is, the conductive hole H1 electrically connected to the inner circuit pattern 170 is processed and a metal material is filled therein, and the first metal layer 110 and the outer circuit layer 190 are patterned to form the outer circuit 191. Pattern (P steps 3-4).

Thereafter, a process of forming a surface treatment layer by applying a solder resist on the outer circuit 191 to treat the surface of the outer circuit may be further added. The surface treatment layer may be formed by plating a single layer or multiple layers using any one of Cu, Ni, Pd, Au, Sn, Ag, Co, or a binary or raw alloy thereof on the exposed surface of the outer circuit. . This process allows the minimum circuit layer to implement four layers.

(2) Multi layer implementation with internal circuit pattern

Referring to FIG. 3B, a process example of manufacturing a printed circuit board having a multilayer structure through a process of adding a plurality of circuit layers after step P 4 is illustrated.

After the process of step P4, a separate insulating layer 210 is laminated on the upper surfaces of the outer layer circuits 111 and 191, the via holes H2 are processed, and the metal material 220 is filled thereafter. A process of forming the circuit pattern 230 may be performed. Thereafter, a process of coating and patterning the solder resist 240 and surface treating the exposed circuit pattern 230 may be performed (Q 1 to Q 4).

Of course, the above-mentioned insulating layer 210 and the metal layer 230 are laminated at the same time, and then processing the metal layer to process the circuit pattern electrically connected to the outer layer circuits 111 and 191 or the inner layer circuit at least. By performing the process repeated one or more times, the basic four-layer structure can be implemented with at least six layers. In this case, after laminating the insulating layer and the metal layer on the upper surface of the outer layer circuit 191, the implementation of the circuit pattern through the processing of the through hole and filling of the metal material, patterning the metal layer, the application of solder resist, the formation of the surface treatment layer, etc. The same technique can be applied to one technique.

(3) Structure without internal circuit pattern-circuit pattern structure of at least 2 layers

In the present embodiment, the buried printed circuit board may be formed in a structure without the internal hero pattern 170 in the structure of step P4 of FIG. 3A. That is, in stacking the insulating layer for embedding the electronic device chip directly in the structure of step S4, at least the structure surrounding the peripheral portion of the electronic device chip (C) without forming an insulation stack group having an internal circuit pattern The at least one first insulating stack group and the second insulating stack group covering the upper portion of the first insulating stack group are arranged, and an outer circuit layer is stacked on the upper portion to be heated and pressurized to form an outer circuit pattern layer. In this case, the first insulation laminate group and the second insulation laminate group may be implemented by laminating in a semi-cured state (B-stage). In addition, the first insulating laminated group may be formed as a single layer, but may be formed in the above-described structure by pressing and then forming a plurality of layers, respectively, as shown, the material is epoxy, phenol resin, prepreg , Polyimide film, ABF film and the like may be applied to form the same material.

The structure of the buried printed circuit board having the various structures described above may have different structures depending on the number of circuit layers, but basically includes the structure of FIG. 4.

That is, the buried printed circuit board according to the present invention includes a connection well 130 having a partition structure for accommodating the metal paste 140 formed on the upper surface of the outer circuit pattern 110, and the upper portion of the connection well. The electronic device chip 150 has a structure in which it is mounted. Here, the outer circuit pattern 110 is illustrated as one layer, but the final circuit is formed as a circuit pattern as described in the manufacturing process.

In particular, the connection well 130 is formed on the outer circuit pattern, the upper portion of the connection well is formed in a protruding structure that is sealed in a partition structure, the metal paste inside the connection well of the protrusion height of the connection well It can be filled above. In addition, the connection well 130 may be formed using any one of Cu, Ni, Pd, Au, Sn, Ag, Co, or a binary or original alloy thereof, and is filled in the connection well 130. The metal paste may be formed of Cu, Ag, Au, Sn, or Pb as a main component or an alloy thereof. Although the structure shown in FIG. 4 is one application example, the thickness X1 of the side wall of each connection well is 50 μm, and the diameter X2 of the portion to be filled with solder is 300 μm, between each connection well. The spacing Y1 has been shown to be able to be implemented at 200 μm. Overall, the whole diameter of the connection well is shown as an example of implementing the 300 ~ 400㎛.

With this basic structure, as shown in the step P4 of FIG. 3A, a third insulating stack group having an internal circuit pattern is further formed in the insulating layer embedding the electronic device chip, wherein the inner circuit pattern and the outer layer are formed. The buried printed circuit board may be formed to further include a through hole for electrically connecting the circuit pattern. Of course, in this case, a structure having at least one conductive hole for electrically connecting the insulating layer embedding the electronic device chip and the outer circuit pattern formed on the surface of the insulating layer may be formed without the inner circuit pattern. May be as described above.

In addition, as shown in Q 3 of FIG. 3B, a structure in which at least one second outer circuit pattern including an insulating layer and a circuit pattern electrically connected to the outer circuit pattern is stacked on the outer circuit pattern. It may be formed as.

In this structure, the outer circuit exposed to the outermost shell may have a solder resist pattern or a surface treatment layer as described above. In this case, the surface treatment layer may be formed by plating or the like as a single layer or multiple layers using any one of Cu, Ni, Pd, Au, Sn, Ag, Co, or a binary or raw alloy thereof.

In the foregoing detailed description of the present invention, specific examples have been described. However, various modifications are possible within the scope of the present invention. The technical idea of the present invention should not be limited to the embodiments of the present invention but should be determined by the equivalents of the claims and the claims.

110: first metal layer
111, 191: outer circuit
120: carrier
130: connection well
140: metal paste
150: electronic device chip
160: first insulating laminated group
170: internal circuit pattern
180: second insulation laminated group
190: second metal layer
210: insulating layer
220: metal material
230: circuit pattern
240: solder resist

Claims (19)

Forming a well of a partition structure capable of accommodating a metal paste on the first metal layer;
Filling the connection well with a metal paste to an upper surface of the connection well and mounting the electronic device chip such that a terminal of the electronic device chip is joined to the metal paste in the connection well;
Method of manufacturing a buried printed circuit board comprising a.
The method according to claim 1,
The well of the first stage,
The upper part is opened on the first metal layer, and the side surface is any one of electroplating, screen printing, sputtering, evaporation, ink jetting, and dispensing the protrusion structure sealed by the partition structure. Or a method of manufacturing a buried printed circuit board formed by using a combination thereof.
The method according to claim 2,
The well of the first stage,
A method of manufacturing a buried printed circuit board formed using any one of Cu, Ni, Pd, Au, Sn, Ag, and Co, or a binary or raw alloy thereof.
The method according to claim 1,
The metal paste of the second step is a method of manufacturing a buried printed circuit board containing Cu, Ag, Au, Sn, Pb or any one of these alloys.
5. The method according to any one of claims 1 to 4,
After step 2,
Forming an outer circuit pattern layer including an insulating layer filling the periphery of the electronic device chip and a second metal layer;
Method of manufacturing a buried printed circuit board further comprising.
The method according to claim 5,
The third step,
Arrange at least one or more first insulating stacked groups having a structure surrounding the periphery of the electronic device chip, and a second insulating stacked group and an outer circuit layer covering the upper portion of the insulating stacked group.
And arranging and stacking a third insulating layer group including an internal circuit pattern between the first insulating laminated group and the second insulating laminated group.
The method of claim 6,
The third step,
a1) separating the carrier from the first metal layer;
a2) forming a through hole electrically connecting the internal circuit pattern to the first and second metal layers;
a3) filling the through hole with a metal material and patterning the first and second metal layers to implement an outer layer circuit;
Method of manufacturing a buried printed circuit board further comprising.
The method of claim 7,
After step a3),
Insulating an insulating layer and a metal layer on the upper surface of the outer layer circuit,
And processing the metal layer to process the circuit pattern electrically connected to the outer layer circuit or the inner circuit pattern at least one or more times.
The method according to claim 8,
The method of manufacturing a buried printed circuit board further comprising the step of applying a pattern of the solder resist to the upper surface of the circuit pattern exposed to the outside from the buried printed circuit board or performing a surface treatment on the exposed circuit pattern.
The method according to claim 5,
After step 2,
Forming an outer circuit pattern layer including an insulating layer filling the electronic device chip and a second metal layer;
Method of manufacturing a buried printed circuit board further comprising.
The method of claim 10,
The third step,
b1) separating the carrier from the first metal layer;
b2) forming a through hole for electrically connecting the first and second metal layers;
b3) plating the conductive hole and patterning the first and second metal layers to implement an outer layer circuit;
Method of manufacturing a buried printed circuit board further comprising.
Electronic device chip;
An outer circuit pattern on which the electronic device chip is mounted;
And a connection well formed on an upper surface of the outer circuit pattern corresponding to the terminals of the electronic device chip and filled with metal paste to an upper surface thereof.
Embedded printed circuit board comprising a.
The method of claim 12,
The connection wells are formed in a protruding structure in which an upper part is opened on an outer layer circuit pattern and a side surface thereof is sealed by a partition structure.
A buried type printed circuit board in which the metal paste is filled in the connection wells beyond the protrusion height of the connection wells.
The method of claim 12,
The connection well (well) is a buried printed circuit board formed using any one of Cu, Ni, Pd, Au, Sn, Ag, Co or their binary, raw alloy.
The method according to claim 14,
The metal paste may include any one of Cu, Ag, Au, Sn, Pb, or an alloy thereof.
The method of claim 12,
A third insulating stacked group having an internal circuit pattern is further formed in the insulating layer to embed the electronic device chip.
A buried printed circuit board further comprising a through hole for electrically connecting the inner circuit pattern and the outer layer circuit pattern.
18. The method of claim 16,
On top of the outer circuit pattern,
And at least one second printed circuit board comprising a circuit pattern electrically connected to the outer circuit pattern and an insulating layer.
The method according to claim 16 or 17,
In the circuit pattern exposed to the outside from the buried printed circuit board,
A solder resist layer covering a portion of the exposed circuit pattern;
A buried printed circuit board having a plating layer formed as a single layer or multiple layers using any one of Cu, Ni, Pd, Au, Sn, Ag, and Co, or a binary or raw alloy thereof formed on the surface of an exposed circuit pattern.
The method of claim 12,
The buried printed circuit board,
An insulation layer filling the electronic device chip;
A buried printed circuit board having at least one conductive hole for electrically connecting the outer circuit patterns formed on the surface of the insulating layer.

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