KR20180070276A - Printed circuit board, package and manufacturing method of printed circuit board - Google Patents

Abstract

The present invention discloses a printed circuit board capable of rapidly transmitting a signal between a semiconductor chip and a main board. According to an embodiment of the present invention, the printed circuit board comprises: a first insulating part; a second insulating part formed on the first insulating part; a receiving groove formed by passing through the second insulating part; a protective layer formed between the first insulating part and the second insulating part and between the first insulating part and the receiving groove; and a connection conductor pattern layer including a connection pattern exposed in the receiving groove, and embedded in the protective layer.

Description

TECHNICAL FIELD [0001] The present invention relates to a printed circuit board, a package, and a method of manufacturing a printed circuit board.

The present invention relates to a printed circuit board, a package, and a method of manufacturing a printed circuit board.

There is a demand for a package technology capable of quickly transmitting a signal as the semiconductor chip becomes more sophisticated. Further, there is a demand for a technique of reducing the thickness of the package in accordance with the shortening of the thickness of the electronic equipment.

Chip manufacturers are developing FO-WLP packages in which a wiring layer is formed directly on the chip to speed up and stabilize signals. Package substrate manufacturers are attempting to develop substrates with thicknesses below 100 um to reduce package thickness.

Korean Patent Publication No. 10-2013-0055335 (published on May 28, 2013)

According to the embodiment of the present invention, a printed circuit board capable of thinning the thickness of the package can be provided.

Further, according to the embodiment of the present invention, a printed circuit board capable of rapidly transmitting signals between the semiconductor chip and the main substrate can be provided.

1 shows a printed circuit board and a package according to an embodiment of the present invention.
2 shows a printed circuit board and a package according to another embodiment of the present invention.
FIGS. 3 to 9 sequentially illustrate a manufacturing process for explaining a method of manufacturing a printed circuit board according to an embodiment of the present invention. FIG.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof. In the specification, "on" means to be located above or below the object portion, and does not necessarily mean that the object is located on the upper side with respect to the gravitational direction.

In addition, the term " coupled " is used not only in the case of direct physical contact between the respective constituent elements in the contact relation between the constituent elements, but also means that other constituent elements are interposed between the constituent elements, Use them as a concept to cover each contact.

The sizes and thicknesses of the respective components shown in the drawings are arbitrarily shown for convenience of explanation, and thus the present invention is not necessarily limited to those shown in the drawings.

Hereinafter, embodiments of a printed circuit board, a package, and a method of manufacturing a printed circuit board according to the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals refer to like And a detailed description thereof will be omitted.

Printed Circuit Boards and Packages

1 is a view illustrating a printed circuit board and a package according to an embodiment of the present invention. 2 is a view illustrating a printed circuit board and a package according to another embodiment of the present invention.

Referring to FIG. 1, a printed circuit board 500 according to an embodiment of the present invention includes a first insulating part 100, a second insulating part 200, a receiving groove CV, a protective layer 300, And a conductor pattern layer 400.

Each of the first insulation part 100 and the second insulation part 200 includes at least one insulation layer 110, 210. The insulating layer forming the first insulating layer 100 is referred to as a first insulating layer 110 and the insulating layer forming the second insulating layer 200 is referred to as a second insulating layer 210. The first insulating layer 110 ) And the second insulating layer 210 are generally referred to as an insulating layer unless otherwise noted.

The insulating layers 110 and 210 may be formed of a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin impregnated with a reinforcing material such as a glass fiber or an inorganic filler, for example, a prepreg. As another example, the insulating layers 110 and 210 may be formed of build-up films such as ABF. As another example, the insulating layers 110 and 210 may be formed of a photocurable resin. In another and another example of the insulating layers 110 and 210, the insulating layers 110 and 210 may include an inorganic filler.

The inorganic filler may be at least one or more selected from the group consisting of alumina, silica, glass and silicon carbide, and mixtures thereof. The inorganic filler may be formed into various shapes such as spherical, hemispherical, polygonal, cylindrical or plate-like shapes. The diameter of the inorganic filler can be varied from several nanometers to several hundred nanometers in size. When the inorganic filler is not spherical, the diameter of the inorganic filler refers to the longest length of each of a plurality of line segments connecting two different points on the surface of the inorganic filler and passing through the center of gravity of the inorganic filler.

The conductor pattern layers 120 and 220 are formed on the insulating portions 100 and 200, respectively. That is, the first conductor pattern layer 120 is formed on the first insulation portion 100, and the second conductor pattern layer 220 is formed on the second insulation portion 200. Each of the first conductor pattern layer 120 and the second conductor pattern layer 220 may be formed in plurality.

The conductor pattern layers 120 and 220 are embedded in the first and second insulating portions 100 and 200 and are not exposed to the outside. However, at least a part of the conductor pattern layers 120 and 220 formed on the outermost layer are protruded from the insulating portions 100 and 200.

The conductor pattern layers 120 and 220 are formed of an electrically conductive material. For example, the conductor pattern layers 120 and 220 may be formed of copper (Cu), but the conductor pattern layers 120 and 220 may be formed of various electrically conductive materials such as nickel (Ni) and aluminum (Al).

In FIG. 1, each of the first and second insulating portions 100 and 100 is formed of two insulating layers 110 and 210, but this is merely an example. That is, each of the first insulation part 100 and the second insulation part 200 may be formed of three or more insulation layers or one insulation layer.

Also, the numbers of the first conductor pattern layer 120 and the second conductor pattern layer 220 shown in FIG. 1 are only illustrative. As another example, the first conductor pattern layer 120 may be formed in the first insulation portion 100 in a four-layer structure. As another example, the second conductor pattern layer 220 may be formed in a three-layer structure in the second insulation portion 200.

The receiving groove CV is formed through the second insulating portion 200. The receiving groove CV is provided with an electronic component 600 to be described later. The width and depth of the receiving groove CV may correspond to the width and height of the electronic component 600, but are not limited thereto. By way of example, the receiving groove CV is formed to have a width larger than the width of the electronic component 600, so that the electronic component 600 can be more easily disposed in the package 1000 according to the present embodiment.

The receiving groove (CV) can be formed by laser drilling, CNC drilling, punching or chemical etching. Alternatively, when the second insulating layer 210 includes a photocurable resin, the receiving groove CV may be formed through a photolithography process.

The passivation layer 300 is formed between the first insulating portion 100 and the second insulating portion 100 and between the first insulating portion 100 and the receiving groove CV. That is, the protective layer 300 is formed on one surface of the first insulating portion 100 and is formed between the first insulating portion 100 and the second insulating portion 200. Therefore, at least a part of the protective layer 300 is exposed to the outside by the receiving groove CV.

The protective layer 300 is formed of a thermosetting solder resist. The protective layer 300 applied to this embodiment is not a conventional photocurable solder resist but a thermosetting solder resist.

As described later, since the protective layer 300 is formed before the first insulating portion 100, the protective layer 300 is formed of a thermosetting solder resist. When the protective layer 300 to be applied to this embodiment is formed of a photocurable solder resist, gas may be generated due to heat and pressure applied to the protective layer 300 while the substrate is being processed, thereby increasing the possibility of substrate failure .

The thermosetting solder resist may include epoxy and cyanate series resins. The thermosetting solder resist may include inorganic fillers such as alumina, silica, glass and silicon carbide.

The connection conductor pattern layer 400 includes the connection pattern 410 exposed in the receiving groove CV and is formed to be embedded in the protection layer 300. The connection conductor pattern layer 400 is formed on the protection layer 300 in a buried shape from one side of the protection layer 300.

The connection pattern 410 is electrically connected to an electronic component to be described later. The connection pattern 410 is also embedded in the protection layer 300. One surface of the connection pattern 410 is located on the same plane as one surface of the protection layer 300 or is exposed from one surface of the protection layer 300 to the receiving groove CV.

1, the connection pattern 410 is illustrated as penetrating the protective layer 300, but this is merely an example. That is, the connection pattern 410 may be formed in a pad shape that does not penetrate the passivation layer 300 according to design needs. The number of the connection patterns 410 and the pitch between the connection patterns 410 can be variously changed according to the number of external connection terminals of the electronic component 600 and the pitch between the external connection terminals to be described later.

The connection conductor pattern layer 400 may further include a connection via 420 connecting the first conductor pattern layer 120 and the second conductor pattern layer 220 to each other through the protection layer 300. The connection via penetrates the protection layer 300 to electrically connect the first conductor pattern layer 120 and the second conductor pattern layer 220.

The connecting conductor pattern layer 400 may further include a stop pattern 430 formed over a boundary between the second insulating portion 200 and the receiving groove CV.

The stop pattern 430 is included in the connection conductor pattern layer 400 and the connection conductor pattern layer 400 is buried in the protection layer 300 as described above. The protection layer 300 can be divided into a first region where the second insulation portion 200 is formed and not exposed to the outside and a second region that is exposed to the outside due to the receiving groove CV. The reason why the stop pattern 430 is formed over the boundary between the second insulating portion 200 and the receiving groove CV is that the stop pattern 430 is formed in the first region and the second region of the passivation layer 300 It should be understood that it is formed over.

In the manufacturing process of the printed circuit board according to the present embodiment, when the resin forming the second insulating layer 210 flows into the receiving groove CV, the stopped pattern 430 is removed by laser The first insulating portion 100 and the protective layer 300 can be prevented from being removed by the laser. That is, the stop pattern 430 can function as a stopper for the laser.

The connection conductor pattern layer 400, the connection pattern 410, the connection pattern 420, and the stop pattern 430 are formed of an electrically conductive material. For example, the connection pattern 410 may be formed of copper (Cu), but may be formed of various electrically conductive materials such as nickel (Ni) and aluminum (Al).

A package 1000 according to an embodiment of the present invention includes a printed circuit board 500 according to an embodiment of the present invention and an electronic component 600 disposed in a receiving groove CV and connected to a connection pattern 410. [ .

The electronic component 600 may be a semiconductor chip. The semiconductor chip may have an active surface on one side and an inactive surface on the other side. An external connection terminal may be formed on one surface of the semiconductor chip so as to be electrically connected to the printed circuit board 500 according to the present embodiment.

The number of external connection terminals of the electronic component 600 shown in Fig. 1 and the like is merely an example.

The printed circuit board 500 and the package 1000 according to an embodiment of the present invention may further include a solder resist layer SR formed on the lower surface of the first insulation portion 100 and the upper surface of the second insulation portion 200 . The solder resist layer SR may be formed with openings for exposing at least a part of the conductor pattern layers 120 and 220 formed on the outermost layers of the first and second insulating parts 100 and 200 to the outside.

The solder resist layer SR may include a photocurable or thermosetting resin. When the solder resist layer SR includes a photocurable resin, the opening may be formed through a photolithography process. When the solder resist layer SR includes a thermosetting resin, the opening may be formed through a laser drill or a sandblast.

The printed circuit board 500 and the package 1000 according to an embodiment of the present invention are formed on the first insulating part 100 and the second insulating part 200 to form the first conductive pattern layers 120 And connecting the second conductive pattern layers 220 to each other.

The vias are formed of an electrically conductive material. For example, the vias may be formed of copper (Cu), but not limited thereto, and may be formed of various electrically conductive materials such as nickel (Ni) and aluminum (Al).

Although not shown, the package 1000 according to an embodiment of the present invention includes a molding material formed between the side surface of the electronic component 600 and the inner surface of the receiving groove CV to protect the electronic component 600 .

Printed circuit board and manufacturing method of package

FIGS. 3 to 9 are views sequentially illustrating manufacturing processes for explaining a method of manufacturing a printed circuit board according to an embodiment of the present invention.

A method of manufacturing a printed circuit board according to an embodiment of the present invention includes the steps of: forming a first insulating portion having a protective layer on one surface thereof on a carrier; separating the carrier and the first insulating portion; And forming the formed second insulating portion. The step of forming the first insulating portion on the carrier includes a step of forming a protective layer on the carrier and a step of forming a through hole in the protective layer.

First, the carrier C is prepared as shown in Fig.

The carrier C includes a support S, a first copper foil CF1 formed on both sides of the support S, a second copper foil CF2 formed on the first copper foil CF1, And a third copper foil CF3 formed on the etching stopper layer ES and the etching stopper layer ES.

The supporting portion S is not limited to any material if it is strong enough to support the protective layer 300 and the first insulating portion 100 between the process of forming the protective layer 300 and the first insulating portion 100. [ The support portion S may be a resin material such as a PET film, but is not limited thereto and may be a metal material.

The first copper foil CF1 supports the protective layer 300 and the first insulating portion 100 between the process of forming the protective layer 300 and the first insulating portion 100 together with the supporting portion S. The first copper foil CF1 may be formed of copper or an alloy including copper. The first copper foil CF1 may be formed to a thickness of, for example, 18 mu m.

The second copper foil CF2 is separated from the first copper foil CF1 in the process of separating the carrier C and the first insulating portion 100, which will be described later. The carrier C may further include a release layer RL formed between the first copper foil CF1 and the second copper foil CF1 to facilitate separation between the second copper foil CF2 and the first copper foil CF1 have. The second copper foil CF2 may be formed to a thickness of, for example, 5 mu m.

The etch stop layer ES is formed by removing the first insulating portion 100 from the carrier C and removing the second copper foil CF2 attached to the first insulating portion 100 by etching. (400) from being etched. The anti-etching layer ES may be formed of a material which does not chemically react with the etching solution for etching the second copper foil CF2. Illustratively, the etch stop layer ES may be formed of nickel (Ni).

The third copper foil CF3 can function as a seed layer in forming the connecting conductor pattern layer 400 by electrolytic plating. The third copper foil CF3 may be formed to a thickness of 0.3 占 퐉 as an example. Even when the pitch between the external connection terminals of the electronic component 600 is small because the contact pattern 410 can be finely formed when the third copper foil CF3 is thin, And can be electrically connected.

On the other hand, the structure of the carrier C described above is merely an example, and the scope of the present invention is not limited to the structure of the carrier C described above. The structure of the carrier C can be variously changed according to design needs.

Next, as shown in FIG. 4, a connecting conductor pattern layer 400, a protective layer 300 and a first conductor pattern layer 120 are formed on the carrier C. Next, as shown in FIG. The formation order of the connection conductor pattern layer 400 and the protection layer 300 may be changed according to design needs. In addition, a part of the connection conductor pattern layer 400 may be formed first, and another portion of the connection conductor pattern layer 400 may be formed after the protection layer 300 is formed.

1, a protective layer 300 is first formed of a thermosetting solder resist on a carrier C, and then a contact pattern 410 is formed on the carrier C, A connection via pattern 420, and a stop pattern 430. The connection conductive pattern layer 400 may be formed of a metal, The protective layer 300 may be formed by laminating a film-form thermosetting solder resist. The connection conductor pattern layer 400 is formed by electrolytically plating a part of the protective layer 300 with sandblast to expose the carrier C to the outside and the third copper foil CF3 of the carrier C as a seed layer . The first conductor pattern layer 120 may be formed through electrolytic plating after forming a patterned plating resist on the protective layer 300. The connection conductor pattern layer 400 and the first conductor pattern layer 120 may be formed through the same plating process or a separate plating process.

In this embodiment, to form the connecting conductor pattern layer 400, a part of the protective layer 300 is removed with a sandblast having a relatively high straightness as compared with laser drilling. Therefore, the connection conductor pattern layer 400 formed according to the present embodiment is formed to have a more steep side surface as compared with a laser via or the like.

2, a contact pattern 410 is first formed on the carrier C, a contact pattern 410 is formed on the carrier C, After the protective layer 300 is formed on the carrier C, the connection vias 420 and the stop patterns 430 can be formed. In this case, the first conductor pattern layer 120 may be formed through the same plating process or separate plating process as the connection via 420 and the stop pattern 430, as described above.

Next, as shown in FIG. 5, a first insulating layer 110 and another first conductor pattern layer 120 are formed on the first conductor pattern layer 120 and the protective layer 300. The process of forming the first insulating layer 110 and the process of forming the first conductor pattern layer 120 may be repeated several times according to design requirements.

The first insulating layer 110 may be formed by laminating a film-form prepreg or an ABF film. The first conductor pattern layer 120 may be formed by any one of a subtractive method, an additive method, a semiadaptive method, and an MSAP (Modified Semi-Additive Process) method.

The via may be formed by laminating the first insulating layer 110, forming a via hole in the first insulating layer 110, and filling the via hole with a conductive material. The via hole may be formed by any one of laser drilling, CNC drilling, chemical etching, and photolithography according to the type of the first insulating layer 110. The via may be formed in the via hole through electrolytic plating, but not limited thereto, and may be formed by filling the via hole with the conductive paste. The via may be formed together with the first conductor pattern layer 120 in a plating process for forming each first conductor pattern layer 120.

Next, as shown in Fig. 6, a solder resist layer SR is formed on the first conductor pattern layer 120 of the outermost layer. The solder resist layer SR may be formed by laminating a solder resist film. In the solder resist layer SR, an opening is formed to expose at least a part of the first conductor pattern layer 120 in the outermost layer. The openings may be formed in the solder resist layer through laser drilling, sandblasting or photolithography.

Next, as shown in Fig. 7, the first insulating portion 100 is separated from the carrier C. As shown in Fig. Specifically, the first copper foil CF1 and the second copper foil CF1 of the carrier C are separated from each other. The second copper foil CF2 of the carrier C and the etching stopper layer ES and the third copper foil CF3 are separated from the first copper foil CF1 of the carrier C together with the first insulating portion 100 .

Next, as shown in Fig. 8, the second copper foil CF2, the etch stop layer ES and the third copper foil CF3 are sequentially removed. In removing the second copper foil CF2 by etching, the anti-etching layer ES prevents the third copper foil CF3 and the connecting conductor pattern layer 400 from being removed by etching. A part of the connecting conductor pattern layer 400 in contact with the third copper foil CF3 is partially removed to etch the third copper foil CF3 by etching so that one surface of the connecting conductor pattern layer 400 is exposed to the outside of the protective layer 300 Or may be formed in a form embedded from one side.

Next, as shown in FIG. 9, a second insulating portion 200 is formed on the passivation layer 300.

The second insulating portion 200 may be formed by sequentially forming a second insulating layer 210, a via, and a second conductive pattern layer 220 on the passivation layer 300. At this time, the second insulating layer 210 may be stacked on the protective layer 300 in a state where the through-holes forming the receiving grooves CV are formed in advance. In this case, the second insulating layer 210 may be formed of a non-flow PPG having low fluidity. The process of forming the second insulating layer 210, the via, and the second conductor pattern layer 220 may be repeated several times according to design needs.

A method of manufacturing a package according to an embodiment of the present invention includes the steps of disposing an electronic component in a receiving groove of a printed circuit board and forming a molding material between a side surface of the electronic component and an inner wall of the receiving groove.

First, the electronic component 600 is placed in the receiving groove CV of the printed circuit board 500 '. An external connection terminal is formed on the active surface of the electronic component 600. The external connection terminal of the electronic component 600 is connected to the contact pattern 410 of the printed circuit board 500 ' So as to be disposed in the receiving groove CV.

Next, a molding material is formed between the side surface of the electronic component 600 and the inner wall of the receiving groove CV. The molding material may be EMC.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

100:
110: first insulating layer
120: first conductor pattern layer
200: second insulating portion
210: second insulating layer
220: second conductor pattern layer
300: protective layer
400: connecting conductor pattern layer
410: contact pattern
420: connecting vias
430: stop pattern
500, 500 ': printed circuit board
600: Electronic parts
1000, 1000 ': package
CV: Receiving groove
SR: solder resist layer
C: Carrier
S: Support
CF1, CF2, CF3: Copper foil
RL:
ES: Etch-preventing layer

Claims (9)

A first insulating portion;
A second insulation portion formed on the first insulation portion;
A receiving groove formed through the second insulating portion;
A protective layer formed between the first insulating portion and the second insulating portion and between the first insulating portion and the receiving groove; And
A connection conductor pattern layer including a connection pattern exposed in the receiving groove, the connection conductor pattern layer being embedded in the protection layer;
And a printed circuit board.
The method according to claim 1,
Wherein the protective layer is formed of a thermosetting solder resist.
The method according to claim 1,
A first conductor pattern layer formed on the first insulating portion; And
And a second conductor pattern layer formed on the second insulation portion,
The connection conductor pattern layer may be formed of a metal,
And a connection via for connecting the first conductor pattern layer and the second conductor pattern layer to each other through the protective layer.
The method of claim 3,
The connection conductor pattern layer may be formed of a metal,
And a stop pattern formed over a boundary between the second insulating portion and the receiving groove.
A printed circuit board according to any one of claims 1 to 4; And
And an electronic component disposed in the receiving groove and connected to the connection pattern.
6. The method of claim 5,
Wherein the electronic component is a semiconductor chip.
A method for manufacturing a semiconductor device, comprising: forming a first insulating portion on a carrier having a protective layer on one surface;
Separating the carrier and the first insulation portion; And
And forming a second insulating portion having a receiving groove on the protective layer,
The step of forming the first insulating portion on the carrier includes:
Forming the protective layer on the carrier, and
And forming a through hole in the protection layer.
8. The method of claim 7,
Wherein the protective layer is formed of a thermosetting solder resist.
8. The method of claim 7,
Wherein the through hole is formed of a sand blast.

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