KR101730468B1 - Printed circuit board which contains bumps and manufacturing method thereof - Google Patents

Abstract

The present invention provides a printed circuit board comprising: a first circuit layer formed by processing one surface of a first conductive foil; A support plate laminated on the first circuit layer; And a first bump for flip chip bonding formed by processing the other surface of the first conductive foil, and a method of manufacturing the same. The printed circuit board according to the present invention has a wiring structure that is realized as a circuit layer with respect to one conductive foil and a bump for flip chip bonding for mounting a semiconductor chip or the like is integrally formed and processed, It is possible to increase the competitiveness of the substrate itself based on utilization, reduce the process time and cost, and simplify the semiconductor package process. In addition, such a bump for flip chip bonding can be uniformly formed in a columnar shape by using a lithography process, improvement in mounting density due to a narrow pitch during semiconductor package operation, securing of excellent supporting force, and improvement of thermal and electrical characteristics Do.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a printed circuit board including a bump,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board and a method of manufacturing the same, and more particularly, to a printed circuit board used for mounting a semiconductor chip by flip chip bonding and a manufacturing method thereof.

2. Description of the Related Art [0002] With the recent development of high integration technology of semiconductor chips, it has become possible to arrange more circuits in the same size semiconductor chip, and a semiconductor chip having a larger number of input / output pins for transferring input / Packages are in the spotlight.

Conventionally, a connection between a semiconductor chip and a printed circuit board for such a semiconductor package is performed by a wire bonding method and a flip chip bonding method. In the wire bonding method, a semiconductor chip is disposed on a lead-formed substrate, and a lead is connected to an electrode pattern of the semiconductor chip using fine wires. Since the chip and the substrate are connected to the fine wires one at a time, There is a problem that the cost is increased and the mounting size is increased.

The flip chip bonding method is a method in which a bump is electrically connected to a substrate by using a bump in the form of an electrode pattern of a semiconductor chip or a solder ball formed on an inner lead, Since the semiconductor chip is directly mounted on the substrate with the semiconductor chip turned over, it is possible to miniaturize the product, and it is advantageous in improving chip performance and cost, and is a semiconductor chip mounting method which has recently been popular. The bump is made of a conductive material such as copper or metal and generally means a conductive protrusion for electrically / mechanically connecting the semiconductor chip and the substrate.

On the other hand, during the ordinary flip chip bonding, the solder ball-shaped bumps formed on the semiconductor chip are deformed during the remelting process or the reflow process, so that the spacing between the bumps becomes uneven. When the interval between the bumps is narrow, There is a problem that the reliability of the product is lowered.

In addition, in the case of a spherical solder ball used in the conventional flip-chip bonding, it is difficult to form the solder ball into a constant shape, and there is a limit to realize a narrow pitch due to spatial limitation.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a printed circuit board and a method of manufacturing the same that can improve reliability of a product during flip chip bonding and enable high density mounting.

Another object of the present invention is to provide a printed circuit board for flip chip bonding and a method of manufacturing the same, which can shorten the processing time and cost.

In order to accomplish the above-mentioned technical object, the gist of the present invention is as follows.

(1) processing one surface of the first conductive foil into a first circuit layer; Stacking a support plate on the first circuit layer; And processing the first bump for chip bonding on the other surface of the first conductive foil.

(2) The step of processing the first bonding bump includes: (a) laminating a photosensitive film on the first conductive foil; (b) exposing and developing the photosensitive film pattern corresponding to the first bump pattern to the photosensitive film; (c) forming the first bump by etching; And (d) removing the residual photosensitive film pattern. The method of manufacturing a printed circuit board according to claim 1,

(3) The method of manufacturing a printed circuit board according to the above (1), further comprising printing a protective layer on the first circuit layer.

(4) The method of manufacturing a printed circuit board according to (3), wherein the protective layer is a PSR (Photo Solder Resist).

(5) The method of manufacturing a printed circuit board according to (1) above, further comprising a step of plating the first bump for chip bonding.

(6) The method for manufacturing a printed circuit board according to (5), wherein the material used for the plating is any one selected from gold, silver, tin and lead.

(7) The method of manufacturing a printed circuit board according to (5), wherein the plating is performed by electroless plating and electrolytic plating.

(8) forming a second bump for electrical connection with another printed circuit board, wherein the second bump is electrically connected to the first circuit layer and exposed to the lower portion of the support plate A method for manufacturing a printed circuit board according to the above (1).

(9) The method of manufacturing a semiconductor device according to any one of the above items (1) to (3), wherein the supporting plate is formed by laminating an insulating layer and a second conductive foil, wherein the insulating layer is bonded to the first circuit layer, (1). ≪ / RTI >

(10) The method for manufacturing a printed circuit board according to (9), wherein the insulating layer is a semi-cured prepreg sheet.

(11) The step of processing the second circuit layer includes the steps of: (a) forming a via hole in a predetermined region on the support plate up to the exposed surface of the first circuit layer; (b) forming a plating layer for electrical connection between the second circuit layer and the first circuit layer; (c) forming a photosensitive film on a lower portion of the plating layer; (d) exposing and developing the photosensitive film pattern corresponding to the second circuit layer pattern to the photosensitive film formed on the plating layer, respectively; (e) etching and forming the second circuit layer pattern; And (f) removing the residual photosensitive film pattern. The method of manufacturing a printed circuit board according to claim 9,

(12) The method of manufacturing a printed circuit board according to (9) or (11), wherein the step of processing the second circuit layer is performed simultaneously with the step of processing the first bump.

(13) In the step (b), a plating layer is formed on the upper surface of the first conductive foil, and the first bumps having the plating layer formed on the upper surface thereof are integrally patterned in accordance with the step of processing the second circuit layer (11). ≪ / RTI >

(14) a first circuit layer formed by processing one surface of the first conductive foil; A support plate laminated on the first circuit layer; And a first bump for flip chip bonding formed by processing the other surface of the conductive foil.

(15) The printed circuit board according to (14), wherein the first bumps are columnar.

(16) The printed circuit board according to (14), further comprising a protective layer printed on the first circuit layer.

(17) The printed circuit board according to (16), wherein the protective layer is a PSR (Photo Solder Resist).

(18) The printed circuit board according to (14), further comprising a plating layer formed on the first bump.

(19) The printed circuit board according to (18), wherein the plating layer is any one selected from gold, silver, tin and lead.

(20) further comprising a second bump for electrical connection with another printed circuit board, the second bump being electrically connected to the first circuit layer and exposed to the lower portion of the support plate. Lt; / RTI >

(21) The method according to (14), wherein the supporting plate has a structure in which an insulating layer and a second conductive foil are laminated, the insulating layer is bonded to the first circuit layer, and the second circuit layer is formed on the second conductive foil. Lt; / RTI >

(22) The printed circuit board according to (21), wherein the insulating layer is a semi-cured prepreg sheet.

The printed circuit board according to the present invention has a wiring structure that is realized as a circuit layer with respect to one conductive foil and a bump for flip chip bonding for mounting a semiconductor chip or the like is integrally formed and processed, It is possible to increase the competitiveness of the substrate itself based on utilization, reduce the process time and cost, and simplify the semiconductor package process.

In addition, such a bump for flip chip bonding can be uniformly formed into a columnar shape by using a lithography process, and it is possible to improve the mounting density by narrow pitch during semiconductor package operation, securing excellent supporting force, and improving thermal and electrical characteristics Do.

1 is a cross-sectional structural view of a single-layer printed circuit board according to an embodiment of the present invention;
2 is a cross-sectional structural view of a multilayer printed circuit board according to another embodiment of the present invention;
3 is a flowchart of a method of forming a single-layer printed circuit board according to FIG.
4 is a schematic view of a process of forming a first circuit layer according to the present invention;
5 is a cross-sectional structural view of a printed circuit board in a state in which a support plate is laminated on a first circuit layer according to the present invention.
6 is a schematic view of a process of forming a first bump according to the present invention;
7 is a cross-sectional structural view of a printed circuit board in a state where a protective layer is formed according to the present invention.
8 is a cross-sectional structural view of a printed circuit board in a state where a plating layer is formed according to the present invention.
9 is a schematic view of a process of manufacturing the multilayer printed board according to FIG. 2;

Hereinafter, embodiments of a printed circuit board and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

In the drawings, the same or similar reference numerals are given to the same or equivalent elements in the drawings, and in the specification, when a component is referred to as " including ", unless the context clearly indicates otherwise, But it may include other components.

In the drawings, the film thickness or the size of the regions are exaggerated for convenience of explanation, such as a conductive foil, a support plate, a plated layer, a film layer, and the like. The vertical direction of the printed circuit board has been described with reference to the drawings.

First, a structure of a printed circuit board according to an embodiment of the present invention will be described. 1 is a cross-sectional structural view of a single-layer printed circuit board according to an embodiment of the present invention.

The printed circuit board including the bumps according to the present invention basically includes a first circuit layer 120 formed by processing one surface of the first conductive foil 100 and an insulating layer 110 laminated on the first circuit layer 120 And a first bump 300 formed by processing the other surface of the first conductive foil 100.

The first conductive foil 100 may be a single layer structure of pure copper (Cu) as a matrix for processing the first circuit layer 120 and the first bump 300 for flip chip bonding, Layer structure (Cu / Ni / Cu) including nickel between the upper and lower copper layers. In the case of a multi-layer structure, the first bump 300 described above may be formed on the outermost copper layer.

The thickness of the first conductive foil 100 can be appropriately selected based on the design height of the first circuit layer 120 and the bump 300. If the thickness is excessively large, the thickness of the entire semiconductor package becomes large, If it is too thin, the formation and etching of the first bump 300 may become difficult. In this respect, the thickness of the first conductive foil 100 may preferably be selected in the range of 60 [mu] m to 120 [mu] m.

The first circuit layer 120 is a wiring structure of a printed circuit board, and the first bumps 300 are conductive protrusions for electrically / mechanically connecting a semiconductor chip to a substrate. The first circuit layer 120 and the first bump 300 may be formed through a lithography process as described below.

The first bump 300 can reliably be formed in a predetermined shape using a lithography process and can be formed into a column shape unlike a spherical solder ball formed on a chip during conventional flip chip bonding, It can be advantageously applied to a narrow pitch implementation.

The support plate 200 is stacked on the surface on which the first circuit layer 120 is formed to physically support the substrate and to electrically isolate the substrate. In this case, the first circuit layer 120 is included in the insulating layer 210 of the support plate 200 and the upper surface thereof is exposed. The first bump 300 protrudes to the outside of the insulating layer 210 Respectively.

The supporting plate 200 includes an insulating layer 210 to electrically isolate the insulating layer 210. The present invention is not limited to the material of the insulating layer. Alternatively, the support plate 200 may have a structure in which a second conductive foil 220 is laminated together with an insulating layer 210 to form a multilayer printed circuit board. In this case, A separate circuit layer may be formed on the second conductive foil 220. A prepreg coated copper (PCC) layer, which is a copper-coated conductive material, is formed by impregnating a base material such as glass fiber or the like with a thermosetting resin and then curing the pre- ) May be used, but the present invention is not limited thereto.

The thickness of the support plate 200 may be appropriately selected in consideration of the role of the support plate, and may be selected preferably in the range of 50 탆 to 100 탆.

A protective layer 400 may be formed on the first circuit layer 120. The upper surface of the first circuit layer 120 is exposed to the outside in the process of etching the first bump 300. The protective layer 400 protects the upper surface of the exposed first circuit layer 120 Thereby preventing the solder bridge phenomenon from occurring between the circuits. However, since the first circuit layer 120 is formed in the dielectric and can be protected by the final surface treatment as described above, the formation of the protective layer 400 can be selectively performed only when necessary, May be omitted in order to save.

The protective layer 400 may be formed by printing a PSR (photo solder resist), which is a kind of durable inks, in a physicochemical environment.

A plating layer 500 may be formed on the upper surface of the first bump 300. The plating layer 500 prevents oxidation of metals such as copper and improves electrical conductivity, abrasion resistance, heat resistance, corrosion resistance, and the like. The plating layer 500 may be any one selected from gold, silver, tin, and lead, and may be formed by electroless plating and electrolytic plating.

A second bump 600 may be formed on the lower surface of the first circuit layer 120 and the second bump 600 may be formed on the lower surface of the first circuit layer 120 and another printed circuit board And performs mechanical / electrical connection with the substrate. A hole 610 is formed at a predetermined position corresponding to the first circuit layer 120 with respect to the support plate 200 for forming the second bump 600 and the second bump 600 is formed through a hole 610, On the lower surface of the first circuit layer 120 exposed. The formation of the second bump 600 may be done by filling the hole 610 with a conductive paste.

One of the features of the printed circuit board according to the present invention is that a wiring structure implemented by the first circuit layer 120 is formed for one first conductive foil 100, And the bump 300 is integrally formed and processed, it is possible to efficiently use the conductive foil. One further feature of the printed circuit board according to the present invention, it is possible to a first bump 300 for the replicon-chip bonding using a lithographic process to form reliably a constant shape as mentioned above, prior to their shape Unlike the spherical solder balls formed on the chip in the flip chip bonding, it is possible to produce a columnar shape, so that it can be advantageously applied to narrow pitch implementation.

2 is a cross-sectional structural view of a multilayer printed circuit board according to another embodiment of the present invention. The multilayer printed circuit board is a printed circuit board in which a plurality of circuit layers are formed on one substrate and each circuit layer is electrically connected. Basically, the support plate 200 is connected to the second conductive foil And the second circuit layer 700 formed on the second conductive foil 220 is electrically connected to the first circuit layer 120 formed in advance.

The electrical connection between the first circuit layer 120 and the second circuit layer 700 may be achieved by forming a via hole 900 at a predetermined position of the support plate 200 and electrically connecting the first circuit layer exposed by the via hole 900 The first conductive foil 220 and the second conductive foil 220 are integrally formed on the side surface of the via hole 900 and the lower surface of the second conductive foil 220, And then patterning the circuit layer 700.

In the case of the multilayer printed circuit board according to FIG. 2, the configuration for the first circuit layer 120 and the first bump 300 is the same as that of the single-layer printed circuit board of FIG. 1, The protective layer 400 for the first bump 300 and the plating layer 500 on the first bump 300 may be applied as in the case of the single-layer printed circuit board according to FIG.

Next, a method of manufacturing a printed circuit board according to an embodiment of the present invention will be described. FIG. 3 is a flowchart of a method of forming a single-layer printed circuit board according to FIG. 1, and FIGS. 4 to 8 are sectional views or explanatory views of a printed circuit board according to a unit process.

Referring to FIGS. 3 and 4, a first circuit layer 120, which is a wiring structure of a printed circuit board, is formed on one surface of the first conductive foil 100 (S10). The first circuit layer 120 may be formed by coating a photosensitive film on a surface of the first conductive foil 100 and then patterning the first circuit layer 120 through a lithography process or an etching process But is not limited thereto. Specifically, (a) a step of laminating a photosensitive film 110 such as a dry film on the surface of the first conductive foil 100 where at least the first circuit layer 120 is to be formed; (b) exposing and developing the photosensitive film pattern corresponding to the pattern of the first circuit layer 120 to the photosensitive film 110; (c) forming the first circuit layer 120 by etching; And (d) removing the residual photosensitive film in a sequential manner.

The process of laminating the photosensitive film 110 is performed by placing the photosensitive film 110 on the first conductive foil 100, which is a target substrate, and then applying the photosensitive film 110 with a predetermined heat and pressure. If necessary, the first conductive foil 100 may be subjected to a surface treatment to form surface roughness by chemical polishing or mechanical polishing before the lamination process, in order to improve the adhesion of the photosensitive film 110.

The exposure process is performed by aligning and aligning a working film for a pattern mask on the laminated photosensitive film 110, and then irradiating light energy such as UV light. Thus, the photosensitive film 110 ) Is changed from a monomer to a polymer. The photosensitive film 110 is exposed to a developing solution in a subsequent developing process to remove the unexposed monomer photosensitive film 110 to form a photosensitive film pattern.

The area of the first conductive foil 100 to which the photosensitive film pattern is not applied in the etching process is dry or wet etched to form the first circuit layer 120 pattern and the photosensitive film pattern is peeled off using sodium hydroxide, The first circuit layer 120 is formed on the lower surface of the first conductive foil 100 as shown in FIG.

Referring to FIGS. 3 and 5, a supporting plate (not shown) is mounted on the surface of the first conductive foil 100, on which the first circuit layer 120 is formed, 200 are stacked (S20).

The supporting plate 200 includes an insulating layer 210 to electrically isolate the insulating layer 210 and the second conductive foil 220. The insulating layer 210 and the second conductive foil 220 are laminated to each other. A commercially available PCC (Prepreg Coated Copper) coated with a conductive material such as a prepreg using a prepreg which is cured in a semi-cured state as an insulating material can be generally used.

The laminating process may be performed by stacking prepregs, conductive foils, etc. in accordance with design specifications, and applying heat and pressure to adhere the prepregs.

In the case where the support plate 200 has a structure in which the insulating layer 210 and the second conductive foil 220 are laminated, the second conductive foil 220 may be formed in a multilayer printed circuit board having a multi- It can be used to form a circuit layer and can be removed if necessary in the case of manufacturing a single-layer printed circuit board.

Next, referring to FIGS. 3 and 6, a first bump 300 for flip-chip bonding a semiconductor chip is formed on the other surface of the first conductive foil 100 (S30). The process of forming the first bumps 300 may be performed by coating the photosensitive film 310 on the surface of the first conductive foil 100 on which bumps are to be formed as in the case of forming the first circuit layer 120 A lithography process and an etching process. (A) laminating a photosensitive film 310 on the other surface of the first conductive foil 100; (b) exposing and developing the photosensitive film pattern corresponding to the first bump pattern to the photosensitive film 310; (c) forming the first bump (300) by etching; And (d) removing the residual photosensitive film pattern. In this case, the lamination, exposure and development, etching, and peeling processes can be applied in the same manner as in the process of forming the first circuit layer 120 described above.

Next, referring to FIGS. 3 and 7, a protective layer 400 is formed to protect the exposed first circuit layer 120 and prevent solder stagnation (S40). The formation of the protective layer 400 is performed by printing a PSR (photo solder resist), which is a kind of a persistent ink having a durability under a physicochemical environment. However, as described above, since the first circuit layer 120 is formed inside the dielectric and can be protected by the final surface treatment, the formation of the protective layer 400 may be omitted in some cases.

3 and 8, a top surface of the first bump 300 is coated with a plating layer 500 (hereinafter referred to as " plating layer ") that prevents oxidation of metals such as copper and improves electrical conductivity, abrasion resistance, heat resistance, (S50). The process of forming the plating layer 500 may be performed by electroless plating or electrolytic plating using gold, silver, tin, or lead. In this case, the electroless electroplating is a chemical plating or an electrocatalyst plating in which the metal ions are coated by using the chemical oxidation / reduction reaction without receiving the electric energy, and the electroplating is a plating using the electrodeposition method do. The electroless plating and the electrolytic plating are performed by using both the electroless plating and the electrolytic plating.

Next, referring to FIG. 3 and FIG. 1, a second bump 600 for mechanical / electrical connection with another printed circuit board is formed (S60). A hole 610 is formed at a predetermined position corresponding to the first circuit layer 120 with respect to the support plate 200 to form the second bump 600 and then the second bump 600 is inserted into the hole 610, On the lower surface of the first circuit layer 120 exposed. In this case, the hole 610 may be formed by a mechanical drilling process, a plasma etching process, a laser process, or the like, and the formation of the second bump 600 may be performed by filling the hole 610 with a conductive paste. have.

Since the second bumps 600 are formed for the purpose of mechanical / electrical connection with other printed circuit boards, the second bumps 600 are not necessarily involved in the process of manufacturing a single-layer printed circuit board.

According to another embodiment of the present invention, a printed circuit board in which the bumps 300 for flip chip bonding are integrated can be formed in multiple layers, and FIG. 9 shows a process of manufacturing such a multilayer printed circuit board by a simplified process .

The process of forming the first circuit layer 120, the first bump 300, and the protective layer 400 may be similarly applied to the process of manufacturing the multilayer printed circuit board, And the process of forming an electrical connection between the circuit layers constituted by the first layer and the second layer.

Basically, a multilayer printed circuit board is manufactured by forming the support plate 200 with a structure in which the second conductive foil 220 is laminated together with the insulating layer 210, and the second conductive foil 220, Layer 700 and the first circuit layer 120 previously formed on the first conductive foil 100 are electrically connected to each other by using a plating layer 800. [

First, a hole serving as an electrical connection path between circuit layers is formed at a predetermined lower portion of the support plate 200. Such a hole is generally referred to as a via hole 900. A blind via hole selectively penetrated only through the support plate 200 through laser processing is formed so that the lower surface of the first circuit layer 120 It is possible to expose it to the outside. The lower surface of the first circuit layer 120 exposed to the outside is integrally formed with the side surface of the via hole 900 and the lower surface of the second conductive foil 220 and with the upper surface of the first conductive foil 100 A plating layer 800 is formed. The plating layer 800 on the upper surface of the substrate is patterned integrally with the first bump 300 in the subsequent process and the plating layer 800 on the lower surface of the substrate includes the first circuit layer 120 and the second circuit layer 700 are electrically connected. The plating may be performed using a conductive material including copper, and the plating layer 800 may be formed by an electroless plating method or an electrolytic plating method. Next, a photosensitive film 310 such as a dry film is laminated on the upper surface of the first conductive foil 100 and the lower surface of the second conductive foil 220 on which the plating layer 800 is formed. In this case, the inside of the via hole 900 is sealed by the photosensitive film 310 laminated on the lower side of the second conductive foil 220. Next, a photosensitive film pattern corresponding to the first bump pattern 300 is formed on the photosensitive film 310 coated on the upper surface side of the first conductive foil 100, The photosensitive film pattern corresponding to the second circuit layer 700 is formed by exposing and developing the photosensitive film 310 located in the second circuit layer 700, respectively. Next, the patterns of the first bump 300 and the second circuit layer 700 are formed through an etching process. In this case, the patterning of the first bump 300 and the second circuit layer 700 formed by the etching process is also performed for the plating layer 800. Next, the residual photosensitive film patterns are peeled off by using sodium hydroxide, potassium hydroxide, or the like to produce a multilayer printed circuit board in which the flip chip bonding bumps 300 are integrally formed.

In the embodiment of FIG. 9, patterning is performed on the second circuit layer 700 simultaneously with the formation of the first bumps 300, thereby reducing the processing time and cost. However, in the embodiment, the patterning is also performed on the second circuit layer 700 by using the lamination coating process in the process of forming the first bumps 300. However, the pattern for the second circuit layer 700 The process of forming the via hole 900 and the plating layer 800 may be separated by a separate process and the plating layer 800 formed on the first bump 300 may be separately formed.

The foregoing is a description of specific embodiments of the present invention. While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments or constructions. It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. It should be understood that this is possible. It is therefore to be understood that all such modifications and alterations are intended to fall within the scope of the invention as disclosed in the following claims or their equivalents.

100: first conductive foil 110: photosensitive film
120: first circuit layer 200:
210: insulating layer 220: second conductive foil
300: first bump 310: photosensitive film
400: protective layer 500: plated layer
600: second bump 610: hole
700: second circuit layer 800: plated layer
900: via hole

Claims (22)

Processing one surface of the first conductive foil into a first circuit layer; Stacking the first circuit layer of the first conductive foil so as to be embedded so as to face the insulating layer provided on the support plate; And processing the first bump for chip bonding to be integrated with the first circuit layer on the other surface opposite to the first conductive foil,
The step of processing the first bonding bump includes: (a) laminating a photosensitive film on the first conductive foil; (b) exposing and developing the photosensitive film pattern corresponding to the first bump pattern to the photosensitive film; (c) forming the first bump by etching; And (d) removing the residual photosensitive film pattern,
Wherein the first circuit layer is included in the insulating layer and only the top surface is exposed. delete delete delete delete delete delete delete delete delete delete 2. The method of claim 1, wherein the support plate further comprises a layer of an insulating layer and a second conductive foil, wherein the insulating layer is bonded to the first circuit layer, and the second conductive foil is processed to form a second circuit layer And the step of machining the second circuit layer comprises:
(a) forming a via hole in a predetermined region on the support plate to the exposed surface of the first circuit layer;
(b) forming a plating layer for electrical connection between the second circuit layer and the first circuit layer;
(c) forming a photosensitive film on a lower portion of the plating layer;
(d) exposing and developing the photosensitive film pattern corresponding to the second circuit layer pattern to the photosensitive film formed on the plating layer, respectively;
(e) etching and forming the second circuit layer pattern; And
(f) removing the residual photosensitive film pattern,
Wherein the step of machining the second circuit layer is performed simultaneously with the step of machining the first bump. 2. The method of claim 1, wherein the support plate further comprises a layer of an insulating layer and a second conductive foil, wherein the insulating layer is bonded to the first circuit layer, and the second conductive foil is processed to form a second circuit layer And the step of machining the second circuit layer comprises:
(a) forming a via hole in a predetermined region on the support plate to the exposed surface of the first circuit layer;
(b) forming a plating layer for electrical connection between the second circuit layer and the first circuit layer;
(c) forming a photosensitive film on a lower portion of the plating layer;
(d) exposing and developing the photosensitive film pattern corresponding to the second circuit layer pattern to the photosensitive film formed on the plating layer, respectively;
(e) etching and forming the second circuit layer pattern; And
(f) removing the residual photosensitive film pattern,
Forming a plating layer on the upper surface of the first conductive foil in the step (b), and patterning the first bumps integrally formed with the plating layer on the upper surface in accordance with the step of processing the second circuit layer. ≪ / RTI > delete delete delete delete delete delete delete delete delete

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