KR20110136314A - Printed circuit board which contains bumps and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A printed circuit board and a manufacturing method thereof are provided to simplify a semiconductor package process based on the effective utilization of a conductive foil by integrally forming a wiring structure and a bump for flip chip bonding. CONSTITUTION: A first circuit layer(120) is formed by processing the one side of a first conductive foil. A supporting plate includes an insulating layer(210) which is laminated in the first circuit layer. A first bump(300) is formed by processing the other side of the first conductive foil. The first conductive foil is used as a base material for processing the first circuit layer and the first bump for flip-chip bonding. The thickness of the first conductive foil can be appropriately selected based on the designed height of the bump and the first circuit layer. The first bump is reliably formed into a fixed shape using a lithographic process.

Description

Printed circuit board including bumps and manufacturing method therefor {PRINTED CIRCUIT BOARD WHICH CONTAINS BUMPS AND MANUFACTURING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board and a method for manufacturing the same, and more particularly, to a printed circuit board and a method for manufacturing the same, when the semiconductor chip is mounted by flip chip bonding.

With the recent development of high integration technology of semiconductor chips, more circuit arrangements are possible on semiconductor chips of the same size, and semiconductors composed of semiconductor chips and printed circuit boards having the same number of input / output pins for transmitting input / output signals have been increased. The package is in the spotlight.

Conventionally, the connection between a semiconductor chip and a printed circuit board for such a semiconductor package is performed by a wire bonding method and a flip chip bonding method. Wire bonding is a method of arranging a semiconductor chip on a substrate on which a lead is formed and connecting electrode patterns of the lead and the semiconductor chip using fine wires. There is a problem that it takes a lot of cost and the mounting size becomes large.

Flip chip bonding is a method in which bumps are electrically connected to a substrate by using bumps in the form of solder balls formed on an electrode pattern or inner lead of a semiconductor chip. Since the semiconductor chip is mounted upside down and directly mounted on the substrate, it is possible to reduce the size of the product, and it is a semiconductor chip mounting method that has recently been in the spotlight for the improvement of the chip performance and the cost reduction. The bump is made of a conductive material such as copper or metal, and generally means a conductive protrusion for electrically / mechanically connecting the semiconductor chip and the substrate.

Meanwhile, during the remelting or reflowing process in general flip chip bonding, bumps in the form of solder balls formed on the semiconductor chip are deformed, resulting in uneven spacing between bumps. Therefore, the empty space is generated, there is a problem that the reliability of the product is lowered.

In addition, in the case of a spherical solder ball used in the conventional flipping bonding, it is difficult to form a uniform shape, there is a limit to implement a narrow pitch due to spatial constraints.

Therefore, the technical problem to be solved by the present invention is to provide a printed circuit board and a method of manufacturing the same that can improve the reliability of the product when the flip chip bonding, and can be mounted in high density.

Another technical problem of the present invention is to provide a flip chip bonding printed circuit board and a method of manufacturing the same, which can reduce the process time and cost.

The gist of the present invention for achieving the above technical problem is as follows.

(1) processing one surface of the first conductive foil into a first circuit layer; Stacking a support plate on the first circuit layer; And processing a first bump for chip bonding on the other surface of the first conductive foil.

(2) processing the first bump for chip bonding may include: (a) laminating a photosensitive film on the first conductive foil; (b) exposing and developing a photosensitive film pattern corresponding to the first bump pattern on the photosensitive film; (c) forming the first bump by etching; And (d) removing the residual photosensitive film pattern.

(3) The method of manufacturing a printed circuit board according to (1), further comprising the step of printing a protective layer over the first circuit layer.

(4) The method of manufacturing a printed circuit board according to (3), wherein the protective layer is a PSR (Photo Solder Resist).

(5) The method of manufacturing a printed circuit board according to (1), further comprising the step of plating the first bump for chip bonding.

(6) The method for manufacturing a printed circuit board according to (5), wherein the material used for plating is any one selected from gold, silver, tin, and lead.

(7) The method of manufacturing a printed circuit board according to (5), wherein the plating is performed by electroless and electrolytic plating.

(8) forming a second bump for electrical connection with another printed board, the second bump being electrically connected with the first circuit layer and being exposed under the support plate. The printed circuit board manufacturing method according to (1).

(9) The supporting plate has a structure in which an insulating layer and a second conductive foil are laminated, and the insulating layer is bonded to the first circuit layer, and further comprising the step of processing the second circuit layer on the second conductive foil. Printed circuit board manufacturing method according to (1).

(10) The method of manufacturing a printed circuit board according to (9), wherein the insulating layer is a prepreg sheet in a semi-cured state.

(11) processing the second circuit layer comprises: (a) forming a via hole in a predetermined portion of the support plate up to a first circuit layer exposed surface; (b) forming a plating layer for electrical connection between the second circuit layer and the first circuit layer; (c) forming a photosensitive film under the plating layer; (d) exposing and developing the photosensitive film pattern corresponding to the second circuit layer pattern, respectively, on the photosensitive film formed on the plating layer; (e) etching to form the second circuit layer pattern; And (f) removing the residual photosensitive film pattern.

12. The method of manufacturing a printed circuit board according to (9) or (11), wherein the processing of the second circuit layer is performed simultaneously with the processing of the first bump.

(13) forming a plating layer on the upper surface of the first conductive foil in the step (b), and processing the second circuit layer to integrally pattern the first bumps having the plating layer formed on the upper surface thereof. Printed circuit board manufacturing method according to (11).

(14) a first circuit layer formed by processing one surface of the first conductive foil; A support plate laminated on the first circuit layer; And a first bump for flip chip bonding formed by processing the other surface of the conductive foil.

(15) The printed circuit board according to (14), wherein the first bumps are columnar.

(16) The printed circuit board according to (14), further comprising a protective layer printed on the first circuit layer.

(17) The printed circuit board according to (16), wherein the protective layer is PSR (Photo Solder Resist).

(18) The printed circuit board according to (14), further comprising a plating layer formed on the first bump.

(19) The printed circuit board according to (18), wherein the plating layer is any one selected from gold, silver, tin, and lead.

(20) further comprising a second bump for electrical connection with another printed board, wherein the second bump is electrically connected to the first circuit layer and is exposed under the support plate. Printed circuit board according to.

(14) The support plate has a structure in which an insulating layer and a second conductive foil are stacked, and an insulating layer is bonded to the first circuit layer, and a second circuit layer is formed on the second conductive foil. Printed circuit board according to.

(22) The printed circuit board according to (21), wherein the insulating layer is a prepreg sheet in a semi-cured state.

The printed circuit board according to the present invention forms a wiring structure implemented as a circuit layer for one conductive foil and simultaneously processes and forms flip chip bonding bumps for mounting a semiconductor chip, thereby efficiently forming a conductive foil. Based on the application, it is possible to increase the competitiveness of the substrate itself, reduce processing time and cost, and simplify the semiconductor package process.

In addition, the bumps for flip chip bonding may be uniformly formed in a columnar shape using a lithography process, and may improve the mounting density due to a narrow pitch, secure excellent supporting force, and improve thermal and electrical characteristics when working with a semiconductor package. Do.

1 is a cross-sectional structure diagram of a single-layer printed circuit board according to an embodiment of the present invention.
2 is a cross-sectional structural view of a multilayer printed circuit board according to another exemplary embodiment of the present invention.
3 is a flowchart of a method of forming a single-layer printed circuit board according to FIG. 1.
4 is a schematic diagram of a process of forming a first circuit layer according to the present invention;
5 is a cross-sectional structural view of a printed circuit board in a state in which a supporting plate is stacked on a first circuit layer according to the present invention.
Figure 6 is a schematic diagram of a process of forming the first bump in accordance with the present invention.
7 is a cross-sectional structural view of a printed circuit board in a state of forming a protective layer according to the present invention.
8 is a cross-sectional structural view of a printed circuit board in a state where a plating layer is formed according to the present invention.
9 is a schematic diagram of a process of manufacturing a multilayer printed circuit board according to FIG. 2;

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of a printed circuit board and its manufacturing method according to the present invention.

In the drawings, the same or equivalent reference numerals are given the same or similar reference numerals, and throughout the specification, when a part is said to include a component, except for a component other than a component, unless otherwise stated, It does not mean that it may further include other components.

In the drawings, elements such as a conductive foil, a support plate, a plating layer, a film layer, and the like that form a printed circuit board or are used in a manufacturing process are exaggerated for the convenience of description. In addition, the vertical direction of the printed circuit board has been described with reference to the drawings.

First, the structure of a printed circuit board according to an embodiment of the present invention will be described. 1 is a cross-sectional structural view of a single-layer printed circuit board according to an embodiment of the present invention.

The printed circuit board including the bump according to the present invention basically includes a first circuit layer 120 formed by processing one surface of the first conductive foil 100 and an insulating layer laminated on the first circuit layer 120 ( A support plate 200 including 210 (see FIG. 4) and a first bump 300 formed by processing the other surface of the first conductive foil 100 are configured.

The first conductive foil 100 is a base material for processing the first circuit layer 120 and the first bump 300 for flip chip bonding, and is a single layer structure made of pure copper (Cu), It may be made of a three-layer structure (Cu / Ni / Cu) containing nickel between the upper and lower copper layers. In the case of the multilayer structure, the first bumps 300 described above may be formed on the outermost layer copper.

The thickness of the first conductive foil 100 may be appropriately selected based on the design height of the first circuit layer 120 and the bump 300. If the thickness is excessively large, the thickness of the entire semiconductor package is increased, and conversely, If too thin, it may be difficult to form and etch the first bump 300. In this aspect, the thickness of the first conductive foil 100 may be preferably selected in the range of 60 μm to 120 μm.

The first circuit layer 120 is a wiring structure of a printed circuit board, and the first bump 300 is a conductive protrusion for electrically / mechanically connecting a semiconductor chip to the substrate. The first circuit layer 120 and the first bump 300 may be formed through a lithography process as described below.

The first bump 300 may be reliably formed in a predetermined shape by using a lithography process, and the shape of the first bump 300 may be manufactured in a columnar shape unlike a spherical solder ball formed on a chip during conventional flip chip bonding. It can be advantageously applied to narrow pitch implementations.

The support plate 200 is stacked on the surface on which the first circuit layer 120 is formed to serve to physically support the substrate and to electrically insulate the substrate. In this case, the first circuit layer 120 is included in the insulating layer 210 of the support plate 200 and has an upper surface exposed, and the first bump 300 protrudes out of the insulating layer 210. It is formed.

The support plate 200 includes an insulating layer 210 to electrically insulate, and the present invention is not particularly limited with respect to the material of the insulating layer. Optionally, the support plate 200 may have a structure in which a second conductive foil 220 is stacked together with an insulating layer 210 to form a multilayer printed circuit board, in which case the first circuit layer 120 and The separate circuit layer may be formed on the second conductive foil 220 processed. A structure in which an insulating layer and a conductive foil are laminated, and a prepreg cured in a semi-cured state after impregnating a thermosetting resin into a base material such as glass fiber, and coated with a conductive material copper, also known as PCC (Prepreg Coated Copper). ) May be used, but is not limited thereto.

The thickness of the support plate 200 may be appropriately selected in consideration of the role of the support plate, and may be preferably selected in the range of 50 μm to 100 μm.

A protective layer 400 may be formed on an upper surface of the first circuit layer 120. In the process of forming the first circuit layer 120 by etching the first bump 300, the upper surface thereof is exposed to the outside, and the protective layer 400 protects the upper surface of the exposed first circuit layer 120. It serves to prevent the occurrence of solder bridges between circuits. However, as described above, since the first circuit layer 120 is formed inside the dielectric and can be protected by the final surface treatment, the formation of the protective layer 400 may be selectively made only when necessary, and thus the manufacturing cost. It may be omitted to save.

The protective layer 400 may be formed by printing a photo solder resist (PSR), which is a kind of invariant ink having durability in a physicochemical environment.

A plating layer 500 may be formed on the top surface of the first bump 300. The plating layer 500 serves to prevent oxidation of metals such as copper and to improve electrical conductivity and wear resistance, heat resistance, corrosion resistance, and the like. The plating layer 500 may be any one selected from gold, silver, tin, and lead, and may be formed by electroless plating and electrolytic plating.

A second bump 600 may be formed on a bottom surface of the first circuit layer 120, and the second bump 600 is another printed circuit disposed below the first circuit layer 120 and the printed circuit board. Perform mechanical / electrical connection with the substrate. In order to form the second bump 600, a hole 610 is processed at a predetermined position corresponding to the first circuit layer 120 with respect to the support plate 200, and the second bump 600 has a hole 610. It is formed on the lower surface of the first circuit layer 120 exposed by. The second bump 600 may be formed by filling a conductive paste in the hole 610.

One of the features of the printed circuit board according to the present invention is a first structure for mounting a semiconductor chip and the like while forming a wiring structure implemented by the first circuit layer 120 on one first conductive foil 100. By integrally forming and forming the bumps 300, efficient use of the conductive foil is possible. One further feature of the printed circuit board according to the present invention, it is possible to a first bump 300 for the replicon-chip bonding using a lithographic process to form reliably a constant shape as mentioned above, prior to their shape Unlike the spherical solder balls formed on the chip during the flip chip bonding, it can be manufactured in a columnar shape, and thus it can be advantageously applied to narrow pitch implementation.

2 is a cross-sectional structural view of a multilayer printed circuit board according to another exemplary embodiment of the present invention. The multilayer printed circuit board is a printed circuit board having a plurality of circuit layers formed on a single substrate and electrically connected to each circuit layer. The multilayer printed circuit board basically includes the supporting plate 200 together with the insulating layer 210 and the second conductive foil ( 220 is a stacked structure, and the second circuit layer 700 formed on the second conductive foil 220 and the pre-formed first circuit layer 120 is electrically connected.

Electrical connection between the first circuit layer 120 and the second circuit layer 700 forms a via hole 900 at a predetermined position of the support plate 200 and exposes the first circuit layer (exposed by the via hole 900). After forming the plating layer 800 integrally on the lower surface of the via hole 900 and the lower surface of the second conductive foil 220, the second conductive foil 220 may be formed together with the plating layer 800. This is achieved by patterning the circuit layer 700.

Also in the case of the multilayer printed circuit board according to FIG. 2, the configurations of the first circuit layer 120 and the first bump 300 are the same as those of the single-layer printed circuit board of FIG. 1, and the protection of the first circuit layer 120 is improved. The protective layer 400 and the plating layer 500 on the first bump 300 may be applied as in the single-layer printed circuit board of FIG. 1.

Next, a method of manufacturing a printed circuit board according to an embodiment of the present invention will be described. 3 is a flowchart illustrating a method of forming a single-layer printed circuit board according to FIG. 1, and FIGS. 4 to 8 are cross-sectional views or explanations of a printed circuit board according to a unit process.

3 and 4, the first circuit layer 120, which is a wiring structure of the printed circuit board, is formed on one surface of the first conductive foil 100 (S10). The process of forming the first circuit layer 120 is preferably a method of patterning the first circuit layer 120 through a lithography process and an etching process after coating the photosensitive film on the surface of the first conductive foil 100. It may be performed as, but is not limited thereto. Specifically, (a) laminating a photosensitive film 110, such as a dry film, on at least one surface of the first conductive foil 100 surface on which the first circuit layer 120 is to be formed; (b) exposing and developing a photosensitive film pattern corresponding to the first circuit layer 120 pattern on the photosensitive film 110; (c) forming the first circuit layer 120 by etching; And (d) removing the residual photosensitive film sequentially.

The photosensitive film 110 lamination process is performed by placing the photosensitive film 110 on the first conductive foil 100, which is a target substrate, and then applying the film with a predetermined heat and pressure. If necessary, in order to improve the adhesion of the photosensitive film 110, the surface treatment may be accompanied with the first conductive foil 100 to form surface roughness through chemical polishing or mechanical polishing before the lamination process.

The exposure process is performed by aligning and arranging a working film for a pattern mask on the laminated photosensitive film 110, and then irradiating light energy such as UV, and thus, the photosensitive film 110 at the light irradiated portion ) Is changed from monomer to polymer. In the subsequent development process, the photosensitive film 110 is exposed to the developer, thereby removing the unirradiated monomer photosensitive film 110 to form a photosensitive film pattern.

In the etching process, a first circuit layer 120 pattern is formed by dry or wet etching an area of the first conductive foil 100 to which the photosensitive film pattern is not applied, and peels the photosensitive film pattern using sodium hydroxide or potassium hydroxide. As a result, the first circuit layer 120 is formed on the lower surface of the first conductive foil 100 as shown in FIG. 4.

Next, referring to FIGS. 3 and 5, a support plate that physically supports and electrically insulates a substrate on a surface of the first conductive foil 100 on which the first circuit layer 120 is formed ( 200 is stacked (S20).

The support plate 200 includes an insulating layer 210 in order to electrically insulate, and has a structure in which the insulating layer 210 and the second conductive foil 220 are laminated, and a thermosetting resin on a base material such as glass fiber. Prepreg Coated Copper (PCC), which is coated with a conductive material copper, may be generally used, as a prepreg cured in a semi-cured state after impregnation.

The lamination process may be performed by stacking the prepreg, the conductive foil, etc. according to a design specification, and applying heat and pressure to bond the prepreg and the conductive foil.

When the supporting plate 200 has a structure in which the insulating layer 210 and the second conductive foil 220 are stacked, the second conductive foil 220 may be further formed when a multilayer printed circuit board having a multilayered circuit layer is manufactured. It can be used to form a circuit layer and can be removed as needed when manufacturing a single layer printed circuit board.

Next, referring to FIGS. 3 and 6, a first bump 300 for flip chip bonding a semiconductor chip to the other surface of the first conductive foil 100 is formed (S30). The process of forming the first bumps 300 may be performed by coating the photosensitive film 310 on the surface of the first conductive foil 100 on which the bumps are to be formed, as in the case of forming the first circuit layer 120 described above. It may be carried out through a lithography process and an etching process. Specifically, (a) laminating the photosensitive film 310 on the other surface of the first conductive foil (100); (b) exposing and developing a photosensitive film pattern corresponding to the first bump 300 pattern on the photosensitive film 310; (c) forming the first bumps 300 by etching; And (d) removing the residual photosensitive film pattern sequentially. In this case, lamination, exposure and development, etching, and peeling process may be applied in the same manner as in the process of forming the first circuit layer 120 described above.

Next, referring to FIGS. 3 and 7, a protective layer 400 is formed to protect the exposed first circuit layer 120 and to prevent solder delamination (S40). The formation of the protective layer 400 is performed by printing a photo solder resist (PSR), which is a kind of invariant ink having durability under a physicochemical environment. However, as described above, since the first circuit layer 120 is formed in the dielectric and may be protected through final surface treatment, the formation of the protective layer 400 may be omitted in some cases.

Next, referring to FIGS. 3 and 8, an upper surface of the first bump 300 prevents oxidation of a metal such as copper and improves electrical conductivity and wear resistance, heat resistance, corrosion resistance, and the like. ) Is formed (S50). The plating layer 500 may be formed by any one selected from gold, silver, tin, and lead, and may be performed by an electroless and electrolytic plating method. In this case, electroless electroplating refers to coating metal ions using chemical oxidation / reduction reactions without receiving electrical energy, also called chemical plating or self-catalytic plating, and electroplating means plating using electroprecipitation. do. Electroless plating and electrolytic plating are plating using both of these electroless plating and electrolytic plating.

Next, referring to FIGS. 3 and 1, a second bump 600 for mechanically / electrically connecting with another printed circuit board is formed (S60). In order to form the second bump 600, the support plate 200 is processed to the hole 610 at a predetermined position corresponding to the first circuit layer 120, and then the second bump 600 is drilled into the hole 610. It is formed on the lower surface of the first circuit layer 120 exposed by. In this case, the hole 610 may be processed by a mechanical drilling method, a plasma etching method, a laser method, or the like, and the second bump 600 may be formed by filling a conductive paste in the hole 610. have.

Since the second bump 600 is formed for the purpose of mechanical / electrical connection with another printed circuit board, the second bump 600 may not necessarily be involved in the manufacturing process of the single-layer printed circuit board.

According to another embodiment of the present invention, a printed circuit board in which the flip chip bonding bumps 300 are integrally implemented may be configured in a multilayer, and FIG. 9 illustrates a process of manufacturing the multilayer printed circuit board in a simplified process. Indicates.

Meanwhile, in the process of manufacturing the multilayer printed circuit board, the above-described process of forming the first circuit layer 120, the first bump 300, and the protective layer 400 may be applied in the same manner. It will be described with a focus on the process of forming an electrical connection between the circuit layers consisting of.

Basically, in the manufacture of a multilayer printed circuit board, a second circuit formed on the second conductive foil 220 is formed by a structure in which the supporting plate 200 is laminated with the second conductive foil 220 together with the insulating layer 210. The first circuit layer 120 formed on the layer 700 and the first conductive foil 100 is electrically connected to each other using the plating layer 800.

First, a hole serving as an electrical connection path between circuit layers is formed at a predetermined lower portion of the support plate 200. Such a hole is generally referred to as a via hole 900. The bottom surface of the first circuit layer 120 is formed by forming blind via holes selectively penetrated only through the support plate 200 through laser processing. It is possible to expose to the outside. Next, the lower surface of the first circuit layer 120 exposed to the outside, integrally with respect to the side surface of the via hole 900 and the lower surface of the second conductive foil 220, and on the upper surface of the first conductive foil 100, respectively The plating layer 800 is formed. The plating layer 800 of the upper surface of the substrate is patterned integrally with the first bump 300 in a subsequent process, and the plating layer 800 of the lower surface of the substrate is formed of the first circuit layer 120 and the second circuit layer formed in the subsequent process ( 700 is electrically connected. Plating may use a conductive material including copper, and the plating layer 800 may be formed using an electroless and electrolytic plating method. Next, the photosensitive film 310 such as a dry film is laminated on the upper surface of the first conductive foil 100 and the lower surface of the second conductive foil 220 having the plating layer 800 formed thereon. In this case, the inside of the via hole 900 is sealed by the photosensitive film 310 laminated on the lower surface of the second conductive foil 220. Next, a photosensitive film pattern corresponding to the first bump 300 pattern may be formed on the photosensitive film 310 coated on the upper surface side of the first conductive foil 100, and the lower surface side of the second conductive foil 220. The photosensitive film 310 positioned at is formed by exposing and developing a photosensitive film pattern corresponding to the second circuit layer 700, respectively. Next, a pattern of the first bump 300 and the second circuit layer 700 is formed through an etching process. In this case, the pattern processing for the first bump 300 and the second circuit layer 700 formed by the etching process is also performed for the plating layer 800. Next, the residual photosensitive film patterns are peeled off using sodium hydroxide or potassium hydroxide, thereby manufacturing a multilayer printed circuit board in which the flip chip bonding bumps 300 are integrally formed.

In the embodiment of FIG. 9, process time and cost may be reduced by performing pattern processing on the second circuit layer 700 simultaneously with the process of forming the first bump 300. However, the embodiment is intended to pattern the second circuit layer 700 using a lamination coating process accompanying the first bump 300 forming process, but the pattern for the second circuit layer 700 The process of forming the via hole 900 and the plating layer 800 may be separated by a separate process, and the formation of the plating layer 800 formed on the first bump 300 may be performed separately.

The above description relates to specific embodiments of the present invention. The above embodiments according to the present invention are not to be understood as limiting the scope of the present invention or the matter disclosed for the purpose of description, and those skilled in the art without departing from the spirit of the present invention various changes and modifications It should be understood that this is possible. Accordingly, all such modifications and variations can be understood as fall within the scope of the invention as set forth in the claims or their equivalents.

100: first conductive foil 110: photosensitive film
120: first circuit layer 200: support plate
210: insulating layer 220: second conductive foil
300: first bump 310: photosensitive film
400: protective layer 500: plating layer
600: second bump 610: hole
700: second circuit layer 800: plating layer
900: via hole

Claims (22)

Processing one surface of the first conductive foil into a first circuit layer;
Stacking a support plate on the first circuit layer; And
And processing a first bump for chip bonding on the other surface of the first conductive foil. The method of claim 1, wherein the processing of the first bump for chip bonding comprises:
(a) laminating a photosensitive film on the first conductive foil;
(b) exposing and developing a photosensitive film pattern corresponding to the first bump pattern on the photosensitive film;
(c) forming the first bump by etching; And
(d) removing the residual photosensitive film pattern. The method of claim 1, further comprising printing a protective layer over the first circuit layer. The method of claim 3, wherein the protective layer is a photo solder resist (PSR). The method of claim 1, further comprising plating the first bump for chip bonding. 6. The method of claim 5, wherein the material used for plating is any one selected from gold, silver, tin, and lead. The method of claim 5, wherein the plating is performed by electroless and electrolytic plating. The method of claim 1, further comprising forming a second bump for electrical connection with another printed board, wherein the second bump is electrically connected with the first circuit layer and is exposed under the support plate. Printed circuit board manufacturing method characterized in that. The method of claim 1, wherein the support plate has a structure in which an insulating layer and a second conductive foil are stacked, and the insulating layer is bonded to the first circuit layer, and the second conductive foil further comprises a step of processing a second circuit layer. Printed circuit board manufacturing method characterized in that. The method of claim 9, wherein the insulating layer is a prepreg sheet in a semi-cured state. The method of claim 9, wherein processing the second circuit layer comprises:
(a) forming a via hole in the support plate to a first circuit layer exposed surface in a predetermined portion;
(b) forming a plating layer for electrical connection between the second circuit layer and the first circuit layer;
(c) forming a photosensitive film under the plating layer;
(d) exposing and developing the photosensitive film pattern corresponding to the second circuit layer pattern on the photosensitive film formed on the plating layer, respectively;
(e) etching to form the second circuit layer pattern; And
(f) a method of manufacturing a printed circuit board, comprising the step of removing the residual photosensitive film pattern. 12. The method of claim 9 or 11, wherein the processing of the second circuit layer is performed at the same time as the processing of the first bump. 12. The method of claim 11, wherein in the step (b) to form a plating layer on the upper surface of the first conductive foil, in accordance with the step of processing the second circuit layer to integrally pattern the first bump formed with a plating layer on the upper surface Printed circuit board manufacturing method characterized in that. A first circuit layer formed by processing one surface of the first conductive foil; A support plate laminated on the first circuit layer; And a first bump for flip chip bonding formed by processing the other surface of the first conductive foil. The printed circuit board of claim 14, wherein the first bumps have a columnar shape. The printed circuit board of claim 14, further comprising a protective layer printed on the first circuit layer. The printed circuit board of claim 16, wherein the protective layer is a photo solder resist (PSR). The printed circuit board of claim 14, further comprising a plating layer formed on the first bumps. 19. The printed circuit board of claim 18, wherein the plating layer is any one selected from gold, silver, tin, and lead. 15. The method of claim 14, further comprising a second bump for electrical connection with another printed board, the second bump being electrically connected with the first circuit layer and being exposed under the support plate. Circuit board. 15. The printing method according to claim 14, wherein the supporting plate has a structure in which an insulating layer and a second conductive foil are stacked, and an insulating layer is bonded to the first circuit layer, and a second circuit layer is formed on the second conductive foil. Circuit board. 22. The printed circuit board of claim 21, wherein the insulating layer is a prepreg sheet in a semi-cured state.

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