KR100601476B1 - Packaging substrate using metal core and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a package substrate and a method for manufacturing the thin plate build-up circuit layer that can be implemented by forming a multilayer circuit layer by a build-up method on both sides using a metal core as an inner layer core. .

Metal Core, Package Substrate, Copper Plating, Conductive Paste

Description

Package substrate using metal core and manufacturing method thereof             

1 is a cross-sectional view showing the configuration of a conventional BGA package,

2 is a process chart showing a manufacturing process of a package substrate by a conventional build-up method,

3 is a cross-sectional view of a package substrate according to the present invention;

4 is a process chart showing a manufacturing method of a package substrate according to one embodiment of the present invention,

5 is a flowchart illustrating a method of manufacturing a package substrate according to another exemplary embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings *

100, 200: metal core 110, 240: circuit layer

120 and 210: via hole 130 and 230: etching resist pattern

140, 220: oxide layer 150: conductive paste

160: copper foil layer 170, 260: blind via hole

225: seed layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package substrate and a method of manufacturing the same, and more particularly, to provide excellent heat dissipation effect during chip mounting, to reduce the thickness of the inner layer, and to shorten the interlayer connection of the substrate to reduce inductance noise The present invention relates to a package substrate using a metal core that can be reduced as a metal core, and a method of manufacturing the same.

As electronic products become smaller and thinner, thinner, denser, more compact, and smaller in size, more and more, multilayer printed circuit boards are also undergoing fine patterns, miniaturization, and packaging. Accordingly, in order to increase the micropattern formation, reliability, and design density of multilayer printed circuit boards, there is a tendency to change the structure of the multilayer structure of the circuit together with the change of raw materials, and the parts are also SMT (Dual In-Line Package) type. As the surface mount technology type is changed, the mounting density is also increasing. In addition to the portableization of electronic devices, high functionalization, the Internet, moving pictures, and high-capacity data transmission and reception make the design of printed circuit boards complicated and require high-level technology.

The printed circuit board includes a single-sided PCB in which wiring is formed only on one side of the insulated substrate, a double-sided PCB in which wiring is formed on both sides, and an MLB (Multi Layered Board) that is wired in multiple layers. In the past, single-sided PCBs were used because of simple components and simple circuit patterns. However, in recent years, due to increased complexity of circuits and increased demand for high-density and miniaturized circuits, it is common to use double-sided PCBs or MLBs. The present invention relates to a process for producing MLB among them.

The MLB is an additional wiring layer formed to enlarge the wiring area. Specifically, MLB is divided into an inner layer and an outer layer, and a four-layer MLB (two inner layers and two outer layers) having a thin core (T / C) as a material of the inner layer and pre-gluing the outer layer and the inner layer with a preplex. Floor). That is, the multilayer printed circuit board has at least four layers. As the complexity of the circuit increases, it may be composed of six, eight, and ten or more layers.

A power circuit, a ground circuit, a signal circuit, and the like are formed in the inner layer, and a preplex is sandwiched between the inner layer and the outer layer or between the outer layers to insulate and bond. At this time, the wiring of each layer is connected using a via hole (conducting hole).

MLB has a great advantage that it can significantly increase the wiring density, but there is a difficulty that the manufacturing process is complicated. In particular, since the inner layer is not deformable when the process is completed according to the conventional build-up method, if there is an error in the inner layer, all the finished products become defective. Many inspection devices have been developed and used to prevent such errors in advance.

Meanwhile, a configuration diagram of the BGA package will be described in detail with reference to FIG. 1.

As shown in FIG. 1, the chip pad 3 is formed near the center of the active surface of the chip 1, and an adhesive 7 is applied to the non-active surface, and the chip 1 is formed through the adhesive 7. ) And the substrate 2 are bonded to each other.

A substrate pad 9 is formed on an upper surface of the substrate 2, and a plurality of solder pads 8 are formed on a lower surface thereof, and photosolder resistors are applied to the entire lower surface of the substrate except for the solder pads 8. A plurality of solder balls 5 are attached to the substrate 2 through (8).

In addition, a bonding wire 4 is bonded between the chip pad 3 and the substrate pad 9 to electrically connect the chip 1 and the substrate 2 to each other. A molding resin 6 is formed to surround 1) and the bonding wire 4 and protect them from the external environment.

A ground and heat path via 10 and a ground and signal via 11 are provided for providing electrical connection between the top and bottom surfaces of the substrate 2.

Hereinafter, a substrate used in a BGA package will be described in detail with a manufacturing process formed by a conventional build-up method with reference to FIG. 2.

Here, the build-up method refers to a manufacturing method of forming an inner layer on which a circuit pattern is formed, and additionally stacking outer layers one by one.

First, as shown in FIG. 2A, a copper clad laminate (CCL; Copper Clad Laminate) 21 having a thin copper foil 22 formed on both surfaces thereof is provided through an insulating layer 23.

Here, the copper-clad laminate 21 is a thin plate coated with a thin copper layer on an insulating layer, which is generally a printed circuit board, and is made of glass / epoxy copper foil laminate, heat-resisting copper foil laminate, and paper / phenolic copper laminate according to its purpose. There are many kinds of high frequency copper clad laminates, flexible copper clad laminates (polyimide films) and composite copper clad laminates, but glass / epoxy copper clad laminates are mainly used for double-sided PCBs and multilayer PCBs.

Glass / epoxy copper clad laminates are made of copper foil and reinforcing substrates that have impregnated epoxy resin (a combination of resin and hardener) into glass fibers. Glass / epoxy copper clad laminates are classified according to reinforcement materials. Generally, grades according to reinforcement materials and heat resistance are determined by standards set by the National Electrical Manufacturers Association (NEMA), such as FR-1 to FR-5. have. Among these grades, FR-4 is most commonly used, but in recent years, the demand for FR-5, which has improved the Tg (glass transition temperature) characteristics of resins, has also increased.

Subsequently, as shown in FIG. 2B, via holes 24 for interlayer connection are formed in the copper clad laminate 21 by drilling.

As described above, after forming the via holes 24 in the copper-clad laminated disc 21, as shown in FIG. 2C, the electroless copper plating and the electrolytic copper plating are performed on the copper foil layer and the via holes, and thus the copper plating layer 25 is formed. To form.

Here, electroless copper plating is performed first and then electrolytic copper plating is performed because electrolytic copper plating that requires electricity cannot be performed on the insulating layer. That is, in order to form the electroconductive film required for electrolytic copper plating, electroless copper plating is thinly performed as the pretreatment. Since electroless copper plating has a disadvantage in that it is difficult to process and economical, it is preferable to form the conductive portion of the circuit pattern by electrolytic copper plating.

After the electroless and electrolytic copper plating is performed as described above, as shown in FIG. 2D, paste is applied to the inner region of the via hole to protect the electroless and electrolytic copper plating layer formed on the inner wall of the via hole 24. Fill in (26).

Here, the paste 26 generally uses an insulating ink material, but a conductive paste may also be used depending on the purpose of the printed circuit board. The conductive paste is obtained by mixing a metal such as Cu, Ag, Au, Sn, Pb as a main component alone or in an alloy form with an organic adhesive. However, this paste filling process may be omitted depending on the purpose of producing MLB.

As described above, after the paste is filled in the inner region of the via hole, an etching resist pattern 27 for forming a circuit pattern of the inner layer circuit is formed, as shown in FIG. 2E.

In order to form the etching resist pattern 27, the circuit pattern printed on the artwork film must be transferred onto the substrate. There are various methods of transferring, but the most commonly used method is a method of transferring a circuit pattern printed on an artwork film by ultraviolet light to a dry film using a photosensitive dry film. Recently, LPR (Liquid Photo Resist) is used instead of dry film.

The dry film or LPR to which the circuit pattern is transferred serves as the etching resist 27, and when the substrate is immersed in the etching solution, as shown in FIG. 2F, the copper foil layer in the region where the etching resist pattern 27 is not formed. 25 is removed to form a predetermined circuit pattern.

After the circuit pattern is formed, the appearance of the circuit is inspected by AOI (Automatic Optical Inspection) or the like to check whether the inner layer circuit is properly formed thereon, and the surface treatment such as black oxide treatment is performed.

AOI (Automatic Optical Inspection) is a device that automatically inspects the appearance of the PCB. The device automatically checks the appearance of the substrate using image sensors and computer pattern recognition technology. The pattern information of the circuit to be inspected is read by the image sensor and compared with the reference data to read the defect.

Using AOI inspection, it is possible to inspect the minimum of the annular ring of the land (the part where the component of the PCB will be mounted) and the ground state of the power supply. In addition, the width of the wiring pattern can be measured and missing holes can be checked. It is not possible to check the condition inside the hall.

A blackening process is a process performed to strengthen adhesive force and heat resistance, before bonding the inner layer in which the wiring pattern was formed with an outer layer.

After the circuit pattern is formed as described above, as shown in FIG. 2G, both sides of the substrate are laminated using Resin Coated Copper (RCC) or a coreless material.

In this invention, the method to form using RCC is demonstrated.

Here, the RCC is a substrate in which the copper foil layer 29 is formed only on one side of the resin layer 28, and the resin layer 28 serves as an insulator between the circuit layers.

Thereafter, as illustrated in FIG. 2H, the blind via hole 30 serving as a folding connection between the inner layer and the outer layer is processed.

In this case, the blind via hole 30 may be mechanical drilling, but it is preferable to use YAG (Yttrium Aluminum Garnet) laser or CO2 laser because it requires more precise processing than when processing the through hole. The YAG laser is a laser capable of processing both a copper foil layer and an insulating layer, and the CO2 laser is a laser capable of processing only an insulating layer.

After forming the blind via hole as described above, as illustrated in FIG. 2I, the outer layer 31 is laminated by a plating process.

Thereafter, as shown in FIG. 2J, the circuit pattern is formed on the outer layer 31 using the same method as the circuit pattern forming method of the inner layer described above. Then, circuit inspection and surface treatment are performed again, similarly after forming an inner layer circuit pattern.

Thereafter, as shown in FIG. 2K, lamination is carried out using RCC or coreless material for additional outer layer deposition on both sides of the substrate.

In this specification, a method of forming using RCC will be described.

Here, the RCC also includes a resin layer 32 and a copper foil layer 33 on one side, and the resin layer 32 serves as an insulator from other circuit layers.

After forming the RCC layer as described above, as shown in FIG. 2L, the blind via hole 34 for the connection between the original outer layer and the additional outer layer is processed by laser drilling as described above.

Thereafter, as shown in FIG. 2M, an additional outer layer 35 is laminated by a plating process.

After the additional outer layer 35 is formed as described above, as illustrated in FIG. 2N, a bump is formed to die attach the semiconductor chip by performing a predetermined circuit pattern process on the added outer layer 35. To form an area 36.

Thereafter, as shown in FIG. 20, a die attach bump 37 composed of solder paste for attaching the semiconductor element is finally formed, thereby forming a six-layer package substrate.

In general, in the BGA package substrate process, BVHs have a staggered structure in the stacking process, which entails a problem in that the connection lines of the circuits are lengthened and high density circuit freedom cannot be realized.

In addition, the conventional BGA package substrate manufactured by such a process uses a thick copper-clad laminate, which is a laminate plate thinly coated with an insulating layer, thereby increasing the thickness of the substrate and increasing the inductance noise. There is this. This not only makes it impossible to cope with high density and high speed, but also has a problem of low thermal conductivity and low heat dissipation effect when the chip is mounted.

The present invention provides a package substrate using a metal core as an inner layer core and a method of manufacturing the same, without using a thick copper clad laminate, which is a laminated plate coated with a thin copper layer on an insulating layer. There is.

According to an aspect of the present invention, there is provided a package substrate including: a metal core layer having recesses and via holes corresponding to inner circuit patterns on or underneath; An oxide layer surrounding the metal core layer to a predetermined height and providing electrical insulation of the metal core layer; An inner circuit layer forming a circuit by filling a conductive material in a recess in the via hole and the inner circuit pattern of the oxide layer; And an outer circuit layer stacked on the inner circuit layer.

In addition, the package substrate according to the present invention, a metal core layer having a via hole for providing electrical connection of the upper and lower layers; An oxide layer surrounding the metal core layer to a predetermined height and providing electrical insulation of the metal core layer; An inner circuit layer having conductive layers stacked on the oxide layer according to an inner circuit pattern to form an inner circuit; And an outer circuit layer formed on the inner circuit layer.

In addition, the method for manufacturing a package substrate according to the present invention comprises: forming a via hole (IVH) for inter-layer connection in a metal core layer; Etching the surface of the metal core layer to form an inner circuit pattern; Oxidizing a surface of the metal core layer on which the inner circuit pattern is formed to form an oxide layer; Forming an inner circuit layer by filling a conductive material in the recess of the oxide layer corresponding to the via hole and the inner circuit pattern; And forming a multilayer outer circuit layer by a build-up method on the inner circuit pattern.

In addition, the method for manufacturing a package substrate according to the present invention comprises the steps of: forming via holes for contact between both layers of the metal core; Oxidizing a surface of the metal core layer to form an oxide layer; Forming an inner circuit layer on the oxide layer by a lithography process; And forming an outer circuit layer on the inner circuit layer by a build-up method.

Hereinafter, a package substrate using a metal core according to the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings.

First, the configuration of a package substrate according to the present invention will be described with reference to FIG. 3.

As shown in FIG. 3, the package substrate according to the present invention includes a metal core layer 100, an oxide layer 140, a conductive paste layer 150, and an outer circuit layer 110 formed in a build-up manner. .

The metal core layer 100 serves as a support for the outer circuit layer 110 formed by a build-up method on both sides as an inner core and a circuit line connecting both circuits.

That is, the recessed portion according to the circuit pattern is formed on the upper or lower portion of the metal core layer 100, and the via hole 120 (IVH: Interstitial Via Hole) for connecting the two layers is formed in the metal core layer. Here, the metal core layer 100 is composed of any one of aluminum (Al), magnesium (Mg), titanium (Ti), zinc (Zn), tantalum (Ta) having a thickness of 0.2mm to 1.0mm.

The aluminum (Al) is a good conductor of electricity, the resistivity of which corresponds to about 1.6 times that of copper, and has a high thermal conductivity, and thus has excellent heat dissipation effect during chip mounting. In addition, as a typical light metal, the strength per weight is high, thereby reducing the weight and thickness of the entire printed circuit board.

The oxide layer 140 is formed by oxidizing all surfaces of the metal core layer.

The conductive paste layer 150 is formed by filling the conductive paste in the recessed portion corresponding to the via hole and the circuit pattern formed in the metal core layer, and forms an inner layer circuit according to the circuit pattern. As the paste, an insulating ink material is generally used, but in the present invention, a conductive paste is used.

The outer circuit layer 110 is a multilayer circuit layer formed on both sides of the metal core layer 100 by a build-up method, and the circuit layers on both sides through the via holes 120 of the metal core layer. Is electrically connected. Here, the outer circuit layer 110 formed by the build-up method is not formed by the build-up method using a thick core layer in the form of a conventional copper clad laminate, but builds using the metal core 100 as the core layer. Raised coreless circuitry layer.

As described above, a recess is formed along the circuit pattern in the metal core 100 to implement a circuit, and the outer circuit layer 110 is stacked on both sides of the metal core layer 100 in a build-up manner to increase density and speed. And a package substrate that can cope with miniaturization and has a large heat dissipation effect.

Hereinafter, a package substrate manufacturing process of the build-up method according to the present invention will be described in detail with reference to FIG. 4.

First, as shown in FIG. 4A, a metal core 100 is provided. Here, the metal core 100 is composed of any one of aluminum (Al), magnesium (Mg), titanium (Ti), zinc (Zn), tantalum (Ta) having a thickness of 0.2mm to 1.0mm.

Thereafter, as shown in FIG. 4B, a via hole 120 (IVH: Interstitial Via Hole) for connecting between the two layers is formed in the metal core 100 by drilling.

After forming the via hole as described above, as shown in FIG. 4C, an etching resist pattern 130 for forming a circuit pattern of the inner layer circuit is formed.

In order to form the etching resist pattern 130, a circuit pattern printed on an artwork film must be transferred onto a substrate. The most commonly used method is a circuit printed on an artwork film by ultraviolet light using a photosensitive dry film. The pattern is transferred to a dry film.

The dry film to which the circuit pattern is transferred serves as the etching resist 130, and when the substrate is immersed in the etching solution, as shown in FIG. 4D, the metal core of the region where the etching resist pattern 130 is not formed is removed. Thus, a predetermined circuit pattern is formed.

As described above, as illustrated in FIG. 4E, all surfaces of the metal core layer on which the circuit pattern is formed are oxidized to form the oxide layer 140. The oxide layer 140 enables circuit formation thereon.

Thereafter, as shown in FIG. 4F, the conductive paste 150 is filled in the oxide layer 140 of the recessed portion formed according to the via hole 120 and the circuit pattern. Here, the filled paste 150 forms a circuit according to the circuit pattern. Then, as shown in Figure 4g, through the buffing (buffing) to make the inner circuit pattern uniform.

Then, as shown in Figure 4h, by forming a multi-layer outer circuit layer 110 by a build-up method, to complete a package substrate using a metal core. Here, the blind via hole (BLV) 170 of the multilayer circuit layer 110 is formed as a stack via.

In another embodiment, a package substrate manufacturing process according to the present invention will be described in detail with reference to FIG. 5.

First, as shown in FIG. 5A, a metal core 200 is provided. Here, the metal core 200 is composed of any one of aluminum (Al), magnesium (Mg), titanium (Ti), zinc (Zn), tantalum (Ta) having a thickness of 0.2mm to 1.0mm.

Thereafter, as shown in FIG. 5B, a via hole 210 (IVH: Interstitial Via Hole) for connecting between the two layers is formed in the metal core 200 by drilling.

After the via hole 210 is formed as described above, the entire surface of the metal core 200 is anodized as shown in FIG. 5C to the surface of the metal core 200. The oxide film layer 220 is formed to enable the formation of the circuit layer.

Thereafter, as shown in FIG. 5D, a thin seed layer 225 is formed of chemical copper plating. As shown in FIG. 5E, an etching resist pattern 230 for forming a circuit pattern of the inner layer circuit is formed.

In order to form the etching resist pattern 230, a circuit pattern printed on an artwork film must be transferred onto a substrate. The most commonly used method is a circuit printed on an artwork film by ultraviolet light using a photosensitive dry film. The pattern is transferred to a dry film.

The dry film to which the circuit pattern is transferred serves as the etching resist 230, and when the substrate is immersed in the etching liquid, as shown in FIG. 5F, the seed layer 225 in the region where the etching resist pattern 230 is not formed. ) Is removed to form a predetermined circuit pattern. The circuit layer 240 is formed by fill plating in the region where the seed layer 225 is removed, and uniformly forms an inner circuit pattern through a buffing operation.

Thereafter, the resist pattern 230 is removed to form a multilayered outer circuit layer 250 by a build-up method, as shown in FIG. 5G, thereby completing a build-up multilayer printed circuit board using a metal core. do. Here, the blind via hole (BLV) 260 of the multilayer outer circuit layer 250 is formed as a stack via.

As described above, according to the BGA package substrate and the manufacturing method using the metal core according to the present invention, by removing the existing thick inner core portion, and the metal core layer to replace the role, the high speed, high density of the BGA package substrate And not only improve thermal conductivity, but also increase the mechanical strength of chip-set products.

In addition, the present invention provides an effect that the time and cost can be reduced by removing the existing thick inner core portion and applying the existing build-up method directly to the metal core layer.

Herein, the present invention described above has been described with reference to preferred embodiments, but those skilled in the art can variously modify the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be appreciated that this can be changed.

Claims (8)

A metal core layer having a depression and a via hole corresponding to an inner circuit pattern at an upper portion or a lower portion thereof; An oxide layer surrounding the metal core layer to a predetermined height and providing electrical insulation of the metal core layer; An inner circuit layer forming a circuit by filling a conductive material in a recess in the via hole and the inner circuit pattern of the oxide layer; And And an outer circuit layer stacked on the inner circuit layer. The oxide layer and the inner circuit layer is a package substrate using a metal core, characterized in that formed in the same height. delete The method of claim 1, The metal core is a package substrate using a metal core, characterized in that having a thickness of 0.2mm to 1.0mm. The method of claim 1, The metal core is a package substrate using a metal core, characterized in that composed of any one of aluminum (Al), magnesium (Mg), titanium (Ti), zinc (Zn), tantalum (Ta). Forming an interstitial via hole (IVH) for interconnection between the two layers in the metal core layer; Etching the surface of the metal core layer to form an inner circuit pattern; Oxidizing a surface of the metal core layer on which the inner circuit pattern is formed to form an oxide layer; Forming an inner circuit layer by filling a conductive material in the recess of the oxide layer corresponding to the via hole and the inner circuit pattern; And And forming a multilayer outer circuit layer by a build-up method on the inner circuit pattern. The method of claim 5, The conductive material filled in the depression of the oxide layer is a manufacturing method of a package substrate using a metal core, characterized in that the conductive paste. Forming via holes and interlayer recesses for interlayer interconnections in the metal core; Oxidizing a surface of the metal core layer to form an oxide layer; Filling an conductive layer over the oxide layer to form an inner circuit layer; And A method of manufacturing a package substrate using a metal core comprising the step of forming an outer circuit layer on the inner circuit layer by a build-up method. The method of claim 7, wherein The conductive material filled in the depression of the oxide layer is a manufacturing method of a package substrate using a metal core, characterized in that the conductive paste.

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