JP4609074B2 - Wiring board and method of manufacturing wiring board - Google Patents

Description

  The present invention relates to a wiring board and a method for manufacturing the wiring board.

  The development of the information society in recent years has been remarkable, and consumer devices have been reduced in size, weight, performance, and functionality, such as personal computers and mobile phones. Industrial equipment includes wireless base stations, optical communication devices, and servers. In addition, there is a demand for improvement in functions in the same way regardless of whether it is large or small, such as routers and other network-related devices. In addition, with the increase in the amount of information transmitted, the frequency of signals handled tends to increase year by year, and high-speed processing and high-speed transmission technology are being developed. With regard to mounting relations, high functionality has progressed mainly in LSI, and development of CPU, DSP, various memories, etc., system-on-chip (SoC), system-in-package (SiP), etc. corresponding to equipment has been actively conducted. The function of semiconductor chips is improving year by year, and miniaturization and high integration are progressing. For this reason, wiring boards (semiconductor chip mounting substrates, motherboards) have also responded to higher frequencies, higher density wiring, and higher functionality.

  FIG. 1 shows a cross-sectional shape of a conventional wiring board. The minimum angle is α, the maximum wiring width is M, the minimum wiring width is m, the top width is a, the bottom width is b, and the bottom to the maximum wiring width is shown. When the height is y and the wiring height from the bottom to the top is t, a trapezoid such as b / M = 1 and y / t = 0 (FIG. 1A), a / M = 1, y It can be classified into an inverted trapezoidal shape such as / t = 1 (FIG. 1B) and a rectangular shape such as m / M = 1 (FIG. 1C). Trapezoids are often formed by the subtractive method, and inverted trapezoids or rectangles are often formed by the additive method. Among them, there are many patent applications in which the cross-sectional shape of the wiring is rectangular, and examples thereof include Patent Document 1, Patent Document 2, and Patent Document 3.

JP-A-5-243217 JP 2000-196224 A JP 2000-307218 A

  In any of these wiring shapes (trapezoid, inverted trapezoid, rectangle), there is always a portion where the minimum angle α is a right angle or an acute angle as shown in FIG. With the increase in wiring density, particularly when L / S = 20 μm / 20 μm or less, that is, when M is 20 μm or less, there is a problem that the electric corrosion concentration is reduced due to the concentration of the electric field at a right angle or acute angle portion of the wiring. I understand that. The object of the present invention is to improve the above-described problems of the prior art, and the object is to achieve L / S = 20 μm / 20 μm or less, that is, M becomes 20 μm or less as the wiring density becomes higher. Even in such a case, it is to provide a wiring board (motherboard, semiconductor chip mounting substrate) having good electric corrosion resistance and a manufacturing method thereof.

In order to achieve the above object, the present invention is configured as follows.
(1) In a wiring board having an insulating layer and wiring thereon, the maximum wiring width of the wiring is M, the bottom width of the wiring is b, the height from the bottom of the wiring to the maximum wiring width is y, and from the bottom of the wiring A wiring board having a wiring satisfying 0.1 ≦ b / M <1 and 0.1 ≦ y / t ≦ 0.9, where t is a wiring height to the top.
(2) The wiring board according to item (1), wherein M is M ≦ 20 μm.
(3) The wiring board according to item (1) or (2), wherein a shape of a top portion of the wiring is an arc shape.
(4) In the step of forming the insulating layer and the method of manufacturing the wiring board on which the wiring is formed, the maximum wiring width of the wiring is M, the bottom width of the wiring is b, and the height from the bottom of the wiring to the maximum wiring width is high. When the height is y and the wiring height from the bottom to the top of the wiring is t, a wiring that satisfies 0.1 ≦ b / M <1 and 0.1 ≦ y / t ≦ 0.9 is formed. A method for manufacturing a wiring board.
(5) The method for manufacturing a wiring board according to item (4), wherein M is M ≦ 20 μm.
(6) The method for manufacturing a wiring board according to item (4) or (5), wherein a shape of a top portion of the wiring is an arc shape.
(7) The method for manufacturing a wiring board according to any one of Items (4) to (6), wherein the step of forming the wiring is a step of forming the wiring using a positive resist.
(8) The method for manufacturing a wiring board according to any one of Items (4) to (7), wherein the step of forming the wiring is a step of forming the wiring by plating.

  According to the present invention, even when L / S = 20 μm / 20 μm or less, that is, when M is 20 μm or less, it is possible to provide a wiring board (motherboard, semiconductor chip mounting substrate) having good electric corrosion resistance and a method for manufacturing them. .

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, although a semiconductor chip mounting substrate is described as an example of the wiring board, it is not particularly limited.

(Cross sectional shape of wiring)
The wiring cross-sectional shape of the wiring board of the present invention is 0 when the maximum wiring width is M, the bottom width is b, the height from the bottom to the maximum wiring width is y, and the wiring height from the bottom to the top is t. It is preferable that 1 ≦ b / M <1 and 0.1 ≦ y / t ≦ 0.9. Further, 0.5 ≦ b / M <1 is more preferable, and 0.2 ≦ y / t ≦ 0.8 is more preferable. When b / M is less than 0.1, the wiring shape is close to an inverted triangle, and the wiring tends to be easily peeled off. Further, as shown in FIG. 2A where y / t is 0.05, when y / t is less than 0.1, the wiring shape is close to a trapezoid, and y / t is 0.95. As shown in FIG. 2B, when y / t is larger than 0.9, the wiring shape becomes close to an inverted trapezoid. In these cases, as shown in FIGS. 2A and 2B, the minimum angle α can be strictly made obtuse, but the substantial angle β can be regarded as an acute angle. Accordingly, the electric field concentrates on such a substantially acute angle portion and the electric corrosion resistance decreases, which is not preferable. Further, when the portion up to t above y is defined as the wiring top portion 119 as shown in FIG. 3A, the top portion is preferably arcuate. In addition, when performing high-density wiring at L / S = 20 μm / 20 μm level, the maximum wiring width M is preferably M ≦ 20 μm. From the viewpoint of economy and efficiency, the wiring is made of copper wiring. It is preferable that

(Semiconductor chip mounting substrate)
In FIG. 4, the cross-sectional schematic diagram of one Example (2 single-sided buildup layers) of the semiconductor chip mounting board | substrate of this invention is shown. Here, an embodiment in which the insulating layer 104 is formed only on one side will be described, but the insulating layer 104 may be formed on both sides as shown in FIG. As shown in FIG. 4, the semiconductor chip mounting substrate of the present invention has a semiconductor chip connection terminal (not shown) and a first interlayer connection terminal 101 on a core substrate 100 which is an insulating layer on the side where the semiconductor chip is mounted. The first wiring 106a including is formed. A second wiring 106 b including a second interlayer connection terminal 103 is formed on the opposite side of the core substrate 100, and the first interlayer connection terminal and the second interlayer connection terminal are connected to the first interlayer connection layer of the core substrate 100. Electrical connection is established via a connection via hole (hereinafter referred to as a first via hole) 102. An insulating layer 104 is formed on the side on which the second wiring is formed on the core substrate 100, and a third wiring 106c including a third interlayer connection terminal is formed on the insulating layer 104, and the second interlayer connection is formed. The terminal and the third interlayer connection terminal are electrically connected through a second interlayer connection blind via hole (hereinafter referred to as a second via hole) 108.

  When a plurality of insulating layers 104 are formed, the same structure is stacked. For example, in the third wiring 106c, the third interlayer connection terminal is connected to the interlayer connection terminal of the next insulating layer 104 and the third interlayer connection. Electrically connected via a blind via hole (hereinafter referred to as a third via hole) 105 for use. On the outermost insulating layer 104, an external connection terminal 107 connected to the mother board is formed. The configuration of the substrate and the arrangement of the connection terminals are not particularly limited, and can be appropriately designed to manufacture a semiconductor chip to be mounted and a target semiconductor package. Further, the semiconductor chip connection terminal and the first interlayer connection terminal can be shared. Furthermore, an insulating coating 109 such as a solder resist can be provided on the outermost insulating layer 104 as necessary.

(Core substrate)
The material of the core substrate 100 that is an insulating material is not particularly limited, and an organic base material, a ceramic base material, a silicon base material, a glass base material, and the like can be used. As the organic substrate, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used. Furthermore, it is more preferable that a thermosetting organic insulating material is a main component. Thermosetting resins include phenol resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, silicone resin, resin synthesized from cyclopentadiene, tris (2-hydroxyethyl) ) Resin containing isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimetallate, furan resin, ketone resin, xylene resin, thermosetting containing condensed polycyclic aromatic Resin, benzocyclobutene resin, etc. can be used. Examples of the thermoplastic resin include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, and liquid crystal polymer. Moreover, what molded these resin so that it might become integral with a glass cloth, a glass nonwoven fabric, etc. may be used.

In consideration of the thermal expansion coefficient and insulation, it is preferable to use ceramic or glass. Among the glass, non-photosensitive glass includes soda lime glass (component example: SiO ₂ 65 to 75%, Al ₂ O ₃ 0.5 to 4%, CaO 5 to 15%, MgO 0.5 to 4%, Na ₂ O 10-20%), borosilicate glass (component example: SiO ₂ 65-80%, B ₂ O ₃ 5-25%, Al ₂ O ₃ 1-5%, CaO 5-8%, MgO 0.5 ˜2%, Na ₂ O 6-14%, K ₂ O 1-6%) and the like. Also, it includes those containing gold ions and silver ions as a photosensitive agent into Li _{2 O-SiO} 2 based crystallized glass as photosensitive glass. The thickness of the core substrate 100 is preferably in the range of 100 to 800 μm from the viewpoint of IVH formation, and more preferably in the range of 150 to 500 μm.

(Insulating layer)
The insulating layer 104 is preferably made of an insulating material. As the insulating material, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used. Furthermore, it is more preferable that a thermosetting organic insulating material is a main component. Thermosetting resins include phenol resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, silicone resin, resin synthesized from cyclopentadiene, tris (2-hydroxyethyl) ) Resin containing isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimetallate, furan resin, ketone resin, xylene resin, thermosetting containing condensed polycyclic aromatic Resin, benzocyclobutene resin, etc. can be used. Examples of the thermoplastic resin include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, and liquid crystal polymer. A filler may be added to the insulating material. Examples of the filler include silica, talc, aluminum hydroxide, aluminum borate, aluminum nitride, and alumina.

  As a method for forming the insulating layer 104, a varnish-like insulating material can be formed by spin coater, comma coater, printing or the like, and then dried and cured. Alternatively, it may be formed in advance in a film shape and bonded to the core substrate 100 by pressing or laminating. Depending on the insulating material, it can be formed by impregnating a glass cloth or non-woven fabric with the material, forming a prepreg, and then bonding. Furthermore, varnish can be apply | coated to metal foil and it can also adhere | attach on the core board | substrate 100 after drying.

(Coefficient of thermal expansion)
Preferably, the thermal expansion coefficient of the semiconductor chip and the thermal expansion coefficient of the core substrate 100 are approximated, and the thermal expansion coefficient of the core substrate 100 and the thermal expansion coefficient of the insulating layer 104 are approximated. Further, when the thermal expansion coefficients of the semiconductor chip, the core substrate 100, and the insulating layer 104 are α1, α2, and α3 (ppm / ° C.), it is more preferable that α1 ≦ α2 ≦ α3. Specifically, the thermal expansion coefficient α2 of the core substrate 100 is preferably 7 to 13 ppm / ° C, and more preferably 9 to 11 ppm / ° C. The thermal expansion coefficient α3 of the insulating layer 104 is preferably 10 to 40 ppm / ° C., more preferably 10 to 20 ppm / ° C.

(Young's modulus)
The Young's modulus of the insulating layer 104 is preferably 1 to 5 GPa from the viewpoint of stress relaxation against thermal stress. The filler in the insulating layer 104 is preferably added by appropriately adjusting the addition amount so that the thermal expansion coefficient of the insulating layer 104 is 10 to 40 ppm / ° C. and the Young's modulus is 1 to 5 GPa.

(Average surface roughness)
The average roughness (Ra) of the surface of the insulating material such as the core substrate 100 and the insulating layer 104 is preferably Ra ≦ 1.0 μm, particularly 0.01 μm ≦ Ra ≦ 1.0 μm. In view of the above, it is more preferable that 0.01 μm ≦ Ra ≦ 0.4 μm. When Ra> 1.0 μm, the width of the formed wiring varies greatly, and the attenuation of the high-speed electrical signal tends to increase. When Ra <0.01 μm, there is a tendency that sufficient peel strength cannot be obtained. Similarly, the average roughness (Ra) of the wiring surface is also preferably Ra ≦ 1.0 μm, and more preferably 0.01 μm ≦ Ra ≦ 0.4 μm. That is, an interface between the core substrate 100 and the first wiring 106a, an interface between the core substrate 100 and the second wiring 106b, an interface between the second wiring 106b and the insulating layer 104, and the insulating layer 104 As for the interface between the first wiring 106c and the third wiring 106c, it is preferable that the unevenness of at least one of the interfaces is Ra ≦ 1.0 μm. In particular, 0.01 μm ≦ Ra ≦ 1.0 μm is preferable, and 0.01 μm ≦ Ra ≦ 0.4 μm is more preferable. The average roughness (Ra) of the surface of the insulating layer and the average roughness (Ra) of the wiring surface are both particularly preferably Ra ≦ 1.0 μm.

(Manufacturing method of semiconductor chip mounting substrate)
The semiconductor chip mounting substrate can be manufactured by a combination of the following manufacturing methods. The order of the manufacturing process is not particularly limited as long as it does not depart from the object of the present invention.

(Wiring formation method)
As a method of forming the wiring, a metal foil is formed on the surface of the core substrate 100 or the insulating layer 104, an etching resist is further formed, and unnecessary portions of the metal foil are removed by etching (subtract method). And forming a wiring by plating only on a necessary portion on the surface of the core substrate 100 or the insulating layer 104 (additive method), and forming a thin metal layer (seed layer) on the surface of the core substrate 100 or the insulating layer 104 Further, there is a method (semi-additive method) in which a plating resist is further formed, and then a necessary wiring is formed by electroplating, and then a thin metal layer is removed by etching. Any method may be used as the method for forming the wiring, but the semi-additive method is more preferable in order to form a fine wiring with M ≦ 20 μm in the wiring shape of the present invention. The etching resist or plating resist used for forming the wiring can be either a positive type or a negative type. However, a positive type resist is preferable because the wiring shape of the present invention can be easily formed.

(Formation of seed layer in semi-additive process)
In the case of wiring formation by the semi-additive method, there are a method of forming a seed layer on the surface of the core substrate 100 or the insulating layer 104, a method of vapor deposition or plating, and a method of bonding a metal foil.

(Formation of seed layer by vapor deposition or plating)
A seed layer can be formed on the surface of the core substrate 100 or the insulating layer 104 by vapor deposition or plating. For example, when a base metal and a thin film copper layer are formed by sputtering as a seed layer, the sputtering apparatus used to form the thin film copper layer is a bipolar sputtering, a three-pole sputtering, a four-pole sputtering, a magnetron sputtering, a mirror. Tron sputtering or the like can be used. A target used for sputtering is sputtered 5 to 50 nm using, for example, a metal such as Cr, Ni, Co, Pd, Zr, Ni / Cr, or Ni / Cu as a base metal in order to ensure adhesion. Thereafter, a seed layer can be formed by sputtering 200 to 500 nm using copper as a target. Alternatively, plated copper can be formed on the surface of the core substrate 100 or the insulating layer 104 by electroless copper plating of 0.5 to 3 μm.

(Method of bonding metal foil)
In the case where the core substrate 100 or the insulating layer 104 has an adhesive function, the seed layer can be formed by bonding metal foils together by pressing or laminating. However, since it is very difficult to directly bond a thin metal layer, there are methods such as a method of thinning a thick metal foil and then thinning it by etching or a method of removing a carrier layer after bonding a metal foil with a carrier. is there. For example, the former has a three-layer copper foil of carrier copper / nickel / thin film copper, the carrier copper is removed with an alkaline etching solution, nickel is removed with a nickel etching solution, and the latter is made of aluminum, copper, insulating resin or the like as a carrier. A peelable copper foil or the like can be used, and a seed layer of 5 μm or less can be formed. Alternatively, a 9 to 18 μm thick copper foil may be attached, and the seed layer may be formed by etching so that the thickness is 5 μm or less.

(Wiring formation by semi-additive method)
A plating resist is formed in a necessary pattern on the seed layer formed by the above-described method, and wiring is formed by electroplating through the seed layer. Thereafter, the plating resist is peeled off, and finally the seed layer is removed by etching or the like to form a wiring.

(Cross sectional shape of plating resist)
The plating resist 118 in the semi-additive method preferably has a trapezoidal or triangular cross-sectional shape after development (the seed layer on the insulating layer 104 is not shown in FIG. 6). When the cross-sectional shape of the plating resist 118 is rectangular, the cross-sectional shape of the wiring is also rectangular as shown in FIG. 6A, and when the cross-sectional shape of the plating resist 118 is an inverted trapezoid, it is shown in FIG. As shown, the cross-sectional shape of the wiring becomes a trapezoidal shape such as b / M = 1 and y / t = 0, both of which are not preferable contrary to the spirit of the present invention. By making the cross-sectional shape of the plating resist 118 trapezoidal or triangular, the cross-sectional shape of the wiring can be 0.1 ≦ b / M <1 and 0.1 ≦ y / t ≦ 1, and further 0.1 ≦ It is possible to satisfy b / M <1 and 0.1 ≦ y / t ≦ 0.9. The plating resist 118 having such a cross-sectional shape may be either a positive type or a negative type, but a positive type resist is preferable because it is easier to form than a negative type.

(Electroplating of wiring)
If only the cross-sectional shape of the plating resist 118 is trapezoidal or triangular, the cross-sectional shape of the wiring is 0.1 ≦ b / M <1 and y / t = 1 depending on the subsequent plating as shown in FIG. 6C. Although such an inverted trapezoidal wiring shape can be formed, this is not preferable because the minimum angle α becomes an acute angle. However, in the case of the semi-additive method, since the wiring is formed by electroplating, the top part of the wiring can be formed in an arc shape by adding a brightener and a smoothing agent as appropriate and adjusting the current density. As shown in FIG. 6D, it is possible to satisfy 0.1 ≦ b / M <1 and 0.1 ≦ y / t ≦ 0.9. Alternatively, soft etching or the like may be performed after forming the wiring so that the top portion of the wiring has an arc shape as shown in FIG. In any case, any of the minimum angles α can be an obtuse angle, which is preferable. What is necessary is just to use what is generally used about the kind of electroplating, Although it does not specifically limit, In order to form wiring, it is preferable to use copper as a plating metal. Therefore, in the wiring board of the present invention, it is preferable that the top portion of the wiring has an arc shape, and the manufacturing method of the wiring board of the present invention includes a wiring forming step of forming the top portion of the wiring in an arc shape. Is preferred.

(Wiring formation by additive method)
In the case of the wiring formation by the additive method, as in the case of the semi-additive method, it is formed by performing plating only on necessary portions on the core substrate 100 or the insulating layer 104. However, the plating used in the additive method is usually not used. Electroplating is used. For example, after depositing an electroless plating catalyst on the core substrate 100, a plating resist 118 is formed on a surface portion where plating is not performed, and the substrate is immersed in an electroless plating solution and not covered with the plating resist 118. Only, the electroless plating is performed to form the wiring. In the case of electroless plating, the flatness is large, and it is somewhat difficult to make the top of the wiring arc-shaped compared to electroplating. Therefore, when the cross-sectional shape of the plating resist 118 is trapezoidal or triangular, an inverted trapezoidal wiring shape such that the wiring cross-sectional shape is 0.1 ≦ b / M <1 and 0.9 <y / t ≦ 1 is easily formed. . Therefore, in order to make the cross-sectional shape of the wiring 0.1 ≦ b / M <1 and 0.1 ≦ y / t ≦ 0.9, soft etching or the like is performed after the wiring is formed, and the top portion of the wiring is made circular. It may be arcuate.

(Wiring arrangement)
The wiring arrangement is not particularly limited, but as shown in FIG. 7 (inner layer wiring, interlayer connection terminals, etc. are omitted), a fan-in type in which external connection terminals are formed inside the semiconductor chip connection terminals, or FIG. A fan-out type in which external connection terminals are formed outside the semiconductor chip connection terminals as shown, or a combination of these may be used. FIG. 9 is a plan view of the fan-in type semiconductor chip mounting substrate, and FIG. 10 is a plan view of the fan-out type semiconductor chip mounting substrate. The shape of the semiconductor chip connection terminal 16 is not particularly limited as long as wire bond connection or flip chip connection is possible. Moreover, wire-bond connection and flip-chip connection are possible for both fan-out and fan-in types. If necessary, a dummy pattern 21 (see FIG. 10) that is not electrically connected to the semiconductor chip may be formed. The shape and arrangement of the dummy pattern are not particularly limited, but it is preferable to arrange the dummy pattern uniformly in the semiconductor mounting region. As a result, voids are less likely to occur when a semiconductor chip is mounted with a die bond adhesive, and reliability can be improved.

(Substrate structure)
The structure of the substrate is not particularly limited. As shown in FIG. 7 or FIG. 8, at least a semiconductor chip connection terminal (wire bond terminal or the like) is mounted on the side where the semiconductor chip is mounted, and the opposite surface is electrically connected to the motherboard. External connection connecting terminals (locations where solder balls or the like are mounted), developed wirings connecting them, interlayer connection terminals, and the like.

(Bahia Hall)
Since the semiconductor chip mounting substrate of the present invention has a plurality of wiring layers, via holes for electrically connecting the wirings of the respective layers can be provided. The via hole can be formed by providing a connection hole in the core substrate 100 or the insulating layer 104 and filling the hole with a conductive paste, plating, or the like. Examples of the hole processing method include mechanical processing such as punching and drilling, laser processing, chemical etching processing using a chemical solution, and dry etching using plasma.

(Desmear)
As the smear removal of the via hole formed by the above-described method, a dry process or a wet process can be used. As the dry treatment, plasma treatment, reverse sputtering treatment, or ion gun treatment can be used. Furthermore, plasma processing includes atmospheric pressure plasma processing, vacuum plasma processing, and RIE processing, which can be selected as necessary. As a gas used for these treatments, nitrogen, oxygen, argon, freon (CF ₄ ), or a mixed gas thereof is preferable. An oxidizing agent such as chromate or permanganate can be used for the wet treatment.

(Interlayer connection)
As a method for interlayer connection, in addition to the above-described method using via holes, a method in which a conductive layer is formed in advance on the insulating layer 104 by a conductive paste or plating, and this insulating layer is stacked on the core substrate 100 by pressing, laminating, or the like. There are also.

(Formation of insulation coating)
An insulating coating can be formed on the external connection terminal side of the semiconductor chip mounting substrate. The pattern can be formed by printing if it is a varnish-like material, but it is preferable to use a photosensitive solder resist, a coverlay film, or a film-like resist in order to ensure higher accuracy. As a material, an epoxy-based material, a polyimide-based material, an epoxy acrylate-based material, or a fluorene-based material can be used.

  Since such an insulating coating has shrinkage at the time of curing, if it is formed only on one side, a large warp tends to occur on the substrate. Therefore, an insulating coating can be formed on both surfaces of the semiconductor chip mounting substrate as necessary. Furthermore, since the warpage varies depending on the thickness of the insulating coating, it is more preferable to adjust the thickness of the insulating coating on both sides so that no warpage occurs. In that case, it is preferable to conduct preliminary examination and determine the thicknesses of the insulating coatings on both sides. In order to obtain a thin semiconductor package, the thickness of the insulating coating is preferably 50 μm or less, and more preferably 30 μm or less.

(Plating of wiring)
Nickel and gold plating can be sequentially applied to necessary portions of the wiring. Furthermore, nickel, palladium, or gold plating may be used as necessary. These platings are generally applied to semiconductor chip connection terminals of wiring and external connection terminals for electrical connection with a mother board or other semiconductor package. For this plating, either electroless plating or electroplating may be used.

(Manufacturing method of semiconductor chip mounting substrate)
Such a semiconductor chip mounting substrate can be manufactured by the following processes. FIGS. 11A to 11G are schematic cross-sectional views showing an example of an embodiment of a method for manufacturing a semiconductor chip mounting substrate according to the present invention. However, the order of the manufacturing process is not particularly limited as long as it does not depart from the object of the present invention.

(Process a)
(Step a) is a step of forming the first wiring 106a on the core substrate 100 as shown in FIG. For example, an etching resist having a first wiring shape can be formed on the core substrate 100 having a copper layer formed on one side, and wiring can be produced using an etching solution such as copper chloride or iron chloride. In order to produce a copper layer on a substrate, a copper layer can be obtained by forming a thin film by sputtering, vapor deposition, plating or the like and then plating the film to a desired thickness by electrolytic copper plating.

  Note that the first wiring 106a includes the first interlayer connection terminal 101 and the semiconductor chip connection terminal (portion electrically connected to the semiconductor chip), and a semi-additive method is used as a method for forming the fine wiring. May be.

(Process b)
In step (b), as shown in FIG. 11B, a first interlayer connection IVH 102 (via hole) for connecting the first interlayer connection terminal 101 and a second wiring described later. Is a step of forming.

The via hole can be formed by using laser light when the core substrate 100 is a non-photosensitive base material. Examples of the non-photosensitive substrate include the non-photosensitive glass described above, but are not limited thereto. In this case, the laser beam to be used is not limited, and a CO ₂ laser, a YAG laser, an excimer laser, or the like can be used. Further, when the core substrate 100 is a photosensitive base material, a region other than the via hole is masked, and the via hole portion is irradiated with ultraviolet light. Examples of the photosensitive base material include the above-described photosensitive glass, but are not limited thereto. In this case, via holes are formed by heat treatment and etching after irradiation with ultraviolet light. Further, when the core substrate 100 is a base material that can be chemically etched by a chemical solution such as an organic solvent, a via hole can be formed by chemical etching. The formed via hole can be filled with a conductive paste or plating to form an electrically conductive layer for interlayer connection in order to electrically connect the interlayer.

(Process c)
(Step c) is a step of forming the second wiring 106b on the surface of the core substrate 100 opposite to the first wiring 106a, as shown in FIG. A copper layer is formed on the surface opposite to the first wiring of the core substrate 100 in the same manner as in the step (a), an etching resist is formed on the copper layer in a necessary wiring shape, and an etching solution such as copper chloride or iron chloride. The second wiring 106b is formed using As a method for forming a copper layer, a copper layer is obtained by forming a copper thin film by sputtering, vapor deposition, electroless plating, etc. in the same manner as in (Step a) and then copper plating to a desired thickness using electrolytic copper plating. It is done. Note that the second wiring includes the second interlayer connection terminal 103, and a semi-additive method may be used as a method for forming the fine wiring.

(Process d)
(Step d) is a step of forming an insulating layer 104 (build-up layer) on the surface on which the second wiring is formed as shown in FIG. First, the surface of the second wiring 106b is degreased or washed with sulfuric acid. It is immersed in an aqueous solution containing an acid, an alkali or an oxidizing agent, and a treatment is performed so that the Ra (average roughness) of the copper wiring surface is 0.01 to 1.0 μm. When immersed in an aqueous solution containing an oxidizing agent, the surface of the copper wiring surface is reduced to 0.01 to 1 by further immersion in an aqueous solution containing a reducing agent and reducing the copper oxide film. The process is performed so that the thickness becomes 0. Furthermore, a metal selected from copper, tin, chromium, nickel, zinc, aluminum, cobalt, gold, platinum, silver, palladium or an alloy containing the metal is electrolessly plated, electroplated, substitution reaction, spray sprayed, applied. By such a method, the surface of the wiring surface is processed to have a Ra of 0.01 to 1.0 μm. A compound having a Si—O—Si bond is formed on the surface, followed by treatment with a solution containing at least one coupling agent or adhesion improver to form a very thin insulating film on the second wiring surface. To do.

  Next, the insulating layer 104 is formed on the surface of the core substrate 100 and the surface of the second wiring 106b. As the insulating material of the insulating layer 104, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used as described above, but the thermosetting material is preferably a main component. In the case of a varnish-like material, the insulating layer 104 can be obtained by printing or spin coating, or in the case of a film-like insulating material, using a technique such as laminating or pressing. When the insulating material includes a thermosetting material, it is desirable to further heat and cure.

(Process e)
(Step e) is a step of forming a second interlayer connection IVH (via hole) 108 in the insulating layer 104, as shown in FIG. 11E. As a via hole forming means, A general laser drilling device can be used. A CO ₂ laser, a YAG laser, an excimer laser, or the like can be used as the type of laser used in the laser drilling machine, but a CO ₂ laser is preferable in terms of productivity and hole quality. Further, when the IVH diameter is less than 30 μm, a YAG laser capable of focusing the laser beam is suitable. In the case where the insulating layer 104 is a material that can be chemically etched by a chemical solution such as an organic solvent, a via hole can be formed by chemical etching.

(Process f)
(Step f) is a step of forming the third wiring 106c on the insulating layer 104 in which the second via hole is formed, as shown in FIG. 11 (f). Further, as a process for forming a fine wiring with L / S = 20 μm / 20 μm or less, the above-described semi-additive method is preferable. A seed layer is formed on the insulating layer 104 by a method such as vapor deposition or plating or a method of bonding a metal foil. Next, a plating resist is formed on the seed layer formed by the above method. As a method for forming a plating resist, a varnish-like resist material can be formed by spin coating, dip coating, comma coating, printing, etc., and then dried and cured. Also, a film-like resist material can be adhered by pressing or laminating. Next, a plating resist image having a trapezoidal or triangular cross-sectional shape is formed by adjusting the exposure wavelength, exposing, and developing. Next, wiring is formed by electrolytic copper plating through the seed layer. In electrolytic copper plating, a brightening agent and a smoothing agent are appropriately added to adjust the current density, whereby the top portion of the wiring can be formed into an arc shape, as shown in FIG. It is possible to satisfy ≦ b / M <1 and 0.1 ≦ y / t ≦ 0.9. Thereafter, the plating resist is peeled off, and finally the seed layer is removed by etching or the like to form fine wiring. The top portion of the wiring can be formed in an arc shape by not only the above-described electrolytic copper plating but also soft etching or the like during the above-described seed layer etching or after wiring formation.

  By repeating steps (d) to (f), two or more insulating layers 104 may be formed as shown in FIG. In this case, the interlayer connection terminal formed in the outermost insulating layer 104 becomes the external connection terminal 107.

(Process g)
(Step g) is a step of forming an insulating coating 109 for protecting the wiring and the like other than the external connection terminals, as shown in FIG. As the insulating coating material, a solder resist is generally used, and a thermosetting type or an ultraviolet curing type can be used, but an ultraviolet curing type capable of finishing the resist shape with high accuracy is preferable.

(Shape of semiconductor chip mounting substrate)
The shape of the semiconductor chip mounting substrate 22 is not particularly limited, but is preferably a frame shape as shown in FIG. By making the shape of the semiconductor chip mounting substrate in this way, it is possible to efficiently assemble the semiconductor package. Hereinafter, a preferable frame shape will be described in detail.

  As shown in FIG. 12, a block 23 is formed in which a plurality of semiconductor package regions 13 (parts to be a single semiconductor package) are arranged in rows and columns at equal intervals. Further, such a block is formed in a plurality of rows and columns. Although only two blocks are shown in FIG. 12, the blocks may be arranged in a lattice shape as necessary. Here, the width of the space between the semiconductor package regions is preferably 50 to 500 μm, and more preferably 100 to 300 μm. Furthermore, it is most preferable that the blade width of the dicer used when the semiconductor package is cut later is made the same.

  By arranging the semiconductor package region in this way, the semiconductor chip mounting substrate can be effectively used. Further, a positioning mark 11 or the like is preferably formed at the end of the semiconductor chip mounting substrate, and more preferably a pin hole by a through hole. The shape and arrangement of the pin holes may be selected so as to match the forming method and the semiconductor package assembly apparatus.

  Furthermore, it is preferable to form a reinforcing pattern 24 in the space between the semiconductor package regions or outside the block. The reinforcing pattern may be separately manufactured and bonded to the semiconductor chip mounting substrate, but is preferably a metal pattern formed at the same time as the wiring formed in the semiconductor package region, and the surface thereof is similar to the wiring. More preferably, nickel, gold, or the like is plated or an insulating coating is applied. When the reinforcing pattern is such a metal, it can be used as a plating lead in electroplating. Moreover, it is preferable to form the cutting position alignment mark 25 at the time of cutting with a dicer outside the block. In this way, a frame-shaped semiconductor chip mounting substrate can be manufactured.

(Semiconductor package)
FIG. 7 is a schematic sectional view showing an example of an embodiment of the flip chip type semiconductor package of the present invention. As shown in FIG. 7, the semiconductor package of the present invention is such that the semiconductor chip 111 is further mounted on the semiconductor chip mounting substrate of the present invention, and the connection bumps 112 are used to connect the semiconductor chip and the semiconductor chip connection terminals. Then, it can be obtained by electrical connection by flip-chip connection.

  Further, in these semiconductor packages, it is preferable to seal between the semiconductor chip and the semiconductor chip mounting substrate with an underfill material 113 as shown in the figure. The thermal expansion coefficient of the underfill material is preferably close to the thermal expansion coefficient of the semiconductor chip and the core substrate 100, but is not limited thereto. More preferably, (thermal expansion coefficient of the semiconductor chip) ≦ (thermal expansion coefficient of the underfill material) ≦ (thermal expansion coefficient of the core substrate). Furthermore, the semiconductor chip can be mounted using an anisotropic conductive film (ACF) or an adhesive film (NCF) that does not contain conductive particles. In this case, since it is not necessary to seal with an underfill material, it is more preferable. Furthermore, it is particularly preferable to use ultrasonic waves together with the semiconductor chip because electrical connection can be made at a low temperature and in a short time.

  FIG. 8 shows a cross-sectional view of an embodiment of a wire bond type semiconductor package. Although a general die bond paste can be used for mounting the semiconductor chip, it is more preferable to use a die bond film 117. Electrical connection between the semiconductor chip and the semiconductor chip connection terminal can be performed by wire bonding using a gold wire 115. The semiconductor chip can be sealed by transfer molding using a semiconductor sealing resin 116. In that case, at least the face surface of the semiconductor chip is sealed with a semiconductor sealing resin, but only the necessary portion of the sealing region may be sealed, but the entire semiconductor package region is sealed as shown in FIG. It is more preferable to stop. This is a particularly effective method in the case where a plurality of semiconductor package regions are arranged in rows and columns and the substrate and the sealing resin are cut simultaneously with a dicer or the like.

For example, solder balls 114 can be mounted on the external connection terminals for electrical connection with the motherboard. For the solder balls, eutectic solder or Pb-free solder can be used. As a method for fixing the solder balls to the external connection terminals, an N ₂ reflow device can be used, but the method is not limited to this.

  In a semiconductor chip mounting substrate in which a plurality of semiconductor package regions are arranged in rows and columns, the semiconductor package region is finally cut into individual semiconductor packages using a dicer or the like.

Next, although an Example is given and this invention is demonstrated, this invention is not limited to these Examples. In addition, in order to compare with a comparative example by performing electrical corrosion resistance evaluation, the board | substrate for electrical corrosion resistance evaluation was used instead of the board | substrate for semiconductor chip mounting as a board | substrate of an Example and a comparative example.
Example 1
(Process a)
As shown in FIG. 13A, a 0.4 mm thick soda glass substrate (thermal expansion coefficient 11 ppm / ° C.) was prepared as the core substrate 100, and the insulating layer 104 was formed as follows. That is, using an insulating varnish of a cyanate ester resin composition, a spin coating method was applied on a glass substrate under conditions of 1500 rpm to form an insulating layer 104 having a thickness of 20 μm. Heating was performed up to 230 ° C. at a temperature rising rate of ° C./min, and thermosetting was performed by holding at 230 ° C. for 80 minutes, whereby a 15 μm insulating layer 104 was formed.

(Process b)
As shown in FIG. 13B, for forming the first wiring, a base metal Ni layer 20 nm (not shown) to be a seed layer is formed by sputtering, and a thin film copper layer 200 nm (not shown) is further formed. did. Sputtering was performed under the condition 1 shown below using MLH-6315 manufactured by Nippon Vacuum Technology Co., Ltd.
Condition 1
(nickel)
Current: 5.0A
Current: 350V
Argon flow rate: 35 SCCM
Pressure: 5 × 10 ⁻³ Torr (4.9 × 10 ⁻² Pa)
Deposition rate: 0.3 nm / second (copper)
Current: 3.5A
Voltage: 500V
Argon flow rate: 35 SCCM
Pressure: 5 × 10 ⁻³ Torr (4.9 × 10 ⁻² Pa)
Deposition rate: 5 nm / second

Next, a 10 μm-thick plating resist layer was formed on the seed layer by spin coating using a positive type plating resist PMER P-LA900PM (trade name, manufactured by Tokyo Ohka Kogyo Co., Ltd.). Exposure is performed at 1000 mJ / cm ² , and immersion rocking is performed for 6 minutes at 23 ° C. using PMER developer P-7G. As shown in FIG. 14A, L / S = A resist pattern having a trapezoidal cross section of 14 μm / 6 μm was formed. Then, as shown in FIG.14 (b), pattern electrolytic copper plating was performed about 5 micrometers using the copper sulfate plating solution. The plating resist was removed by dipping for 1 minute at room temperature (25 ° C.) using methyl ethyl ketone. For quick etching of the seed layer, a 5-fold diluted solution of CPE-700 (manufactured by Mitsubishi Gas Chemical Co., Ltd., trade name) is used for etching removal by immersing and shaking at 30 ° C. for 30 seconds. As shown in FIG. 14C, the comb-shaped wiring 106 with L / S = 10 μm / 10 μm was formed as observed from directly above.

(Process c)
As shown in FIG. 13C, a film (not shown) containing a silane coupling agent was formed on the surface of the wiring by performing a silane coupling agent treatment on the surface of the wiring 106 formed in (Step b). Thereafter, (Step a) was repeated again to further form an insulating layer 104, and an electrolytic corrosion resistance evaluation substrate having a comb-type wiring 106 as shown in FIG. 15 was produced.

(Comparative Example 1)
After forming the seed layer in the same manner as in the example in (Step b), panel electrolytic copper plating was performed using a copper sulfate plating solution by about 5 μm. Next, an etching resist layer having a thickness of 3 μm was formed on the electrolytic copper plating by spin coating using a negative etching resist PMER N-HC40 (trade name, manufactured by Tokyo Ohka Kogyo Co., Ltd.). Exposure was performed at 100 mJ / cm ² , and immersion rocking was performed for 2 minutes at 23 ° C. using PMER developer N-A5. As shown in FIG. 16A, L / S = An etching resist 120 of 12 μm / 8 μm was formed. Thereafter, as shown in FIG. 16B, after etching the electrolytic copper plating 121 using a ferric chloride etching solution, the etching resist 120 is removed by dipping in the PMER stripping solution NS at 60 ° C. for 1 minute. Then, as shown in FIG. 16C, the comb-shaped wiring 106 with L / S = 10 μm / 10 μm was formed as observed from directly above. In other steps, a substrate for evaluation of electrolytic corrosion resistance having comb-shaped wiring 106 as shown in FIG.

After cutting the sample of each of the electric corrosion resistance evaluation substrates of Example 1 and Comparative Example 1 manufactured as described above, the cross-section of the wiring 106 is observed to measure the dimensions of the wiring. The electric corrosion resistance test between the wirings 106 was performed using each of the 22 samples of Comparative Example 1. The test conditions of the electric corrosion resistance test were 85 ° C./85% RH and DC 5 V applied, a sample was taken every 100 hours and the insulation resistance value was measured, and 10 ⁹ Ω or less was determined as NG. The results of the electric corrosion resistance test are shown in Table 1. FIG. 3 shows a cross-sectional shape of the wiring 106. 3A shows Example 1, and FIG. 3B shows Comparative Example 1. FIG. Table 2 shows the dimension measurement result of the wiring 106.

  As shown in Table 2, the maximum wiring width M was 10 μm in both Example 1 and Comparative Example 1, but the wiring shape in Example 1 was a circle of b / M = 0.6 and y / t = 0.6. In contrast to the arc shape, the wiring shape of Comparative Example 1 was a trapezoidal shape of b / M = 1 and y / t = 0. The results of the electric corrosion resistance test were not problematic in Example 1, but in Comparative Example 1, the number of NG increased with the passage of test time.

(A) Trapezoidal shape, (b) Reverse trapezoidal shape, (c) Cross-sectional view of the conventional wiring which is a rectangle. (A) The cross-sectional shape figure of the wiring which is a shape close | similar to a trapezoid, (b) The shape close | similar to an inverted trapezoid. (A) One Example of this invention, (b) Sectional shape figure of the wiring 106 which is one comparative example of this invention. 1 is a cross-sectional view of a semiconductor chip mounting substrate to which an embodiment of the present invention is applied. 1 is a cross-sectional view of a semiconductor chip mounting substrate to which an embodiment of the present invention is applied. The cross-sectional shape of the plating resist and wiring whose cross-sectional shape of a plating resist is (a) rectangle, (b) inverted trapezoid, (c) trapezoid, (d) trapezoid. 1 is a cross-sectional view of a flip chip type semiconductor package to which an embodiment of the present invention is applied. 1 is a cross-sectional view of a wire bond type semiconductor package to which an embodiment of the present invention is applied. The top view of the fan-in type semiconductor chip mounting substrate which is one Embodiment of this invention. The top view of the fan-out type semiconductor chip mounting substrate which is another embodiment of this invention. (A)-(g) is process drawing which shows one Embodiment of the manufacturing method of the semiconductor chip mounting substrate of this invention. The top view showing the frame shape of the semiconductor chip mounting substrate of this invention. (A)-(c) is process drawing which shows one Example and one comparative example of the manufacturing method of the semiconductor chip mounting substrate of this invention. (A)-(c) is process drawing which shows further the process of FIG.13 (b) which is one Example of the manufacturing method of the semiconductor chip mounting substrate of this invention. The schematic diagram of the comb-type wiring (L / S = 10micrometer / 10micrometer) of the board | substrate for electric corrosion resistance evaluation evaluated by one Example and one comparative example of this invention. (A)-(c) is process drawing which shows the process of FIG.13 (b) which is one comparative example of the manufacturing method of the semiconductor chip mounting substrate of this invention further in detail.

Explanation of symbols

a. Top width of wiring b. Bottom width of wiring α. Minimum angle of wiring β. Substantial angle of wiring t. Wiring height from bottom to top of wiring y. Height from the bottom of the wiring to the maximum wiring width Maximum wiring width of wiring m. Minimum wiring width of wiring L. Wiring line width 10. Space width of wiring Positioning mark (guide hole for alignment)
13. Semiconductor package region 14. Die bond film bonding area (flip chip type)
15. Semiconductor chip mounting area (flip chip type)
16. Semiconductor chip connection terminal 17. Die bond film bonding area (wire bond type)
18. Semiconductor chip mounting area (wire bond type)
19. External connection terminal 20. Expanded wiring 21. Dummy pattern 22. Semiconductor chip mounting substrate 23. Block 24. Reinforcing pattern 25. Cutting alignment mark 100 Core substrate 101 First interlayer connection terminal 102 IVH (via hole) for first interlayer connection
103 Second interlayer connection terminal 104 Insulating layer (build-up layer)
105 Third layer connection IVH (via hole)
106 Wiring (comb type wiring)
106a First wiring 106b Second wiring 106c Third wiring 107 External connection terminal 108 Second interlayer connection IVH (via hole)
109 Insulation coating (solder resist)
111 Semiconductor chip 112 Connection bump 113 Underfill material 114 Solder ball 115 Gold wire 116 Semiconductor sealing resin 117 Die bond film 118 Plating resist 119 Wiring top portion 120 Etching resist 121 Electro copper plating

Claims (5)

A method of manufacturing a wiring board in which wiring is formed on an insulating layer,
A seed layer forming step of forming a seed layer on the insulating layer;
A plating resist forming step of forming a plating resist at a predetermined interval on the seed layer;
A wiring forming step of forming wiring between the plating resists by electroplating;
Removing the plating resist and the seed layer from the insulating layer after the formation of the wiring,
In the plating resist process, the plating resist is formed such that a region defined by a side surface of one plating resist and a side surface of the other plating resist facing the side surface extends in the height direction of the plating resist. Forming,
In the wiring formation step, an additive containing a brightening agent and a smoothing agent is added to the electroplating, and the top portion of the wiring is convex in a height direction at a position equal to or lower than the height of the plating resist. A method for manufacturing a wiring board, comprising: forming a wiring board. The method for manufacturing a wiring board according to claim 1, wherein a cross-sectional shape of the plating resist is a trapezoidal shape or a triangular shape. The method according to claim 1 or 2, wherein the wiring board, characterized in Rukoto using a positive resist as the plating resist. It is a wiring board manufactured using the manufacturing method of the wiring board as described in any one of Claims 1-3, Comprising: The maximum wiring width of the said wiring is M, The bottom width of the said wiring is b, The bottom of the said wiring 0.1 ≦ b / M <1 , and 0.1 ≦ y /, where y is the height from the bottom to the maximum wiring width and t is the wiring height from the bottom to the top of the wiring. A wiring board satisfying t ≦ 0.9. The wiring board according to claim 4, wherein the maximum wiring width M is M ≦ 20 μm.

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