JP2009117721A - Wiring board, circuit board and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board having a wiring pattern of which an upper face has a shape close to a flat one. <P>SOLUTION: In the wiring board, a plurality of wiring patterns 22 in which a conductive metal is electrocast through a seed layer are formed on a surface of an insulating film. An upper face 25 of the wiring pattern is made to coincide with a circular arc of any virtual circle 30 having a radius of 1.0 time or more of a line width of the wiring pattern. In a circuit board, an electronic component is packaged on the wiring board. Accordingly, as the upper face of the wiring pattern is flattened, a stable electric connection can be established relative to the other members such as an electronic component, etc. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a wiring board on which a wiring pattern is formed by a semi-additive method, a circuit board, a manufacturing method of the wiring board, and a manufacturing method of the circuit board.

  In recent years, with the demand for higher definition of liquid crystal screens, printed wiring boards for IC mounting such as COF (Chip On Film) have been made finer, and it is necessary to form wiring patterns with a pitch width of 20 μm or less. In such a wiring board, a wiring pattern having a pitch width of 15 μm or less is also required.

  Up to now, a wiring board has a photosensitive resin layer formed on the surface of a copper foil laminated on an insulating film such as a polyimide film, and the photosensitive resin layer is exposed and developed into a desired shape on the surface of the copper foil. The remaining photosensitive resin was used as a masking agent and was manufactured by a subtractive method of selectively etching a copper foil. However, the wiring width that can be formed by the subtractive method as described above is limited to 35 μm. Subsequent improvement of the subtractive method cannot barely form a wiring with a line width of up to 30 μm, but it is impossible to manufacture a wiring with a line width of less than 30 μm by the subtractive method.

  This is a subtractive method in which the developed photosensitive resin is used as a masking material, and the copper foil in the portion where no masking material is present is removed by etching. Therefore, the upper surface is etched by etching the copper foil in the depth direction. Since the newly formed wiring protected by the masking material is eroded from the side surface portion, the wiring with a line width of 20 μm or less cannot be formed by the subtractive method.

Accordingly, when forming a wiring having a line width of 20 μm or less, it is necessary to adopt another method that is not the subtractive method as described above.
As a method for forming a wiring pattern, there is a semi-additive method in addition to the subtractive method as described above. In this semi-additive method, a photosensitive resin layer is formed on the surface of a base metal layer of an insulating film having a base metal layer (seed layer) formed on the surface, and this photosensitive resin layer is formed on a portion where wiring is formed. The photosensitive resin is exposed and developed so that a reverse circuit from which the photosensitive resin is removed is formed. Next, after forming a circuit by depositing copper on the part where the photosensitive resin is removed using the base metal layer as an electrode, the photosensitive resin formed in the reverse circuit shape is removed, and further formed from the photosensitive resin. This is a method of forming a wiring pattern by electrically removing wiring formed by removing the base metal layer under the reverse circuit and depositing copper. According to this semi-additive method, a wiring having a line width corresponding to the resolution of the photosensitive resin layer can theoretically be formed, so that even a wiring pattern having a line width of 20 μm or less can be formed. become.

  However, the wiring formed by the semi-additive method has an arched shape because the upper part of the formed wiring is not flat due to the characteristics of the deposited copper. For this reason, when the formed wiring pattern is inspected by using an automatic inspection device, the edge of the formed wiring pattern is not clear, so it is often judged as a line width defect and treated as a defective product. The problem that becomes. In addition, when connecting an ACF (Anisotropic Conductive Film), if the conductor is round, the conductive particles contained in the ACF adhesive are not fixed on the conductor in a stable state. This causes a problem that sufficient electrical connection cannot be established with the (Oxide) terminal. Furthermore, when connecting the inner lead and bump electrode formed on the electronic component, if the conductor is round, the pressure when thermocompression bonding with the electronic component may increase and damage the electronic component. Since the connection area is smaller than in the case of the above, there arises a problem that the joint portion is easily peeled off due to a thermal cycle or stress, which may adversely affect the reliability of electronic component connection.

  By the way, claim 1 of Patent Document 1 (Japanese Patent Laid-Open No. 2000-87292) states that “the object to be plated is first wetted with a plating solution to make the current zero for a predetermined time, and then the object to be plated in the plating solution. And a plating method characterized in that a plating process is performed by applying an electric current to the electrode plate. " That is, Patent Document 1 uses a cleaning action of a plating solution to form a highly uniform plating by performing plating after washing an object to be plated with the washing power of the plating solution before plating. It is described to do. Although this cited reference 1 discloses a plating method by a semi-additive method, there is no description about the fact that a wiring pattern formed by a semi-additive method is formed in a kamaboko shape. There is no mention of how to do it.

  The claim of Patent Document 2 (Japanese Patent Application Laid-Open No. 8-242061) states that “a plating layer having a pattern having a region in which the occupation area of the plating pattern is rougher than other regions is formed by electroplating. A method for forming a plating layer, wherein the width in the plating bath is substantially the same as the width of the object to be plated, and an insulator corresponding to the rough region is disposed between the electrodes. Is disclosed. However, even if the fine pitch portion and the rough pitch portion are mixed, a method is disclosed in which an insulator is provided and plating is formed to a uniform thickness. However, this Patent Document 2 does not describe that the upper part of the wiring pattern formed by the semi-additive method is formed in a semi-cylindrical shape, and does not describe anything about how to do this because it is not formed in the semi-cylindrical shape. It has not been.

Further, Patent Document 3 (Japanese Patent Application Laid-Open No. 2000-87292) states that “when electroplating a conductive surface to be plated, the surface to be plated is a cathode and the metal to be plated is an anode. The electroplating method is characterized in that the electroplating is performed intermittently while keeping the voltage between the anode and the cathode constant. " In this Patent Publication 3, it is disclosed that the voltage applied intermittently is changed when electroplating is performed in the semi-additive method. However, this Patent Document 2 does not describe that the upper part of the wiring pattern formed by the semi-additive method is formed in a semi-cylindrical shape, and does not describe anything about how to do this because it is not formed in the semi-cylindrical shape. It has not been.
JP 2000-87292 A JP-A-8-242061 JP 2000-87292 A

  An object of the present invention is to provide a wiring board on which a wiring pattern formed by a semi-additive method is formed and having a wiring pattern whose upper surface shape is closer to flat.

  Further, the present invention provides a circuit board on which a wiring pattern formed by a semi-additive method is formed, and an electronic component is mounted on the wiring board having a wiring pattern whose upper surface shape is almost flat. The purpose is to do.

  Another object of the present invention is to provide a method for manufacturing the above wiring board and circuit board.

  The wiring board of the present invention is a wiring board in which a large number of wiring patterns in which a conductive metal is electroformed via a seed layer is formed on the surface of an insulating film, and the upper surface of the wiring pattern has a line width of the wiring pattern. It is characterized by being coincident with an arc of any virtual circle having a radius of 1.0 times or more.

  Further, the circuit board of the present invention is a circuit board in which electronic components are mounted on a wiring board in which a large number of wiring patterns in which a conductive metal is electroformed via a seed layer is formed on the surface of an insulating film. The upper surface of the pattern is characterized by being coincident with an arc of any virtual circle having a radius of 1.0 times or more the line width of the wiring pattern.

  The wiring board as described above includes a wiring pattern to be formed using a photosensitive resin on the surface of the conductive metal layer of the base material layer in which the base metal layer and the conductive metal layer are formed on the surface of the insulating film. Forms a reverse pattern having reverse irregularities, deposits a conductive metal on the reverse pattern to form a wiring pattern precursor, and then removes part of the wiring pattern precursor by etching to leave the wiring pattern remaining part After forming the conductive pattern, the conductive pattern is electroformed by depositing conductive metal on the remaining part of the wiring pattern, the reverse pattern made of the photosensitive resin is removed, the conductive metal layer is removed, and the wiring pattern is electrically connected. It can manufacture by making it independent.

  Further, the circuit board of the present invention is a wiring pattern to be formed using a photosensitive resin on the surface of the conductive metal layer of the base material layer in which the base metal layer and the conductive metal layer are formed on the surface of the insulating film. And forming a wiring pattern precursor by depositing a conductive metal on the reverse pattern, and then removing a part of the wiring pattern precursor by etching to leave the wiring pattern After forming the part, conductive metal is deposited on the remaining part of the wiring pattern and the wiring pattern is electroformed. Then, the reverse pattern made of the photosensitive resin is removed, and the conductive metal layer is removed to electrically connect the wiring pattern. Can be manufactured by mounting electronic components on the formed wiring pattern.

According to the present invention, the upper surface of the wiring board or the wiring pattern constituting the circuit board formed by employing the semi-additive method does not have a semi-cylindrical shape but has a flat cross-sectional form.
That is, the wiring pattern formed on the wiring board or circuit board of the present invention is a wiring board or circuit board having a pitch width (P) of 25 μm or less and a line width of 20 μm or less, which is difficult to manufacture by the subtractive method. The upper surface of the wiring pattern formed on this wiring board or circuit board matches the curvature of a virtual circle having a radius of 1.0 times or more with respect to the line width (W) of this wiring pattern. Therefore, the upper surface of the wiring pattern constituting the wiring board or circuit board of the present invention is formed flat. For this reason, the reliability of electrical connection is high, and many contacts can be formed, for example, in the case of ACF connection.

  In order to make the upper surface of the wiring pattern flatter in this way, in the present invention, a part of the wiring pattern (wiring pattern precursor) once formed by the semi-additive method is etched from the upper surface of the wiring pattern precursor. After forming the wiring pattern remaining portion from which the upper surface portion of the wiring pattern precursor has been removed, conductive metal is deposited again on the wiring pattern remaining portion to form the wiring pattern. After forming the wiring pattern precursor in this way, the surface of the precursor is removed by etching to form a wiring pattern remaining portion having a rough surface, and a conductive metal is deposited on the wiring pattern remaining portion. Therefore, it is possible to form a wiring pattern having a highly planar surface that coincides with an arc of a virtual circle having a large virtual radius based on the line width of the formed wiring pattern.

  When the cross section of the wiring pattern formed in this way is observed with an electron microscope, the wiring pattern remaining portion formed by etching the surface of the wiring pattern precursor is deposited on the wiring pattern remaining portion. A partition line indicating the boundary with the conductive metal is observed, and the partition line is generally not flat and has unevenness on the surface of the remaining portion of the wiring pattern. Therefore, the surface roughness of the remaining wiring pattern portion generally shows a value considerably higher than the surface roughness of the wiring pattern precursor before being etched.

  The method for manufacturing a wiring board according to the present invention solves the problem that the upper surface of the formed wiring pattern is formed in a semi-additive shape when manufacturing a wiring board by the semi-additive method, and the semi-additive method. Since the wiring pattern is formed by this method, a very thin wiring pattern having a pitch width of 25 μm or less and a line width of 20 μm or less, which cannot be formed by the subtractive method, is accurately formed. be able to.

Next, the wiring board of the present invention will be specifically described with reference to the drawings.
FIG. 1 is a longitudinal sectional view showing an example of a wiring pattern formed on a wiring board of the present invention, and a virtual circle that coincides with the shape of the upper surface of the wiring pattern is described together.

  As shown in FIG. 1, the wiring board of the present invention is formed on the surface of a base metal layer 12 formed on the surface of an insulating film 11 constituting the base material layer 10 and a conductive metal layer 13 laminated thereon. The wiring pattern 22 is made of electroformed conductive metal.

  Here, the pitch width (P) of the narrowest part of the wiring pattern forming the wiring board of the present invention is usually 25 μm or less, preferably 15 to 25 μm. The line width (w) of the narrowest portion is usually 20 μm or less, preferably 7 to 20 μm. Even if the pitch width (P) and the line width (w) exceed the above upper limit, it can be formed by the semi-additive method shown in the present invention, but it is more economical than the conventional method. There are few advantages in terms of productivity.

Further, the height of this wiring pattern (wiring pattern thickness) is usually in the range of 3 to 12 μm, preferably 5 to 10 μm.
That is, the wiring board of the present invention is suitable for forming a wiring pattern having a very narrow pitch width and line width that is extremely difficult to form by the subtractive method conventionally employed.

  In the wiring board of the present invention, the insulating film 11 constituting the base material layer 10 comes into contact with an acid or the like during etching, so that it is not affected by such chemicals and is not altered by heating during bonding. It has such heat resistance. Examples of the material for forming such an insulating film include polyester, polyamide, polyamideimide, liquid crystal polymer, glass fiber-containing epoxy resin and polyimide. In particular, in the present invention, it is preferable to use a film made of polyimide.

  Examples of the polyimide film constituting the insulating film 10 include wholly aromatic polyimide synthesized from pyromellitic dianhydride and aromatic diamine, and biphenyl synthesized from biphenyltetracarboxylic dianhydride and aromatic diamine. Mention may be made of wholly aromatic polyimides having a skeleton. In particular, in the present invention, a wholly aromatic polyimide having a biphenyl skeleton (eg, trade name: Upilex, manufactured by Ube Industries, Ltd.) is preferably used. The thickness of the insulating film 11 is usually 125 μm or less, preferably 75 μm or less, particularly preferably 50 μm or less, and more preferably 5 to 50 μm. In addition, when this insulating film 11 is thin, it may be difficult to handle it alone. In such a case, a reinforcing support film is peelably attached to the surface opposite to the surface on which the wiring pattern is formed. Can be worn.

A base metal layer 12 is formed on such an insulating film 11, and a conductive metal layer 13 made of a conductive metal is formed on the surface of the base metal layer 12.
The base metal layer 12 is usually a sputtering layer of nickel, chromium, copper or the like, and its thickness is usually in the range of 20 to 300 mm, preferably in the range of 30 to 250 mm.

  Further, a conductive metal layer 13 made of a conductive metal is formed on the surface of the base metal layer 12, and the thickness of the conductive metal layer 13 is usually 0.1 to 2 μm, preferably 0. It is in the range of 1 to 1.5 μm. The conductive metal that forms the conductive metal layer 13 may be the same as or different from the metal that forms the wiring pattern 22, and the metal that forms the conductive metal layer 13 and the wiring pattern 22 When the metal to be formed is the same, the conductive metal layer 13 is integrated with the wiring pattern 22, and the boundary between the two cannot be identified by a normal method. Here, examples of the metal forming the conductive metal layer 11 include copper or a copper alloy.

  When the upper surface 25 of the wiring pattern 22 formed on the wiring board of the present invention is formed by a semi-additive method, the curvature of the upper surface becomes the line width of the wiring (see FIG. 2B-2). The radius (R) coincides with an arc having a radius of about 0.5 with respect to w), and its cross-sectional shape is typically a kamaboko shape as shown in FIG. 2 (b-2). Further, even when the conductive metal deposition condition is set to a suitable condition, the curvature of the upper surface of the wiring pattern 22 is R = 0 with respect to the line width (w) as shown in FIG. Although it is not impossible to match the curvature of the .75 virtual circle 30, it is considerably difficult to make the upper surface 25 of the wiring pattern 22 flatter than this.

  The upper surface 25 of the thinnest wiring pattern 22 formed on the wiring board shown in FIG. 1 has a radius R = 0.8 or more with respect to the line width (w), and the virtual circle shown in FIG. The radius of 30 has a curvature of the upper surface that coincides with an arc of 0.8 with respect to the line width (w), but the vicinity of this curvature is the limit in the conventional semi-additive method.

  According to the present invention, this limit can be exceeded, and as shown in FIG. 1 (a-1), the radius (R) of the virtual circle 30 is 1 times the line width (w) and In this example, the upper surface 25 of the wiring pattern 22 coincides with the arc of the virtual circle 30. FIG. 1A-2 shows that the radius (R) of the virtual circle 30 is 1.5 with respect to the line width (w). This is an example in which the arc and the upper surface 25 of the wiring pattern 22 coincide with the arc of the virtual circle 30. FIG. 1A-2 shows the radius (R) of the virtual circle 30 with respect to the line width (w). ) Is 2.5 times, and this is an example in which the arc and the upper surface 25 of the wiring pattern 22 coincide with the arc of the virtual circle 30.

  When the wiring pattern is formed by the semi-additive method in this way, the upper surface 25 of the wiring pattern 22 tends to be formed in a somewhat arc shape. In this way, the upper surface portion of the cross section of the wiring pattern formed by the semi-additive method is formed in an arc shape, whereas the upper surface portion of the cross section of the wiring pattern formed by the subtractive method is flat. Is the difference. However, the lower limit of the pitch of the wiring pattern that can be formed by the subtractive method is up to about 30 μm, and it is practically impossible to manufacture a wiring pattern having a narrower pitch than this by the subtractive method. However, as electronic devices become smaller and lighter, electronic components are also becoming smaller. The line width of the wiring pattern of the wiring board on which the electronic components are mounted, particularly the pitch width (P) of the inner lead portion directly connected to the electronic components is 25 μm or less and the line width (w) must be 20 μm or less, which cannot be handled by a conventionally used subtractive method. For this reason, an attempt has been made to form a wiring pattern by a semi-additive method that can be made thinner. However, as described above, the cross-section of the wiring pattern formed by the semi-additive method usually has an upper surface shape of 0. 0 with respect to the line width (w) as shown in FIG. In general, it is formed in an arc shape that coincides with an arc of a virtual circle having a radius of about 5 times. Even if the optimum conditions are selected by changing the plating conditions, it is shown in FIG. In this way, the limit was to form an arc shape that matches the arc of a virtual circle having a radius 0.8 times the line width (w).

Thus, when the upper surface of the wiring pattern is formed in a kamaboko shape, it is difficult to establish a stable electrical connection with other members.
In the wiring board of the present invention, as a result of studying the shape of the condition of the wiring pattern formed by the semi-additive method, a virtual circular arc having a radius of 1.0 times or more with respect to the line width (w) of the wiring pattern By forming the upper surface of the wiring pattern so as to match, a stable electrical connection is formed.

In order to make the shape of the upper surface of the wiring pattern as described above, the wiring pattern is formed, for example, as shown in FIG.
FIG. 3A shows the base material layer 10 used in the present invention. The base material layer 10 includes an insulating film 11, a base metal layer 12 formed on the surface of the insulating film 11, and a conductive metal layer 13 formed on the surface of the base metal layer 12. The base metal layer 12 is a sputtering layer, and is usually a sputtering layer containing nickel and chromium. The conductive metal layer 13 laminated on the base metal layer 12 is a conductive metal layer made of copper or a copper alloy, and can be formed by an electrolytic plating method or an electroless plating method. The conductive metal layer 13 is formed so as to cover the base metal layer 12 that is the sputtering layer, and the thickness thereof is usually in the range of 0.1 to 2 μm.

  In the present invention, it is not necessary to increase the thickness of the conductive metal layer 13 as described above. Therefore, as shown in FIG. The flash etching process is performed so as to be in the range of 1.5 μm, preferably in the range of 0.05 to 1.0 μm. A normal etching solution such as an etching solution containing sulfuric acid and hydrogen peroxide can be used for the flash etching process.

  After the conductive metal layer 13 on the surface of the base material layer 10 is thinned by flash etching as necessary, as shown in FIG. 3C, the conductive metal layer subjected to flash etching is processed as shown in FIG. A photosensitive resin layer 15 is formed on the surface 13. The photosensitive resin that forms the photosensitive resin layer 15 includes a photosensitive resin coating solution containing a solvent and an adhesive material that is formed and adhered in the form of a film. Can be used.

  In addition, the photosensitive resin includes a type in which a portion irradiated with light is cured and becomes insoluble in a developer, and a type in which a portion irradiated with light is soluble in a developer. These types of photosensitive resins can also be used.

  The thickness of the photosensitive resin layer formed from such a photosensitive resin is usually in the range of 2 to 15 μm, preferably 4 to 15 μm. In general, the thickness of the photosensitive resin layer is preferably in the range of 125 to 180% of the thickness of the wiring pattern precursor 20 to be formed next.

  After forming the photosensitive resin layer 15 using the photosensitive resin as described above, the wiring to be formed as shown in FIG. A reverse pattern 19 is formed in which unevenness opposite to the unevenness corresponding to the pattern is formed of a photosensitive resin. Here, in contrast to the subtractive method, the reverse pattern is formed such that the photosensitive resin layer 19 is formed in the portion where the wiring pattern is not formed and the photosensitive resin is not present in the portion 19a where the wiring pattern is formed. It is a pattern made of a photosensitive resin.

Next, as shown in FIG. 3E, a conductive metal is deposited on a portion 19a where a wiring pattern is formed without the presence of a photosensitive resin, thereby forming a wiring pattern precursor 20. The wiring pattern precursor 20 can be formed by electroplating copper or a copper alloy using the base metal layer 11 and the conductive metal layer formed on the base layer 10 as electrodes. There is no particular restriction on the copper plating solution used when forming this wiring pattern precursor 20, for example, CuSO ₄ .5H ₂ O is contained at a concentration of 45 to 125 g / liter, and sulfuric acid at a concentration of 170 to 210 g / liter. A copper plating solution to be used can be used. Using such a copper plating solution, a current of Dk = 0.5-3 A / dm ² is allowed to flow for 10-60 minutes at a temperature of 20-30 ° C. to form a wiring pattern precursor 20 having a thickness of 5-12 μm. Can do.

  In the normal semi-additive method, after forming the wiring pattern precursor as described above, the reverse pattern made of the photosensitive resin is removed, and then the conductive metal layer 13 and the base metal layer 12 constituting the base material layer 10. The wiring pattern is formed by electrically removing each of the wirings by etching away. Since the wiring pattern 22 is also dissolved when the conductive metal layer 13 and the base metal layer 12 are removed in this way, a wiring pattern made of a conductive metal, for example, as shown in FIG. The shape of the upper surface 25-4 of 22 becomes a kamaboko shape.

  In the present invention, after the wiring pattern precursor 20 is formed as described above, a part of the formed wiring pattern precursor 20 is dissolved and removed without removing the reverse pattern 20 made of a photosensitive resin. A pattern remaining portion is formed. FIG. 3F shows a state in which a wiring pattern remaining portion 21 in which a part of the wiring pattern precursor 20 is dissolved and removed is formed.

In order to remove a part of the wiring pattern precursor 20 and form the wiring pattern remaining portion 21, it is usually preferable to use a cupric chloride etchant. This cupric chloride etching solution contains CuCl ₂ in an amount of 132 to 162 g / l, HCl in an amount of 107 to 130 g / l and H ₂ O _2, and the Cu ⁺⁺ concentration in this etching solution is An etching solution containing 62 to 77 g / liter. When such a cupric chloride etching solution is used, the wiring pattern formed by bringing the wiring pattern precursor 20 into contact with the cupric chloride etching solution at a temperature of 35 to 45 ° C. for 60 to 90 seconds. 10 to 80% (in terms of height) of the precursor 20 is removed, and the wiring pattern remaining portion 21 is formed. At this time, the wiring pattern precursor 20 is adjusted so that the depth from the edge of the reverse pattern 19 made of the photosensitive resin to the wiring pattern remaining portion 21 is usually in the range of 1 to 12 μm, preferably 2 to 10 μm. It is preferable to remove by etching.

  In the above description, an example using a cupric chloride etchant is shown. However, as the etchant used here, for example, the above-described cupric chloride etchant is preferably used. A normal etching solution such as an etching solution containing sulfuric acid and hydrogen peroxide used in the flash etching process can be used.

When the wiring pattern precursor 20 is etched to form the wiring pattern remaining portion 21 as described above, the surface of the wiring pattern remaining portion 21 may be modified with an etching solution. For example, 100 to 200 g / liter. Using a microetching solution containing potassium persulfate (K ₂ S ₂ O ₈ ) as a main component, the surface is microetched at a room temperature of about 20 to 35 ° C. for 5 to 30 seconds, and a wiring pattern remaining portion 21 is obtained. Surface treatment is performed.

Copper or copper alloy, which is a conductive metal, is again deposited on the wiring pattern remaining portion 21 that has been microetched as described above, thereby forming the wiring pattern 22.
Here is not particularly limited to the copper plating solution used, for example CuSO ₄ · 5H ₂ O was used in the formation of the wiring pattern precursor 20 concentration of 45～125G / l, sulfuric acid in 170～210G / liter A copper plating solution contained in a concentration can be used. Using such a copper plating solution, a current of Dk = 0.5-3 A / dm ² is passed for 10-60 minutes at a temperature of 20-30 ° C. to form a wiring pattern precursor 20 having a thickness of 5-12 μm. Can do.

  The plating process is performed as described above, and copper or a copper alloy is deposited on the surface of the wiring pattern remaining portion 21 shown in FIG. 3 (f), and the wiring pattern 22 is shown in FIG. 3 (g). Is formed. At this time, the thickness of the wiring pattern 22 is normally in the range of 50 to 100%, preferably 55 to 99% with respect to the thickness (100%) of the reverse pattern 19.

  By controlling the thickness of the wiring pattern 22 thus formed to be equal to or less than the thickness of the reverse pattern 19, the side surface of the wiring pattern 22 to be formed can be formed substantially perpendicular to the insulating film 11. it can.

  After the wiring pattern 22 is formed in this way, the reverse pattern 19 made of a cured photosensitive resin is removed. For removing the reverse pattern 19, an alkaline stripping solution can be used. For example, a stripping solution mainly composed of a basic compound such as 2-aminoethanol is heated to about 30 to 70 ° C. The reverse pattern 19 made of a photosensitive resin can be removed by immersing in a stripping solution for 5 seconds to 5 minutes.

  When the reverse pattern 19 made of a photosensitive resin is removed in this way, the conductive metal layer 13 is exposed on the surface of the portion where the reverse pattern is formed, as shown in FIG. A base metal layer 12 is laminated below the metal layer 13. Since these layers have electrical conductivity, in order to make the wiring pattern 22 an independent wiring pattern, it is necessary to remove the conductive metal layer 13 and the base metal layer 12 between the wiring patterns 22. There is.

  As described above, the conductive metal layer 13 is a thin layer usually made of copper or a copper alloy having a thickness of 0.1 to 2 μm. For example, as shown in FIG. Can be easily removed by treating for 20 to 60 seconds at a temperature of 25 to 45 ° C.

  The base metal layer 12 is usually a sputtering layer made of nickel, chromium, etc. As shown in FIG. 3 (j), 5 to 15% hydrochloric acid etching solution heated to about 40 to 70 ° C. It can be removed by treating for 30 seconds, usually without washing with water, and subsequently with 5-15% sulfuric acid + 5-15% hydrochloric acid mixed solution heated to about 40-70 ° C. for 5-30 seconds. Polyimide, which is an insulating film, is exposed between the wiring patterns 22 after the treatment.

In the present invention, after the wiring pattern precursor 20 once formed is removed by a flash etching process to form a wiring pattern remaining portion 21, copper or a copper alloy is charged on the wiring pattern remaining portion 21. After the solid wiring pattern 22 is formed by casting, Au plating (0.1 to 0.5 μm thickness) is performed to remove the conductive metal layer 13 after the reverse pattern 19 is removed. When the layer 12 is removed, the wiring pattern 22 is not eroded, and the upper surface portion of the formed wiring pattern 22 has a shape close to a planar shape, and the flatness is maintained as it is. In the present invention, Au plating is performed on the upper surface of the wiring pattern 22 as Au plating conditions, for example, using Temperex # 8400 (manufactured by EEJA) at a temperature of 65 to 70 ° C. and Dk = 0.2. It is preferable to perform the treatment at ˜0.8 A / dm ² for 30 seconds to 2 minutes. The anode used at this time is usually a Pt-plated titanium mesh plate or the like.

  The wiring pattern thus formed can be subjected to plating treatment such as tin plating, nickel plating, nickel / gold plating, solder plating, etc., but the entire pattern is usually subjected to electroless Sn plating treatment. Is desirable.

  Further, among the formed wiring patterns, the other end of the wiring pattern is connected to the input-side outer lead, the input-side inner lead, the output-side inner lead, and the output-side outer lead at the tip of the wiring pattern. Since it is not necessary to form an electrical connection in this portion, it is possible to protect the wiring pattern by forming a solder resist layer on the surface of the wiring pattern except for the above portion.

  For example, the upper surface 25 of the wiring pattern of the wiring board manufactured by the method as described above has a substantially planar cross section when the reverse pattern is removed as shown in FIG. have. However, when Au plating is not performed, when the conductive metal layer 13 is etched, the upper surface 25-2 of the wiring pattern 22 is slightly etched along with the etching of the conductive metal layer 13, and the base metal layer 12 is further etched. The upper surface 25-3 of the wiring pattern 22 is also slightly etched when etching is removed. However, as described above, it does not have a semi-cylindrical shape like the wiring pattern obtained by removing the reverse pattern 19 directly from FIG. 3E (the upper surface 25-4 of FIG. 4Jc).

  That is, the upper surface 25 of the wiring pattern 22 formed on the wiring board of the present invention has a curvature of a virtual circle having a radius (R) of 1.0 times or more with respect to the line width (w) of the wiring pattern 22. Since they have the same curvature and are not extremely curved, it is possible to increase the contact area when forming an electrical connection by joining with other members, and high electrical connection reliability is obtained. It is done.

  In addition, the wiring pattern formed on the wiring board or circuit board of the present invention has a wiring pattern having a pitch width (P) of 25 μm or less and a line width of 20 μm or less, and is manufactured by the conventional subtractive method. It is possible to form a narrow wiring pattern at a high density, which has been impossible.

  The wiring pattern formed on the wiring board or circuit board of the present invention is formed by once forming the wiring pattern precursor 20 as described above, and then dissolving and removing a part of the formed wiring pattern precursor 20. A wiring pattern remaining portion is formed. FIG. 3F shows a state in which a wiring pattern remaining portion 21 in which a part of the wiring pattern precursor 20 is dissolved and removed is formed. The surface of the wiring pattern remaining portion 21 is not smooth and is usually a rough surface having an Rz of about 3 to 10 μm. In the present invention, a copper or copper alloy, which is a conductive metal, is deposited on the surface of the wiring pattern remaining portion 21 to form a robust wiring pattern. A boundary line is usually present at the boundary between the metal and the remaining wiring pattern portion 21 due to the difference in the conductive metal deposition history. FIG. 5 is an electron micrograph of a cross section of the wiring pattern, and FIG. 6 is a traced view of FIG. The bold line highlighted in FIG. 6 is a line that clearly shows different boundaries of the precipitation state of the metal as viewed crystallographically. In the present invention, after the wiring pattern precursor is formed, the wiring pattern precursor thus formed is melted from the upper surface to form the remaining wiring pattern portion, and the lower portion of the portion shown in bold lines in FIG. It is a pattern residual part, and the upper part from a thick line is the electroconductive metal which precipitated in the subsequent process. Such a deposition history of the deposited metal is confirmed by observing the cross section of the wiring pattern and finding the deposited partition line of the deposited metal with an electron microscope even after the electronic component is mounted on the wiring substrate and the wiring substrate. be able to.

  Furthermore, as shown in FIG. 6, the partition lines of the deposited metal are generally not formed as flat straight lines but are generally formed in an uneven shape, and such a wiring pattern remaining portion having a high surface roughness. Copper or copper alloy, which is a conductive metal, is deposited on the surface, and a wiring pattern close to a planar shape is obtained on the surface.

In FIGS. 5 and 6, descriptions regarding the insulating film, the solder resist, the base metal layer, and the like are omitted.
In addition, said manufacturing method shows the suitable example which manufactures the wiring board or circuit board of this invention, and the wiring board of this invention is not limited by said manufacturing method.

And the circuit board of this invention can be manufactured by mounting an electronic component in the inner lead of the above wiring boards.
Even if electronic components are mounted in this way, the partition lines in the cross section of the wiring pattern are not usually lost.
〔Example〕
Next, although the Example of this invention is shown and the wiring board of this invention is demonstrated, this invention is not limited by these.

  A 35 μm thick polyimide film (trade name: Upilex, Ube Industries, Ltd.) is formed by sputtering a Ni—Cr (20%) seed layer to a thickness of 250 mm, and copper is added on the seed layer. A 70 mm wide film of two-layer CCL (backside PET attached) plated to a thickness of 3 μm was prepared.

The two-layer CCL was flash-etched with a sulfuric acid + hydrogen peroxide etching solution at 30 ° C. for 40 seconds to make the thickness of the copper layer 0.8 μm.
Next, a photosensitive resin film (negative dry film resist, trade name: M-50B, manufactured by Asahi Kasei Co., Ltd., 15 μm thickness) is applied to the surface of the copper layer flash-etched as described above at 110 ° C. using a laminator. Sticking at a temperature of

Thereafter, an exposure apparatus (manufactured by Ushio Electric Co., Ltd.) using a glass photomask on which output outer lead test patterns having 15 μm pitch width, 18 μm pitch width, and 20 μm pitch width, each having 40 lines each having a length of 20 mm, are drawn. ) Was exposed to ultraviolet light at an output of 180 mJ / cm ² .

After the exposure, development was performed at 30 ° C. for 30 seconds using a 1% sodium carbonate solution to dissolve unexposed portions of the photosensitive resin film, thereby forming a photoresist pattern of each pitch.
Next, using a copper plating solution (CuSO ₄ : 60 g / liter, sulfuric acid: 190 g / liter) to which a copper sulfate plating solution (Rohm and Haas, manufactured by Capper Gream ST-900) was added, Dk = 1. A 9 μm high Cu plating circuit was formed by plating for 17 minutes under the condition of 6 A / dm ² .

Then, in the cupric chloride etchant (CuCl ₂ (140 g / liter) + HCl (57 g / liter) + H ₂ O ₂ : Cu ⁺ = 0.5 g / liter or less) at 40 ° C without peeling off the photoresist pattern The sample was immersed for 90 seconds, and the upper surface of the conductor was etched to a thickness of 5 μm.

Furthermore, after removing the discoloration of the copper surface by etching for 10 seconds with a 30 ° C. microetching solution (mainly 150 g / liter of K ₂ S ₂ O ₈ (potassium persulfate)), the above-mentioned copper sulfate plating solution Was used for 6 minutes under the condition of Dk = 2 A / dm ² to obtain a Cu plating circuit having a height of 8 μm.

Next, the sample was immersed in a 50 ° C. stripping solution containing 2-aminoethanol as a main component for 30 seconds to strip the dry film resist.
Furthermore, it processed for 45 seconds at 35 degreeC using the sulfuric acid + hydrogen peroxide type etching liquid, and the 0.8 micrometer copper layer of the base material was etched away.

  Next, it was treated with a 9% sulfuric acid solution at 55 ° C. for 13 seconds, washed without water and subsequently treated with a mixed solution of 13% sulfuric acid + 13% hydrochloric acid at 55 ° C. for 13 seconds to dissolve the Ni—Cr layer, and the polyimide layer was A predetermined circuit was formed by exposure.

The line width of the 15 μm pitch circuit was 11 μm and the thickness was 7 μm.
As a result of observing the cross section of the conductor, the upper surface of the circuit was a flat shape formed in a slightly arc shape, and a virtual circle corresponding to the shape of the upper surface of the circuit was assumed. However, the arc of the virtual circle having a radius of 22 μm coincides with the arc of the formed copper pattern, and the radius of the virtual circle corresponds to twice the line width of 11 μm.

An electron micrograph of a cross section of the wiring pattern formed on the obtained wiring board is shown in FIG. 5, and a trace diagram of FIG. 5 is shown in FIG.
5 and 6, the wiring pattern clearly has a partition line between the wiring pattern remaining portion formed by dissolving the wiring pattern precursor and copper deposited on the wiring pattern remaining portion. You can see clearly.

  A solder resist layer was formed on the wiring board formed as described above so that the outer leads and inner leads were exposed, and electronic components were mounted on the inner leads to manufacture a circuit board.

  When the circuit board manufactured as described above is incorporated into a liquid crystal display device using a terminal formed on the liquid crystal display device and an anisotropic electric adhesive, the conductivity contained in the anisotropic electric adhesive is The particles established a good electrical connection between the circuit board and the liquid crystal display.

  A 35 μm thick polyimide film (trade name: Upilex, Ube Industries, Ltd.) is formed by sputtering a Ni—Cr (20%) seed layer to a thickness of 250 mm, and copper is added on the seed layer. A 70 mm wide film of two-layer CCL (backside PET attached) plated to a thickness of 3 μm was prepared.

The two-layer CCL was flash-etched with a sulfuric acid + hydrogen peroxide etching solution at 30 ° C. for 40 seconds to make the thickness of the copper layer 0.8 μm.
Next, a photosensitive resin film (negative dry film resist, trade name: M-50B, manufactured by Asahi Kasei Co., Ltd., 15 μm thickness) is applied to the surface of the copper layer flash-etched as described above at 110 ° C. using a laminator. Sticking at a temperature of

Thereafter, an exposure apparatus (manufactured by Ushio Electric Co., Ltd.) using a glass photomask on which output outer lead test patterns having 15 μm pitch width, 18 μm pitch width, and 20 μm pitch width, each having 40 lines each having a length of 20 mm, are drawn. ) Was exposed to ultraviolet light at an output of 180 mJ / cm ² .

After the exposure, development was performed at 30 ° C. for 30 seconds using a 1% sodium carbonate solution to dissolve unexposed portions of the photosensitive resin film, thereby forming a photoresist pattern of each pitch.
Next, using a copper plating solution (CuSO ₄ : 60 g / liter, sulfuric acid: 190 g / liter) to which a copper sulfate plating solution (Rohm and Haas Co., Ltd., Capper Gream ST-900) was added, Dk = 2A / A Cu plating circuit having a height of 8 μm was formed by plating for 12 minutes under the condition of dm ² .

  Thereafter, the sample was immersed in a 30 ° C. microetching solution (150 g / liter, sulfuric acid 10 ml / liter, Cu 3 g / liter) for 90 seconds without removing the photoresist pattern, and the upper surface of the conductor was etched to a thickness of 5 μm.

Furthermore, after removing the discoloration of the copper surface by etching for 10 seconds with a 30 ° C. microetching solution (mainly 150 g / liter of K ₂ S ₂ O ₈ (potassium persulfate)), the above-mentioned copper sulfate plating solution Was used for 6 minutes under the condition of Dk = 2 A / dm ² to obtain a Cu plating circuit having a height of 8 μm.

Next, the sample was immersed in a 50 ° C. stripping solution containing 2-aminoethanol as a main component for 30 seconds to strip the dry film resist.
Furthermore, it processed for 45 seconds at 35 degreeC using the sulfuric acid + hydrogen peroxide type etching liquid, and the 0.8 micrometer copper layer of the base material was etched away.

  Next, it was treated with a 9% sulfuric acid solution at 55 ° C. for 13 seconds, washed without water and subsequently treated with a mixed solution of 13% sulfuric acid + 13% hydrochloric acid at 55 ° C. for 13 seconds to dissolve the Ni—Cr layer, and the polyimide layer was A predetermined circuit was formed by exposure.

The line width of the 15 μm pitch circuit was 10 μm and the thickness was 7 μm.
As a result of observing the cross section of the conductor, the upper surface of the circuit was a flat shape formed in a slightly arc shape, and a virtual circle corresponding to the shape of the upper surface of the circuit was assumed. However, the arc of a virtual circle having a radius of 10.4 to 12.6 μm coincides with the arc of the formed copper pattern, and the radius of this virtual circle is equivalent to 1.04 to 1.26 times the line width of 10 μm. To do. It was found that the wiring pattern formed in this way had an overall cross section close to an ellipse.
[Comparative Example 1]
A 35 μm thick polyimide film (trade name: Upilex, Ube Industries, Ltd.) is formed by sputtering a Ni—Cr (20%) seed layer to a thickness of 250 mm, and copper is added on the seed layer. A 70 mm wide film of two-layer CCL (backside PET attached) plated to a thickness of 3 μm was prepared.

The two-layer CCL was flash-etched with a sulfuric acid + hydrogen peroxide etching solution at 30 ° C. for 40 seconds to make the thickness of the copper layer 0.8 μm.
Next, a photosensitive resin film (negative dry film resist, trade name: M-50B, manufactured by Asahi Kasei Co., Ltd., 15 μm thickness) is applied to the surface of the copper layer flash-etched as described above at 110 ° C. using a laminator. Sticking at a temperature of

Thereafter, an exposure apparatus (manufactured by Ushio Electric Co., Ltd.) using a glass photomask on which output outer lead test patterns having 15 μm pitch width, 18 μm pitch width, and 20 μm pitch width, each having 40 lines each having a length of 20 mm, are drawn. ) Was exposed to ultraviolet light at an output of 180 mJ / cm ² .

After the exposure, development was performed at 30 ° C. for 30 seconds using a 1% sodium carbonate solution to dissolve unexposed portions of the photosensitive resin film, thereby forming a photoresist pattern of each pitch.
Next, using a copper plating solution (CuSO ₄ : 60 g / liter, sulfuric acid: 190 g / liter) to which a copper sulfate plating solution (Rohm and Haas Co., Ltd., Capper Gream ST-900) was added, Dk = 1. A 9 μm high Cu plating circuit was formed by plating for 17 minutes under the condition of 6 A / dm ² .

Next, the sample was immersed in a 50 ° C. stripping solution containing 2-aminoethanol as a main component for 30 seconds to strip the dry film resist.
Furthermore, it processed for 45 seconds at 35 degreeC using the sulfuric acid + hydrogen peroxide type etching liquid, and the 0.8 micrometer copper layer of the base material was etched away.

  Next, it was treated with a 9% sulfuric acid solution at 55 ° C. for 13 seconds, washed without water and subsequently treated with a mixed solution of 13% sulfuric acid + 13% hydrochloric acid at 55 ° C. for 13 seconds to dissolve the Ni—Cr layer, and the polyimide layer was A predetermined circuit was formed by exposure.

The line width of the 15 μm pitch circuit was 10 μm and the thickness was 8 μm.
As a result of observing the cross section of the conductor in the copper pattern having a pitch of 15 μm obtained in this way, the circuit upper surface is formed in an arc shape. Assuming a virtual circle corresponding to the shape of the circuit upper surface, the radius is 6. The arc of the virtual circle of 7 to 7.9 μm coincides with the arc of the formed copper pattern, and the radius of this virtual circle corresponds to 0.67 to 0.79 times the line width of 10 μm.

  The cross section of the wiring board obtained as described above was observed with an electron microscope, but there was no partition line as shown in FIG.

ADVANTAGE OF THE INVENTION According to this invention, a semi-additive method is employ | adopted and the wiring board or circuit board which has a wiring pattern which has a flat cross-sectional form is not provided in the upper surface.
That is, in the present invention, since the semi-additive method is used, a wiring board or circuit board having a wiring pattern having a pitch width (P) of 25 μm or less and a line width of 20 μm or less, which is difficult to manufacture by the subtractive method. The upper surface of the wiring pattern formed on the wiring board or the circuit board matches the curvature of a virtual circle having a radius of 1.0 times or more with respect to the line width (W) of the wiring pattern. To do. Therefore, since the upper surface of the wiring pattern constituting the wiring board or circuit board of the present invention is formed flat, the reliability of the electrical connection is high, and a large number of contacts can be formed at the time of ACF connection, for example. it can.

FIG. 1 is a cross-sectional view showing an example of a cross-section of a wiring pattern at the narrowest portion formed on the wiring board or circuit board of the present invention. FIG. 2 is a cross-sectional view showing an example of a cross-section of a wiring pattern formed by a semi-additive method that has been conventionally performed. FIG. 3 is a cross-sectional view schematically showing a cross section of the substrate in each process when manufacturing the wiring board or circuit board of the present invention. FIG. 4 is a cross-sectional view showing an example of a cross-section of a wiring pattern obtained by directly removing the reverse pattern 19 from FIG. FIG. 5 is an electron micrograph of a cross section of the wiring pattern of the present invention. FIG. 6 is a trace diagram of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Base material layer 11 ... Insulating film 12 ... Base metal layer 13 ... Conductive metal layer 15 ... Photosensitive resin layer 17 ... Mask 19 ... Reverse pattern 20 ..Wiring pattern precursor 21 ... Wiring pattern remaining portion 22 ... Wiring pattern 25 ... Upper surface 30 of wiring pattern ... Virtual circle w ... Line width P ... Pitch width R ... Radius of virtual circle

Claims (17)

  In a wiring board in which a large number of wiring patterns in which a conductive metal is electroformed via a seed layer is formed on the surface of an insulating film, the upper surface of the wiring pattern has a radius of 1.0 times or more the line width of the wiring pattern A wiring board characterized by being coincident with an arc of any one of virtual circles.   2. The wiring board according to claim 1, wherein the wiring pattern has a base metal layer formed by sputtering on the surface of the insulating film.   2. The wiring board according to claim 1, wherein a pitch width of the narrowest portion of the wiring pattern is 25 μm or less and a line width is 20 μm or less.   2. The wiring board according to claim 1, wherein the wiring pattern has a thickness in a range of 3 to 12 μm.   2. The wiring board according to claim 1, wherein an upper surface of the wiring pattern coincides with an arc of any virtual circle having a radius of 1.0 to 80 times the line width of the wiring pattern.   In the longitudinal section of the wiring pattern, there are a wiring pattern remaining portion obtained by removing a part of the wiring pattern precursor formed when the wiring pattern is formed, and a conductive metal deposited on the wiring pattern remaining portion. 2. The wiring board according to claim 1, wherein there is a partition line for partitioning.   In a circuit board in which electronic components are mounted on a wiring board in which a large number of wiring patterns in which a conductive metal is electroformed via a seed layer is formed on the surface of the insulating film, the upper surface of the wiring pattern is A circuit board characterized by being coincident with an arc of any virtual circle having a radius of 1.0 times or more of a line width.   8. The circuit board according to claim 7, wherein the wiring pattern has a base metal layer formed on the surface of the insulating film by sputtering.   8. The circuit board according to claim 7, wherein the pitch width of the narrowest portion of the wiring pattern is 25 [mu] m or less and the line width is 20 [mu] m or less.   8. The circuit board according to claim 7, wherein the upper surface of the wiring pattern coincides with an arc of any virtual circle having a radius of 1.0 to 80 times the line width of the wiring pattern.   In the longitudinal section of the wiring pattern, there are a wiring pattern remaining portion obtained by removing a part of the wiring pattern precursor formed when the wiring pattern is formed, and a conductive metal deposited on the wiring pattern remaining portion. 8. The circuit board according to claim 7, wherein a partition line for partitioning is present.   A reverse pattern having concavities and convexities opposite to the wiring pattern to be formed using a photosensitive resin on the surface of the conductive metal layer of the base material layer in which the base metal layer and the conductive metal layer are formed on the surface of the insulating film Forming a wiring pattern precursor by depositing a conductive metal on the reverse pattern, and then removing a part of the wiring pattern precursor by etching to form a wiring pattern remaining portion, A conductive metal is deposited on the remaining portion and a wiring pattern is electroformed. Then, a reverse pattern made of a photosensitive resin is removed, and the conductive metal layer is removed to make the wiring pattern electrically independent. A method for manufacturing a wiring board.   13. The method for manufacturing a wiring board according to claim 12, wherein the pitch width of the narrowest portion of the wiring pattern is 25 [mu] m or less and the line width is 20 [mu] m or less.   8. The wiring according to claim 7, wherein the upper surface of the formed wiring pattern coincides with an arc of any virtual circle having a radius of 1.0 to 80 times the line width of the wiring pattern. A method for manufacturing a substrate.   A reverse pattern having concavities and convexities opposite to the wiring pattern to be formed using a photosensitive resin on the surface of the conductive metal layer of the base material layer in which the base metal layer and the conductive metal layer are formed on the surface of the insulating film Forming a wiring pattern precursor by depositing a conductive metal on the reverse pattern, and then removing a part of the wiring pattern precursor by etching to form a wiring pattern remaining portion, After the conductive metal was deposited on the remaining portion and the wiring pattern was electroformed, the reverse pattern made of the photosensitive resin was removed, the conductive metal layer was removed, and the wiring pattern was made electrically independent. A circuit board manufacturing method comprising mounting an electronic component on a wiring pattern.   16. The method for manufacturing a circuit board according to claim 15, wherein the narrowest portion of the wiring pattern has a pitch width of 25 [mu] m or less and a line width of 20 [mu] m or less.   16. The circuit according to claim 15, wherein the upper surface of the formed wiring pattern coincides with an arc of any virtual circle having a radius of 1.0 to 80 times the line width of the wiring pattern. A method for manufacturing a substrate.