JP2002246506A - Multilayer printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable multilayer printed wiring board in which electrical connection can be made directly with an IC chip not through a lead component. SOLUTION: An IC chip 20 incorporated in a multilayer printed wiring board 10 is beveled at the corner part 20a thereof. Consequently, even when the multilayer printed wiring board 10 is subjected to heat cycle, stress is not concentrated at the corner part 20a of the IC chip 20. Since stripping of an interlayer insulation layer 50 from a core substrate 30 or the IC chip is prevented and the interlayer insulation layer 50 is protected against cracking in the vicinity of the corner part 20a, reliability of the multilayer printed wiring board 10 can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a build-up multilayer printed wiring board, and more particularly to a multilayer printed wiring board containing electronic components such as IC chips.

[0002]

2. Description of the Related Art IC chips are manufactured by wire bonding,
The electrical connection with the printed wiring board has been established by a mounting method such as TAB or flip chip. Wire bonding is to bond the IC chip to the printed wiring board with an adhesive and connect the pad of the printed wiring board and the pad of the IC chip with a wire such as a gold wire, and then to protect the IC chip and the wire. To a sealing resin such as a thermosetting resin or a thermoplastic resin. In TAB, after a wire called a lead is collectively connected between a bump of an IC chip and a pad of a printed wiring board by soldering or the like, sealing with resin is performed. The flip chip has been performed by connecting an IC chip and a pad portion of a printed wiring board via a bump, and filling a gap between the bump and the resin with a resin.

[0003]

However, in each mounting method, an electrical connection is made between the IC chip and the printed wiring board via a connecting lead component (wire, lead, bump). Each of those lead parts
They are easily cut and corroded, which may cause the connection with the IC chip to be interrupted or malfunction.

The inventor of the present invention has built in an IC chip in a multilayer printed wiring board, so that the IC chip can be used without using lead components.
It has been devised to establish an electrical connection between the C chip and the multilayer printed wiring board. In other words, an opening, a through hole, and a counterbore portion are provided in a resin insulating substrate, and electronic components such as an IC chip are built in in advance, an interlayer insulating layer is laminated, and photo-etching or laser is applied on a pad of the IC chip. After forming a via hole and forming a conductive circuit that is a conductive layer,
Furthermore, a structure was devised in which a multilayer printed wiring board was provided by repeating an interlayer insulating layer and a conductive layer.

However, it has been found that in the structure incorporating the IC chip, peeling and cracking occur in the interlayer insulating layer disposed above the IC chip, thereby lowering the reliability.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to enable direct electrical connection to an IC chip without using a lead component, and to achieve high reliability. It is an object of the present invention to propose a multilayer printed wiring board having the same.

[0007]

Means for Solving the Problems The present inventor has found that peeling and cracking of the interlayer insulating layer occur near the corner of the IC chip. For this reason, it was found that peeling and cracking were caused by stress concentration at the corners of the IC chip, and the endurance test was performed by chamfering the corners of the four sides of the IC chip. Delamination in layers,
Cracks no longer occur. In other words, it has been found that high reliability can be obtained by chamfering the IC chip.

Preferably, a transition layer is provided on the pad of the IC chip. The reason is as follows. The pads of the IC chip are generally made of aluminum or the like. When via holes in the interlayer insulating layer were formed by photoetching with the die pad having no transition layer formed thereon, the resin was likely to remain on the surface of the pad after exposure and development if the die pad was still formed. In addition, the adhesion of the developing solution caused discoloration of the pad. On the other hand, even when a via hole was formed by a laser, if the process was performed under the condition that the die pad was not burnt, resin residue was left on the pad. In the post-process,
When immersed in an acid, an oxidizing agent or an etching solution, or subjected to various annealing processes, discoloration of the pads of the IC chip,
Dissolution occurred. Further, the pad of the IC chip is 40 μm.
The diameter of the via hole is about m, and the via hole is larger than that.

On the other hand, by providing a transition layer made of copper or the like on the die pad, it becomes possible to use a solvent and prevent resin residue on the pad. Also,
No discoloration or dissolution of the pad occurs even when the pad is immersed in an acid, an oxidizing agent, or an etching solution in a later step, or undergoes various annealing steps. This improves the connectivity and reliability between the pad and the via hole. Further, the via hole can be reliably connected by interposing a transition layer having a diameter larger than 40 μm on the pad of the IC chip. Desirably, the transition layer has a diameter equal to or greater than the diameter of the via hole.

[0010] Each of them can function only by a multilayer printed wiring board. However, in some cases, in order to make it function as a package substrate as a semiconductor device, it has to be connected to an external substrate such as a motherboard or a daughter board.
GAs, solder bumps or PGAs (conductive connection pins) may be provided. In addition, with this configuration, the wiring length can be made shorter than in the case where the connection is made by the conventional mounting method, and the loop inductance can be reduced.

[0011] The resin substrate in which electronic components such as IC chips used in the present invention are incorporated may be a resin in which a reinforcing material such as a glass epoxy resin or a core material is impregnated into an epoxy resin, a BT resin, a phenol resin, or the like, or an epoxy resin. A laminate of prepregs impregnated with is used, but those generally used for printed wiring boards can be used. In addition, a double-sided copper-clad laminate, a single-sided plate, a resin plate having no metal film, and a resin sheet can be used. However, if a temperature of 350 ° C. or more is applied, the resin will melt and carbonize.

A cavity for accommodating an electronic component such as an IC chip on a resin insulating substrate such as a core substrate or the like in which a counterbore, a through hole, and an opening are formed is bonded to the electronic component with an adhesive or the like. Physical vapor deposition such as vapor deposition or sputtering is performed on the entire surface of the core substrate in which the IC chip is built to form a conductive metal film on the entire surface. The metals include tin, chromium, titanium, nickel, zinc, cobalt, gold,
It is preferable to form one or more layers of a metal such as copper. The thickness is preferably between 0.001 and 2.0 μm. In particular, 0.01 to 1.0 μm is desirable. In particular,
It is good to form with nickel, chromium, and titanium. This is because there is no penetration of moisture from the interface and the metal adhesion is excellent.

The metal film is thickened by electroless or electrolytic plating. Examples of the type of plating formed include copper, nickel, gold, silver, zinc, and iron. It is preferable to use copper because the electrical characteristics, economy, and the conductor layer, which is a build-up formed later, are mainly copper. The thickness is preferably in the range of 1 to 20 μm.
If the thickness is larger than that, an undercut occurs at the time of etching, and a gap may be generated at the interface between the formed transition layer and the via hole. afterwards,
An etching resist is formed, exposed and developed to expose portions of the metal other than the transition layer, and etching is performed to form a transition layer on the pads of the IC chip.

The transition layer defined in the present invention will be described. The transition layer means an intermediate mediation layer provided for directly connecting an IC chip as a semiconductor element and a printed wiring board without using a conventional IC chip mounting technique. It is characterized in that it is formed of two or more metal layers and is larger than a die pad of an IC chip as a semiconductor element. Thereby, electrical connection and alignment are improved, and via holes can be formed by laser or photoetching without damaging the die pad. Therefore, embedding, accommodation, accommodation, and connection of the IC chip in the printed wiring board can be ensured. In addition, it is possible to directly form a metal which is a conductor layer of a printed wiring board on the transition layer.
Examples of the conductor layer include via holes in an interlayer resin insulating layer and through holes on a substrate.

In addition to the above-described method of manufacturing the transition layer, a dry film resist is formed on a metal film formed on an IC chip and a core substrate, and a portion corresponding to the transition layer is removed. After thickening, the resist can be peeled off, and a transition layer can be similarly formed on the pad of the IC chip using an etching solution.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] First, a multilayer printed wiring board 1 according to a first embodiment of the present invention will be described.
This will be described with reference to FIG.

As shown in FIG. 7, the multilayer printed wiring board 10
Comprises a core substrate 30 for accommodating the IC chip 20, an interlayer resin insulation layer 50, and an interlayer resin insulation layer 150. Via holes 60 and conductive circuits 58 are formed in interlayer resin insulating layer 50, and via holes 160 and conductive circuits 158 are formed in interlayer resin insulating layer 150.

The IC chip 20 is covered with a passivation film 24, and a die pad 22 constituting an input / output terminal is provided in an opening of the passivation film 24. A transition layer 38 mainly made of copper is formed on the pad 22.

On the interlayer resin insulating layer 150, a solder resist layer 70 is provided. The conductor circuit 158 below the opening 71 of the solder resist layer 70 is provided with a solder bump 76 for connecting to an external board (not shown) such as a daughter board or a mother board.

In the multi-layer printed wiring board 10 of the present embodiment, the IC chip 20 is built in the core substrate 30 in advance.
A transition layer 38 is provided on the pad 22 of the IC chip 20. Therefore, the electrical connection between the IC chip and the multilayer printed wiring board (package substrate) can be established without using a lead component or a sealing resin.

IC built in multilayer printed wiring board 10
FIG. 1B shows a plan view of the chip 20. Four corners 20a of the IC chip 20 are chamfered and formed in a semicircular shape. Therefore, even when the multilayer printed wiring board 10 is subjected to a heat cycle, the corners 20 of the IC chip 20 are not affected.
No stress is concentrated at a. Therefore, near the corner 20a, the core substrate 30 and the interlayer resin insulation layer 50,
The peeling of the IC chip from the interlayer resin insulating layer 50 and the occurrence of cracks in the interlayer resin insulating layer 50 can be prevented, and the reliability of the multilayer printed wiring board 10 can be improved. Note that, as shown in FIG.
Instead of forming 0a in a semicircular shape, as shown in FIG. 1C, the corner 20a is cut and the IC chip 20 is made octagonal, so that stress concentration at the corner 20a can be prevented. .

The multilayer printed wiring board of this embodiment is an IC
Since the transition layer 38 is formed in the chip portion, the IC chip portion is flattened. Therefore, the upper interlayer insulating layer 50 is also flattened and the film thickness becomes uniform.
Furthermore, the transition layer can maintain the shape stability even when the upper via hole 60 is formed.

Further, by providing a copper transition layer 38 on the die pad 22, resin residue on the pad 22 can be prevented. Also, in a later step, the resin can be immersed in an acid, an oxidizing agent, an etching solution, or the like. Discoloration and dissolution of the pad 22 do not occur even after various annealing processes. This improves the connectivity and reliability between the pads of the IC chip and the via holes. Further, by interposing the transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm, a via hole having a diameter of 60 μm can be reliably connected.

Next, a method of manufacturing the multilayer printed wiring board described above with reference to FIG. 7 will be described with reference to FIGS.

(1) First, the multi-piece IC chip shown in FIG. 1 (A) is cut into individual pieces as shown in FIG. 1 (B) by dicing, and the corners 20a are formed into a semicircular shape by polishing. To bevel. (2) On the other hand, an insulating resin substrate (core substrate) 30 in which a prepreg obtained by impregnating a resin such as epoxy into a core material such as a glass cloth is prepared as a starting material (see FIG. 2A). Next, an IC is formed on one surface of the core substrate 30 by counterboring.
A recess 32 for accommodating a chip is formed (see FIG. 2B). Here, the concave portion is formed by counterboring, but a core substrate having an accommodating portion can be formed by laminating an insulating resin substrate having an opening and a resin insulating substrate having no opening.

(3) Thereafter, an adhesive material 34 is applied to the recess 32 using a printing machine. At this time, besides coating,
Potting may be performed. Next, the IC chip 20
Is placed on the adhesive material 34 (see FIG. 2C).

(4) Then, the upper surface of the IC chip 20 is pushed or hit and completely accommodated in the recess 32 (see FIG. 2D). Thereby, the core substrate 30 can be smoothed.

(5) Thereafter, physical vapor deposition such as vapor deposition or sputtering is performed on the entire surface of the core substrate 30 accommodating the IC chip 20 to form a conductive metal film 33 on the entire surface (FIG. 3A). ). As the metal, it is preferable to form one or more layers of a metal such as tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper. As the thickness,
The thickness is preferably between 0.0001 and 2.0 μm, particularly preferably between 0.01 and 1.0 μm.

A plating film 36 may be formed on the metal film 33 by electroless plating (FIG. 3B). Examples of the type of plating formed include copper, nickel, gold, silver, zinc, and iron. It is preferable to use copper because the electrical characteristics, economy, and the conductor layer, which is a build-up formed later, are mainly copper. The thickness is preferably in the range of 1 to 20 μm.

(6) After that, a resist is applied, exposed,
After development, a plating resist 35 is provided so as to provide an opening above the pad of the IC chip, and electroless plating is performed to provide an electroless plating film 37 (FIG. 3C). After the plating resist 35 is removed, the transition layer 38 is formed on the pads 22 of the IC chip by removing the electroless plating film 36 and the metal film 33 under the plating resist 35 (FIG. 3D). Here, the transition layer is formed by a plating resist, but after an electrolytic plating film is uniformly formed on the electroless plating film 36, an etching resist is formed, and exposure and development are performed to form a metal layer in a portion other than the transition layer. It is also possible to form a transition layer on the pad of the IC chip by exposing the substrate and etching. In this case, the thickness of the electrolytic plating film is preferably in the range of 1 to 15 μm. If the thickness is larger than that, an undercut occurs at the time of etching, and a gap may be generated at the interface between the formed transition layer and the via hole.

(7) Next, a roughened surface 38α is formed by spraying an etching solution onto the substrate by spraying and etching the surface of the transition layer 38 (FIG. 4A).
reference).

(8) The substrate having undergone the above-described steps is provided with a thickness of 50 μm.
The thermosetting resin sheet having a thickness of m is vacuum-press-laminated at a pressure of 5 kg / cm ² while the temperature is raised to a temperature of 50 to 150 ° C. to provide an interlayer resin insulating layer 50 (see FIG. 4B). The degree of vacuum during vacuum compression is 10 mmHg.

(9) Next, using a CO ₂ gas laser having a wavelength of 10.4 μm, a beam diameter of 5 mm, a top hat mode,
Under the conditions of a pulse width of 5.0 μsec, a mask hole diameter of 0.5 mm, and one shot, a via hole opening 48 having a diameter of 80 μm is provided in the interlayer resin insulating layer 50 (see FIG. 4C). The residual resin in the opening 48 is removed using chromic acid. By providing the copper transition layer 38 on the die pad 22, resin residue on the pad 22 can be prevented, thereby improving the connectivity and reliability between the pad 22 and via holes 60 described later. Further, by interposing a transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm, the opening 48 for a via hole having a diameter of 60 μm is formed.
Can be reliably connected. Here, the resin residue is removed using chromic acid, but desmearing can be performed using oxygen plasma.

(10) Next, a roughened surface 50α of the interlayer resin insulating layer 50 is provided by dipping in an oxidizing agent such as chromic acid or permanganate (see FIG. 4D).
The roughened surface 50α is preferably formed in a range of 0.1 to 5 μm. As an example, a roughened surface 50α of 2 to 3 μm is provided by immersing in a sodium permanganate solution 50 g / l at a temperature of 60 ° C. for 5 to 25 minutes.
Other than the above, SV-454 manufactured by Japan Vacuum Engineering Co., Ltd.
By performing a plasma treatment using 0, a roughened surface 50α can be formed on the surface of the interlayer resin insulating layer 50. On this occasion,
Argon gas is used as the inert gas, and power 200
Plasma treatment is performed for 2 minutes under the conditions of W, gas pressure of 0.6 Pa, and temperature of 70 ° C.

(9) A metal layer 52 is provided on the interlayer resin insulating layer 50 on which the roughened surface 50α is formed (see FIG. 5A). The metal layer 52 is formed by electroless plating. By applying a catalyst such as palladium to the surface layer of the interlayer resin insulating layer 50 in advance, and immersing it in the electroless plating solution for 5 to 60 minutes, the metal layer 52 as a plating film is provided in a range of 0.1 to 5 μm. As one example, [aqueous electroless plating solution] NiSO ₄ 0.003 mol / l tartaric acid 0.200 mol / l copper sulfate 0.030 mol / l HCHO 0.050 mol / l NaOH 0.100 mol / l α, α '-Bipirdyl 100 mg / l Polyethylene glycol (PEG) 0.10 g / l Dipped at a liquid temperature of 34 ° C for 40 minutes. Other than the above, after replacing the argon gas inside using the same apparatus as the above-described plasma processing, sputtering using Ni and Cu as targets was performed at a pressure of 0.6 Pa, a temperature of 80 ° C., and a power of 2
00W for 5 minutes, and the Ni / Cu metal layer 5
2 can be formed on the surface of the interlayer resin insulation layer 50. At this time, the thickness of the formed Ni / Cu metal layer 52 is 0.2 μm.

(12) A commercially available photosensitive dry film is affixed to the substrate 30 that has been subjected to the above processing, a photomask film is placed, and after exposure at 100 mJ / cm ² ,
Develop with 0.8% sodium carbonate to provide a plating resist 54 having a thickness of 15 μm. Next, electrolytic plating is performed under the following conditions to form an electrolytic plated film 56 having a thickness of 15 μm (see FIG. 5B). The additive in the aqueous electrolytic plating solution was Capparaside HL manufactured by Atotech Japan.
It is.

[Aqueous electrolytic plating solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive (captoside HL, manufactured by Atotech Japan) 19.5 ml / l [Electroplating conditions] Current density 1 A / dm ² Time 65 minutes Temperature 22 ± 2 ℃

(13) Plating resist 54 is made of 5% NaO
After stripping and removing with H, the metal layer 5 under the plating resist is removed.
2 is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and the metal layer 52 and the electrolytic plating film 56 are removed.
A conductor circuit 58 having a thickness of 16 μm and a via hole 60 are formed, and roughened surfaces 58α and 60α are formed using an etching solution containing a cupric complex and an organic acid (see FIG. 5C). The roughened surface can be formed by using electroless plating or oxidation-reduction treatment.

(14) Next, the above steps (8) to (13) are repeated to form an upper interlayer resin insulation layer 150 and a conductor circuit 158 (including via holes 160) (FIG. 6 ( A)).

(15) Next, a cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) so as to have a concentration of 60% by weight was used. Oligomer for imparting properties (molecular weight 4000) 46.67
15 parts by weight of a bisphenol A type epoxy resin (trade name: Epicoat 1001 manufactured by Yuka Shell Co., Ltd.) of 80% by weight dissolved in methyl ethyl ketone, imidazole hardener (trade name: 2E4MZ-CN)
1.6 parts by weight, 3 parts by weight of a polyfunctional acrylic monomer (manufactured by Kyoei Chemical Co., trade name: R604) as a photosensitive monomer,
Similarly, polyvalent acrylic monomer (manufactured by Kyoei Chemical Co., Ltd., trade name:
1.5 parts by weight of DPE6A) and 0.71 part by weight of a dispersant antifoaming agent (manufactured by San Nopco, trade name: S-65) are placed in a container, stirred and mixed to prepare a mixed composition. Of benzophenone (manufactured by Kanto Kagaku) and 0.2 parts by weight of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to give a viscosity of 25.
A solder resist composition (organic resin insulating material) adjusted to 2.0 Pa · s at ° C is obtained. The viscosity was measured using a B-type viscometer (DVL-B type, manufactured by Tokyo Keiki Co., Ltd.) at 60 rpm and rotor No. 4 at 6 rpm.
According to In addition, a commercially available solder resist can be used as the solder resist.

(16) Next, the above-mentioned solder resist composition is applied to the substrate 30 at a thickness of 30 μm,
After performing a drying process at 70 ° C. for 30 minutes for 0 minute, a 5 mm-thick photomask on which a pattern of the opening of the solder resist resist is drawn is brought into close contact with the solder resist layer 70, and an ultraviolet ray of 1000 mJ / cm ² is applied. And developing with a DMTG solution to form an opening 71 having a diameter of 200 μm (see FIG. 6B).

(17) Next, the substrate on which the solder resist layer (organic resin insulating layer) 70 is formed is coated with nickel chloride (2.3 × 10 ^-1 mol / l) and sodium hypophosphite (2.8 × 10 ^-1 mol / l) and an electroless nickel plating solution having a pH of 4.5 containing sodium citrate (1.6 × 10 ^-1 mol / l) for 20 minutes.
Then, a nickel plating layer 72 having a thickness of 5 μm is formed. Further, the substrate was subjected to potassium gold cyanide (7.6 × 10 ^−3).
mol / l), ammonium chloride (1.9 × 10 ^-1 mo)
1 / l), sodium citrate (1.2 × 10 ^-1 mol)
/ L), sodium hypophosphite (1.7 × 10 ^-1 mol)
/ L) is immersed for 7.5 minutes at 80 ° C. in an electroless plating solution containing
By forming the gold plating layer 74 of the length m, the conductor circuit 158 can be formed.
Then, a solder pad 75 is formed (see FIG. 6C).

(18) Thereafter, the solder resist layer 70
A solder paste is printed in the opening 71 of the substrate and reflowed at 200 ° C. to form a solder bump.
Thereby, the IC chip 20 is built in and the solder bump 76
Can be obtained (see FIG. 7).

In the above embodiment, the interlayer resin insulating layer 5
Thermosetting resin sheets were used for Nos. 0 and 150. The thermosetting resin sheet resin contains a hardly soluble resin, soluble particles, a curing agent, and other components. Each is described below.

In the thermosetting resin sheet used in the production method of the first embodiment, particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble particles”) are made of a resin hardly soluble in an acid or an oxidizing agent (hereinafter referred to as a hardly soluble resin). (Referred to as resin). Note that the terms "sparingly soluble" and "soluble" used in the first embodiment mean that those having a relatively high dissolution rate when immersed in a solution containing the same acid or oxidizing agent for the same time are referred to as "soluble" for convenience. Those having a relatively low dissolution rate are referred to as "poorly soluble" for convenience.

Examples of the soluble particles include resin particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble resin particles”), inorganic particles soluble in an acid or oxidizing agent (hereinafter referred to as “soluble inorganic particles”), and acid or oxidizing agents. Soluble metal particles (hereinafter referred to as “soluble metal particles”) and the like. These soluble particles may be used alone or in combination of two or more.

The shape of the soluble particles is not particularly limited.
Spherical, crushed and the like. The shape of the soluble particles is desirably a uniform shape. This is because a roughened surface having unevenness with a uniform roughness can be formed.

The average particle size of the above-mentioned soluble particles is 0.1.
1 to 10 μm is desirable. Within this particle size range, 2
More than one kind of particles having different particle sizes may be contained. That is, it contains soluble particles having an average particle size of 0.1 to 0.5 μm and soluble particles having an average particle size of 1 to 3 μm.
Thereby, a more complicated roughened surface can be formed,
Excellent adhesion to conductor circuits. In addition, in 1st Embodiment, the particle size of a soluble particle is the length of the longest part of a soluble particle.

Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like. When immersed in a solution containing an acid or an oxidizing agent, the soluble resin particles have a higher dissolution rate than the hardly soluble resin. If it is, there is no particular limitation. Specific examples of the soluble resin particles include, for example, those made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin, and the like, and may be made of one of these resins. Alternatively, it may be composed of a mixture of two or more resins.

As the soluble resin particles, resin particles made of rubber can also be used. Examples of the rubber include polybutadiene rubber, various modified polybutadiene rubbers such as epoxy-modified, urethane-modified, (meth) acrylonitrile-modified, and (meth) acrylonitrile-butadiene rubber containing a carboxyl group. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. In other words, when dissolving the soluble resin particles using an acid, an acid other than a strong acid can be dissolved, and when dissolving the soluble resin particles using an oxidizing agent, permanganese having a relatively weak oxidizing power is used. Acid salts can also be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, the acid or the oxidizing agent does not remain on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after forming the roughened surface, the catalyst is not applied or the catalyst is oxidized. Or not.

Examples of the soluble inorganic particles include particles made of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds and silicon compounds.

Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and
Examples of the potassium compound include potassium carbonate.Examples of the magnesium compound include magnesia, dolomite, and basic magnesium carbonate.Examples of the silicon compound include silica and zeolite. Is mentioned. These may be used alone or in combination of two or more.

Examples of the soluble metal particles include, for example,
Copper, nickel, iron, zinc, lead, gold, silver, aluminum,
Examples include particles made of at least one selected from the group consisting of magnesium, calcium, and silicon. These soluble metal particles may have a surface layer coated with a resin or the like in order to ensure insulation.

When two or more of the above-mentioned soluble particles are used in combination, the combination of the two types of soluble particles to be mixed is preferably a combination of resin particles and inorganic particles. Both have low conductivity, so that the insulation of the resin sheet can be ensured, and the thermal expansion can be easily adjusted with the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin sheet. This is because peeling does not occur between the interlayer resin insulating layer and the conductor circuit.

The hardly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed using an acid or an oxidizing agent in the interlayer resin insulating layer. Examples thereof include thermosetting resins, thermoplastic resins, and composites thereof. Further, a photosensitive resin obtained by imparting photosensitivity to these resins may be used. By using a photosensitive resin, an opening for a via hole can be formed in an interlayer resin insulating layer by using exposure and development processes. Among these, those containing a thermosetting resin are desirable. Thereby, the shape of the roughened surface can be maintained even by the plating solution or various heat treatments.

Specific examples of the hardly soluble resin include, for example, epoxy resin, phenol resin, phenoxy resin,
Examples thereof include a polyimide resin, a polyphenylene resin, a polyolefin resin, and a fluorine resin. These resins may be used alone or in combination of two or more. Further, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the above-described roughened surface be formed, but also excellent in heat resistance, etc., even under heat cycle conditions, stress concentration does not occur in the metal layer, and peeling of the metal layer does not easily occur. Because.

Examples of the epoxy resin include cresol novolak epoxy resin, bisphenol A epoxy resin, bisphenol F epoxy resin, phenol novolak epoxy resin, alkylphenol novolak epoxy resin, biphenol F epoxy resin, and naphthalene epoxy resin. Resin, dicyclopentadiene type epoxy resin, epoxidized product of condensate of phenols and aromatic aldehyde having phenolic hydroxyl group,
Triglycidyl isocyanurate, alicyclic epoxy resin and the like. These may be used alone or in combination of two or more. Thereby, it becomes excellent in heat resistance and the like.

In the resin sheet used in the first embodiment, it is preferable that the soluble particles are substantially uniformly dispersed in the hardly-soluble resin. It is possible to form a roughened surface with unevenness of uniform roughness, and even if via holes and through holes are formed in the resin sheet, it is possible to secure the adhesion of the metal layer of the conductor circuit formed thereon. Because you can. Alternatively, a resin sheet containing soluble particles only in the surface layer forming the roughened surface may be used. Thereby, since the portions other than the surface layer of the resin sheet are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulating layer is reliably maintained.

In the above resin sheet, the amount of the soluble particles dispersed in the poorly soluble resin is preferably 3 to 40% by weight based on the resin sheet. If the amount of the soluble particles is less than 3% by weight, a roughened surface having desired irregularities may not be formed.
When the soluble particles are dissolved using an acid or an oxidizing agent, they dissolve to the deep part of the resin sheet, failing to maintain the insulation between the conductor circuits via the interlayer resin insulation layer made of the resin sheet, and causing a short circuit. It may be.

The resin sheet desirably contains a curing agent, other components, and the like in addition to the soluble particles and the poorly soluble resin. Examples of the curing agent include imidazole-based curing agents, amine-based curing agents, guanidine-based curing agents, epoxy adducts of these curing agents and those obtained by microencapsulating these curing agents, triphenylphosphine, and tetraphenylphosphonate. Organic phosphine-based compounds such as ammonium tetraphenylborate.

The content of the curing agent is desirably 0.05 to 10% by weight based on the resin sheet. 0.0
If the content is less than 5% by weight, the resin sheet is insufficiently cured, so that the degree of penetration of acid or oxidizing agent into the resin sheet becomes large, and the insulating property of the resin sheet may be impaired. On the other hand, when the content exceeds 10% by weight, an excessive curing agent component may modify the composition of the resin, which may cause a decrease in reliability.

Examples of the other components include fillers such as inorganic compounds or resins which do not affect the formation of the roughened surface. As the inorganic compound, for example,
Examples of the resin include silica, alumina, and dolomite. Examples of the resin include a polyimide resin, a polyacryl resin, a polyamideimide resin, a polyphenylene resin, a melanin resin, and an olefin resin. By incorporating these fillers, the performance of the multilayer printed wiring board can be improved by matching thermal expansion coefficients, improving heat resistance and chemical resistance, and the like.

Further, the resin sheet may contain a solvent. Examples of the solvent include ketones such as acetone, methyl ethyl ketone and cyclohexanone, ethyl acetate, butyl acetate, aromatic hydrocarbons such as cellosolve acetate, toluene and xylene. These may be used alone or in combination of two or more. However, these interlayer resin insulation layers are dissolved and carbonized when a temperature of 350 ° C. or more is applied.

Next, a multilayer printed wiring board according to a first modification of the first embodiment will be described with reference to FIG. In the first embodiment described above, the case where the BGA is provided has been described. The first modified example is almost the same as the first embodiment, but is configured as a PGA system in which connection is made via conductive connection pins 96 as shown in FIG.

Next, a multilayer printed wiring board according to a second modification of the first embodiment will be described with reference to FIG.
In the first embodiment described above, the IC chip is accommodated in the recess 32 provided in the core substrate 30 with a counterbore. On the contrary,
In the second modification, the through holes 32 formed in the core
The C chip 20 is accommodated. In this second modification, I
Since the heat sink can be directly attached to the back surface of the C chip 20, there is an advantage that the IC chip 20 can be efficiently cooled.

Next, a multilayer printed wiring board according to a third modification of the first embodiment will be described with reference to FIG. In the above-described first embodiment, the transition layer 38 is formed on the pad 22 of the IC chip 20, and the via hole 6 of the interlayer resin insulating layer 50 is formed in the transition layer 38.
0 was connected. On the other hand, in the third modification, the via hole 60 is directly connected to the pad 22 without providing a transition layer. The third modification can reduce the number of steps as compared with the first embodiment, and thus has an advantage that it can be configured at a low cost.

Next, a multilayer printed wiring board according to a fourth modification of the first embodiment will be described with reference to FIG. In the first embodiment described above, the IC chip is accommodated in the multilayer printed wiring board. On the other hand, in the fourth modification, the IC chip 20 is housed in the multilayer printed wiring board, and the IC chip 120 is mounted on the surface. A cache memory that generates a relatively small amount of heat is used as the built-in IC chip 20, and an arithmetic CPU is mounted as the IC chip 120 on the front surface.

The pad 22 of the IC chip 20 and the pad 124 of the IC chip 120 are connected to the transition layer 38-
Via hole 60-Conductor circuit 58-Via hole 160
-Conductor circuit 158-connected via solder bump 76U. On the other hand, the pads 124 of the IC chip 120 and the pads 92 of the daughter board 90 are connected to the solder bumps 76U-
Conductor circuit 158-Via hole 160-Conductor circuit 58-
Via hole 60-Through hole 136-Via hole 60-Conductor circuit 58-Via hole 160-Conductor circuit 1
58-connected via solder bumps 76U.

In the fourth modification, the IC chip 120 and the cache memory 20 can be arranged close to each other while manufacturing the cache memory 20 with a low yield separately from the CPU IC chip 120. Can operate at high speed. In the fourth modification, an electronic component such as an IC chip having a different function can be mounted by incorporating the IC chip and mounting the IC chip on the surface, thereby obtaining a higher-performance multilayer printed wiring board. Can be.

[Second Embodiment] A multilayer printed wiring board according to a second embodiment of the present invention will be described with reference to the drawings.
In the above-described first embodiment, the transition layer is provided after the IC chip is mounted on the core substrate. On the contrary,
In the second embodiment, a transition layer is provided on an IC chip and then mounted on a core substrate.

As shown in FIG. 20, the multilayer printed wiring board 10 of the second embodiment comprises a core substrate 30 for accommodating an IC chip 20, an interlayer resin insulation layer 50, and an interlayer resin insulation layer 150.
Consists of In the interlayer resin insulation layer 50, the via hole 6
0 and the conductor circuit 58 are formed, and the interlayer resin insulation layer 15 is formed.
At 0, a via hole 160 and a conductor circuit 158 are formed.

On the interlayer resin insulation layer 150, a solder resist layer 70 is provided. The conductor circuit 158 below the opening 71 of the solder resist layer 70 is provided with a solder bump 76 for connecting to an external board (not shown) such as a daughter board or a mother board.

The multilayer printed wiring board 1 according to the second embodiment
FIG. 14A showing a cross section of the semiconductor element 20 with respect to the configuration of the semiconductor element (IC chip) housed in the semiconductor chip 20;
This will be described with reference to FIG.

As shown in FIG.
A die pad 22 and a wiring (not shown) are provided on the upper surface of the substrate, and a passivation film 24 is coated on the die pad 22 and the wiring, and an opening of the passivation film 24 is formed in the die pad 22. Have been.
On the die pad 22, a transition layer 38 mainly made of copper is formed. Transition layer 38
Comprises a thin film layer 33 and an electrolytic plating film 37.

In the multilayer printed wiring board 10 of the present embodiment, the IC chip 20 is built in the core
A transition layer 38 is provided on the pad 22 of the C chip 20. Therefore, the electrical connection between the IC chip and the multilayer printed wiring board (package substrate) can be established without using a lead component or a sealing resin. Further, since the transition layer 38 is formed in the IC chip portion, the IC chip portion is flattened, so that the upper interlayer insulating layer 50 is also flattened and the film thickness becomes uniform. Further, the transition layer allows the upper via hole 6 to be formed.
Even when 0 is formed, the stability of the shape can be maintained.

Further, by providing the copper transition layer 38 on the die pad 22, the resin residue on the pad 22 can be prevented, and it can be immersed in an acid, an oxidizing agent, an etching solution, or the like in a later step. Discoloration and dissolution of the pad 22 do not occur even after various annealing processes. This improves the connectivity and reliability between the pads of the IC chip and the via holes. Further, by interposing the transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm, a via hole having a diameter of 60 μm can be reliably connected.

As shown in FIG. 15B, the IC chip 20
Are chamfered to form a semicircle. Therefore, even when the multilayer printed wiring board 10 is subjected to a cold heat cycle, the corners 2
No stress is concentrated at 0a. For this reason, the core substrate 30 and the interlayer resin insulating layer 5 near the corner 20a.
0, peeling of the IC chip and the interlayer resin insulation layer 50, and
The occurrence of cracks in the interlayer resin insulation layer 50 can be prevented, and the reliability of the multilayer printed wiring board 10 can be improved.

Next, a method of manufacturing the multilayer printed wiring board described above with reference to FIG. 20 will be described with reference to FIGS. First, a method for manufacturing the semiconductor device described above with reference to FIG. 14B will be described with reference to FIGS.

(1) First, a wiring 21 and a die pad 22 are formed on a silicon wafer 20A shown in FIG. 12A by a conventional method (FIG. 15B showing a plan view of FIG. 12B and FIG. A), and FIG. 12B shows a BB cross section of FIG. 15A). (2) Next, a passivation film 24 is formed on the die pad 22 and the wiring 21, and an opening 24a is provided on the die pad 22 (FIG. 12C).

(3) By performing physical vapor deposition such as vapor deposition and sputtering on the silicon wafer 20A, a conductive metal film (thin film layer) 33 is formed on the entire surface (FIG. 13).
(A)). The thickness is preferably in the range of 0.001 to 2.0 μm. If it is below the range, a thin film layer cannot be formed on the entire surface. If it is higher than this range, the thickness of the formed film will vary. The optimal range is from 0.01 to 1.0 μm. Metals to be formed include tin, chromium, titanium, nickel,
It is preferable to use one selected from zinc, cobalt, gold, and copper. These metals serve as a protective film for the die pad and do not degrade the electrical characteristics. In the second embodiment, the thin film layer 33 is formed of chromium.

(4) Thereafter, a resist layer of any of a liquid resist, a photosensitive resist, and a dry film is formed on the thin film layer 33. A mask (not shown) on which a portion for forming the transition layer 38 is drawn is placed on the resist layer, and exposed and developed, and the plating resist 35 is formed.
To form a non-formed portion 35a. Thick layer (electrolytic plating film) on the non-formed portion 35a of the resist layer by applying electrolytic plating
37 are provided (FIG. 13B). Examples of the type of plating formed include copper, nickel, gold, silver, zinc, and iron. Since the electrical characteristics, economy, and the conductor layer, which is a build-up formed later, are mainly made of copper, copper is preferably used. In the second embodiment, copper is used. The thickness is preferably in the range of 1 to 20 μm.

(5) After the plating resist 35 is removed with an alkaline solution or the like, the metal film 33 under the plating resist 35 is coated with sulfuric acid-hydrogen peroxide, ferric chloride, cupric chloride, cupric complex-organic By removing with an etching solution such as an acid salt, the transition layer 38 is formed on the pad 22 of the IC chip.
Is formed (FIG. 13C).

(6) Next, a roughened surface 38α is formed by spraying an etching solution on the substrate by spraying and etching the surface of the transition layer 38 (FIG. 14).
(A)). The roughened surface can be formed by using electroless plating or oxidation-reduction treatment.

(7) Finally, the silicon wafer 20A on which the transition layer 38 is formed is divided into individual pieces by dicing or the like, and the semiconductor elements 20 are formed by chamfering the four-sided corners 20a in a semicircular shape. (Fig. 14
(B) and FIG. 15 (B) which is a plan view of FIG. 14 (B)). Then, if necessary, the divided semiconductor elements 2
An operation check of 0 or an electrical inspection may be performed. Since the semiconductor element 20 has the transition layer 38 larger than the die pad 22, the probe pins can be easily applied to the semiconductor element 20, and the inspection accuracy is high.

In the semiconductor device according to the second embodiment described above with reference to FIG.
8 has a two-layer structure including the thin film layer 33 and the electrolytic plating film 37. On the other hand, the transition layer may have a three-layer structure including a thin film layer (first thin film layer), an electroless plating film (second thin film layer), and an electrolytic plating film (thickened layer). In the case of a three-layer structure, a second thin film layer is laminated on the first thin film layer 33 by sputtering, vapor deposition, and electroless plating. The thickness is preferably 0.01 to 5 μm, and particularly preferably 0.1 to 3.0 μm. In this case, the metal that can be laminated is preferably selected from nickel, copper, gold, and silver.

In the above-described example, the transition layer 38 is formed by forming the thickening layer 37 in the non-resist forming portion by using the semi-additive process. On the other hand, it is also possible to form the transition layer 38 by forming a thick layer 37 uniformly using a full additive process, providing a resist, and removing the resist non-formed portion by etching.

Next, a description will be given of a process of manufacturing a multilayer printed wiring board containing the above-described IC chip 20. (1) A starting material is a 0.5 mm-thick insulating resin substrate 30A obtained by laminating and curing a prepreg in which a core material such as glass cloth is impregnated with a resin such as BT (bismaleimide triazine) resin or epoxy. First, a through hole 32 for accommodating an IC chip is formed in the insulating resin substrate 30A (FIG. 16A).
reference). Here, a resin substrate 3 in which a core material is impregnated with resin is used.
Although 0A is used, a resin substrate having no core material may be used. In addition, it is preferable to provide a taper 32 a at the upper end opening of the through hole 32. By the taper 32a, it is possible to eliminate the groove of the filling resin generated in the cavity edge portion in the laminating step described later. In addition, flatness can be ensured.

(2) Thereafter, the IC chip 2 described above with reference to FIG.
0 (see FIG. 16B).

(3) Then, the insulating resin substrate 30A accommodating the IC chip 20 and a prepreg impregnated with a core material such as glass cloth or a resin such as BT or epoxy are laminated and cured to a thickness of 0%. .2 mm insulating resin substrate (core substrate) 30B and an uncured prepreg 30C in which a core material such as glass cloth is impregnated with a resin such as epoxy.
(Thickness: 0.1 mm)
(C)). Here, the resin substrate 30B in which the core material is impregnated with the resin is used, but a resin substrate having no core material may be used. Further, instead of the prepreg, various thermosetting resins or a sheet obtained by impregnating a core material with a thermosetting resin and a thermoplastic resin can be used.

(4) Stainless steel (SUS) press plate 10
At 0A and 100B, the above-described laminate is pressed from above and below. At this time, the epoxy resin 3 is removed from the prepreg 30C.
Oα exudes and fills the space between the through hole 32 and the IC chip 20 and covers the upper surface of the IC chip 20. Thereby, the upper surfaces of the IC chip 20 and the insulating resin substrate 30A become completely flat. (FIG. 16D). For this reason, when forming the build-up layer in a step described later, the via hole and the wiring can be appropriately formed, and the reliability of the wiring of the multilayer printed wiring board can be improved.
The pressure and / or temporary curing is preferably performed under reduced pressure. By reducing the pressure, the IC chip 20, the insulating resin substrate 3
0A, between the prepreg 30C and the resin substrate 30B, and
No air bubbles remain in the prepreg 30C, and the reliability of the multilayer printed wiring board can be improved.

(5) Thereafter, the core substrate 30 accommodating the IC chip 20 is formed by heating and curing the uncured epoxy resin 30α (FIG. 16E). This main curing is preferably performed under reduced pressure. By reducing the pressure, no bubbles remain in the prepreg 30C,
The reliability of the multilayer printed wiring board can be improved.

(6) A substrate having a thickness of 50 μm
m of the same thermosetting resin sheet as in the first embodiment at a temperature of 5
Vacuum compression lamination is performed at a pressure of 5 kg / cm ² while increasing the temperature to 0 to 150 ° C. to provide an interlayer resin insulation layer 50 (FIG. 1).
7 (A)). The degree of vacuum during vacuum pressure bonding is 10 mmHg
It is.

(7) Next, a via hole opening 48 having a diameter of 60 μm is formed in the interlayer resin insulating layer 50 by a CO ₂ gas laser having a wavelength of 10.4 μm (see FIG. 17B). The residual resin in the opening 48 is removed using chromic acid. By providing the copper transition layer 38 on the die pad 22, resin residue on the pad 22 can be prevented, thereby improving the connectivity and reliability between the pad 22 and via holes 60 described later. Further, by interposing a transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm, the opening 48 for a via hole having a diameter of 60 μm is formed.
Can be reliably connected.

(8) Next, the surface of the interlayer resin insulating layer 50 is roughened with permanganic acid to form a roughened surface 50α (FIG. 1).
7 (C)).

(9) Next, a metal layer 52 is formed on the surface of the interlayer resin insulating layer 50 as in the first embodiment (FIG. 18).
(A)).

(10) A commercially available photosensitive dry film is affixed to the substrate 30 that has been subjected to the above processing, a photomask film is placed, and after exposure at 100 mJ / cm ² ,
Develop with 0.8% sodium carbonate to provide a plating resist 54 having a thickness of 20 μm. Next, electrolytic plating is performed under the same conditions as in the first embodiment to form an electrolytic plated film 56 having a thickness of 15 μm (see FIG. 18B).

(11) The plating resist 54 is made of 5% NaO
After stripping and removing with H, the metal layer 5 under the plating resist is removed.
2 is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and the metal layer 52 and the electrolytic plating film 56 are removed.
A conductor circuit 58 having a thickness of 16 μm and a via hole 60 are formed, and roughened surfaces 58α and 60α are formed using an etching solution containing a cupric complex and an organic acid (see FIG. 18C). In the present embodiment, as described above with reference to FIG. 16E, since the upper surface of the core substrate 30 is formed completely smooth, it is possible to appropriately connect to the transition layer 38 by the via hole 60. it can. For this reason, it is possible to improve the reliability of the multilayer printed wiring board.

(12) Then, the above steps (6) to (11) are repeated to form a further upper interlayer resin insulation layer 150 and a conductor circuit 158 (including the via hole 160) (FIG. 19 ( A)).

(13) Next, a solder resist composition (organic resin insulating material) is obtained in the same manner as in the first embodiment.

(14) Next, the above-mentioned solder resist composition is applied to the substrate 30 at a thickness of 20 μm,
After performing a drying process at 70 ° C. for 30 minutes for 0 minutes, a 5 mm-thick photomask on which a pattern of the opening of the solder resist resist is drawn is brought into close contact with the solder resist layer 70, and an ultraviolet ray of 1000 mJ / cm ² is applied. And developing with a DMTG solution to form an opening 71 having a diameter of 200 μm (see FIG. 19B).

(15) Next, the thickness 5 is formed in the opening 71 of the substrate on which the solder resist layer (organic resin insulating layer) 70 is formed.
A μm nickel plating layer 72 is formed. Further, a gold plating layer 7 having a thickness of 0.03 μm is formed on the nickel plating layer 72.
4, the solder pad 75 is formed on the conductive circuit 158.
Is formed (see FIG. 19C).

(16) Thereafter, the solder resist layer 70
The solder paste is printed on the opening 71 of
To form the solder bumps 76. Thereby, the multilayer printed wiring board 10 having the IC chip 20 built-in and having the solder bumps 76 can be obtained (see FIG. 20).

[Third Embodiment] Next, the configuration of a multilayer printed wiring board according to a third embodiment will be described. FIG.
As shown in FIG. 6, the multilayer printed wiring board 10 of the third embodiment
Is the I of the second embodiment described above with reference to FIG.
It comprises a heat sink 30D on which the C chip 20 is mounted, a core substrate 31 for accommodating the IC chip 20, and an interlayer resin insulating layer 50 and an interlayer resin insulating layer 150 on the IC chip 20. Via holes 60 and conductor circuits 58 are formed in the interlayer resin insulation layer 50, and
Via holes 160 and conductive circuits 158 are formed.

On the interlayer resin insulating layer 150, a solder resist layer 70 is provided. The conductor circuit 158 below the opening 71 of the solder resist layer 70 is provided with a solder bump 76 for connecting to an external board (not shown) such as a daughter board or a mother board.

The heat sink 30D is made of a ceramic such as aluminum nitride, alumina or mullite, or a metal such as an aluminum alloy, copper, or adjacent bronze. Here, it is preferable to use an aluminum alloy having a high thermal conductivity or a copper foil subjected to a roughening treatment on both surfaces. In the present embodiment, the heat sink 30D is attached to the back surface of the IC chip 20 embedded in the core substrate 31, so that the IC chip 2
0 is released to prevent the core substrate 31 and the interlayer resin insulating layers 50 and 150 formed on the core substrate from warping, and to form via holes 60 and 160 on the interlayer resin insulating layer.
Disconnection of the conductor circuits 58 and 158 is prevented. Thereby, the reliability of the wiring is improved.

Note that the IC chip 20 is
OD is attached by a conductive adhesive 29.
The conductive adhesive 29 contains metal powder such as copper, gold, silver, and aluminum in a resin and has high thermal conductivity, so that heat generated in the IC chip 20 is efficiently released to the heat sink 30D side. be able to. Here, a conductive adhesive is used for attaching the IC chip 20, but various adhesives can be used as long as the adhesive has high thermal conductivity.

In the multilayer printed wiring board 10 of the present embodiment, the IC chip 20 is built in the core
A transition layer 38 is provided on the pad 22 of the C chip 20. Therefore, the electrical connection between the IC chip and the multilayer printed wiring board (package substrate) can be established without using a lead component or a sealing resin. Further, since the transition layer 38 is formed in the IC chip portion, the IC chip portion is flattened, so that the upper interlayer insulating layer 50 is also flattened and the film thickness becomes uniform. Further, the transition layer allows the upper via hole 6 to be formed.
Even when 0 is formed, the stability of the shape can be maintained.

Further, by providing a copper transition layer 38 on the die pad 22, resin residue on the pad 22 can be prevented, and it can be immersed in an acid, an oxidizing agent, an etching solution, or the like in a later step. Discoloration and dissolution of the pad 22 do not occur even after various annealing processes. This improves the connectivity and reliability between the pads of the IC chip and the via holes. Further, by interposing the transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm, a via hole having a diameter of 60 μm can be reliably connected.

Also, as in the second embodiment, the IC chip 2
The corners 20a of the four sides of 0 are chamfered and formed in a semicircular shape. Therefore, even when the multilayer printed wiring board 10 is subjected to a heat cycle, the corners 20 a
Does not concentrate the stress. Therefore, the corner 2
0a, the core substrate 30 and the interlayer resin insulation layer 50, I
Separation of the C chip from the interlayer resin insulating layer 50 and occurrence of cracks in the interlayer resin insulating layer 50 can be prevented, and the reliability of the multilayer printed wiring board 10 can be improved.

Subsequently, a method of manufacturing the multilayer printed wiring board described above with reference to FIG. 26 will be described with reference to FIGS.

(1) A plate-like heat sink 30D made of ceramic such as aluminum nitride, alumina, mullite, or an aluminum alloy, adjacent bronze, etc. (FIG. 21A)
Then, a conductive adhesive 29 is applied (FIG. 21B). As the conductive adhesive, a paste containing copper particles having an average particle diameter of 2 to 5 μm and having a thickness of 10 to 20 μm was used.

(2) The IC chip 20 according to the second embodiment is mounted (FIG. 21C).

(3) Next, the heat sink 30D to which the IC chip 20 is attached is placed on a stainless (SUS) press plate 100A. Then, a prepreg laminate 31α having a thickness of 0.5 mm formed by laminating an uncured prepreg obtained by impregnating a core material such as a glass cloth with a resin such as a BT (bismaleimide triazine) resin or an epoxy resin is used as a heat sink 3.
0D (FIG. 22A). Prepreg laminate 3
In 1α, a through hole 32 is provided in advance at the position of the IC chip 20. Here, the prepreg in which the core material is impregnated with the resin is used, but a resin substrate having no core material may be used. Further, instead of the prepreg, various thermosetting resins or a sheet obtained by impregnating a core material with a thermosetting resin and a thermoplastic resin can be used.

(4) Stainless steel (SUS) press plate 10
At 0A and 100B, the above-described laminate is pressed from above and below. At this time, the epoxy resin 3
1β exudes and fills the space between the through hole 32 and the IC chip 20 and covers the upper surface of the IC chip 20. Thereby, the IC chip 20 and the prepreg laminate 31α
Is completely flattened. (FIG. 22 (B)). For this reason, when forming a build-up layer in a process described below,
Via holes and wiring can be properly formed, and the reliability of wiring of a multilayer printed wiring board can be improved. Note that, as in the second embodiment, by performing depressurization and pressurization and / or temporary curing, air bubbles can be prevented from being mixed, and the reliability of the multilayer printed wiring board can be increased.

(5) Thereafter, the core substrate 31 accommodating the IC chip 20 is formed by heating and curing the epoxy resin of the prepreg (FIG. 22C). In addition,
Similarly to the second embodiment, by performing the curing under reduced pressure, it is possible to prevent air bubbles from being mixed and to increase the reliability of the multilayer printed wiring board.

(6) A substrate having a thickness of 50 μm
m of the same thermosetting resin sheet as in the first embodiment at a temperature of 5
Vacuum compression lamination is performed at a pressure of 5 kg / cm ² while the temperature is raised to 0 to 150 ° C. to provide an interlayer resin insulating layer 50 (see FIG. 23A). The degree of vacuum during vacuum compression is 10 mmH
g.

(7) Next, a via hole opening 48 having a diameter of 60 μm is formed in the interlayer resin insulating layer 50 by a CO ₂ gas laser having a wavelength of 10.4 μm (see FIG. 23B). The residual resin in the opening 48 is removed using chromic acid. By providing the copper transition layer 38 on the die pad 22, resin residue on the pad 22 can be prevented, thereby improving the connectivity and reliability between the pad 22 and via holes 60 described later. Further, by interposing a transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm, the opening 48 for a via hole having a diameter of 60 μm is formed.
Can be reliably connected.

(8) Next, the surface of the interlayer resin insulating layer 50 is roughened with permanganic acid to form a roughened surface 50α (FIG. 2).
3 (C)).

(9) Next, the metal layer 52 is formed on the surface of the interlayer resin insulation layer 50 as in the first embodiment (FIG. 24).
(A)).

(10) A commercially available photosensitive dry film is adhered to the substrate 30 that has been subjected to the above processing, a photomask film is placed, and after exposure at 100 mJ / cm ² ,
Develop with 0.8% sodium carbonate to provide a plating resist 54 having a thickness of 15 μm. Next, electrolytic plating is performed under the same conditions as in the first embodiment to form an electrolytic plated film 56 having a thickness of 15 μm (see FIG. 24B).

(11) Plating resist 54 is made of 5% NaO
After stripping and removing with H, the metal layer 5 under the plating resist is removed.
2 is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, and the metal layer 52 and the electrolytic plating film 56 are removed.
A conductor circuit 58 having a thickness of 16 μm and a via hole 60 are formed, and roughened surfaces 58α and 60α are formed using an etching solution containing a cupric complex and an organic acid (see FIG. 24C). In the present embodiment, as described above with reference to FIG. 22C, since the upper surface of the core substrate 31 is formed completely smooth, it is possible to appropriately connect to the transition layer 38 by the via hole 60. it can. For this reason, it is possible to improve the reliability of the multilayer printed wiring board.

(12) Next, the above steps (6) to (11) are repeated to form an upper interlayer resin insulation layer 150 and a conductor circuit 158 (including via holes 160) (FIG. 25 ( A)).

(13) Next, a solder resist composition (organic resin insulating material) similar to that of the first embodiment is obtained.

(14) Next, the above-mentioned solder resist composition is applied on the substrate 30 to a thickness of 20 μm,
After performing a drying process at 70 ° C. for 30 minutes for 0 minutes, a 5 mm-thick photomask on which a pattern of the opening of the solder resist resist is drawn is brought into close contact with the solder resist layer 70, and an ultraviolet ray of 1000 mJ / cm ² is applied. And developing with a DMTG solution to form an opening 71 having a diameter of 200 μm (see FIG. 25B).

(15) Next, a thickness 5 is formed in the opening 71 of the substrate on which the solder resist layer (organic resin insulating layer) 70 is formed.
A μm nickel plating layer 72 is formed. Further, by forming a gold plating layer 74 on the nickel plating layer 72, a solder pad 75 is formed on the conductor circuit 158 (FIG. 2).
5 (C)).

(16) Thereafter, the solder resist layer 70
A solder paste is printed in the opening 71 of the substrate and reflowed at 200 ° C. to form a solder bump.
Finally, the heat sink 30D is divided into individual pieces by dicing or the like to obtain the multilayer printed wiring board 10.
6).

[First Comparative Example] As a first comparative example, a multilayer printed wiring board was formed in the same manner as in the first embodiment. However, the corners of the IC chip were not chamfered.

[Second Comparative Example] As a second comparative example, a multilayer printed wiring board was formed in the same manner as in the second embodiment. However, the corners of the IC chip were not chamfered.

[Third Comparative Example] As a third comparative example, a multilayer printed wiring board was formed in the same manner as in the third embodiment. However, the corners of the IC chip were not chamfered.

After the heat cycle of the multilayer printed wiring boards of the first, second, and third embodiments and the multilayer printed wiring boards of the first, second, and third comparative examples was performed, The results of evaluating the occurrence of peeling and cracks are shown in the table of FIG. In the first, second, and third embodiments, peeling and cracking did not occur in the interlayer resin insulating layer. However, in the first, second, and third comparative examples, peeling and cracking occurred in the interlayer resin insulating layer. .

[0131]

As described above, in the multilayer printed wiring board of the present invention, since the corners of the IC chip are chamfered, stress is not concentrated at the corners of the IC chip, and peeling at the interlayer insulating layer is prevented. Cracks can be eliminated and high reliability can be obtained.

[Brief description of the drawings]

FIG. 1A is a plan view of a multi-piece IC chip before cutting, and FIGS. 1B and 1C are plan views of a chamfered and divided IC chip.

FIGS. 2A, 2B, 2C, and 2D are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 3A, 3B, 3C, and 3D are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 4A, 4B, 4C, and 4D are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 5A, 5B, and 5C are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 6A, 6B, and 6C are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 7 is a sectional view of the multilayer printed wiring board according to the first embodiment.

FIG. 8 is a sectional view of a multilayer printed wiring board according to a modification of the first embodiment of the first embodiment.

FIG. 9 is a sectional view of a multilayer printed wiring board according to a second modification of the first embodiment.

FIG. 10 is a cross-sectional view of a multilayer printed wiring board according to a third modification of the first embodiment.

FIG. 11 is a cross-sectional view of a multilayer printed wiring board according to a fourth modification of the first embodiment.

FIGS. 12A, 12B, and 12C are manufacturing process diagrams of an IC chip housed in a multilayer printed wiring board according to a second embodiment of the present invention.

FIGS. 13A, 13B, and 13C are manufacturing process diagrams of an IC chip housed in a multilayer printed wiring board according to a second embodiment of the present invention.

FIGS. 14A and 14B are manufacturing process diagrams of an IC chip housed in a multilayer printed wiring board according to a second embodiment of the present invention.

FIG. 15A is a plan view of a silicon wafer according to a second embodiment of the present invention, and FIG. 15B is a plan view of a singulated semiconductor element.

FIG. 16 (A), (B), (C), (D), (E)
FIG. 7 is a manufacturing process diagram of the multilayer printed wiring board according to the second embodiment of the present invention.

FIGS. 17 (A), (B), and (C) are manufacturing process diagrams of the multilayer printed wiring board according to the second embodiment of the present invention.

FIGS. 18A, 18B, and 18C are manufacturing process diagrams of the multilayer printed wiring board according to the second embodiment of the present invention.

FIGS. 19A, 19B, and 19C are manufacturing process diagrams of the multilayer printed wiring board according to the second embodiment of the present invention.

FIG. 20 is a sectional view of a multilayer printed wiring board according to a second embodiment of the present invention.

FIGS. 21 (A), (B), and (C) are manufacturing process diagrams of a multilayer printed wiring board according to a third embodiment of the present invention.

FIGS. 22A, 22B, and 22C are manufacturing process diagrams of the multilayer printed wiring board according to the third embodiment of the present invention.

FIGS. 23A, 23B, and 23C are manufacturing process diagrams of the multilayer printed wiring board according to the third embodiment of the present invention.

FIGS. 24A, 24B, and 24C are manufacturing process diagrams of the multilayer printed wiring board according to the third embodiment of the present invention.

FIGS. 25A, 25B, and 25C are manufacturing process diagrams of the multilayer printed wiring board according to the third embodiment of the present invention.

FIG. 26 is a sectional view of a multilayer printed wiring board according to a third embodiment of the present invention.

FIG. 27 is a table showing evaluation results of each embodiment and a comparative example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 20 IC chip 20 a corner 22 pad 24 passivation film 30 core substrate 30 D heat sink 32 recess 36 resin layer 38 transition layer 50 interlayer resin insulation layer 58 conductive circuit 60 via hole 70 solder resist layer 76 solder bump 90 daughter board 96 conductive connection pin 97 Conductive adhesive 150 Interlayer resin insulation layer 158 Conductor circuit 160 Via hole

Claims (3)

[Claims] 1. A multilayer printed wiring board in which an interlayer insulating layer and a conductor layer are repeatedly formed on a substrate, a via hole is formed in the interlayer insulating layer, and electrically connected via the via hole. A multilayer printed wiring board, wherein an IC chip with four corners chamfered is built in the substrate. 2. The multilayer printed wiring board according to claim 1, wherein the corner is chamfered in a semicircular shape. 3. The multilayer printed wiring board according to claim 1, wherein a transition is formed on a die pad of the IC chip.