JP2002246500A - Multilayer printed wiring board and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To propose a multilayer printed wiring board, incorporating a semiconductor device for improving electric connectivity and reliability. SOLUTION: A resin substrate 130 having a small thermal coefficient of expansion is placed on the surface layer of a printed wiring board 10, and a solder bump 76 is provided on a resin substrate 130. In the solder bump 76, that is held between a daughter board 230 having a small thermal coefficient of expansion and the resin substrate 130, stress due to thermal expansion is not concentrated, thus preventing omission and misalignment in the solder bump 76, and improving the electric connectivity and reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a build-up multilayer printed wiring board, and more particularly to a multilayer printed wiring board containing electronic components such as IC chips.

[0002]

2. Description of the Related Art IC chips are manufactured by wire bonding,
The electrical connection with the printed wiring board has been established by a mounting method such as TAB or flip chip. Wire bonding is to bond the IC chip to the printed wiring board with an adhesive and connect the pad of the printed wiring board and the pad of the IC chip with a wire such as a gold wire, and then to protect the IC chip and the wire. To a sealing resin such as a thermosetting resin or a thermoplastic resin. In TAB, after a wire called a lead is collectively connected between a bump of an IC chip and a pad of a printed wiring board by soldering or the like, sealing with resin is performed. The flip chip has been performed by connecting an IC chip and a pad portion of a printed wiring board via a bump, and filling a gap between the bump and the resin with a resin.

[0003]

However, in each mounting method, an electrical connection is made between the IC chip and the printed wiring board via a connecting lead component (wire, lead, bump). Each of those lead parts
They are easily cut and corroded, which may cause the connection with the IC chip to be interrupted or malfunction. Also,
In each mounting method, sealing is performed with a thermoplastic resin such as an epoxy resin to protect the IC chip. However, if the resin is filled with air bubbles, the air bubbles become a starting point, and the lead component becomes Damage, IC pad corrosion,
This leads to a decrease in reliability. For sealing with thermoplastic resin, it is necessary to create a resin loading plunger and mold according to each part, and even for thermosetting resin, consider materials such as lead parts and solder resist Since it is necessary to select a suitable resin, the cost of each resin is also increased.

Therefore, various techniques for embedding a semiconductor element in a substrate have been proposed. Japanese Patent Application Laid-Open No. 9-32140 discloses a technique for establishing electrical connection by embedding a semiconductor element in a substrate and forming a build-up layer thereon.
No. 8 (US Pat. No. 5,875,100), JP-A-10-2564
No. 29, JP-A-11-126978 and the like have been proposed.

[0005] JP-A-9-321408 (USP587)
No. 5100), a semiconductor element having a stud bump formed on a die pad is built in a printed wiring board, and wiring is formed on the stud bump to establish electrical connection. However, there is a problem in the connectivity due to the large variation in the height of the stud bumps. In addition, these stud bumps are planted one by one by bonding, which has a problem in productivity.

In Japanese Patent Application Laid-Open No. Hei 10-256429, a semiconductor element is built in a ceramic substrate, and electrical connection is made in a flip-chip form. However, ceramics have poor external formability and do not fit well in semiconductor elements. In addition, there is a problem in the connectivity due to a large variation in the height of the bumps.

In Japanese Patent Application Laid-Open No. H11-126978, a semiconductor element is built in an accommodating portion of a gap of a multilayer printed wiring board stored via a via hole, and is connected to a conductor circuit. However, since the housing portion is a gap, it is likely to cause positional displacement, and there is a problem in connectivity. Further, since the die pad and the conductor circuit are directly connected, there is a problem that an oxide film is easily formed on the die pad and the insulation resistance is increased.

On the other hand, when a multilayer printed wiring board composed of a substrate in which a semiconductor element is embedded, accommodated, and accommodated is used as a package substrate, a chip set, or the like, an external substrate (a so-called motherboard or a daughter board) is electrically connected. The function can be exhibited by connecting. For this reason, a solder bump is provided on the surface of the solder resist layer of the multilayer printed wiring board so that the multilayer printed wiring board is connected to an external substrate.

However, when a solder bump is provided on a surface layer of a substrate in which a semiconductor element is embedded and electrically connected to an external substrate to perform a function test or a reliability test, an interlayer insulating layer, a solder resist layer, an interlayer Cracks and peeling occurred around the resin insulating layer, the solder resist, the solder bumps, and the solder bumps (intended to be a solder layer and a corrosion-resistant metal, etc.). The reason why these solder bumps are broken is that the core substrate and the external substrate in which the semiconductor element is embedded have a small expansion due to thermal expansion because they contain a core material such as glass cloth, and the interlayer resin insulation layer without the core material has thermal expansion. The elongation is large. That is, stress is concentrated on solder bumps between the external substrate and the interlayer resin insulating layer due to a large difference in thermal expansion between the core substrate and the external substrate in which the semiconductor element is embedded and the interlayer resin insulating layer. is there. Therefore, in a multilayer printed wiring board having a built-in semiconductor element, it has become clear that the electrical connectivity and the reliability between the solder bumps and the conductor circuits are reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to propose a multilayer printed wiring board in which a semiconductor element having high electrical connectivity and high reliability is incorporated. With the goal.

[0011]

In order to achieve the above-mentioned object, in the multilayer printed wiring board according to the first aspect, a semiconductor element is embedded and an interlayer insulating layer and a conductor layer are formed on a substrate accommodated or accommodated. In the multilayer printed wiring board which is repeatedly formed and in which the via holes are formed in the interlayer insulating layer and are electrically connected through the via holes, a resin substrate having a core material on the uppermost interlayer insulating layer is formed. It is a technical feature that an external connection terminal for mounting and connecting to an external substrate is provided on the resin substrate having the core material.

According to the first aspect of the present invention, a resin substrate having a core material is placed on an interlayer resin insulating layer of a multilayer printed wiring board, and connected to the external substrate via external connection terminals on the resin substrate. I do. External connection terminal is BGA / PGA
(Conductive connecting pin). In other words, by mounting a resin substrate having a low thermal expansion on an interlayer resin insulating layer having a high thermal expansion, an external connection terminal is provided between a resin substrate having a core material and a low thermal expansion coefficient and an external substrate such as a daughter board. Since the external connection terminals are arranged, peeling and cracks occurring around the external connection terminals can be prevented, and the external connection terminals can be prevented from falling off or displaced, and the electrical connectivity and reliability can be improved.

According to a second aspect of the present invention, in the multilayer printed wiring board according to the first aspect, a pad portion of the semiconductor element is connected to the via hole formed in the lowermost interlayer insulating layer. It is a technical feature that a transition layer is formed.

According to the second aspect of the present invention, the transition layer is formed so as to cover the pads of the semiconductor element.
The reason for providing the transition layer on the die pad of the IC chip is as follows. A die pad of an IC chip is generally made of aluminum or the like. When via holes in the interlayer insulating layer were formed by photoetching with the die pad having no transition layer formed thereon, the resin was likely to remain on the surface of the die pad after exposure and development if the die pad was left as it was. In addition, the adhesion of the developer caused discoloration of the die pad. On the other hand, in the case of laser, when the via diameter is larger than the die pad diameter,
The die pad and passivation (IC protective film) are destroyed by the laser. Further, in a later step, when the substrate is immersed in an acid, an oxidizing agent, or an etching solution, or undergoes various annealing steps, discoloration and dissolution of the die pad of the IC chip occur. Furthermore, the die pad of the IC chip is 20 to 60.
Since the via hole is formed with a diameter of about μm and the via hole is larger than that, disconnection is likely to occur when the position is shifted.

On the other hand, by providing a transition layer made of copper or the like on the die pad, it is possible to use a solvent and prevent resin residue on the die pad. Further, discoloration and dissolution of the die pad do not occur even when the die pad is immersed in an acid, an oxidizing agent, or an etchant at the time of a post process, or undergoes various annealing processes. Prevents formation of oxide film on die pad. Thereby, the connectivity and reliability between the die pad and the via hole are improved. Further, the via hole can be reliably connected by interposing a transition layer having a diameter larger than 20 μm on the die pad of the IC chip. Desirably, the transition layer has a diameter equal to or greater than the diameter of the via hole.

Further, by forming a transition layer larger than the pad, the inspection probe pins can be easily contacted, and the inspection can be performed easily. That is, since the inspection can be performed before or after the semiconductor element is incorporated in the substrate, it is possible to determine in advance whether the product is acceptable. Therefore, productivity can be improved and costs can be reduced. That is, it can be said that the semiconductor element including the transition layer is a semiconductor element for embedding, housing, and housing the printed wiring board.

The transition layer defined in the present invention will be described. The transition layer means an intermediate layer provided for directly connecting an IC chip as a semiconductor element and a printed wiring board. As a feature, the thin film layer is formed on the die pad, and a thick layer is formed thereon. The thin film layer is formed of at least two or more metal layers. And it is made larger than the die pad of the IC chip which is a semiconductor element. Thereby, electrical connection and alignment are improved, and via holes can be formed by laser or photoetching without damaging the die pad. Therefore, embedding, accommodation, accommodation, and connection of the IC chip into the printed wiring board can be ensured. Further, it is possible to directly form a metal which is a conductor circuit of a printed wiring board on the transition layer. Examples of the conductor circuit include a via hole in an interlayer insulating layer and a through hole on a substrate.

The transition layer is formed as follows. A conductive metal film (first thin film layer) is formed on the entire surface of the IC chip by vapor deposition, sputtering, or the like. As the metal, nickel, zinc, chromium, cobalt, titanium, gold, tin, iron and the like are preferable. The thickness is preferably between 0.001 and 2.0 μm. If it is less than 0.001 μm, it cannot be uniformly laminated on the entire surface. It was difficult to form a layer having a thickness exceeding 2.0 μm, and the effect was not enhanced. In the case of chromium, a thickness of 0.1 μm is desirable. 0.01-1.0 μm
Is more desirable.

With the first thin film layer, the die pad is covered, and the adhesion between the transition layer and the IC chip at the interface with the die pad can be improved. In addition, by covering the die pad with these metals, it is possible to prevent moisture from entering the interface, prevent dissolution and corrosion of the die pad, and improve reliability. Further, the first thin film layer allows connection with an IC chip by a lead-free mounting method. Here, it is desirable to use chromium, nickel, and titanium in order to prevent moisture from entering the interface.

On the first thin film layer, sputtering, vapor deposition, or
A second thin film layer is formed by electroless plating. The metal includes nickel, copper, gold, silver and the like. Electrical properties,
It is preferable to use copper because it is economical and the thick layer to be formed later is mainly copper.

The reason why the second thin film layer is provided here is that the first thin film layer cannot take a lead for electrolytic plating for forming a thick layer described later. The second thin film layer 36 is used as a thick lead. The thickness is preferably in the range of 0.01 to 5 μm. 0.01
If it is less than 5 μm, it cannot serve as a lead,
If it exceeds m, the lower first thin film layer will be shaved more during etching to form a gap, moisture will easily enter, and the reliability will be reduced. Combinations of chromium-copper, chromium-nickel, titanium-copper, and titanium-nickel are preferred. It is superior to other combinations in terms of bonding to metals and electrical conductivity.

On the second thin film layer, it is thickened by electroless or electrolytic plating. Examples of the type of metal formed include copper, nickel, gold, silver, zinc, and iron. Electrical characteristics, economy, strength and structural resistance as a transition layer, and since the conductor layer, which is a build-up formed later, is mainly copper, it is desirable to form it by electrolytic plating using copper . The thickness is preferably in the range of 1 to 20 μm. If it is thinner than 1 μm, the reliability of connection with the upper via hole is reduced. Because. Further, depending on the case, thick plating may be performed directly on the first thin film layer, or a multilayer may be further laminated.

Thereafter, an etching resist is formed,
Exposure and development are performed to expose portions of the metal other than the transition layer and to perform etching, thereby forming a transition layer including a first thin film layer, a second thin film layer, and a thick layer on the die pad of the IC chip.

In addition to the above-described method of manufacturing the transition layer, after a metal film formed on an IC chip is thickened by electrolytic plating, a dry film resist is formed to remove portions other than those corresponding to the transition layer. Thus, a transition layer can be formed on the die pad. Furthermore, after attaching the IC chip to the core substrate, a transition layer can be formed on the die pad of the IC chip in the same manner.

The transition layer defined in the present invention will be described. The transition layer means an intermediate mediation layer provided for directly connecting an IC chip as a semiconductor element and a printed wiring board without using a conventional IC chip mounting technique. It is characterized in that it is formed of two or more metal layers and is larger than a die pad of an IC chip as a semiconductor element. Thereby, electrical connection and alignment are improved, and via holes can be formed by laser or photoetching without damaging the die pad. Therefore, embedding, accommodation, accommodation, and connection of the IC chip in the printed wiring board can be ensured. In addition, it is possible to directly form a metal which is a conductor layer of a printed wiring board on the transition layer.
Examples of the conductor layer include via holes in an interlayer resin insulating layer and through holes on a substrate.

The method for manufacturing a multilayer printed wiring board according to claim 3 is characterized by including at least the following steps (a) to (e): (a) embedding a semiconductor element in a core substrate; b) a step of repeatedly forming an interlayer insulating layer having a via hole and a conductor layer on the core substrate accommodating or accommodating the semiconductor element; and (c) forming a conductor circuit vertically penetrating a resin substrate having a core material. Forming; (d) attaching the resin substrate on the uppermost interlayer insulating layer of the core substrate so that the via holes of the interlayer insulating layer are connected to the conductor circuits of the resin substrate; A) forming an external connection terminal on the resin substrate so as to be connected to the conductor circuit penetrating the resin substrate;

According to a third aspect of the present invention, a resin substrate having a small thermal expansion is mounted on an interlayer resin insulating layer having a large thermal expansion, so that a resin substrate having a core material and a small thermal expansion coefficient can be connected to an external substrate such as a daughter board. Since the external connection terminals are placed between the external connection terminals, peeling and cracking around the external connection terminals can be prevented, and the external connection terminals can be prevented from dropping or dislocating, improving electrical connectivity and reliability. Can be improved.

According to a fourth aspect of the present invention, the resin substrate is mounted on the interlayer insulating layer of the core substrate with an adhesive, so that the resin substrate can be firmly mounted on the interlayer insulating layer.

According to a fifth aspect of the present invention, in the step of forming a conductor circuit vertically penetrating a resin substrate having a core material, a laser beam penetrates from the side where the copper foil is not stretched to the copper foil on the single-sided copper-clad laminate. The conductor circuit is formed in the through-hole by forming a hole and passing an electric current through the copper foil to deposit electrolytic plating. For this reason, a fine conductor circuit can be formed with high reliability.

According to a sixth aspect of the present invention, in the step of forming a conductor circuit vertically penetrating a resin substrate having a core material, an opening is formed in one copper foil of the double-sided copper-clad laminate by etching, and the opening of the copper foil is formed. Is used as a conformal mask, and a laser is irradiated to form a through hole reaching the copper foil on the side where no opening is provided, and the conductive circuit is formed by plating in the through hole. For this reason, a fine conductor circuit can be formed with high reliability.

In the present invention, when the conductor circuit is formed in the through hole, the conductor circuit is projected from the through hole. Therefore, the conductive circuit can be appropriately connected to the via hole of the interlayer insulating layer or the conductive circuit with the adhesive interposed therebetween.

[0032]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] First, a multilayer printed wiring board 1 according to a first embodiment of the present invention will be described.
This will be described with reference to FIGS.

As shown in FIG. 16, the multilayer printed wiring board 1
Reference numeral 0 denotes a core substrate 30 that accommodates the IC chip 20, an interlayer resin insulation layer 50, and an interlayer resin insulation layer 150. Via holes 60 and conductive circuits 58 are formed in interlayer resin insulating layer 50, and via holes 160 and conductive circuits 158 are formed in interlayer resin insulating layer 150.

On the interlayer resin insulating layer 150, a resin substrate 130 having a core material is placed via an adhesive layer 134. The resin substrate 130 is provided with conductive columns 133 for connecting to the pads 75 of the multilayer printed wiring board 10. Conductive circuit 30A is provided on conductive pillar 133, and solder bump 76 for connection to an external substrate such as daughter board 230 is provided on conductive circuit 30A.

The IC chip 20 mounted on the printed wiring board 10 is covered with a passivation film 24 for protecting the IC chip 20, and a die pad 22 constituting an input / output terminal is provided in an opening of the passivation film 24. ing. A transition layer 38 mainly made of copper is formed on the pad 22.

FIG. 17 shows the printed wiring board 1 shown in FIG.
0 indicates a state where the daughter board 230 is attached. The pads 232 of the daughter board 230 are connected to the printed wiring board 10 via the solder bumps 76 of the printed wiring board.

In the multilayer printed wiring board 10 of this embodiment, the resin substrate 13 is formed on the outermost interlayer resin insulation layer 150.
0 is placed, and the solder bumps 76 are provided on the resin substrate 130. That is, the IC chip 2
0, and solder bumps are formed directly above the IC chip 20 via an interlayer resin insulating layer of several tens of μm, so that the core substrate 3
Unlike the IC chip 20, the IC chip 20 has no flexibility, so that the stress generated in the interlayer resin insulating layer having a large expansion coefficient cannot escape to the core substrate side, causing the solder bumps 76 to peel. On the other hand, in the present embodiment, since the solder bumps are formed on the resin substrate 130 having the core material and high rigidity, the peeling of the solder bumps due to the stress generated in the interlayer resin insulating layer can be prevented. FIG. 16 shows an example in which the solder bumps and the BGA are formed. However, as shown in FIG. 25, even in the PGA in which the conductive connection pins 96 are provided, the interlayer resin insulating layer is formed by mounting the resin substrate 130. Of the conductive connection pin 96 due to the stress generated at the same time.

In particular, the daughter board 230 is generally made of glass epoxy and has a low coefficient of thermal expansion because of incorporating a glass core material, while the interlayer resin insulation layer 5 having no core material is provided.
0 and 150 have a large coefficient of thermal expansion, and when solder bumps are directly disposed on the interlayer resin insulating layer 150, the difference in the coefficient of thermal expansion between the daughter board 230 and the interlayer resin insulating layer 150 causes the separation of the solder bumps 76. Had become. On the other hand, in the present embodiment, since the solder bumps are arranged between the resin board 130 having the core material and having a low coefficient of thermal expansion and the daughter board 230, peeling and cracking around the solder bumps 76 and the like are generated. The solder pump 76
Can be prevented from falling off or displaced, and the electrical connectivity and reliability can be improved.

Further, the multilayer printed wiring board 10 of this embodiment
Then, the IC chip 20 is built in the core substrate 30, and the transition layer 38 is provided on the pad 22 of the IC chip 20.
Is arranged. Therefore, the electrical connection between the IC chip and the multilayer printed wiring board (package substrate) can be established without using a lead component or a sealing resin. Also, IC
Since the transition layer 38 is formed in the chip portion, the IC chip portion is flattened, so that the upper interlayer resin insulating layer 50 is also flattened and the film thickness becomes uniform. Furthermore, the transition layer can maintain the shape stability even when the upper via hole 60 is formed.

Further, by providing a copper transition layer 38 on the die pad 22, resin residue on the pad 22 can be prevented. Also, in a later step, the resin can be immersed in an acid, an oxidizing agent, an etching solution, or the like. Discoloration and dissolution of the pad 22 do not occur even after various annealing processes. This improves the connectivity and reliability between the pads of the IC chip and the via holes. Further, by interposing the transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 40 μm, a via hole having a diameter of 60 μm can be reliably connected.

The space between the IC chip 20 and the recess 32 of the substrate 30 is filled with an adhesive material 34 which is a resin material. The IC chip 20 is attached to the substrate 3 by the adhesive material 34.
0 is fixed in the recess. This resin filling material 34
Since the stress generated by thermal expansion is alleviated, it is possible to prevent cracks in the core substrate 30 and undulation of the interlayer resin insulating layers 50 and 150 and the adhesive layer 134.
Therefore, peeling around the solder bumps 76, etc.
Cracks can be prevented. Therefore, since the solder pump 76 can be prevented from falling off or displaced, it is possible to improve electrical connectivity and reliability.

A. Semiconductor Element First, with respect to the configuration of a semiconductor element (IC chip) housed, housed, or embedded in the multilayer printed wiring board 10, FIG. 3B showing a cross section of the semiconductor element 20 and FIG. It will be described with reference to FIG.

As shown in FIG. 3B, a die pad 22 and a wiring (not shown) are provided on the upper surface of the semiconductor element 20, and a passivation film 24 covers the die pad 22 and the wiring. The die pad 22 includes
An opening in the passivation film 24 is formed. On the die pad 22, a transition layer 38 mainly made of copper is formed. The transition layer 38
It comprises a thin film layer 33 and an electrolytic plating film (thick film) 37. In other words, it is formed of two or more metal films.

[First Manufacturing Method] Next, a first manufacturing method of the semiconductor device described above with reference to FIG. 3B will be described with reference to FIGS.

(1) First, a wiring 21 and a die pad 2 are formed on a silicon wafer 20A shown in FIG.
2 (see FIG. 1A and FIG. 4A which shows a plan view of FIG. 1B, and FIG. 1B shows a cross section taken along line BB of FIG. 4A). There). (2) Next, a passivation film 24 is formed on the die pad 22 and the wiring 21, and an opening 24a is provided on the die pad 22 (FIG. 1C).

(3) Physical vapor deposition such as vapor deposition and sputtering is performed on the silicon wafer 20A to form a conductive metal film (thin film layer) 33 on the entire surface (FIG. 2A).
The thickness is preferably formed in the range of 0.001 to 2 μm. If it is below the range, a thin film layer cannot be formed on the entire surface. If it is higher than this range, the thickness of the formed film will vary. The optimal range is from 0.01 to 1.0 μm. As a metal to be formed, a metal selected from tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper is preferably used. These metals serve as a protective film for the die pad and do not degrade the electrical characteristics. In the first manufacturing method, the thin film layer 33 is formed of chromium by using sputtering. Further, a copper thin film layer may be formed on the chromium thin film layer 33 by using sputtering. Two layers of chromium and copper can be formed continuously in a vacuum chamber. At this time, chromium 0.05 μm-0.1 μm, copper 0.5 μm
About the thickness.

(4) Thereafter, a resist layer of any of a liquid resist, a photosensitive resist, and a dry film is formed on the thin film layer 33. A mask (not shown) on which a portion for forming the transition layer 38 is drawn is placed on the resist layer, and through exposure and development, a non-formed portion 35a is formed in the resist 35. Electroplating is performed to provide a thick layer (electrolytic plating film) 37 on the non-formed portion 35a of the resist layer (FIG. 2B). Examples of the type of plating formed include copper, nickel, gold, silver, zinc, and iron. Electrical properties, economics, and because the conductor layer that is a build-up formed later is mainly copper, it is better to use copper,
In the first manufacturing method, copper is used. Its thickness is 1-20
It is preferable to carry out in the range of μm.

(5) After the plating resist 35 is removed with an alkaline solution or the like, the metal film 33 under the plating resist 35 is made of sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, cupric complex-organic By removing with an etching solution such as an acid salt, the transition layer 38
Is formed (FIG. 2C).

(6) Next, a roughened surface 38α is formed by spraying an etching solution onto the substrate by spraying and etching the surface of the transition layer 38 (FIG. 3A).
reference).

(7) Finally, the semiconductor element 20 is formed by dividing the silicon wafer 20A on which the transition layer 38 has been formed into individual pieces by dicing or the like (FIG. 3).
(B) and FIG. 4 (B) which is a plan view of FIG. 3 (B)). Then, if necessary, the divided semiconductor elements 2
An operation check of 0 or an electrical inspection may be performed. Since the semiconductor element 20 has the transition layer 38 larger than the die pad 22, the probe pins can be easily applied to the semiconductor element 20, and the inspection accuracy is high.

[Second Manufacturing Method] A method of manufacturing the semiconductor device 20 according to the second manufacturing method will be described with reference to FIGS. (1) As described above with reference to FIG. 2B in the first manufacturing method, physical vapor deposition such as vapor deposition and sputtering is performed on the silicon wafer 20A, and a conductive metal film (first thin film) is formed on the entire surface. A layer 33 is formed (FIG. 5A). The thickness is preferably in the range of 0.001 to 2 μm. If it is below the range, a thin film layer cannot be formed on the entire surface. If it is higher than this range, the thickness of the formed film will vary. The optimal range is 0.01-1.
It is preferable that the thickness be 0 μm. As a metal to be formed, a metal selected from tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper is preferably used. These metals serve as a protective film for the die pad and do not degrade the electrical characteristics. In the second manufacturing method, the thin film layer 33 is formed of chromium.

(2) Sputtering on the first thin film layer 33
The second thin film layer 36 is laminated by vapor deposition and electroless plating (FIG. 5B). The thickness is preferably 0.01 to 5 μm, and particularly preferably 0.1 to 3 μm. In this case, the metal that can be laminated is preferably selected from nickel, copper, gold, and silver. In particular, it is good to form with either copper or nickel. Copper is inexpensive and has good electrical conductivity. Nickel has good adhesion to a thin film and is unlikely to cause peeling or cracking. In the second manufacturing method, the second thin film layer 36 is formed by electroless copper plating. In addition,
Desirable combinations of the first thin film layer and the second thin film layer are chromium-copper, chromium-nickel, titanium-copper, and titanium-nickel. It is superior to other combinations in terms of bonding to metals and electrical conductivity.

(3) Thereafter, a resist layer is formed on the thick layer. A mask (not shown) on which a portion for forming the transition layer 38 is drawn is placed on the resist layer, and exposed and developed to form a non-formed portion 35 on the resist 35.
a is formed. Electroplating is performed to provide a thick layer (electrolytic plating film) 37 on the non-formed portion 35a of the resist layer (FIG. 5C). The type of plating to be formed is copper,
Nickel, gold, silver, zinc, iron and the like. Since the electrical characteristics, economy, and the conductor layer which is a build-up to be formed later are mainly made of copper, copper is preferably used. In the second manufacturing method, copper is used. The thickness is preferably in the range of 1 to 20 μm.

(4) After removing the plating resist 35 with an alkali solution or the like, the metal film 33 under the plating resist 35
By removing the metal film 36 with an etchant such as sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, cupric complex-organic acid salt, etc., the transition layer 38 is formed on the pad 22 of the IC chip. (FIG. 6).

(5) Next, an etching solution is sprayed on the substrate by spraying, and the surface of the transition layer 38 is etched to form a roughened surface. The roughened surface can be formed by using electroless plating or oxidation-reduction treatment. Subsequent steps are the same as in the first manufacturing method, and a description thereof will be omitted.

[Third Manufacturing Method] A method of manufacturing the semiconductor device 20 according to the third manufacturing method will be described with reference to FIGS. The configuration of the semiconductor element of the third manufacturing method is almost the same as the first manufacturing method described above with reference to FIG. However, in the first manufacturing method, the transition layer 38 was formed by forming the thickening layer 37 in the non-resist forming portion using a semi-additive process. In contrast, the third manufacturing method uses a full additive process,
After uniformly forming the thickened layer 37, a resist is provided, and a portion where the resist is not formed is removed by etching to form the transition layer 38.

The manufacturing method of the third manufacturing method will be described with reference to FIG. (1) As described above with reference to FIG. 2B in the first manufacturing method, physical vapor deposition such as vapor deposition or sputtering is performed on the silicon wafer 20A, and the conductive metal film 3 is formed on the entire surface.
3 is formed (FIG. 7A). The thickness is 0.00
The range is preferably from 1 to 2.0 μm. If it is below the range, a thin film layer cannot be formed on the entire surface. If it is higher than this range, the thickness of the formed film will vary. The optimum range is preferably formed in the range of 0.01 to 1.0 μm. As a metal to be formed, a metal selected from tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper is preferably used. These metals serve as a protective film for the die pad and do not degrade the electrical characteristics. In the third manufacturing method, the thin film layer 33
Is formed by chromium. Further, a thin film layer may be laminated thereon. In this case, the metal that can be laminated is preferably selected from nickel, copper, gold, and silver. In particular,
It is good to form with either copper or nickel. Copper is inexpensive and has good electrical conductivity. Nickel has good adhesion to a thin film and is unlikely to cause peeling or cracking. Note that a desirable combination with the second thin film layer is chromium-copper, chromium-nickel, titanium-copper, or titanium-nickel. It is superior to other combinations in terms of bonding to metals and electrical conductivity. The thin film can be formed by sputtering, vapor deposition, or electroless plating.

The conductive metal film 36 is formed on the entire surface of the IC chip 20A by physical vapor deposition such as evaporation or sputtering (FIG. 7B). As the metal, it is preferable to form one or more layers of a metal such as tin, chromium, titanium, nickel, zinc, cobalt, gold, and copper. The thickness is preferably between 0.01 and 5.0 μm. In particular, the thickness is preferably 0.1 to 3.0 μm.

A metal film may be further provided on the metal film 36 by electroless plating or the like. The upper metal film is
It is preferable to form one or more layers of a metal such as nickel, copper, gold, and silver.

On the metal film 36, a thick plating film 37 is formed by electroless or electrolytic plating (FIG. 7C). The types of plating to be formed include nickel, copper, gold, silver and the like. Electrical properties, economics,
Since the conductor layer, which is a build-up formed later, is mainly made of copper, it is preferable to use copper. Its thickness is 1
It is preferable to carry out in the range of 20 μm. If it gets thicker,
An undercut occurs during the etching, and a gap may be generated at the interface between the formed transition layer and the via hole. Thereafter, an etching resist is formed, exposed and developed to expose portions of the metal other than the transition layer, and etching is performed to form a transition layer on the pads of the IC chip.

(3) Thereafter, a resist layer 35 is formed on the thick layer 37 (FIG. 8A).

(4) The metal film 3 where the resist 35 is not formed
3 and the thickening layer 37 are removed with an etching solution such as sulfuric acid-hydrogen peroxide solution, ferric chloride, cupric chloride, cupric complex-organic acid salt, and the resist 35 is peeled off to remove the IC. A transition layer 38 on the chip pads 22
Is formed (FIG. 8B). Subsequent steps are the same as in the first manufacturing method, and a description thereof will be omitted.

B. Resin Substrate Having Core Material Next, a manufacturing process of the resin substrate 130 having a core material used in the first embodiment will be described with reference to FIG. (1) One side of a resin substrate 130 made of glass epoxy resin or BT (bismaleimide triazine) resin
A single-sided copper-clad laminate obtained by laminating an 8 μm copper foil 30A is used as a starting material (see FIG. 9A).

The copper foil 30A formed on the resin substrate 130 may be subjected to a mat treatment for improving adhesion. The single-sided copper-clad laminate is made by impregnating a glass cloth with a thermosetting resin such as epoxy resin, phenolic resin, bismaleimide-triazine resin and laminating a prepreg and copper foil in the B stage and pressing under heat and pressure. The resulting substrate. The single-sided copper-clad laminate is a rigid substrate, easy to handle, and advantageous in cost.

The thickness of the resin substrate 130 is 10 to 400 μm.
m, preferably 50 to 300 μm, and 75 to 200 μm.
μm is optimal. If the thickness is smaller than these ranges, the strength is reduced and handling becomes difficult. On the other hand, if the thickness is too large, filling of the through holes by plating becomes difficult. On the other hand, copper foil 3
The thickness of OA is 5-35 μm, preferably 8-30 μm
The optimum value is 12 to 25 μm. This is because, as will be described later, when a hole is formed by laser processing, if the hole is too thin, it will penetrate, and if it is too thick, it is difficult to form a fine pattern by etching.

(2) Next, a through hole 130a is formed in the resin substrate 130 by laser processing (see FIG. 9B). As the laser processing machine, carbon dioxide laser processing machine,
A UV laser processing machine, an excimer laser processing machine, or the like can be used. The pore size is preferably 20 to 150 μm. A carbon dioxide laser processing machine is most suitable for industrial use because it has a high processing speed and can be processed at low cost. Here, in the case of using a carbon dioxide laser beam machine, a slightly melted resin is likely to remain on the surface of the copper foil 30A in the through-hole 130a. Therefore, desmearing is desirable to secure connection reliability. .

(3) Then, a protective film 132 is attached so that plating does not deposit on the copper foil 30A (FIG. 9).
(C)). Then, the through holes 130a are filled with electrolytic plating to form the conductive columns 133 (see FIG. 10A). As the electrolytic plating, for example, silver, copper, gold, nickel, and solder can be used. In particular, electrolytic copper plating is most suitable.

When filling by electrolytic plating, electrolytic plating is performed using the copper foil 30A formed on the resin substrate 130 as a plating lead. This copper foil 30 </ b> A is
Since it is formed on the entire upper surface, the electrolytic density becomes uniform, and the through holes 130a can be filled with a uniform height by electrolytic plating. Here, before the electrolytic plating, the through holes 1
The surface of the copper foil 30A in 30a may be activated with an acid or the like.

(4) After the electroplating, the conductive pillars 133 are left slightly higher than the resin substrate 130 (see FIG. 10A). Here, by forming the conductive pillars 133 slightly higher, the connectivity between the conductive pillars 133 of the resin substrate 130 described later and the pads 75 on the interlayer resin insulating layer is improved.

(5) Subsequently, after a mask having a predetermined pattern is covered, the copper foil 30A is etched to form a conductor circuit (see FIG. 10B). Here, first, after applying a photosensitive dry film or applying a liquid photosensitive resist, exposure and development are performed along a predetermined circuit pattern to form an etching resist. The layer is etched to form a conductor pattern. For the etching, at least one selected from aqueous solutions of sulfuric acid-hydrogen peroxide, persulfate, cupric chloride, and ferric chloride is preferable.

As shown in FIG. 10C, the through-holes 130a are filled by electroplating about half, and
Is formed, it is also possible to form the protrusion 133α with a conductive paste such as a solder paste or a silver paste.
In addition, all of the through holes 130a can be filled with a conductive paste without using plating.

C. Multilayer Printed Wiring Board Next, a method of manufacturing the multilayer printed wiring board described above with reference to FIG. 16 will be described with reference to FIGS.

(1) First, an insulating resin substrate (core substrate) 30 in which a prepreg obtained by impregnating a resin such as epoxy into a core material such as glass cloth is prepared as a starting material (see FIG. 11A). Next, a recess 32 for accommodating an IC chip is formed on one surface of the core substrate 30 by counterboring.
1 (B)). Here, the concave portion is formed by counterboring, but a core substrate having an accommodating portion can be formed by laminating an insulating resin substrate having an opening and a resin insulating substrate having no opening.

As a resin substrate in which electronic components such as IC chips are incorporated, a resin in which a reinforcing material such as a glass epoxy resin or a core material is impregnated into an epoxy resin, a BT resin, a phenol resin, or the like, or an epoxy resin is impregnated. Although a laminate of prepregs is used, a laminate generally used for a printed wiring board can be used. In addition, a double-sided copper-clad laminate, a single-sided plate, a resin plate having no metal film, and a resin film can be used. However, 3
If a temperature of 50 ° C. or more is applied, the resin will melt and carbonize.

(2) Thereafter, an adhesive material 34 is applied to the recess 32 using a printing machine. At this time, besides coating,
Potting may be performed. Next, the IC chip 20 according to the manufacturing method described above with reference to FIGS. 1 to 8 is mounted on the adhesive material 34 (see FIG. 11C). Adhesive material 3
4 uses a resin having a larger coefficient of thermal expansion than the core substrate 30. Thereby, the difference in thermal expansion between the IC chip 20 and the core substrate 30 is absorbed.

(3) Then, the upper surface of the IC chip 20 is pushed or hit and completely accommodated in the recess 32 (see FIG. 11D). Thereby, the core substrate 30 can be smoothed. At this time, the adhesive material 34 may be applied to the upper surface of the IC chip 20.
Since the opening for the via hole is provided by the laser after the resin layer on the upper surface of the C chip 20 is provided, the connection between the transition layer and the via hole is not affected.

(4) A thickness of 5
The thermosetting resin sheet 0μm vacuum crimp lamination at a pressure 5 kg / cm ² while raising the temperature to a temperature 50 to 150 ° C., providing interlayer resin insulating layer 50 (see FIG. 12 (A)). The degree of vacuum during vacuum compression is 10 mmHg.

As the interlayer resin insulating layer, a thermosetting resin,
Thermoplastic resins, photosensitive resins, resins in which a part of the thermosetting resin is replaced with photosensitive groups, resin composites of thermosetting resin and thermoplastic resin, composites of photosensitive resin and thermoplastic resin, etc. Can be used. Examples of the thermosetting resin include an epoxy resin, a phenol resin, a polyimide resin, a polyolefin resin, and a fluororesin. As the thermoplastic resin, polyethersulfone (PES), polyetherimide, phenoxy resin, or the like can be used.
Further, even when these are used as a resin composite, one or more resins may be mixed and used. For example, there are combinations such as an epoxy resin, a phenol resin, and a phenoxy resin.

Further, as described above, instead of forming the semi-cured resin into a film and applying heat and pressure as described above, the interlayer resin insulating layer 50 is formed by applying a resin composition whose viscosity has been adjusted in advance to a roll coater, a curtain coater, or the like. It can also be formed by applying with.

[0080] (5) Next, in CO ₂ gas laser having a wavelength of 10.4 .mu.m, the beam diameter 5 mm, top hat mode,
Under the conditions of a pulse width of 5.0 μsec, a mask hole diameter of 0.5 mm, and one shot, a via hole opening 48 having a diameter of 60 μm is provided in the interlayer resin insulating layer 50 (see FIG. 12B).
The resin residue in the opening 48 is removed using permanganic acid at 60 ° C. By providing the copper transition layer 38 on the die pad 22, resin residue on the pad 22 can be prevented, thereby improving the connectivity and reliability between the pad 22 and via holes 60 described later. Furthermore, 4
By interposing the transition layer 38 having a diameter of 60 μm or more on the pad 22 having a diameter of 0 μm, the via hole opening 48 having a diameter of 60 μm can be reliably connected. Here, the resin residue is removed using permanganic acid, but it is also possible to perform desmear treatment using oxygen plasma.

(6) Next, a roughened surface 50α of the interlayer resin insulating layer 50 is provided by dipping in an oxidizing agent such as chromic acid and permanganate (see FIG. 12C).
The roughened surface 50α is preferably formed in a range of 0.05 to 5 μm. As an example, a roughened surface 50α of 2 to 3 μm is provided by immersing in a sodium permanganate solution 50 g / l at a temperature of 60 ° C. for 5 to 25 minutes. Other than the above, SV-4 manufactured by Japan Vacuum Engineering Co., Ltd.
Plasma processing is performed using 540, and the interlayer resin insulation layer 5 is formed.
A roughened surface 50α can also be formed on the surface of No. 0. At this time, argon gas was used as the inert gas, and electric power 2
Plasma treatment is performed for 2 minutes under the conditions of 00 W, a gas pressure of 0.6 Pa, and a temperature of 70 ° C.

(7) A metal layer 52 is provided on the interlayer resin insulating layer 50 on which the roughened surface 50α is formed (see FIG. 12D). The metal layer 52 is formed by electroless plating. By applying a catalyst such as palladium to the surface layer of the interlayer resin insulating layer 50 in advance, and immersing it in the electroless plating solution for 5 to 60 minutes, the metal layer 52 as a plating film is provided in a range of 0.1 to 5 μm. As one example, [aqueous electroless plating solution] NiSO ₄ 0.003 mol / l tartaric acid 0.200 mol / l copper sulfate 0.030 mol / l HCHO 0.050 mol / l NaOH 0.100 mol / l α, α '-Bipirdyl 100 mg / l Polyethylene glycol (PEG) 0.10 g / l Dipped at a liquid temperature of 34 ° C for 40 minutes. Other than the above, after replacing the argon gas inside using the same apparatus as the above-described plasma processing, sputtering using Ni and Cu as targets was performed at a pressure of 0.6 Pa, a temperature of 80 ° C., and a power of 2
00W for 5 minutes, and the Ni / Cu metal layer 5
2 can be formed on the surface of the interlayer resin insulation layer 50. At this time, the thickness of the formed Ni / Cu metal layer 52 is 0.2 μm. Further, instead of sputtering, a metal film can be formed by vapor deposition, electrodeposition, or the like. Furthermore, after forming a thin layer by a physical method such as sputtering, vapor deposition, or electrodeposition, it is also possible to apply electroless plating.

(8) A commercially available photosensitive dry film is affixed to the substrate 30 that has been subjected to the above processing, a photomask film is placed, and after exposure at 100 mJ / cm ² ,
After developing with 0.8% sodium carbonate, a plating resist 54 having a thickness of 15 μm is provided (see FIG. 13A). Next, electrolytic plating is performed under the following conditions to form an electrolytic plating film 56 having a thickness of 15 μm (see FIG. 13B). The additive in the electrolytic plating aqueous solution is Capparaside HL manufactured by Atotech Japan.

[Electroplating aqueous solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive (Capparaside HL, manufactured by Atotech Japan) 19.5 ml / l [Electroplating conditions] Current density 1 A / dm ² Time 65 minutes Temperature 22 ± 2 ℃

(9) Plating resist 54 is made of 5% NaOH
And then remove the metal layer 52 under the plating resist.
Is dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide, a 16 μm-thick conductor circuit 58 composed of a metal layer 52 and an electrolytic plating film 56 and a via hole 6 are formed.
0 is formed (see FIG. 13C). As an etchant, cupric chloride, ferric chloride, persalts, hydrogen peroxide / sulfuric acid, alkali chants, and the like can be used.
Subsequently, roughened surfaces 58α and 60α are formed by an etching solution containing a cupric complex and an organic acid (FIG. 13).
(D)).

(10) Next, the above steps (7) to (12) are repeated to form an interlayer resin insulating layer 150 and a conductor circuit 158 (including via holes 160) on the interlayer resin insulating layer 50. (See FIG. 14A).

(11) Subsequently, any one of a liquid resist, a photosensitive resist and a dry film is formed on the interlayer resin insulating layer 150. A mask (not shown) on which a portion for forming the pad 75 is drawn is placed on the resist layer, and through exposure and development, a non-formed portion 85a is formed in the resist 85 (see FIG. 14B). ).

(12) Thereafter, nickel plating is applied to the non-formed portion 85a of the resist layer so that the nickel plating layer 7
After the formation of No. 2, gold plating is performed to provide a gold plating layer 74 on the nickel plating layer 72 (see FIG. 14C).

(13) The resist 85 is removed with an alkaline solution or the like to form a pad 75 (see FIG. 15A). In the present embodiment, the pad 75 is formed by the nickel plating layer 72 and the gold plating layer 74. However, the nickel plating layer and the gold plating layer can be omitted.

(14) Subsequently, after forming the conductive adhesive layer 134 on the upper surface of the resin substrate 130 of the first embodiment described above with reference to FIG. 10B, the resin substrate 130 is turned upside down. (FIG. 15B), the conductive pillar 133 provided on the resin substrate 130 is replaced with the pad 7 on the conductive circuit 158.
5, and pressure is applied from above to penetrate the adhesive layer 134 to bring the conductive pillar 133 into contact with the pad 75 (see FIG. 15C). When the resin substrate 130 is placed, the conductive pillars 133 are formed to be slightly higher than the resin substrate 130, so that the connection with the pads 75 of the printed wiring board is good. Here, the conductive pillar 133 is used.
Was brought into contact with the pad 75, but as the adhesive layer 130,
By using the different-direction conductive film, the conductive pillar 133 can be electrically connected to the pad 75 without contact.

The conductive adhesive layer 134 is desirably made of an organic adhesive. Examples of the organic adhesive include an epoxy resin, a polyimide resin, a thermosetting polyphenolene ether (PPE), and an epoxy resin. Composite resin with mold resin, composite resin with epoxy resin and silicone resin,
Desirably, it is at least one resin selected from BT resins. Here, as the solvent for the organic adhesive,
NMP, DMF, acetone, and ethanol can be used.

As a method of applying the uncured resin as an organic adhesive, a curtain coater, a spin coater, a roll coater, a spray coat, a screen printing, or the like can be used. After the application of the resin, the pressure reduction and the desorption are performed, and the adhesive layer 134 is removed.
Can be completely removed. The adhesive layer 134 can be formed by laminating an adhesive sheet. The thickness of the adhesive layer is 5 to 50 μm
Is desirable. The adhesive layer is preferably pre-cured (pre-cured) for easy handling.

(15) Next, a solder paste is printed on the conductor circuit 30A on the conductive pillar 133. This solder paste includes Sn / Pb, Sn / Sb, Sn / Ag, Sn
/ Ag / Cu or the like can be used. Alternatively, a low α-ray type solder paste may be used. Then, 200
The solder bumps 76 are formed by reflow at a temperature of ° C. (see FIG. 16). Thereby, the multilayer printed wiring board 10 having the IC chip 20 built-in and having the solder bumps 76 on the resin substrate 130 can be obtained.

A resin substrate 130 having a small influence of thermal expansion is placed on the surface layer of the printed wiring board 10 and the resin substrate 13
The solder bumps 76 are provided on the “0”. Therefore, stress due to the effect of thermal expansion does not concentrate on the solder bumps 76.
It is possible to prevent the solder pump 76 from falling off or being displaced.

In the above embodiment, the interlayer resin insulation layer 5
Thermosetting resin sheets were used for Nos. 0 and 150. The thermosetting resin sheet resin contains a hardly soluble resin, soluble particles, a curing agent, and other components. Each is described below.

In the thermosetting resin sheet used in the production method of the first embodiment, particles soluble in an acid or an oxidizing agent (hereinafter referred to as “soluble particles”) are made of a resin hardly soluble in an acid or an oxidizing agent (hereinafter referred to as a poorly soluble resin). (Referred to as resin). Note that the terms "sparingly soluble" and "soluble" used in the first embodiment mean that those having a relatively high dissolution rate when immersed in a solution containing the same acid or oxidizing agent for the same time are referred to as "soluble" for convenience. Those having a relatively low dissolution rate are referred to as "poorly soluble" for convenience.

Examples of the soluble particles include resin particles soluble in acid or oxidizing agent (hereinafter referred to as “soluble resin particles”), inorganic particles soluble in acid or oxidizing agent (hereinafter referred to as “soluble inorganic particles”), and acid or oxidizing agent. Soluble metal particles (hereinafter referred to as “soluble metal particles”) and the like. These soluble particles may be used alone or in combination of two or more.

The shape of the soluble particles is not particularly limited.
Spherical, crushed and the like. The shape of the soluble particles is desirably a uniform shape. This is because a roughened surface having unevenness with a uniform roughness can be formed.

The average particle size of the above-mentioned soluble particles is 0.1.
1 to 10 μm is desirable. Within this particle size range, 2
More than one kind of particles having different particle sizes may be contained. That is, it contains soluble particles having an average particle size of 0.1 to 0.5 μm and soluble particles having an average particle size of 1 to 3 μm.
Thereby, a more complicated roughened surface can be formed,
Excellent adhesion to conductor circuits. In addition, in 1st Embodiment, the particle size of a soluble particle is the length of the longest part of a soluble particle.

Examples of the soluble resin particles include those made of a thermosetting resin, a thermoplastic resin, and the like. When immersed in a solution containing an acid or an oxidizing agent, the soluble resin particles have a higher dissolution rate than the hardly soluble resin. If it is, there is no particular limitation. Specific examples of the soluble resin particles include, for example, those made of epoxy resin, phenol resin, polyimide resin, polyphenylene resin, polyolefin resin, fluororesin, and the like, and may be made of one of these resins. Alternatively, it may be composed of a mixture of two or more resins.

Further, as the soluble resin particles, resin particles made of rubber can be used. Examples of the rubber include polybutadiene rubber, various modified polybutadiene rubbers such as epoxy-modified, urethane-modified, (meth) acrylonitrile-modified, and (meth) acrylonitrile-butadiene rubber containing a carboxyl group. By using these rubbers, the soluble resin particles are easily dissolved in an acid or an oxidizing agent. In other words, when dissolving the soluble resin particles using an acid, an acid other than a strong acid can be dissolved, and when dissolving the soluble resin particles using an oxidizing agent, permanganese having a relatively weak oxidizing power is used. Acid salts can also be dissolved. Even when chromic acid is used, it can be dissolved at a low concentration. Therefore, the acid or the oxidizing agent does not remain on the resin surface, and as described later, when a catalyst such as palladium chloride is applied after forming the roughened surface, the catalyst is not applied or the catalyst is oxidized. Or not.

Examples of the above-mentioned soluble inorganic particles include particles made of at least one selected from the group consisting of aluminum compounds, calcium compounds, potassium compounds, magnesium compounds and silicon compounds.

Examples of the aluminum compound include alumina and aluminum hydroxide. Examples of the calcium compound include calcium carbonate and
Examples of the potassium compound include potassium carbonate.Examples of the magnesium compound include magnesia, dolomite, and basic magnesium carbonate.Examples of the silicon compound include silica and zeolite. Is mentioned. These may be used alone or in combination of two or more.

As the soluble metal particles, for example,
Copper, nickel, iron, zinc, lead, gold, silver, aluminum,
Examples include particles made of at least one selected from the group consisting of magnesium, calcium, and silicon. These soluble metal particles may have a surface layer coated with a resin or the like in order to ensure insulation.

When two or more kinds of the above-mentioned soluble particles are used in combination, the combination of the two kinds of the soluble particles is preferably a combination of resin particles and inorganic particles. Both have low conductivity, so that the insulation of the resin film can be ensured, and thermal expansion can be easily adjusted with the poorly soluble resin, and no crack occurs in the interlayer resin insulation layer made of the resin film. This is because peeling does not occur between the interlayer resin insulating layer and the conductor circuit.

The hardly soluble resin is not particularly limited as long as it can maintain the shape of the roughened surface when the roughened surface is formed using an acid or an oxidizing agent in the interlayer resin insulating layer. Examples thereof include thermosetting resins, thermoplastic resins, and composites thereof. Further, a photosensitive resin obtained by imparting photosensitivity to these resins may be used. By using a photosensitive resin, an opening for a via hole can be formed in an interlayer resin insulating layer by using exposure and development processes. Among these, those containing a thermosetting resin are desirable. Thereby, the shape of the roughened surface can be maintained even by the plating solution or various heat treatments.

Specific examples of the hardly-soluble resin include, for example, epoxy resin, phenol resin, phenoxy resin,
Examples thereof include a polyimide resin, a polyphenylene resin, a polyolefin resin, and a fluorine resin. These resins may be used alone or in combination of two or more. Further, an epoxy resin having two or more epoxy groups in one molecule is more desirable. Not only can the above-described roughened surface be formed, but also excellent in heat resistance, etc., even under heat cycle conditions, stress concentration does not occur in the metal layer, and peeling of the metal layer does not easily occur. Because.

Examples of the epoxy resin include cresol novolak epoxy resin, bisphenol A epoxy resin, bisphenol F epoxy resin, phenol novolak epoxy resin, alkylphenol novolak epoxy resin, biphenol F epoxy resin, and naphthalene epoxy resin. Resin, dicyclopentadiene type epoxy resin, epoxidized product of condensate of phenols and aromatic aldehyde having phenolic hydroxyl group,
Triglycidyl isocyanurate, alicyclic epoxy resin and the like. These may be used alone or in combination of two or more. Thereby, it becomes excellent in heat resistance and the like.

In the resin film used in the first embodiment, it is desirable that the soluble particles are substantially uniformly dispersed in the hardly-soluble resin. It is possible to form a roughened surface with unevenness of uniform roughness, and even if via holes and through holes are formed in the resin film, it is possible to secure the adhesion of the metal layer of the conductor circuit formed thereon. Because you can. Alternatively, a resin film containing soluble particles only in the surface layer forming the roughened surface may be used. Thereby, since the portions other than the surface layer of the resin film are not exposed to the acid or the oxidizing agent, the insulation between the conductor circuits via the interlayer resin insulating layer is reliably maintained.

In the above resin film, the compounding amount of the soluble particles dispersed in the poorly soluble resin is preferably 3 to 40% by weight based on the resin film. If the amount of the soluble particles is less than 3% by weight, it may not be possible to form a roughened surface having desired irregularities. If the amount exceeds 40% by weight, the soluble particles may be dissolved using an acid or an oxidizing agent. In addition, there is a case where the resin film is melted to a deep portion of the resin film and the insulation between the conductor circuits via the interlayer resin insulating layer made of the resin film cannot be maintained, which may cause a short circuit.

The resin film desirably contains a curing agent and other components in addition to the soluble particles and the hardly soluble resin. As the curing agent, for example,
Imidazole-based curing agents, amine-based curing agents, guanidine-based curing agents, epoxy adducts of these curing agents and microcapsules of these curing agents, and organic materials such as triphenylphosphine, tetraphenylphosphonium, and tetraphenylborate. Phosphine compounds and the like can be mentioned.

The content of the curing agent is desirably 0.05 to 10% by weight based on the resin film. 0.
If the amount is less than 05% by weight, the resin film is insufficiently cured, so that the degree of penetration of the acid or the oxidizing agent into the resin film is increased, and the insulating property of the resin film may be impaired. On the other hand, when the content exceeds 10% by weight, an excessive curing agent component may modify the composition of the resin, which may cause a decrease in reliability.

Examples of the other components include fillers such as inorganic compounds and resins which do not affect the formation of the roughened surface. As the inorganic compound, for example,
Examples of the resin include silica, alumina, and dolomite. Examples of the resin include a polyimide resin, a polyacryl resin, a polyamideimide resin, a polyphenylene resin, a melanin resin, and an olefin resin. By incorporating these fillers, the performance of the multilayer printed wiring board can be improved by matching thermal expansion coefficients, improving heat resistance and chemical resistance, and the like.

Further, the resin film may contain a solvent. As the solvent, for example, acetone,
Ketones such as methyl ethyl ketone and cyclohexanone,
Ethyl acetate, butyl acetate, cellosolve acetate, and aromatic hydrocarbons such as toluene and xylene. These may be used alone or in combination of two or more. However, these interlayer resin insulation layers are dissolved and carbonized when a temperature of 350 ° C. or more is applied.

[Modification of First Embodiment] Next, a printed wiring board according to a modification of the first embodiment will be described with reference to FIG. In the first embodiment described above, FIG.
As shown in FIG. 5, the IC chip 20 is built in the substrate 30 and connected to the external substrate 230 on the resin substrate 130.
On the other hand, in a modified example of the first embodiment, as shown in FIG. 18, a chip capacitor 120 is built in a substrate 30, and an IC chip 20 is mounted and connected on a resin substrate.

[Second Embodiment] Next, the configuration of a multilayer printed wiring board according to a second embodiment of the present invention will be described with reference to FIGS. In the first embodiment described above, FIGS.
As shown in FIG. 7, the resin substrate 130 placed on the interlayer insulating layer 150 has the conductive pillars 1 corresponding to the solder bumps 76.
The conductor circuit was formed by filling 33 with the solder bumps 76. On the other hand, in the second embodiment, the via holes 138 are formed in the resin substrate 130 as shown in FIGS.
6 is connected.

The manufacturing process of the resin substrate 130 having the core material used in the second embodiment will be described with reference to FIGS. (1) Resin substrate 13 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 1 mm
A double-sided copper-clad laminate obtained by laminating 18 μm copper foils 30A and 30B on both sides of No. 0 is used as a starting material (see FIG. 21A).

(2) A commercially available photosensitive dry film was stuck on the copper foil 30B, a mask was placed, and 100 mJ / c
Exposure is performed with m ² and development processing is performed with 0.8% sodium carbonate to provide an etching resist 140 having an opening 140 a and a thickness of 15 μm (see FIG. 21B).

(3) Thereafter, etching is performed with a sulfuric acid-peroxide solution, and the copper foil 3 is made to correspond to the opening 140a.
OB is removed to form an opening 31. Next, the resist 140 is removed with an aqueous sodium hydroxide solution (FIG. 21).
(C)).

(4) The resin substrate 130 exposed from the opening 31 of the copper foil 30B is removed by a carbon dioxide gas laser to provide a through hole 130a (see FIG. 22A). That is, the through hole 130a is formed by laser using the copper foil 30B as a conformal mask. Here, the carbon dioxide laser may be irradiated toward the opening 31 of the copper foil 30B, or may be irradiated so as to scan the entire printed wiring board, and the resin under the opening 31 of the copper foil 30B may be irradiated. The substrate 130 can be removed. The beam diameter is preferably 1.3 times or more the aperture diameter. Further, after the opening 31 is formed, the residue may be removed. For example, immersion in an aqueous solution of chromic acid, permanganate, or potassium,
Resin residue can be removed by using ₂ plasma, CF ₄ plasma, or plasma of a mixed gas of O ₂ and CF ₄ .

(5) Subsequently, a protective film 132 is attached so that plating does not deposit on the copper foil 30A (FIG. 22).
(B)). Next, the resin substrate 130 is immersed in an electroless plating bath having the following composition to form an electroless copper plating film 136 having a thickness of 1.6 μm (see FIG. 22C). Electroless plating solution EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l Electroless plating conditions 30 at a solution temperature of 70 ° C. Minute

(6) A commercially available photosensitive dry film is affixed to the electroless copper plating film 136, and a mask is placed thereon.
Exposure is performed at 00 mJ / cm ² . Then, development processing is performed with 0.8% sodium carbonate to remove unexposed portions, and the thickness of
A plating resist 142 of 0 μm is provided (FIG. 23A)
reference).

(7) Next, electrolytic plating is performed under the following conditions to form an electrolytic plated film 137 having a thickness of 20 μm on the portion where the plating resist 142 is not formed (see FIG. 23B). Electrolytic plating solution Sulfuric acid 180 g / l Copper sulfate 80 g / l Additive (capparaside GL manufactured by Atotech Japan) 1 ml / l Electroplating conditions Current density 1 A / dm ² hours 30 minutes Temperature Room temperature

The plating resist 142 was peeled off with 5% KOH and then etched with a mixed solution of sulfuric acid and hydrogen peroxide to remove the copper foil 3 under the plating resist 142.
0B, the copper foil 30
B, A via hole 138 having a thickness of 18 μm and including the electroless copper plating film 136 and the electrolytic plating film 137 is formed. Then, the copper foil on the back side is pattern-etched to form the conductor circuit 30A (see FIG. 23C).

Next, a method of manufacturing the multilayer printed wiring board 110 according to the second embodiment shown in FIGS. 19 and 20 will be described. Steps (1) to (13) are the same as those in the first embodiment, and a description thereof will not be repeated.

(14) Similarly to the first embodiment, after the steps (1) to (13), the conductive adhesive layer 134 is formed on the lower surface of the resin substrate 130 of the second embodiment. After that (FIG. 24A), the conductive circuit 30A provided on the resin substrate 130 is connected to the pad 7 on the conductive circuit 158.
5 (see FIG. 24B). Subsequent steps are the same as those in the above-described first embodiment, and a description thereof will be omitted.

[0127]

As described above, in the multilayer printed wiring board of the present invention, a resin substrate is mounted on the outermost interlayer resin insulating layer, and external connection terminals (BGA, solder bumps, PGA). According to the present invention, since the external connection terminals are formed on a resin substrate having a core material and high rigidity, the separation of the external connection terminals due to the stress generated in the interlayer resin insulating layer can be prevented.

[Brief description of the drawings]

FIGS. 1A, 1B, and 1C are process diagrams of a first method for manufacturing an IC chip according to a first embodiment of the present invention.

FIGS. 2A, 2B, and 2C are process diagrams of a first method for manufacturing an IC chip according to the first embodiment.

FIGS. 3A and 3B are process diagrams of a first method for manufacturing an IC chip according to the first embodiment.

FIG. 4A is a plan view of a silicon wafer according to the first embodiment, and FIG. 4B is a plan view of an individualized IC chip.

FIGS. 5A, 5B, and 5C are process diagrams of a second method for manufacturing an IC chip according to the first embodiment;

FIG. 6 is a process chart of a second method for manufacturing an IC chip according to the first embodiment.

FIGS. 7A, 7B, and 7C are process diagrams of a third method for manufacturing an IC chip according to the first embodiment;

FIGS. 8A and 8B are process diagrams of a third method for manufacturing an IC chip according to the first embodiment.

FIGS. 9A, 9B, and 9C are manufacturing process diagrams of a resin substrate having a core material used for the multilayer printed wiring board according to the first embodiment.

FIGS. 10A, 10B, and 10C are manufacturing process diagrams of a resin substrate having a core material used for the multilayer printed wiring board according to the first embodiment.

FIGS. 11A, 11B, 11C, and 11D are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 12A, 12B, 12C, and 12D are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 13A, 13B, 13C, and 13D are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 14A, 14B, and 14C are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 15A, 15B, and 15C are manufacturing process diagrams of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 16 is a cross-sectional view of the multilayer printed wiring board according to the first embodiment.

FIG. 17 is a cross-sectional view of the multilayer printed wiring board according to the first embodiment connected to a daughter board.

FIG. 18 is a sectional view of a multilayer printed wiring board according to a modification of the first embodiment.

FIG. 19 is a sectional view of a multilayer printed wiring board according to a second embodiment.

FIG. 20 is a sectional view of a multilayer printed wiring board according to a second embodiment connected to a daughter board.

FIGS. 21A, 21B, and 21C are manufacturing process diagrams of a resin substrate having a core material used for a multilayer printed wiring board according to a second embodiment.

FIGS. 22A, 22B, and 22C are manufacturing process diagrams of a resin substrate having a core material used for a multilayer printed wiring board according to a second embodiment.

FIGS. 23A, 23B, and 23C are manufacturing process diagrams of a resin substrate having a core material used for a multilayer printed wiring board according to a second embodiment.

FIGS. 24A and 24B are manufacturing process diagrams of the multilayer printed wiring board according to the second embodiment of the present invention.

FIG. 25 is a cross-sectional view of the multilayer printed wiring board according to the first embodiment.

[Explanation of symbols]

 Reference Signs List 20 IC chip 22 Pad 24 Passivation film 30 Core substrate 30A, 30B Copper foil (conductor circuit) 31 Opening 32 Depression 33 Metal film 34 Adhesive material 36 Plating film 37 Electroless plating film 38 Transition layer 38α Roughened surface 50 Interlayer resin insulation Layer 50α Roughened surface 52 Metal layer 54 Plating resist 56 Electroplated film 58 Conductor circuit 58α Roughened surface 60 Via hole 60α Roughened surface 72 Nickel plating 74 Gold plating 75 Pad 76 Solder bump 85 Resist 96 Conductive connection pin 120 Chip capacitor 130 resin substrate 130a through hole 132 protective film 133 conductive pillar (conductor circuit) 134 adhesive layer 136 electroless copper plating film 137 electrolytic plating film 140 resist 140a resist opening 142 plating resist 150 interlayer resin Edge layer 158 conductor circuit 160 the via hole 230 daughterboard

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H05K 3/46 H05K 3/46 QL X H01L 23/12 PNF term (Reference) 5E317 AA01 AA24 BB01 BB12 BB18 CC32 CC33 CC51 CD05 CD15 CD27 CD32 CD34 GG11 5E346 AA05 AA06 AA12 AA15 AA16 AA22 AA25 AA43 AA60 BB16 CC32 CC40 CC54 DD03 DD33 EE06 EE07 EE12 EE33 EE38 EE43 FF03 FF13 FF17 GG17 FF14 GG24 FF14 GG17

Claims (7)

[Claims] An interlayer insulating layer and a conductor layer are repeatedly formed on a substrate in which a semiconductor element is buried and housed or housed, and a via hole is formed in the interlayer insulating layer, and electric power is passed through the via hole. In the multilayer printed wiring board to be electrically connected, a resin substrate having a core material is mounted on the uppermost interlayer insulating layer, and an external connection terminal for connecting the resin substrate having the core material to an external substrate is provided. A multilayer printed wiring board, which is provided. 2. The multilayer according to claim 1, wherein a transition layer for connecting to the via hole formed in the lowermost interlayer insulating layer is formed in a pad portion of the semiconductor element. Printed wiring board. 3. A method for manufacturing a multilayer printed wiring board, comprising at least the following steps (a) to (e): (a) a step of embedding a semiconductor element in a core substrate; and (b) a step of embedding the semiconductor element. (C) a step of repeatedly forming an interlayer insulating layer having via holes and a conductor layer on the accommodated or accommodated core substrate; (c) forming a conductor circuit vertically penetrating the resin substrate having a core material; A) attaching the resin substrate on the uppermost interlayer insulating layer of the core substrate so that via holes in the interlayer insulating layer are connected to conductor circuits of the resin substrate; Forming an external connection terminal so as to be connected to the conductor circuit penetrating the resin substrate. 4. The method for manufacturing a multilayer printed wiring board according to claim 3, wherein the mounting of the resin substrate on the interlayer insulating layer of the core substrate is performed using an adhesive. 5. A step of forming a conductor circuit vertically penetrating a resin substrate having a core material, wherein a through hole extending from a side on which a copper foil is not stretched to a copper foil by a laser is formed in a single-sided copper-clad laminate. The method for producing a multilayer printed wiring board according to claim 3, wherein the conductor circuit is formed in the through-hole by piercing and passing an electric current through the copper foil to deposit electrolytic plating. . 6. In the step of forming a conductor circuit vertically penetrating the resin substrate having the core material, an opening is formed in one copper foil of the double-sided copper-clad laminate by etching, and the opening of the copper foil is A laser beam is used as a formal mask, a through hole is formed to reach a copper foil on a side where an opening is not provided, and the conductor circuit is formed by plating the through hole. A method for manufacturing a multilayer printed wiring board according to claim 4. 7. The method for manufacturing a multilayer printed wiring board according to claim 4, wherein, when forming said conductive circuit in said through hole, said conductive circuit is projected from said through hole.