JP5105137B2 - Manufacturing method of substrate having copper foil and substrate having copper foil - Google Patents

Description

  The present invention relates to a copper foil surface treatment method and a copper foil suitable for adhesion between a copper foil and an insulating material.

2. Description of the Related Art In recent years, with the advancement of functions and performance of information communication terminal devices represented by mobile phones and personal computers, rapid progress has been made in network technology that connects these terminal devices and servers.
In these terminal devices and network-related devices, it is indispensable to process and transmit large volumes of data at high speed and with high quality. Therefore, printed circuit boards used in these fields are also compatible with higher speeds and higher frequencies. Has become more demanding.

In order to cope with the higher frequency of signals, it is important to improve the electrical characteristics of the printed wiring board. The electrical characteristics that are important in circuits that handle high-frequency signals and high-speed digital signals include transmission loss, propagation delay time, characteristic impedance, etc. Especially, the problem is signal attenuation (transmission loss) due to high frequency and accompanying it. This is an increase in error rate and power consumption.
This transmission loss is roughly divided into a conductor loss (αc) and a dielectric loss (αd), both of which increase as the frequency increases.

Of these, αd is related to the dielectric constant (εr) and dielectric loss tangent (tanδ) of the insulating layer (dielectric), and uses low polarity resin with low εr and low tanδ, which is advantageous for low transmission loss in high speed and high frequency applications. The wiring board material that was used is necessary.
On the other hand, αc is related to the resistance value of the metal conductor, but as the frequency increases, a phenomenon called a skin effect occurs in which the current concentrates on the conductor surface portion. Becomes larger.

Therefore, when a high-frequency signal is handled, the conductor resistance increases with an increase in the rough shape of the conductor surface. Therefore, the conductor surface needs to be smoothed to reduce the conductor loss.
However, low dielectric constant resins, which are substrate materials used in high frequency applications, generally have a small number of polar groups and tend to have low adhesion to metal conductors. For this reason, development of a high adhesion technique between a low polarity resin and a smoother conductor surface is desired.

On the other hand, the conventional method of bonding an insulating resin and a copper foil is preliminarily roughened by some method so that a stronger bonding strength can be obtained from the bonded surface of the copper foil.
For example, the mainstream method applied as the roughening treatment means is a plating method in the case of electrolytic copper foil. In this method, an acidic copper plating bath is used, and a raw copper foil is used as a cathode, and a dendritic copper electrodeposition layer is first formed on at least one surface of the copper foil by so-called kogashi plating with a current exceeding the limit current density. .

Further, a smooth copper electrodeposition layer (Kabse plating) is formed on the dendritic copper electrodeposition layer with a current less than the limit current density, and the dendritic copper is changed to so-called bumpy copper. Adhesive strength is ensured by the anchor effect of this bump-shaped copper (refer patent document 1).
By forming the bumpy copper, the surface of the copper foil is increased in specific surface area compared to before the electrolytic treatment, and the anchor effect by the bumpy copper is exerted, so that the adhesive strength between the resin base material and the copper foil is increased. Will improve.

When the copper raw foil on which this bumpy copper is formed is an electrolytic copper foil, generally one surface (rough surface side: M surface) is more uneven than the other surface (gloss surface side: S surface). Tends to concentrate mainly on the convex part, and the bump-shaped copper is almost concentrated on the tip of the convex part.
Japanese Patent Publication No.53-39376

In addition, using an acidic copper plating bath containing one or more metal ions selected from molybdenum, iron, cobalt, nickel, and tungsten, electrolysis is performed in the vicinity of the limiting current density, and roughening treatment is performed by minute protrusions containing the added metal. There is a method of forming a layer (Patent Document 2).
JP-A-11-256389

  The first conventional technique for improving the adhesive strength between the resin base material and the copper foil by the roughening treatment described above is to form an unevenness of 7 to 10 μm in Rz on the M surface of the electrolytic copper foil, and the adhesive strength by the anchor effect. Was secured. However, when a high-speed electrical signal is passed through a rugged-shaped wiring having a surface exceeding 1 μm, the electrical signal is concentrated and flows near the surface of the wiring due to the skin effect, so that there is a problem that the conductor loss increases.

In addition, against the small frictional force of the copper foil surface, there is a so-called copper powder falling phenomenon that the copper-like copper falls off, and a residual copper phenomenon that the copper-like copper remains in the resin base material after the etching process performed at the time of printed circuit manufacturing. It tends to occur. Therefore, in order to prevent the above-mentioned residual copper phenomenon, it is necessary to lengthen the etching time.
However, when the etching time is lengthened, there are problems that the wiring becomes thin and the variation in wiring width becomes large.

  The second conventional technique for improving the adhesive strength between the resin base material and the copper foil by forming a roughened layer with fine protrusions on the M surface of the electrolytic copper foil is to form irregularities of about 3 μm in Rz on the M surface. Therefore, in comparison with the first prior art, the surface roughness of the copper foil is suppressed, but similarly there are problems that the conductor loss is large, the problem of copper powder falling off, and the residual copper phenomenon is likely to occur. is there.

  The present invention has been made in order to improve the above-mentioned problems of the prior art, and by forming uniform irregularities on the copper foil surface without forming irregularities exceeding 1 μm, an insulating resin such as a resin base material is provided. It is an object of the present invention to provide a copper foil surface treatment method and a copper foil that can secure the adhesive strength of the copper foil surface, have excellent etching properties, and can form fine wiring.

  In order to achieve the above object, the present invention is based on discretely forming a metal nobler than copper on the surface of the copper foil, and then performing an oxidation treatment. About.

(1) a step than the copper foil surface to discretely form the noble metal,
A step of oxidation treatment with an alkaline solution containing an oxidizing agent to the copper foil surface,
A method for producing a substrate having a copper foil, comprising the step of adhering the surface-treated copper foil surface and a core material .
(2) After the step of oxidizing the copper foil surface, the method further includes a step of performing one or more treatments selected from the group consisting of reduction treatment, coupling treatment, corrosion inhibition treatment, galvanization treatment, and chromate treatment. The manufacturing method of the board | substrate which has a copper foil as described in (1).

(3) The oxidizing agent is one or more selected from the group consisting of chlorate, chlorite, hypochlorite, perchlorate, peroxodisulfate, (1) or ( The manufacturing method of the board | substrate which has a copper foil as described in 2).
(4) The metal nobler than copper is a metal selected from the group consisting of gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium, iridium, or an alloy containing the metal. (1) The manufacturing method of the board | substrate which has the copper foil in any one of-(3).

(5) The formation amount of the noble metal than copper is 0.001 μmol / dm ² or more and 40 μmol / dm ² or less of the substrate having a copper foil according to any one of (1) to (4) Manufacturing method.
(6) A step of discretely forming a metal nobler than copper on the surface of the copper foil, a step of oxidizing the copper foil surface with an alkaline solution containing an oxidizing agent, and the surface-treated copper foil Bonding the surface and the core material;
The board | substrate which has copper foil obtained by passing through .
(7) The substrate having a copper foil according to (6), which is further subjected to one or more treatments selected from the group consisting of a reduction treatment, a coupling treatment, and a corrosion inhibition treatment after the oxidation treatment.

(8) The oxidizing agent is one or more selected from the group consisting of chlorate, chlorite, hypochlorite, perchlorate, peroxodisulfate, (6) or ( The board | substrate which has the copper foil as described in 7).
(9) The metal nobler than copper is a metal selected from the group consisting of gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium, iridium, or an alloy containing the metal. A substrate having the copper foil according to any one of (6) to (8).
(10) The amount of the metal nobler than the copper formed on the copper foil surface is 0.001 μmol / dm ² or more and 40 μmol / dm ² or less, according to any one of (6) to (9). A substrate having a copper foil.

  According to the present invention, without forming irregularities exceeding 1 μm on the surface of the copper foil, the adhesive strength between the insulating resin such as a resin substrate and the copper foil surface is ensured by forming uniform irregularities, and the etching property is improved. It is possible to provide a copper foil surface treatment method and a copper foil that are excellent and enable fine wiring formation.

  The best mode for carrying out the present invention will be described below with reference to the drawings. Here, a semiconductor chip mounting substrate and a semiconductor package using an electrolytic copper foil will be described as an example, but other copper foil surface treatment methods, copper foils, and wiring boards using these copper foils are similarly applied. Can do.

(Copper foil)
Examples of the copper foil used in the present invention include an electrolytic copper foil (raw copper foil) to be electrochemically deposited and a rolled copper foil produced by rolling copper. The surface of the electrolytic copper foil has a shiny surface (S surface) which is the electrodeposited side on the rotating drum side and a mat surface (M surface) on the opposite side. In general, the M surface is roughened and the surface thereof is bonded to the insulating material, but the S surface may be roughened to bond the surface and the insulating material. The surface roughness Rz of the electrolytic copper foil is 0.5 μm to 1.5 μm on the S surface and 1.0 μm to 2.0 μm on the M surface.

(Roughening treatment)
As a roughening treatment means for the copper foil surface, there are a method of depositing copper by electroplating or electroless plating, and a method of forming irregularities by etching, or a method of forming irregularities by etching. As the latter method, for example, by forming a dissimilar metal partially on the surface of the copper foil before the etching treatment, by utilizing the etching difference between the copper and the dissimilar metal, the copper portion is dissolved to form irregularities. be able to.

In addition, by adding an organic substance with adsorption characteristics to copper in the etchant, the organic substance is partially adsorbed on the copper foil surface, and by utilizing the difference, the copper part is dissolved and irregularities are formed. can do.
However, in the above method, it is difficult to maintain the accuracy of the copper foil thickness by copper deposition or copper etching by plating. In addition, there is a problem that roughening treatment cannot be performed by forming dense and uniform unevenness.

  The roughening treatment means according to the present invention is not performed by the above-described method, but a metal noble than copper is discretely formed on the surface of the copper foil, and then oxidized to form a crystal of copper oxide. Fine irregularities can be formed by forming or forming a metal copper crystal obtained by reducing the copper oxide crystal. By using this method, it is possible to maintain the copper foil thickness system as compared with the above method. Further, the conductor loss (αc) can be reduced during high-speed signal transmission at the 10 GHz level.

(Method for forming fine irregularities on the surface of copper foil)
By forming a noble metal more discretely than copper on the copper foil surface, and then oxidizing the copper foil surface with an alkaline solution containing an oxidizing agent, the copper foil surface is made of dense and uniform copper oxide crystals. Fine irregularities can be formed.
Further, by performing a reduction treatment after the oxidation treatment, fine irregularities due to dense and uniform metal copper crystals can be formed.
Furthermore, after the oxidation treatment, it is preferable to perform at least one of coupling treatment, corrosion inhibition treatment, galvanization treatment, and chromate treatment.

“Dense and uniform” means that the surface of the copper foil is processed with a scanning electron microscope (SEM) or with a focused ion beam processing observation device (FIB), and a scanning ion microscope (SIM) image is used. When observed, the size and height of the copper oxide crystals formed by the treatment or the metal copper crystals formed by the treatment are 1 nm or more and 1,000 nm or less, and the formed crystals are densely packed. It means that.
Hereinafter, each process described above will be described in detail. In the present invention, as a pretreatment for each treatment, it is desirable to perform a degreasing treatment for cleaning the surface of the copper foil, a pickling treatment, or a combination thereof as appropriate.

(Metal forming method nobler than copper)
As a method of discretely forming a metal noble from copper on the copper foil surface, there is no particular limitation, but a metal noble than copper is electroless plating, electroplating, displacement plating, spray spraying, coating, sputtering, It is preferable to form the base copper foil so as to be uniformly dispersed on the surface of the copper foil without completely covering the surface of the copper foil by vapor deposition or the like. More preferably, it is a method in which a noble metal than copper is discretely formed on the surface of the copper foil by displacement plating.
Displacement plating uses the difference in ionization tendency between copper and a metal nobler than copper, and according to this, a metal nobler than copper can be easily and inexpensively formed on the surface of the copper foil. it can.

Although there is no restriction | limiting in particular as a metal more precious than copper, The metal selected from gold | metal | money, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium, iridium, or the alloy containing these metals can be used.
Further, the amount of the metal nobler than the copper formed discretely on the copper foil surface is not particularly limited, but is preferably 0.001 μmol / dm ² or more and 40 μmol / dm ² or less.

The formation amount is more preferably at 0.01μmol / dm ² or more and 10 .mu.mol / dm ² or less, more preferably 0.1 [mu] mol / dm ² or more and is 4μmol / dm ² or less. If the formation amount is less than 0.001 μmol / dm ² , it tends to be difficult to form dense and uniform fine irregularities, and if it exceeds 40 μmol / dm ² , the adhesive strength tends to decrease.

In addition, the amount of noble metal discretely formed on the copper foil surface is determined by dissolving the noble metal on the copper foil surface with aqua regia and quantitatively analyzing the dissolved solution with an atomic absorption photometer. Can be obtained.
In addition, “discrete” means that the noble metal formed at 0.001 μmol / dm ² or more and 40 μmol / dm ² or less is dispersed on the copper foil surface without completely covering the copper foil surface with the noble metal. It means that.

(Oxidation method of copper foil surface)
When the copper foil surface is oxidized with a solution containing an oxidizing agent and an additive in an acidic solution, a roughening treatment for forming irregularities on the copper foil surface can be performed by etching the copper. However, there is a problem that the copper foil thickness cannot be maintained by the copper etching, and the roughening treatment for forming the dense and uniform unevenness cannot be performed.
In the present invention, after a metal noble than copper is discretely formed on the copper foil surface as described above, the copper foil surface is oxidized with an alkaline solution containing an oxidizing agent. Thereby, the roughening process which forms the unevenness | corrugation by crystal | crystallization provision of a copper oxide on the copper foil surface can be performed, without performing copper etching almost.

  The alkaline solution containing the oxidizing agent is not particularly limited. For example, chlorate, chlorite, hypochlorite, perchloric acid may be added to an alkaline solution containing an alkali metal or an alkaline earth metal. An alkaline solution further containing an oxidizing agent such as a salt or peroxodisulfate is preferred. The alkaline solution containing the above alkali metal or alkaline earth metal is, for example, an alkali metal compound such as sodium hydroxide, potassium hydroxide or sodium carbonate or water obtained by treating an alkaline earth metal compound with water or an ion exchange resin. It can be obtained by adding to a solvent.

  More specifically, the oxidizing agent is, for example, sodium hypochlorite, sodium chlorite, sodium chlorate, sodium perchlorate, potassium hypochlorite, potassium chlorite, potassium chlorate, Examples include potassium perchlorate, ammonium peroxodisulfate, potassium peroxodisulfate, and sodium peroxodisulfate.

Moreover, you may add a phosphate to the said alkaline solution. The phosphate that can be used is not particularly limited, and examples thereof include trisodium phosphate, tripotassium phosphate, and trilithium phosphate.
Furthermore, you may add a well-known organic acid and a chelating agent to the said alkaline solution.

By the oxidation treatment with the alkaline solution containing the oxidizing agent as described above, irregularities due to copper oxide crystals can be formed on the surface of the copper foil. The crystal amount of copper oxide is preferably 0.001 mg / cm ² or more and 0.3 mg / cm ² or less, more preferably 0.01 mg / cm ² or more and 0.2 mg / cm ² or less. 0.03 mg / cm ² or more and 0.1 mg / cm ² or less is particularly preferable. When the amount of copper oxide crystals is less than 0.001 mg / cm ² , the adhesive strength with an insulating resin or the like tends to be reduced, and when it exceeds 0.3 mg / cm ² , problems of the prior art tend to occur. .

In addition, the amount of copper oxide crystals formed on the copper foil surface can be examined by measuring the amount of electrolytic reduction. For example, using oxidized copper as a working electrode (cathode), a constant amount of electricity of 0.5 mA / cm ² is applied, and the surface potential of copper completely changes from the potential of copper oxide to the potential of metallic copper. The amount of copper oxide crystals can be determined from the amount of electrolytic reduction by measuring the time until a stable potential of −1.0 V or less is obtained.

Further, the temperature of the alkaline solution when performing the oxidation treatment with the alkaline solution containing the oxidizing agent is not particularly limited, but is preferably 20 to 95 ° C, more preferably 30 to 80 ° C, It is particularly preferable to carry out at 40 to 60 ° C.
The concentration of the alkaline solution containing the oxidizing agent and the oxidation treatment time with the solution are appropriately set so that the amount of crystal of the copper oxide is 0.001 mg / cm ² or more and 0.3 mg / cm ² or less. Is preferably selected.

(Reduction treatment method)
The unevenness due to the copper oxide crystals formed on the surface of the copper foil by the oxidation treatment can be made uneven by the reduction treatment. In this reduction treatment, an aqueous solution in which formaldehyde, paraformaldehyde, paraformaldehyde, an aromatic aldehyde compound or the like is added to an alkaline solution adjusted to pH 9.0 to 13.5, hypophosphorous acid, hypophosphite, etc. An aqueous solution added, an aqueous solution added with dimethylamine borane or a compound containing the same, an aqueous solution added with a boron hydride salt or a compound containing the same can be used.

More specifically, for example, HIST-100 (manufactured by Hitachi Chemical Co., Ltd., including trade names, including HIST-100B and HIST-100D) can be used as the solution for the reduction treatment.
Moreover, there is no restriction | limiting in particular as an alkaline solution shown here, For example, it is an alkaline solution containing an alkali metal or an alkaline-earth metal.

More specifically, for example, it can be obtained by adding an alkali metal compound or alkaline earth metal compound such as sodium hydroxide, potassium hydroxide or sodium carbonate to a solvent such as water or water treated with an ion exchange resin. it can.
As another reduction treatment method used in the present invention, by performing electrolytic reduction treatment, the copper foil surface can be made uneven with copper metal.

(Surface modification method after roughening of copper foil surface)
After forming fine irregularities on the copper foil, at least one of coupling treatment, corrosion inhibition treatment, galvanization treatment, and chromate treatment can be performed.

(Coupling process)
After the oxidation treatment, a coupling treatment may be performed to improve the adhesive strength between the copper foil surface and the insulating layer (build-up layer, etc.). The coupling treatment is performed after the reduction treatment or the corrosion inhibition. After the treatment, the treatment may be performed after the galvanization treatment and after the chromate treatment. Thereby, adhesiveness can be improved.

  Examples of the coupling agent used in the coupling treatment include silane coupling agents, aluminum coupling agents, titanium coupling agents, and zirconium coupling agents, and these include one or more types. You may use together. Of these, silane coupling agents are preferable, and the silane coupling agent has a functional group such as an epoxy group, amino group, mercapto group, imidazole group, vinyl group, or methacryl group in the molecule. Is preferred.

The coupling agent can be used as a solution containing the same, and the solvent used for the preparation of the coupling agent solution is not particularly limited, but water, alcohol, ketones, and the like can be used. Is possible.
A small amount of acid such as acetic acid or hydrochloric acid can be added to promote hydrolysis of the coupling agent.

  In addition, the content of the coupling agent is preferably 0.01% by mass to 5% by mass and more preferably 0.1% by mass to 1.0% by mass with respect to the entire coupling agent solution. preferable. The treatment with the coupling agent can be performed by a method of immersing copper to be treated in the coupling agent solution adjusted as described above, or spraying or applying the coupling agent solution to copper.

  The copper treated with the silane coupling agent is dried by natural drying, heat drying, or vacuum drying. Depending on the type of coupling agent used, it may be washed with water or ultrasonically before drying. Is possible.

(Corrosion inhibitor)
After the oxidation treatment, a corrosion inhibition treatment may be performed to suppress copper corrosion. The corrosion inhibition treatment is performed after the reduction treatment or after the coupling treatment, after the galvanization treatment, and after the chromate treatment. May be.
Although there is no restriction | limiting in particular as a corrosion inhibitor used for a corrosion inhibition process, For example, what is necessary is just to contain at least 1 sort (s) or more of a sulfur containing organic compound or a nitrogen containing organic compound.

The corrosion inhibitor is not particularly limited, a mercapto group, a sulfide group, or a compound or a nitrogen-containing organic to the to the molecule comprising a -N = or N = N or -NH ₂ containing a sulfur atom, such as a disulfide group A compound containing at least one compound is preferable.

(Compounds containing sulfur atoms such as mercapto groups, sulfide groups or disulfide groups)
Examples of the compound containing a sulfur atom such as mercapto group, sulfide group or disulfide group include aliphatic thiol (HS— (CH ₂ ) nR (wherein n is an integer from 1 to 23) , R represents a monovalent organic group, a hydrogen group or a halogen atom), and R is preferably any one of an amino group, an amide group, a carboxyl group, a carbonyl group, and a hydroxyl group. However, the alkyl group having 1 to 18 carbon atoms, the alkoxy group having 1 to 8 carbon atoms, the acyloxy group, the haloalkyl group, the halogen atom, the hydrogen group, the thioalkyl group, the thiol group, and being substituted. And good phenyl group, biphenyl group, naphthyl group, heterocyclic ring and the like.

Further, the amino group, amide group, carboxyl group, and hydroxyl group in R may be one, preferably one or more, and may further have a substituent such as the above alkyl group.
Further, in the formula, it is preferable to use a compound in which n is an integer from 1 to 23, more preferably a compound in which n is an integer from 4 to 15, more preferably from 6 to 12. Particularly preferred is a compound.

  Thiazole derivatives include (for example, thiazole, 2-aminothiazole, 2-aminothiazole-4-carboxylic acid, aminothiophene, benzothiazole, 2-mercaptobenzothiazole, 2-aminobenzothiazole, 2-amino-4-methyl Benzothiazole, 2-benzothiazolol, 2,3-dihydroimidazo [2,1-b] benzothiazol-6-amine, 2- (2-aminothiazol-4-yl) -2-hydroxyiminoacetic acid ether, 2-methylbenzothiazole, 2-phenylbenzothiazole, 2-amino-4-methylthiazole, etc.), thiadiazole derivatives (1,2,3-thiadiazole), 1,2,4-thiadiazole, 1,2,5-thiadiazole 1,3,4-thiadiazole, 2-amino-5-ethyl- , 3,4-thiadiazole, 5-amino-1,3,4-thiadiazole-2-thiol, 2,5-mercapto-1,3,4-thiadiazole, 3-methylmercapto-5-mercapto-1,2, 4-thiadiazole, 2-amino-1,3,4-thiadiazole, 2- (ethylamino) -1,3,4-thiadiazole, 2-amino-5-ethylthio-1,3,4-thiadiazole, etc.), mercapto Benzoic acid, mercaptonaphthol, mercaptophenol, 4-mercaptobiphenyl, mercaptoacetic acid, mercaptosuccinic acid, 3-mercaptopropionic acid, thiouracil, 3-thiourazol, 2-thiouramil, 4-thiouramil, 2-mercaptoquinoline, thioformic acid, 1 -Thiocoumarin, Thiocumothiazone, Thiocresol, Thiosarici Acid, thiothianuric acid, thionaphthol, thiotolene, thionaphthene, thionaphthenecarboxylic acid, thionaphthenequinone, thiobarbituric acid, thiohydroquinone, thiophenol, thiophene, thiophthalide, thiobutene, thiolthione carbonate, thiolutidone, thiol histidine, 3-carboxypropyl disulfide 2-hydroxyethyl disulfide, 2-aminopropionic acid, dithiodiglycolic acid, D-cysteine, di-t-butyl disulfide, thiocyan, thiocyanic acid and the like.

(In the molecule, -N = is a compound containing at least one N-containing organic compound containing N = N or NH ₂ )
Preferred compounds as compounds containing at least one N-containing organic compound containing —N═, N═N, or —NH ₂ in the molecule are triazole derivatives (1H-1,2,3-triazole, 2H-1, 2,3-triazole, 1H-1,2,4-triazole, 4H-1,2,4-triazole, benzotriazole, 1-aminobenzotriazole, 3-amino-5-mercapto-1,2,4-triazole 3-amino-1H-1,2,4-triazole, 3,5-diamino-1,2,4-triazole, 3-oxy-1,2,4-triazole, aminourazole, etc.), tetrazole derivatives ( Tetrazolyl, tetrazolylhydrazine, 1H-1,2,3,4-tetrazole, 2H-1,2,3,4-tetrazole, 5-amino-1H-te Tolazole, 1-ethyl-1,4-dihydroxy-5H-tetrazol-5-one, 5-mercapto-1-methyltetrazole, tetrazole mercaptan, etc., oxazole derivatives (oxazole, oxazolyl, oxazoline, benzoxazole, 3-amino-5 -Methylisoxazole, 2-mercaptobenzoxazole, 2-aminooxazoline, 2-aminobenzoxazole, etc.), oxadiazole derivatives (1,2,3-oxadiazole, 1,2,4-oxadiazole, 1 , 2,5-oxadiazole, 1,3,4-oxadiazole, 1,2,4-oxadiazolone-5, 1,3,4-oxadiazolone-5, etc.), oxatriazole derivatives (1 , 2,3,4-oxatriazole, 1,2,3,5-oxatriazol ), Purine derivatives (purine, 2-amino-6-hydroxy-8-mercaptopurine, 2-amino-6-methylmercaptopurine, 2-mercaptoadenine, mercaptohypoxanthine, mercaptopurine, uric acid, guanine, adenine, Xanthine, theophylline, theobromine, caffeine, etc.), imidazole derivatives (imidazole, benzimidazole, 2-mercaptobenzimidazole, 4-amino-5-imidazolecarboxylic acid amide, histidine, etc.), indazole derivatives (indazole, 3-indazolone, indazolol) ), Pyridine derivatives (2-mercaptopyridine, aminopyridine, etc.), pyrimidine derivatives (2-mercaptopyrimidine, 2-aminopyrimidine, 4-aminopyrimidine, 2-amino-4,6-dihydride) Xypyrimidine, 4-amino-6-hydroxy-2-mercaptopyrimidine, 2-amino-4-hydroxy-6-methylpyrimidine, 4-amino-6-hydroxy-2-methylpyrimidine, 4-amino-6-hydroxypyrazolo [3,4-d] pyrimidine, 4-amino-6-mercaptopyrazolo [3,4-d] pyrimidine, 2-hydroxypyrimidine, 4-mercapto-1H-pyrazolo [3,4-d] pyrimidine, 4- Amino-2,6-dihydroxypyrimidine, 2,4-diamino-6-hydroxypyrimidine, 2,4,6-triaminopyrimidine, etc.), thiourea derivatives (thiourea, ethylenethiourea, 2-thiobarbituric acid, etc.) , Amino acids (glycine, alanine, tryptophan, proline, oxyproline, etc.), 1,3,4-thioo Sadiazolone-5, thiocoumazone, 2-thiocoumarin, thiosaccharin, thiohydantoin, thiopyrine, γ-thiopyringanazine, guanazole, guanamine, oxazine, oxadiazine, melamine, 2,4,6-triaminophenol, triaminobenzene, amino Indole, aminoquinoline, aminothiophenol, aminopyrazole and the like can be mentioned.

(Corrosion inhibitor solution)
Moreover, water and an organic solvent can be used for adjustment of the solution containing the said corrosion inhibitor. The type of the organic solvent is not particularly limited, but alcohols such as methanol, ethanol, n-propyl alcohol and n-butyl alcohol, ethers such as di-n-propyl ether, di-n-butyl ether and diallyl ether In addition, aliphatic hydrocarbons such as hexane, heptane, octane, and nonane, and aromatic hydrocarbons such as benzene, toluene, and phenol can be used, and these solvents can be used alone or in combination of two or more.
It is also possible to add the corrosion inhibitor to an alkaline solution or a coupling agent solution containing the oxidizing agent.

(Corrosion inhibitor concentration and treatment time)
The concentration of the solution containing the corrosion inhibitor is preferably 0.1 to 5000 ppm, more preferably 0.5 to 3000 ppm, and particularly preferably 1 to 1000 ppm. If the concentration of the corrosion inhibitor is less than 0.1 ppm, the ion migration suppressing effect and the adhesive strength between the copper foil surface and the insulating layer tend to decrease.
On the other hand, when the concentration of the corrosion inhibitor exceeds 5000 ppm, an ion migration suppressing effect can be obtained, but the adhesive strength between the copper foil surface and the insulating layer tends to decrease.
The treatment time with the solution containing the corrosion inhibitor is not particularly limited, but it is preferable to appropriately change the treatment time according to the type and concentration of the corrosion inhibitor. It is also possible to perform ultrasonic cleaning after the treatment.

(Zinc plating method)
Adhesive strength can be improved by giving affinity with insulating resin by performing a galvanization process after the said reduction process. Although there is no restriction | limiting in particular as a plating solution which performs a zinc plating process, For example, the plating solution of pH 3.5 or more which added the zinc compound and ammonium salt can be used. The zinc compound is not particularly limited, and examples thereof include zinc chloride, zinc sulfate heptahydrate, and zinc acetate dihydrate. As the ammonium salt, the uniformity and denseness of the zinc thin film can be favorably imparted by adding at least one additive such as ammonium chloride, ammonium sulfate, or ammonium acetate.

(Chromate treatment method)
By performing chromate treatment after the galvanizing treatment, discoloration of the galvanized film can be prevented. The aqueous solution for chromate treatment is not particularly limited, and for example, an aqueous solution added with hexavalent chromium ions or an aqueous solution added with trivalent chromium ions can be used. Examples of hexavalent chromium ions include sodium dichromate dihydrate, potassium dichromate, and chromic acid. Examples of the trivalent chromium ions include ammonium chromium sulfate, chromium oxide, and chromium nitrate.

(Semiconductor chip mounting substrate)
FIG. 1 shows a schematic cross-sectional view of one embodiment (two-sided build-up layer) of a semiconductor chip mounting substrate of the present invention. Here, the embodiment in which the build-up layer (interlayer insulating layer) is formed only on one side will be described, but the build-up layer may be formed on both sides as shown in FIG. 8 if necessary.

  As shown in FIG. 1, the semiconductor chip mounting substrate of the present invention includes a first chip including a semiconductor chip connection terminal and a first interlayer connection terminal 101 on a core substrate 100 which is an insulating layer on the side where the semiconductor chip is mounted. Wiring 106a is formed. A second wiring 106 b including a second interlayer connection terminal 103 is formed on the other side of the core substrate 100, and the first interlayer connection terminal 101 and the second interlayer connection terminal are connected to the first layer of the core substrate 100. Are electrically connected through an interlayer connection IVH (via hole) 102. An interlayer insulating layer (hereinafter referred to as a buildup layer) 104 is formed on the second wiring 106b side of the core substrate 100, and a third wiring 106c including a third interlayer connection terminal is formed on the buildup layer 104. And the second interlayer connection terminal and the third interlayer connection terminal are electrically connected via the second interlayer connection IVH 108.

When a plurality of buildup layers are formed, the same structure is stacked, and external connection terminals 107 connected to the motherboard are formed on the outermost buildup layer. The shape of the wiring, the arrangement of each connection terminal, and the like are not particularly limited, and can be appropriately designed for manufacturing a semiconductor chip to be mounted and a target semiconductor package.
Further, the semiconductor chip connection terminal and the first interlayer connection terminal can be shared. Furthermore, an insulating coating 109 such as a solder resist can be provided on the outermost buildup layer as necessary.

(Core substrate)
The material of the core substrate 100 is not particularly limited, but an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, or the like can be used. In consideration of the thermal expansion coefficient and insulation, it is preferable to use ceramic or glass.
Among the non-photosensitive glasses, soda lime glass (component example: SiO ₂ 65 to 75 wt%, Al ₂ O ₃ 0.5 to ₄ wt%, CaO 5 to 15 wt%, MgO 0.5 to 4 wt%, Na ₂ O 10-20 wt%), borosilicate glass (component example: SiO ₂ 65-80 wt%, B ₂ O ₃ 5-25 wt%, Al ₂ O ₃ 1-5 wt%, CaO 5-8 wt%, MgO 0.5 ˜2 wt%, Na ₂ O 6-14 wt%, K ₂ O 1-6 wt%) and the like.
Also, it includes those containing gold ions and silver ions as a photosensitive agent into Li _{2 O-SiO} 2 based crystallized glass as photosensitive glass.

As the organic substrate, a substrate or a resin film obtained by laminating a material in which a glass cloth is impregnated with a resin can be used. As the resin to be used, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used, but a thermosetting organic insulating material is preferable.
Thermosetting resins include phenolic resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, polybenzimidazole resin, polyamide resin, polyamideimide resin, silicon resin, cyclohexane Resin synthesized from pentadiene, resin containing tris (2-hydroxyethyl) isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimetallate, furan resin, ketone resin, A xylene resin, a thermosetting resin containing a condensed polycyclic aromatic, a benzocyclobutene resin, or the like can be used. Examples of the thermoplastic resin include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, and liquid crystal polymer.

A filler may be added to these resins. Examples of the filler include silica, talc, aluminum hydroxide, aluminum borate, aluminum nitride, and alumina.
The thickness of the core substrate 100 is preferably 100 to 800 μm from the viewpoint of IVH formation, and more preferably 150 to 500 μm.

The buildup layer 104 is made of an insulating material, and a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used as the insulating material. The buildup layer 104 is preferably composed mainly of a thermosetting organic insulating material.
Thermosetting resins include phenolic resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, polybenzimidazole resin, polyamide resin, polyamideimide resin, silicon resin, cyclohexane Resin synthesized from pentadiene, resin containing tris (2-hydroxyethyl) isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimetallate, furan resin, ketone resin, A xylene resin, a thermosetting resin containing a condensed polycyclic aromatic, a benzocyclobutene resin, or the like can be used.
Examples of the thermoplastic resin include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, and liquid crystal polymer.

  A filler may be added to the insulating material. Examples of the filler include silica, talc, aluminum hydroxide, aluminum borate, aluminum nitride, and alumina.

(Coefficient of thermal expansion)
Preferably, the thermal expansion coefficient of the semiconductor chip and the thermal expansion coefficient of the core substrate 100 are approximated, and the thermal expansion coefficient of the core substrate 100 and the thermal expansion coefficient of the buildup layer are approximated. It is not limited.
Further, when the thermal expansion coefficients of the semiconductor chip, the core substrate, and the buildup layer are α1, α2, and α3 (ppm / ° C.), it is more preferable that α1 ≦ α2 ≦ α3.

Specifically, the thermal expansion coefficient α2 of the core substrate is preferably 7 to 13 ppm / ° C, more preferably 9 to 11 ppm / ° C.
The thermal expansion coefficient α3 of the buildup layer is preferably 10 to 40 ppm / ° C, more preferably 10 to 20 ppm / ° C, and particularly preferably 11 to 17 ppm / ° C.

(Young's modulus)
The Young's modulus of the buildup layer is preferably 1 to 5 GPa in terms of stress relaxation against thermal stress. It is preferable to add the filler in the buildup layer by appropriately adjusting the addition amount so that the thermal expansion coefficient of the buildup layer is 10 to 40 ppm / ° C. and the Young's modulus is 1 to 5 GPa.

(Manufacturing method of semiconductor chip mounting substrate)
The semiconductor chip mounting substrate can be manufactured by a combination of the following manufacturing methods. The order of the manufacturing process is not particularly limited as long as it does not depart from the object of the present invention.

(Method for forming copper foil)
Electrodeposited electrolytic copper foil or rolled copper foil manufactured by rolling copper is degreased and pickled, and then a noble metal is discretely formed on the copper foil surface. After that, the copper foil surface can be oxidized with an alkaline solution containing an oxidizing agent, and a copper foil in which irregularities due to copper oxide crystals are formed on the copper foil surface can be used.
Moreover, the copper foil which performed the reduction process, the coupling process, the corrosion suppression process, the galvanization process, the chromate process at least 1 or the combination process of 2 or more after an oxidation process as needed can be used.

(Wiring formation method)
As a method of forming wiring using copper foil, a method of forming copper foil on the core substrate surface or build-up layer and removing unnecessary portions of the copper foil by etching (subtractive method), core substrate surface or build There is a method (semi-additive method) in which an ultrathin copper foil (seed layer) is formed on the up layer, and then a necessary wiring is formed by electrolytic plating, and then the thin copper layer is removed by etching.

(Wiring formation by subtractive method)
An etching resist is formed in a portion to be a copper foil wiring, and a chemical etching solution is sprayed and sprayed on a portion exposed from the etching resist to remove unnecessary copper foil by etching to form a wiring. As the etching resist, an etching resist material that can be used for an ordinary wiring board can be used.

  For example, a resist ink is silkscreen printed to form an etching resist, or a negative photosensitive dry film for etching resist is laminated on a copper foil, and a photomask that transmits light on the wiring shape is formed thereon. Overlap, exposure with ultraviolet rays is performed, and portions not exposed are removed with a developer to form an etching resist. As the chemical etching solution, a chemical etching solution used for a normal wiring board such as a solution of cupric chloride and hydrochloric acid, a ferric chloride solution, a solution of sulfuric acid and hydrogen peroxide, an ammonium persulfate solution, or the like can be used.

(Wiring formation by semi-additive method)
When the core substrate or the build-up layer has an adhesive function, the seed layer can be formed by bonding the copper foil by pressing or laminating.
However, since it is very difficult to directly bond a thin metal layer, there are a method of thinning a metal foil with a carrier after laminating a thick metal foil, a method of peeling a carrier layer after laminating a metal foil with a carrier, etc. is there.

For example, as the former, there is a three-layer copper foil of carrier copper / nickel / thin film copper, and carrier copper can be removed with an alkali etching solution and nickel can be removed with a nickel etching solution. As the latter, a peelable copper foil using aluminum, copper, an insulating material or the like as a carrier can be used, and a seed layer of 5 μm or less can be formed. Alternatively, a 9 to 18 μm thick copper foil may be attached, and the seed layer may be formed by etching so that the thickness is 5 μm or less.
A plating resist is formed in a necessary pattern on the seed layer formed by the above-described method, and wiring is formed by electrolytic copper plating through the seed layer. Thereafter, the plating resist is peeled off, and finally the seed layer is removed by etching or the like, whereby the wiring can be formed.

(Wiring shape)
The shape of the wiring is not particularly limited, but at least a semiconductor chip connection terminal 16 (wire bond terminal or the like) is provided on the side where the semiconductor chip is mounted, and an external connection terminal (solder ball) electrically connected to the motherboard on the opposite side. Etc.) and development wirings connecting them, interlayer connection terminals, and the like.
The wiring arrangement is not particularly limited, but a fan-in type semiconductor in which an external connection terminal 19 is formed inside the semiconductor chip connection terminal 16 as shown in FIG. A chip mounting substrate, a fan-out type semiconductor chip mounting substrate in which external connection terminals 19 are formed outside the semiconductor chip connection terminals 16 as shown in FIG. 6, or a combination of these may be used.

5 and 6, reference numeral 13 denotes a semiconductor package area, 14 denotes a die bond film adhesion area (flip chip type), 15 denotes a semiconductor chip mounting area (flip chip type), and 17 denotes a die bond film adhesion area (wire bond type). , 18 is a semiconductor chip mounting area (wire bond type), and 20 is a developed wiring.
The shape of the semiconductor chip connection terminal 16 is not particularly limited as long as wire bond connection or flip chip connection is possible.

In addition, wire-bond connection or flip-chip connection is possible for both fan-out and fan-in types. Further, if necessary, a dummy pattern 21 (see FIG. 6) that is not electrically connected to the semiconductor chip may be formed.
The shape and arrangement of the dummy pattern are not particularly limited, but it is preferable to arrange the dummy pattern uniformly in the semiconductor chip mounting region. As a result, voids are less likely to occur when a semiconductor chip is mounted with a die bond adhesive, and reliability can be improved.

(Bahia Hall)
Since the multilayer semiconductor chip mounting substrate has a plurality of wiring layers, via holes for electrically connecting the wirings of the respective layers can be provided. The via hole can be formed by providing a hole for connection in the core substrate or the build-up layer and filling the hole with a conductive paste, plating or the like. Examples of the hole processing method include mechanical processing such as punching and drilling, laser processing, chemical etching processing using a chemical solution, and dry etching using plasma.
In addition, as a method for forming a via hole in the buildup layer, there is a method in which a conductive layer is formed in advance on the buildup layer with a conductive paste or plating, and this is laminated on a core substrate by pressing or the like.

(Formation of insulation coating)
An insulating coating can be formed on the external connection terminal side of the semiconductor chip mounting substrate. The pattern can be formed by printing if it is a varnish-like material, but it is preferable to use a photosensitive solder resist, a coverlay film, or a film-like resist in order to ensure higher accuracy. As a material, an epoxy-based material, a polyimide-based material, an epoxy acrylate-based material, or a fluorene-based material can be used.

Since such an insulating coating has shrinkage at the time of curing, if it is formed only on one side, a large warp tends to occur on the substrate. Therefore, an insulating coating can be formed on both surfaces of the semiconductor chip mounting substrate as necessary.
Furthermore, since the warpage varies depending on the thickness of the insulating coating, it is more preferable to adjust the thickness of the insulating coating on both sides so that no warpage occurs. In that case, it is preferable to conduct preliminary examination and determine the thicknesses of the insulating coatings on both sides. In order to obtain a thin semiconductor package, the thickness of the insulating coating is preferably 50 μm or less, and more preferably 30 μm or less.

(Plating of wiring)
Nickel and gold plating can be sequentially applied to necessary portions of the wiring. Furthermore, nickel, palladium, or gold plating may be used as necessary.
These platings are applied to the semiconductor chip connection terminals of the wiring and the external connection terminals for electrical connection with the mother board or other semiconductor package. For this plating, either electroless plating or electrolytic plating may be used.

(Manufacturing method of semiconductor chip mounting substrate)
Such a semiconductor chip mounting substrate can be manufactured by the following processes. 2A to 2G are schematic cross-sectional views showing an example of an embodiment of a method for manufacturing a semiconductor chip mounting substrate of the present invention. However, the order of the manufacturing process is not particularly limited as long as it does not depart from the object of the present invention.
(Process a)
(Step a) is a step of forming the first copper layer 118a and the second copper layer 118b on both surfaces of the core substrate 100 as shown in FIG.

(Step a-1)
First, the surface of the copper foil to be bonded to the core substrate 100 is degreased and washed with hydrochloric acid or sulfuric acid.
(Step a-2)
Next, a metal selected from gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium, iridium, or an alloy containing these metals, which is a noble metal than copper, is formed discretely, and an oxidizing agent is added. Oxidation treatment is performed by immersing in an alkaline solution. Thereafter, reduction treatment is preferably performed. Furthermore, at least one or more of coupling treatment, corrosion inhibition treatment, galvanization treatment, and chromate treatment may be performed thereafter.

(Step a-3)
Next, both surfaces of the core substrate 100 and the copper foil on the side processed in (Step a-2) are bonded to form the first copper layer 118a and the second copper layer 118b. As the insulating material of the core substrate 100, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used as described above, but it is preferable that the thermosetting material is a main component.
As a bonding method, a copper layer can be obtained by using a technique such as pressing or laminating. When the insulating material includes a thermosetting material, it is desirable to further heat and cure.

(Process b)
In step (b), as shown in FIG. 2B, a first interlayer connection IVH (via hole) 102 for connecting a first interlayer connection terminal 101 to be described later and the second wiring 106b is used. After that, a conductive layer is formed in order to perform interlayer connection between the first copper layer 118a and the second copper layer 118b.

Via holes can usually be formed by drilling, but when the core substrate 100 is a non-photosensitive substrate, a laser beam such as a CO ₂ laser, a YAG laser, or an excimer laser is irradiated to a portion that becomes a via hole. By doing so, it can be formed. From the viewpoint of productivity and hole quality, it is preferable to use a CO ₂ laser. When the IVH diameter is less than 30 μm, a YAG laser capable of focusing the laser beam is suitable.
In addition, examples of the non-photosensitive substrate include the non-photosensitive glass described above, but there is no limitation thereto. After forming the via hole as described above, in order to electrically connect the layers, after performing desmear treatment as necessary, the hole is made conductive by a conductive paste or plating, This is a via hole.

(Process c)
Step (c) is a step of forming the second wiring 106b on the surface opposite to the first wiring 106a on the core substrate 100 as shown in FIG. 2 (c).
After forming an etching resist in the first wiring shape on the first copper layer 118a and etching the copper layer with an etchant such as copper chloride, iron chloride, sulfuric acid-hydrogen peroxide, nitric acid-hydrogen peroxide, etc. The first wiring 106a can be manufactured by removing the etching resist.

Further, an etching resist having a second wiring shape is formed on the second copper layer 118b, and the copper layer is etched with an etching solution such as copper chloride, iron chloride, sulfuric acid-hydrogen peroxide, and nitric acid-hydrogen peroxide. After that, the second wiring 106b can be manufactured by removing the etching resist.
In addition, the first wiring 106a and the second wiring 106b can be formed at the same time by the above method, which is efficient and preferable.

The first wiring 106a includes a first interlayer connection terminal 101 and a semiconductor chip connection terminal (portion electrically connected to the semiconductor chip).
The second wiring 106 b includes a second interlayer connection terminal 103.
A semi-additive method may be used as a method for forming the fine wiring.

(Process d)
In step (d), as shown in FIG. 2D, a buildup layer (interlayer insulating layer) 104 is formed on the surface on which the second wiring 106b is formed, and a third layer is formed on the buildup layer 104. This is a step of forming the copper layer 118c.

(Step d-1)
First, the surface of the second wiring 106b is subjected to the degreasing treatment and washed with hydrochloric acid or sulfuric acid.
Next, a noble metal than copper, for example, a metal selected from gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium, iridium or an alloy containing these metals is discretely dispersed on the copper wiring surface (first 2 is formed on the wiring 106b) and immersed in an alkaline solution containing an oxidizing agent to perform oxidation treatment, and then at least one of reduction treatment, coupling treatment, and corrosion inhibition treatment is performed as necessary. You may go.

(Step d-2)
Next, the surface of the copper foil to be bonded onto the buildup layer 104 is degreased and washed with hydrochloric acid or sulfuric acid.
Next, a metal selected from gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium, iridium, or an alloy containing these metals, which is a noble metal than copper, is formed discretely, and an oxidizing agent is added. Oxidation treatment may be performed by immersing in an alkaline solution that is contained, and then at least one treatment of reduction treatment, coupling treatment, corrosion inhibition treatment, galvanization treatment, and chromate treatment may be performed as necessary.

(Step d-3)
Next, the buildup layer 104 is adhered to the surface of the core substrate 100 and the surface of the second wiring 106b, and the buildup layer 104 and the copper foil on the side processed in (Step d-2) are adhered to each other. Layer 118c is formed.
As the insulating material of the buildup layer 104, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used as described above, but it is preferable that the thermosetting material is a main component.
As a bonding method, a build-up layer can be obtained by using a technique such as pressing or laminating. When the insulating material includes a thermosetting material, it is desirable to further heat and cure.

(Process e)
(Step e) is a step of forming a second interlayer connection IVH (via hole) 108 in the build-up layer, as shown in FIG. 2 (e). The method is preferred. The method can be performed in the same manner as the first interlayer connection IVH 102 in the step (b). Then, it is preferable to perform a desmear process as needed.

(Process f)
In step (f), as shown in FIG. 2 (f), in order to make an interlayer connection between the second wiring 106b and the third copper layer 118c, the third copper layer 118c and the second interlayer connection IVH 108 are used. In this step, a thin conductive layer is formed on the second interlayer connection terminal 103, and then the second via hole and the third wiring 106c are formed. The second via hole can be formed by filling with a conductive paste or plating.

  Further, the third wiring 106c can be formed in the same manner as the first wiring 106a and the second wiring 106b in the above (step a). As a process for forming a fine wiring of L / S = 35 μm / 35 μm or less, the above-described semi-additive method is preferable.

  A plating resist is formed in a necessary pattern on the third copper layer 118c which is a seed layer, and the third wiring 106c and the second via hole are simultaneously formed by electrolytic copper plating through the seed layer. Thereafter, by removing the plating resist and finally removing the seed layer by etching or the like, a fine wiring can be formed.

  (Steps d) to (step f) may be repeated to produce two or more buildup layers 104 as shown in FIG. In this case, the interlayer connection terminal formed in the outermost buildup layer becomes the external connection terminal 107.

(Process g)
(Step g) is a step of forming an insulating coating 109 for protecting wirings other than the external connection terminals 107 as shown in FIG. As the insulating coating material, a solder resist is used, and a thermosetting type or an ultraviolet curing type can be used, but an ultraviolet curing type capable of finishing the resist shape with high accuracy is preferable.

(Shape of semiconductor chip mounting substrate)
The shape of the semiconductor chip mounting substrate 22 is not particularly limited, but is preferably a frame shape as shown in FIG. By making the shape of the semiconductor chip mounting substrate in this way, it is possible to efficiently assemble the semiconductor package.
Hereinafter, a preferable frame shape will be described in detail.

  As shown in FIG. 7, a block 23 is formed in which a plurality of semiconductor package regions 13 (parts to be a single semiconductor package) are arranged in rows and columns at regular intervals. Further, such a block is formed in a plurality of rows and columns. Although only two blocks are shown in FIG. 7, the blocks may be arranged in a lattice shape as necessary. Here, the width of the space between the semiconductor package regions is preferably 50 to 500 μm, and more preferably 100 to 300 μm. Furthermore, it is most preferable that the blade width of the dicer used when the semiconductor package is cut later is made the same.

By arranging the semiconductor package region in this way, the semiconductor chip mounting substrate can be effectively used.
Further, a positioning mark 11 or the like is preferably formed at the end of the semiconductor chip mounting substrate, and more preferably a pin hole by a through hole. The shape and arrangement of the pin holes may be selected so as to match the forming method and the semiconductor package assembly apparatus.

  Furthermore, it is preferable to form a reinforcing pattern 24 in the space between the semiconductor package regions or outside the block. The reinforcing pattern 24 may be separately manufactured and bonded to the semiconductor chip mounting substrate, but is preferably a metal pattern formed at the same time as the wiring formed in the semiconductor package region. It is more preferable to apply the same plating of nickel, gold or the like or to apply an insulating coating.

When the reinforcing pattern 24 is made of such a metal, it can be used as a plating lead for electrolytic plating.
Moreover, it is preferable to form the cutting position alignment mark 25 at the time of cutting with a dicer outside the block. In this way, a frame-shaped semiconductor chip mounting substrate can be manufactured.

(Semiconductor package)
FIG. 3 is a schematic cross-sectional view showing an example of a flip chip type semiconductor package embodiment of the present invention. As shown in FIG. 3, the semiconductor package of the present invention is such that the semiconductor chip 111 is further mounted on the semiconductor chip mounting substrate of the present invention, and the semiconductor chip and the semiconductor chip connection terminal are connected using the connection bumps 112. It is electrically connected by flip chip connection.

  Further, in these semiconductor packages, it is preferable to seal between the semiconductor chip and the semiconductor chip mounting substrate with an underfill material 113 as shown in the figure. The thermal expansion coefficient of the underfill material is preferably approximate to the thermal expansion coefficient of the semiconductor chip and the core substrate 100, but is not limited thereto. More preferably, (thermal expansion coefficient of the semiconductor chip) ≦ (thermal expansion coefficient of the underfill material) ≦ (thermal expansion coefficient of the core substrate).

  Furthermore, the semiconductor chip can be mounted using an anisotropic conductive film (ACF) or an adhesive film (NCF) that does not contain conductive particles. In this case, since it is not necessary to seal with an underfill material, it is more preferable. Furthermore, it is particularly preferable to use ultrasonic waves together with the semiconductor chip because electrical connection can be made at a low temperature and in a short time.

FIG. 4 shows a cross-sectional view of an embodiment of a wire bond type semiconductor package. Although a general die bond paste can be used for mounting the semiconductor chip, it is more preferable to use a die bond film 117.
Electrical connection between the semiconductor chip and the semiconductor chip connection terminal is performed by wire bonding using a gold wire 115.
The semiconductor chip can be sealed by transfer molding using a semiconductor sealing resin 116.

  In this case, the sealing region may seal only a necessary portion, for example, only the face surface of the semiconductor chip, but it is more preferable to seal the entire semiconductor package region as shown in FIG. This is a particularly effective method in the case where a plurality of semiconductor package regions are arranged in rows and columns and the substrate and the sealing resin are cut simultaneously with a dicer or the like.

In addition, for example, a solder ball 114 can be mounted on the external connection terminal 107 for electrical connection with the motherboard. For the solder balls, eutectic solder or Pb-free solder is used. As a method for fixing the solder ball to the external connection terminal 107, for example, an N ₂ reflow apparatus or the like can be used, but this is not limited.
In a semiconductor chip mounting substrate in which a plurality of semiconductor package regions are arranged in rows and columns, the semiconductor package region is finally cut into individual semiconductor packages using a dicer or the like.

Hereinafter, the present invention will be described in detail based on examples, but the present invention is not limited thereto.
Example 1
(Process a)
(Process a-1)
For the acid degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) adjusted to 200 ml / L for the 18 μm electrolytic copper foil mat surface (M surface) that has not been subjected to roughening treatment, chemical conversion treatment, or rust prevention treatment. After immersing for 2 minutes at a liquid temperature of 50 ° C., it was rinsed with hot water by immersing in water at a liquid temperature of 50 ° C. for 2 minutes, and further washed for 1 minute.
Subsequently, it was immersed in a 3.6 N sulfuric acid aqueous solution for 1 minute and washed with water for 1 minute.

(Process a-2)
After passing through the above pretreatment step, it was immersed in substituted palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. for 3 minutes to give 1.0 μmol / dm ² of substituted palladium plating, and washed with water for 1 minute. Then, it was immersed at 50 ° C. for 1 minute in an oxidation treatment solution in which 15 g / L of sodium chlorite was added to an alkaline solution containing 10 g / L of trisodium phosphate and 25 g / L of potassium hydroxide.
Thereafter, it was washed with water for 5 minutes, immersed in a reduction treatment solution HIST-100D (manufactured by Hitachi Chemical Co., Ltd., trade name) for 1 minute at 30 ° C., and further washed with water for 10 minutes. After this treatment step, it was dried at 85 ° C. for 30 minutes.

(Process a-3)
As a base material to be the core substrate 100, 0.1 mm thickness × 4 sheets of GXA-67Y (manufactured by Hitachi Chemical Co., Ltd., trade name, low dielectric constant resin) prepreg is prepared, and on both sides of the four prepregs, The M surface of the copper foil that is the side treated in (Step a-2) is subjected to an adhesive treatment by pressing under the condition 1 shown below, and the first copper layer 118a and the second copper are applied to the surface of the core substrate 100. Layer 118b was formed.

(Condition 1)
Hot plate heating rate: 5 ° C / min
Hot plate retention time: 200 ° C / 90min
Hot plate cooling time: 5 ° C / min
Hot plate cooling time: 30 min
Pressurization time: 2.94 MPa (30 kgf / cm ² ) · 155 min

(Process b)
A through hole having a diameter of 150 μm was formed with a drill until the first interlayer connection terminal 101 was reached from the surface opposite to the first copper layer 118 a of the core substrate 100.
Subsequently, the desmear process in a hole was performed. As a desmear treatment method, it was immersed in a swelling liquid circular positive hole 4125 (Rohm and Haas Electronic Materials Co., Ltd., product name) at 80 ° C. for 3 minutes and then washed with water for 3 minutes.

Then, it was immersed in desmear liquid circulation MLB promoter 213 (Rohm and Haas Electronic Materials Co., Ltd., product name) at 80 ° C. for 5 minutes and then washed with water for 3 minutes.
Subsequently, it was immersed in a reducing liquid circuposit MLB216-4 (Rohm and Haas Electronic Materials Co., Ltd., product name) at 40 ° C. for 3 minutes, washed with water for 3 minutes, and dried at 85 ° C. for 30 minutes.

  Copper plating was formed on the side wall of the obtained through hole in the order of electroless copper plating and electrolytic copper plating as plating treatment. Then, hole filling was performed, and further, copper plating (lid copper plating) was formed in the order of electroless copper plating and electrolytic copper plating, and a first interlayer connection IVH (via hole) 102 was formed on the core substrate 100.

(Process c)
An etching resist is formed in the shape of the first wiring 106a on the first copper layer 118a formed in (Step a), and the shape of the second wiring 106b is formed on the second copper layer 118b. An etching resist is formed, the copper layer is etched using a ferric chloride etchant, and then the etching resist is removed, whereby the first wiring 106a (the first interlayer connection terminal 101 and the semiconductor chip connection terminal) And the second wiring 106b (including the second interlayer connection terminal 103 and the semiconductor chip connection terminal).

(Process d)
(Step d-1)
The wiring surface on the second wiring 106b side formed in (Step c) was immersed in acidic degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) adjusted to 200 ml / L for 2 minutes at a liquid temperature of 50 ° C. Then, it was washed with hot water by immersing it in water having a liquid temperature of 50 ° C. for 2 minutes, and further washed with water for 1 minute.
Subsequently, it was immersed in a 3.6 N sulfuric acid aqueous solution for 1 minute and washed with water for 1 minute.

After this pretreatment step, it was immersed in substituted palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. for 3 minutes to give 1.0 μmol / dm ² substituted palladium plating, and washed with water for 1 minute. Then, it was immersed for 1 minute at 50 ° C. in an oxidation treatment solution obtained by adding 15 g / L of sodium chlorite to an alkaline solution containing 10 g / L of trisodium phosphate and 25 g / L of potassium hydroxide. Thereafter, it was washed with water for 5 minutes, immersed in a reduction treatment solution HIST-100D (manufactured by Hitachi Chemical Co., Ltd., trade name) for 1 minute at 30 ° C., and further washed with water for 10 minutes. After these steps, it was dried at 85 ° C. for 30 minutes.

(Step d-2a)
After immersing the ultrathin side copper foil surface of copper foil with carrier 3 μm in acidic degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) adjusted to 200 ml / L for 2 minutes at a liquid temperature of 50 ° C., the liquid temperature It was washed with hot water by immersing it in water at 50 ° C. for 2 minutes, and further washed with water for 1 minute.
Subsequently, it was immersed in a 3.6 N sulfuric acid aqueous solution for 1 minute and washed with water for 1 minute.

(Step d-2b)
After passing through the above pretreatment step, it was immersed in a substituted palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. for 3 minutes to give 1.0 μmol / dm ² substituted palladium plating, and washed with water for 1 minute. Then, it was immersed for 1 minute at 50 ° C. in an oxidation treatment solution obtained by adding 15 g / L of sodium chlorite to an alkaline solution containing 10 g / L of trisodium phosphate and 25 g / L of potassium hydroxide.
Thereafter, it was washed with water for 5 minutes, immersed in a reduction treatment solution HIST-100D (manufactured by Hitachi Chemical Co., Ltd., trade name) for 1 minute at 30 ° C., and further washed with water for 10 minutes. After this treatment step, it was dried at 85 ° C. for 30 minutes.

(Step d-3)
A 0.03 mm thick GXA-67Y (manufactured by Hitachi Chemical Co., Ltd., trade name, low dielectric constant resin) prepreg is prepared, and the surface of the second wiring 106b treated in (Step d-1) is formed on one side of the prepreg. The one side of the copper foil surface treated in (step d-2a) (step d-2b) is subjected to an adhesion treatment under the following condition 2 by pressing, and then the carrier of the copper foil with carrier is pulled. The buildup layer 104 and the third copper layer 118c were formed by peeling off.

(Condition 2)
Hot plate heating rate: 5 ° C / min
Heat plate holding time: 175 ° C / 20min, 200 ° C / 90min
Hot plate cooling time: 5 ° C / min
Hot plate cooling time: 30 min
Pressurization time: 0.49 MPa (5 kgf / cm ² ) · 10 min, 2.94 MPa (30 kgf / cm ² ) · 165 min

(Process e)
An IVH hole, which is a second via hole having a hole diameter of 50 μm, was formed with a laser until it reached the second interlayer connection terminal 103 from the surface of the third copper layer 118c. YAG laser LAVIA-UV2000 (manufactured by Sumitomo Heavy Industries, Ltd., trade name) was used as the laser, and IVH holes were formed under the conditions of frequency 4 kHz, number of shots 20 and mask diameter 0.4 mm.
Thereafter, desmear treatment was performed. The desmear treatment method was performed in the same manner as in (Step b).

(Process f)
In order to perform interlayer connection between the copper layer 118 c and the second interlayer connection terminal 103, electroless plating was formed in the formed second IVH 108.
Next, a plating resist layer having a thickness of 10 μm is formed on the seed layer by spin coating using a plating resist PMER P-LA900PM (trade name, manufactured by Tokyo Ohka Kogyo Co., Ltd.) on the third copper layer 118c. did. Exposure was performed under conditions of 1000 mJ / cm ² , and immersion rocking was performed at 23 ° C. for 6 minutes using PMER developer P-7G to form a resist pattern of L / S = 15 μm / 15 μm.

  Then, pattern copper plating was performed about 5 micrometers using the copper sulfate plating solution. The plating resist was removed by dipping for 1 minute at room temperature (25 ° C.) using methyl ethyl ketone. For quick etching of the seed layer, a 5-fold diluted solution of CPE-700 (manufactured by Mitsubishi Gas Chemical Co., Ltd., trade name) is used for etching removal by immersing and shaking at 30 ° C. for 30 seconds, and wiring. Formed.

Thereafter, the steps (d) to (step f) were repeated again to form a further outermost layer wiring including the buildup layer and the external connection terminal 107.
(Process g)
Finally, a solder resist 109 is formed, and a fan-in type as shown in FIG. 1 (sectional view of one package), FIG. 5 (plan view of one package) and FIG. A semiconductor chip mounting substrate for BGA was produced.

(Process h)
Next, an ultrasonic wave is applied to the semiconductor chip 111 on which the connection bumps 112 are formed on the semiconductor chip mounting region of the semiconductor chip mounting substrate manufactured by the above-described (step a) to (step g) using a flip chip bonder. While installing as many as needed.
Furthermore, an underfill material is injected from the end of the semiconductor chip into the gap between the semiconductor chip mounting substrate and the semiconductor chip, and primary curing is performed at 80 ° C. for 1 hour and secondary curing at 150 ° C. for 4 hours using an oven. It was.

Next, a lead / tin eutectic solder ball 114 having a diameter of 0.45 mm was fused to the external connection terminal using an N ₂ reflow apparatus.
Finally, the semiconductor chip mounting substrate was cut with a dicer equipped with a blade having a width of 200 μm to produce the semiconductor package shown in FIG.

Example 2
In (Step a-2) and (Step d-2b), it was immersed in substituted palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. for 3 minutes, and 1.0 μmol / dm ² of substituted palladium. The plate was plated, washed with water for 1 minute, and immersed in an oxidation treatment solution in which 15 g / L of sodium chlorite was added to an alkaline solution containing 10 g / L of trisodium phosphate and 25 g / L of potassium hydroxide at 50 ° C. for 1 minute.

  Thereafter, it was washed with water for 5 minutes, immersed in a reduction treatment solution HIST-100D (manufactured by Hitachi Chemical Co., Ltd., trade name) for 1 minute at 30 ° C., and further washed with water for 10 minutes. After passing through these steps, it was immersed in a 0.5% aqueous solution of γ-aminopropyltriethoxysilane at 30 ° C. for 3 minutes to give a coupling treatment and washed with water for 1 minute. After this treatment step, it was dried at 85 ° C. for 30 minutes. Except for these steps, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1.

Example 3
In (Step a-2) and (Step d-2b), it was immersed in substituted palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. for 3 minutes, and 1.0 μmol / dm ² of substituted palladium. The plate was plated, washed with water for 1 minute, and immersed in an oxidation treatment solution in which 15 g / L of sodium chlorite was added to an alkaline solution containing 10 g / L of trisodium phosphate and 25 g / L of potassium hydroxide at 50 ° C. for 1 minute.

  Thereafter, it was washed with water for 5 minutes, immersed in the reduction treatment liquid HIST-100D (trade name, manufactured by Hitachi Chemical Co., Ltd.) at 30 ° C. for 1 minute, and further washed with water for 10 minutes. After passing through these steps, 2-amino-6-hydroxy-8-mercaptopurine (trade name, manufactured by Wako Pure Chemical Industries, Ltd.) was immersed in an ethanol solution having a concentration of 10 ppm at 25 ° C. for 10 minutes, Washed with water for 1 minute. After this treatment step, it was dried at 85 ° C. for 30 minutes. Except for these steps, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1.

Example 4
In (Step a-2) and (Step d-2b), it was immersed in a substituted palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. for 3 minutes, and 1.0 μmol / dm ² substituted palladium plating. After washing with water for 1 minute, it was immersed in an oxidation treatment solution obtained by adding 15 g / L of sodium chlorite to an alkaline solution containing 10 g / L of trisodium phosphate and 25 g / L of potassium hydroxide at 50 ° C. for 1 minute.

  Thereafter, it was washed with water for 5 minutes, immersed in the reduction treatment liquid HIST-100D (trade name, manufactured by Hitachi Chemical Co., Ltd.) at 30 ° C. for 1 minute, and further washed with water for 10 minutes. After passing through these steps, the concentration of 3-amino-5-mercapto-1,2,4-triazole (made by Wako Pure Chemical Industries, Ltd., trade name) is 10 ppm in an ethanol solution at 25 ° C. for 10 minutes. Immerse and wash with water for 1 minute. After this treatment step, it was dried at 85 ° C. for 30 minutes. Except for these steps, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1.

Example 5
In (Step a-2) and (Step d-2b), it was immersed in substituted palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. for 3 minutes, and 1.0 μmol / dm ² of substituted palladium. The plate was plated, washed with water for 1 minute, and immersed in an oxidation treatment solution in which 15 g / L of sodium chlorite was added to an alkaline solution containing 10 g / L of trisodium phosphate and 25 g / L of potassium hydroxide at 50 ° C. for 1 minute.

  Thereafter, it was washed with water for 5 minutes, immersed in the reduction treatment liquid HIST-100D (trade name, manufactured by Hitachi Chemical Co., Ltd.) at 30 ° C. for 1 minute, and further washed with water for 10 minutes. After passing through these steps, 2-amino-6-hydroxy-8-mercaptopurine (trade name, manufactured by Wako Pure Chemical Industries, Ltd.) was immersed in an ethanol solution having a concentration of 10 ppm at 25 ° C. for 10 minutes, Washed with water for 1 minute. Furthermore, it was immersed in a 0.5% aqueous solution of γ-aminopropyltriethoxysilane at 30 ° C. for 3 minutes for coupling treatment and washed for 1 minute. After this treatment step, it was dried at 85 ° C. for 30 minutes. Except for these steps, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1.

Example 6
In (Step a-2) and (Step d-2b), it was immersed in substituted palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. for 3 minutes, and 1.0 μmol / dm ² of substituted palladium. The plate was plated, washed with water for 1 minute, and immersed in an oxidation treatment solution in which 15 g / L of sodium chlorite was added to an alkaline solution containing 10 g / L of trisodium phosphate and 25 g / L of potassium hydroxide at 50 ° C. for 1 minute.

  Thereafter, it was washed with water for 5 minutes, immersed in the reduction treatment liquid HIST-100D (trade name, manufactured by Hitachi Chemical Co., Ltd.) at 30 ° C. for 1 minute, and further washed with water for 10 minutes. Further, it was immersed in a 0.5% aqueous solution of γ-aminopropyltriethoxysilane at 30 ° C. for 3 minutes to perform a coupling treatment and washed with water for 1 minute. After passing through these steps, the concentration of 3-amino-5-mercapto-1,2,4-triazole (made by Wako Pure Chemical Industries, Ltd., trade name) is 10 ppm in an ethanol solution at 25 ° C. for 10 minutes. Immerse and wash with water for 1 minute. After this treatment step, it was dried at 85 ° C. for 30 minutes. Except for these steps, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1.

Example 7
In (Step a-2) and (Step d-2b), a displacement gold plating solution HGS-500 (Hitachi Chemical Industry Co., Ltd., product name) was immersed for 1 minute at 30 ° C., and a displacement of 1.0 μmol / dm ² The plate was plated, washed with water for 1 minute, and immersed in an oxidation treatment solution in which 15 g / L of sodium chlorite was added to an alkaline solution containing 10 g / L of trisodium phosphate and 25 g / L of potassium hydroxide at 50 ° C. for 1 minute.

  Thereafter, it was washed with water for 5 minutes, immersed in the reduction treatment liquid HIST-100D (trade name, manufactured by Hitachi Chemical Co., Ltd.) at 30 ° C. for 1 minute, and further washed with water for 10 minutes. After this treatment step, it was dried at 85 ° C. for 30 minutes. Except for these steps, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1.

Example 8
In (Step a-2) and (Step d-2b), immersed in a substituted silver plating solution containing 7.5 g / L of silver nitrate, 75 g / L of ammonium hydroxide, and sodium thiosulfate pentahydrate at 30 ° C. for 20 seconds. Then, a substitution silver plating of 1.0 μmol / dm ² was applied, washed with water for 1 minute, and an oxidation treatment in which 15 g / L of sodium chlorite was added to an alkaline solution containing 10 g / L of trisodium phosphate and 25 g / L of potassium hydroxide. It was immersed in the liquid at 50 ° C for 3 minutes.

  Thereafter, it was washed with water for 5 minutes, immersed in the reduction treatment liquid HIST-100D (trade name, manufactured by Hitachi Chemical Co., Ltd.) at 30 ° C. for 1 minute, and further washed with water for 10 minutes. After this treatment step, it was dried at 85 ° C. for 30 minutes. Except for these steps, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1.

Example 9
In (Step a-2) and (Step d-2b), it was immersed in substituted palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. for 3 minutes, and 1.0 μmol / dm ² of substituted palladium. Plating was performed, washed with water for 1 minute, and immersed in an oxidation treatment solution in which 15 g / L of sodium chlorite was added to an alkaline solution containing 10 g / L of trisodium phosphate and 25 g / L of potassium hydroxide at 50 ° C. for 3 minutes.

Thereafter, it was washed with water for 5 minutes, immersed in a reduction treatment solution HIST-100D (manufactured by Hitachi Chemical Co., Ltd., trade name) for 3 minutes at 40 ° C., and further washed with water for 10 minutes. Furthermore, it was immersed in a zinc plating solution having a pH of 7.0 containing 10 g / L of zinc chloride and 20 g / L of ammonium chloride at a current density of 0.4 A / dm ² for 2 seconds and then washed with water for 5 minutes. After this treatment step, it was dried at 85 ° C. for 30 minutes. Except for these steps, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1.

Example 10
In (Step a-2) and (Step d-2b), a substituted palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) was immersed for 3 minutes at 30 ° C., and 1.0 μmol / dm ² of substituted palladium. Plating was performed, washed with water for 1 minute, and immersed in an oxidation treatment solution in which 15 g / L of sodium chlorite was added to an alkaline solution containing 10 g / L of trisodium phosphate and 25 g / L of potassium hydroxide at 50 ° C. for 3 minutes.
Thereafter, it was washed with water for 5 minutes, immersed in a reduction treatment solution HIST-100D (manufactured by Hitachi Chemical Co., Ltd., trade name) for 3 minutes at 40 ° C., and further washed with water for 10 minutes.

Next, it was immersed in a zinc plating solution having a pH of 7.0 containing 10 g / L of zinc chloride and 20 g / L of ammonium chloride at a current density of 0.4 A / dm ² for 2 seconds, then washed with water for 5 minutes, It was immersed in a chromate treatment solution having a pH of 3.5 containing sodium chromate dihydrate (3.5 g / L) at a current density of 0.5 A / dm ² for 5 seconds and then washed with water for 5 minutes. After this treatment step, it was dried at 85 ° C. for 30 minutes. Except for these steps, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1.

Example 11
In (Step a-2) and (Step d-2b), a substituted palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) was immersed for 3 minutes at 30 ° C., and 1.0 μmol / dm ² of substituted palladium. Plating was performed, washed with water for 1 minute, and immersed in an oxidation treatment solution in which 15 g / L of sodium chlorite was added to an alkaline solution containing 10 g / L of trisodium phosphate and 25 g / L of potassium hydroxide at 50 ° C. for 3 minutes.

Thereafter, it was washed with water for 5 minutes, immersed in a reduction treatment solution HIST-100D (manufactured by Hitachi Chemical Co., Ltd., trade name) at 40 ° C. for 3 minutes, and then washed with water for 10 minutes.
Furthermore, it was immersed in a zinc plating solution having a pH of 7.0 containing 10 g / L of zinc chloride and 20 g / L of ammonium chloride at a current density of 0.4 A / dm ² for 2 seconds.

Thereafter, it was washed with water for 5 minutes and further immersed in a chromate treatment solution having a pH of 3.5 containing sodium dichromate dihydrate 3.5 g / L at a current density of 0.5 A / dm ² for 5 seconds. And then washed with water for 5 minutes.

  Furthermore, it was immersed in a 0.5% aqueous solution of γ-aminopropyltriethoxysilane at 30 ° C. for 10 seconds, subjected to a coupling treatment, and washed with water for 1 minute. After this treatment step, it was dried at 85 ° C. for 30 minutes. Except for these steps, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1.

Example 12
Roughening treatment, chemical conversion treatment, and 18μm electrolytic copper foil not subjected to rust prevention treatment were cut into 5cm x 8cm x 2 pieces (for adhesion test and copper foil surface roughness evaluation), and this electrolytic copper foil M surface was tested. As a piece, the surface treatment described in (Step a-1) and (Step a-2) of Example 1 was performed.

  MCL-LX-67 (manufactured by Hitachi Chemical Co., Ltd.), a double-sided copper-clad laminate impregnated with a glass cloth-cyanate ester resin composition having a thickness of 0.8 mm, which can be used as a low dielectric loss tangent high heat resistant multilayer material ), A copper surface having a surface roughness Rz = 3.5 μm was prepared using a chemical etching roughening solution HIST-7300 (manufactured by Hitachi Chemical Co., Ltd., product name).

  Thereafter, GXA-67N of prepreg (trade name, manufactured by Hitachi Chemical Co., Ltd.) in which a glass cloth is impregnated with a cyanate ester resin composition on a copper surface of Rz = 3.5 μm, and the surface treatment is applied to the outermost layer. 1 layered copper foil for adhesion evaluation subjected to adhesion, heated at a pressure of 3.0 MPa from room temperature (25 ° C.) to 200 ° C. at a rate of temperature increase of 5 ° C./min, and held at 200 ° C. for 90 minutes. Was laminated and bonded to prepare an adhesion test substrate.

The surface roughness (Rz) of the electrolytic copper foil M surface for copper foil surface roughness evaluation was measured under the condition 3 shown below using a simple atomic force microscope (AFM) Nanopics 2100.
(Condition 3)
Measurement length: 1 μm
SCAN SPEED: 1.35 μm / sec
FORCE REFERENCE: 160

Example 13
The surface treatment for the electrolytic copper foil was carried out in the same manner as in Example 12 except that the surface treatment was described in (Step a-2) of Example 2.

Example 14
The surface treatment for the electrolytic copper foil was performed in the same manner as in Example 12 except that the surface treatment described in (Step a-2) of Example 3 was performed.

Example 15
The surface treatment for the electrolytic copper foil was performed in the same manner as in Example 12 except that the surface treatment described in (Step a-2) of Example 4 was performed.

Example 16
The surface treatment for the electrolytic copper foil was performed in the same manner as in Example 12 except that the surface treatment described in (Step a-2) of Example 5 was performed.

Example 17
The surface treatment for the electrolytic copper foil was carried out in the same manner as in Example 12 except that the surface treatment was described in (Step a-2) of Example 6.

Example 18
Except that the surface treatment for the electrolytic copper foil was the surface treatment described in (Step a-2) of Example 7, it was performed in the same manner as Example 12.

Example 19
The surface treatment for the electrolytic copper foil was performed in the same manner as in Example 12 except that the surface treatment described in (Step a-2) of Example 8 was performed.

Example 20
The surface treatment for the electrolytic copper foil was performed in the same manner as in Example 12, except that the surface treatment described in (Step a-2) of Example 9 was performed.

Example 21
The surface treatment for the electrolytic copper foil was performed in the same manner as in Example 12 except that the surface treatment described in (Step a-2) of Example 10 was performed.

Example 22
The surface treatment for the electrolytic copper foil was performed in the same manner as in Example 11 except that the surface treatment described in (Step a-2) of Example 11 was performed.

Example 23
(Process a ')
In order to perform an inter-wiring insulation reliability test, as shown in FIG. 13A ', after performing (Step a-1) and (Step a-2) shown in Example 1, (Step a-3) ), The copper foil on the side treated in (Step a-2) was bonded to one side of the prepreg under the same conditions by pressing to form the second copper layer 118b on one side of the core substrate 100. However, the electrolytic copper foil used to form the second copper layer 118b was a 3 μm copper foil obtained by peeling off a carrier of 3 μm copper foil with carrier.

(Process c ')
An etching resist is formed in the shape of the second wiring 106b on the second copper layer 118b formed in (Step a ′), and etching is performed using a ferric chloride etchant, and then the etching resist is formed. By removing, the second wiring 106b having L / S = 10 μm / 10 μm shown in FIG. 9 and L / S = 15 μm / 15 μm shown in FIG. 10 was formed.

(Process d ')
The surface on the second wiring 106b side formed in (Step c ′) was processed in the same manner as in (Step d-1) shown in Example 1. Next, a 0.03 mm thick GXA-67Y (manufactured by Hitachi Chemical Co., Ltd., trade name, low dielectric constant resin) prepreg is prepared, and the surface of the second wiring 106b side is bonded to the prepreg (step d). -3).

The insulation resistance between each L / S wiring was measured by applying a DC5V voltage for 30 seconds at room temperature using an R-8340A type digital ultra-high resistance microammeter manufactured by Advantest Co., Ltd. did.
A digital multimeter 3457A manufactured by Hewlett-Packard (HP) was used for measuring the insulation resistance of 1 GΩ or less.

  Next, a voltage DC5V was continuously applied in a constant humidity and constant temperature layer maintained at 85 ° C. and a relative humidity of 85%, and after 24 h, 48 h, 96 h, 200 h, 500 h and 1,000 h, each L / S was similarly applied to the above. The insulation resistance value between the wirings was measured. The constant temperature and humidity chamber was an EC-10HHPS type constant temperature and constant temperature manufactured by Hitachi, Ltd., and measured up to 1000 hours after charging.

Example 24
(Step a-2) in (Step a ′) was subjected to the surface treatment described in Example 2, and was otherwise performed in the same manner as Example 23.

Example 25
(Step a-2) of (Step a ′) was performed in the same manner as in Example 23 except that the surface treatment described in Example 3 was performed.

Example 26
(Step a-2) in (Step a ′) was subjected to the surface treatment described in Example 4, and was otherwise performed in the same manner as Example 23.

Example 27
(Step a-2) in (Step a ′) was subjected to the surface treatment described in Example 5, and the other procedures were performed in the same manner as in Example 23.

Example 28
(Step a-2) in (Step a ′) was subjected to the surface treatment described in Example 6, and was otherwise performed in the same manner as Example 23.

Example 29
(Step a-2) of (Step a ′) was subjected to the surface treatment described in Example 7, and was otherwise performed in the same manner as Example 23.

Example 30
(Step a-2) of (Step a ′) was subjected to the surface treatment described in Example 8, and was otherwise performed in the same manner as Example 23.

Example 31
(Step a-2) of (Step a ′) was subjected to the surface treatment described in Example 9, and the others were performed in the same manner as Example 23.

Example 32
(Step a-2) of (Step a ′) was subjected to the surface treatment described in Example 10, and the others were performed in the same manner as Example 23.

Example 33
(Step a-2) of (Step a ′) was subjected to the surface treatment described in Example 11, and was otherwise performed in the same manner as Example 23.

Example 34
In order to perform wiring formation evaluation and confirmation of the presence or absence of remaining copper between the wirings, the processes of (step a ′) and (step c ′) shown in Example 23 are performed, and the second wiring 106b is shown in FIG. An evaluation substrate of / S = 30 μm / 30 μm was produced. However, the electrolytic copper foil used to form the second copper layer 118b in (Step a ′) was a 12 μm copper foil.
Next, the top width (WT) of the wiring was measured.

  Thereafter, the surface of the wiring is immersed in acidic degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) at a liquid temperature of 50 ° C. for 2 minutes, and then immersed in water at a liquid temperature of 50 ° C. for 2 minutes. It was further washed with water for 1 minute. Subsequently, it was immersed in a 3.6 N sulfuric acid aqueous solution for 1 minute and washed with water for 1 minute.

After passing through this pretreatment step, it was immersed in a substituted palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. for 3 minutes to give a substituted palladium plating of 1.0 μmol / dm ² and washed with water for 1 minute. Then, it was immersed in an electroless nickel plating solution NIPS-100 (Hitachi Chemical Industry Co., Ltd., product name) at 85 ° C. for 20 minutes. Then, the presence or absence of the remaining copper between wiring was evaluated by confirming the presence or absence of the plating precipitation between wiring.

Example 35
(Step a-2) of (Step a ′) was subjected to the surface treatment described in Example 2, and was otherwise performed in the same manner as Example 34.

Example 36
(Step a-2) in (Step a ′) was subjected to the surface treatment described in Example 3, and was otherwise performed in the same manner as Example 34.

Example 37
(Step a-2) of (Step a ′) was subjected to the surface treatment described in Example 4, and was otherwise performed in the same manner as Example 34.

Example 38
(Step a-2) of (Step a ′) was subjected to the surface treatment described in Example 5, and was otherwise performed in the same manner as Example 34.

Example 39
(Step a-2) in (Step a ′) was subjected to the surface treatment described in Example 6, and was otherwise performed in the same manner as in Example 34.

Example 40
(Step a-2) in (Step a ′) was subjected to the surface treatment described in Example 7, and the other procedures were performed in the same manner as in Example 34.

Example 41
(Step a-2) of (Step a ′) was subjected to the surface treatment described in Example 8, and was otherwise performed in the same manner as Example 34.

Example 42
(Step a-2) of (Step a ′) was subjected to the surface treatment described in Example 9, and was otherwise performed in the same manner as Example 34.

Example 43
(Step a-2) in (Step a ′) was subjected to the surface treatment described in Example 10, and was otherwise performed in the same manner as Example 34.

Example 44
(Step a-2) of (Step a ′) was subjected to the surface treatment described in Example 11, and was otherwise performed in the same manner as Example 34.

Comparative Example 1
In (Step a-2) and (Step d-2b), an electrolytic copper plating solution containing 100 g / L of copper sulfate pentahydrate and 120 g / L of sulfuric acid is used for the electrolytic copper foil M surface, and the processing temperature is 35. The electrolytic treatment (over the limiting current density) was performed for 3.5 seconds at a temperature of 40 ° C. and a current density of 40 A / dm ² .
Thereafter, electrolytic treatment (less than the limit current density) was performed for 80 seconds at a treatment temperature of 50 ° C. and a current density of 5 A / dm ² using an electrolytic copper plating solution containing 250 g / L of copper sulfate pentahydrate and 100 g / L of sulfuric acid.

Next, it was washed with water for 10 minutes.
Furthermore, it was immersed in a zinc plating solution having a pH of 7.0 containing 10 g / L of zinc chloride and 20 g / L of ammonium chloride at a current density of 0.4 A / dm ² for 2 seconds. Thereafter, it was washed with water for 5 minutes and further immersed in a chromate treatment solution having a pH of 3.5 containing sodium dichromate dihydrate 3.5 g / L at a current density of 0.5 A / dm ² for 5 seconds. did.

  Thereafter, it was washed with water for 5 minutes. After this treatment step, it was dried at 85 ° C. for 30 minutes. Except for these steps, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1.

Comparative Example 2
In (Step a-2) and (Step d-2b), copper sulfate pentahydrate 100 g / L, sulfuric acid 120 g / L, and sodium tungstate dihydrate 0.6 g / L on the surface of the electrolytic copper foil M Then, using an electrolytic copper plating solution containing 15 g / L of ferrous sulfate heptahydrate, electrolytic treatment (over the limit current density) was performed for 3.5 seconds at a treatment temperature of 35 ° C. and a current density of 40 A / dm ² .
Thereafter, electrolytic treatment (less than the limit current density) was performed for 80 seconds at a treatment temperature of 50 ° C. and a current density of 5 A / dm ² using an electrolytic copper plating solution containing 250 g / L of copper sulfate pentahydrate and 100 g / L of sulfuric acid.

Next, it was washed with water for 10 minutes.
Furthermore, it was immersed in a zinc plating solution having a pH of 7.0 containing 10 g / L of zinc chloride and 20 g / L of ammonium chloride at a current density of 0.4 A / dm ² for 2 seconds. Thereafter, it was washed with water for 5 minutes and further immersed in a chromate treatment solution having a pH of 3.5 containing sodium dichromate dihydrate 3.5 g / L at a current density of 0.5 A / dm ² for 5 seconds. did.

  Thereafter, it was washed with water for 5 minutes. After this treatment step, it was dried at 85 ° C. for 30 minutes. Except for these steps, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1.

Comparative Example 3
In (Step a-2) and (Step d-2b), an oxidation treatment solution obtained by adding 15 g / L of sodium chlorite to an alkaline solution containing 10 g / L of trisodium phosphate and 25 g / L of potassium hydroxide at 85 ° C. Soaked for 3 minutes.

  Thereafter, it was washed with water for 5 minutes, immersed in a reduction treatment solution HIST-100D (trade name, reducing agent: dimethylamine borane, manufactured by Hitachi Chemical Co., Ltd.) for 5 minutes at 40 ° C., and further washed with water for 10 minutes. After this treatment step, it was dried at 85 ° C. for 30 minutes. Except for these steps, a fan-in type BGA semiconductor chip mounting substrate and a semiconductor package were produced in the same manner as in Example 1.

Comparative Example 4
(Step a-2) of (Step a) was subjected to the surface treatment described in Comparative Example 1, and was otherwise performed in the same manner as Example 12.

Comparative Example 5
(Step a-2) of (Step a) was subjected to the surface treatment described in Comparative Example 2, and was otherwise performed in the same manner as in Example 12.

Comparative Example 6
(Step a-2) of (Step a) was subjected to the surface treatment described in Comparative Example 3, and was otherwise performed in the same manner as Example 12.

Comparative Example 7
(Step a-2) in (Step a ′) was subjected to the surface treatment described in Comparative Example 1, and was otherwise performed in the same manner as in Example 23.

Comparative Example 8
(Step a-2) in (Step a ′) was subjected to the surface treatment described in Comparative Example 2, and was otherwise performed in the same manner as in Example 23.

Comparative Example 9
(Step a-2) of (Step a ′) was subjected to the surface treatment described in Comparative Example 3, and was otherwise performed in the same manner as Example 23.

Comparative Example 10
(Step a-2) of (Step a ′) was subjected to the surface treatment described in Comparative Example 1, and was otherwise performed in the same manner as in Example 34.

Comparative Example 11
(Step a-2) in (Step a ′) was subjected to the surface treatment described in Comparative Example 2, and was otherwise performed in the same manner as in Example 34.

Comparative Example 12
(Step a-2) of (Step a ′) was subjected to the surface treatment described in Comparative Example 3, and was otherwise performed in the same manner as in Example 34.
The following tests were performed on the test samples prepared as described above.

(Semiconductor package reliability test)
Each of the 22 semiconductor packages described in Examples 1 to 11 and Comparative Examples 1 to 3 was subjected to moisture absorption treatment, and then subjected to a reflow furnace having an ultimate temperature of 240 ° C. and a length of 2 m under conditions of 0.5 m / min. Rinse and reflow.
Then, the presence or absence of crack generation was examined for each sample, and the case where it occurred was determined as NG. The results are shown in Table 1.

  Similarly, 22 samples were mounted on a 0.8 mm thick mother board and subjected to a temperature cycle test at −55 ° C., 30 minutes to 125 ° C. for 30 minutes. The 500th cycle, the 1000th cycle, In the 1500th cycle, the conduction resistance value of the wiring was measured using a multimeter 3457A manufactured by Hewlett-Packard Company. The case where the measured resistance value was 10% or more from the initial resistance value and the resistance value changed was determined as NG. The results are shown in Table 1.

(Adhesion test)
Using the adhesion test substrates described in Examples 12 to 22 and Comparative Examples 4 to 6, an adhesion test after leaving at 150 ° C. was performed, and the test was performed up to 240 hours after charging. For the measurement of peel strength (N / m) as an index of adhesion, a rheometer NRM-3002D-H (trade name, manufactured by Fudo Kogyo Co., Ltd.) is used, and the angle of the electrolytic copper foil to the substrate is 90 degrees. It was always maintained and peeled off at a speed of 50 mm / min in the direction perpendicular to the substrate. A case where the peel strength value was 800 N / m or more was indicated by ◯, and a case where the peel strength value was less than 800 N / m was indicated by ×. The results are shown in Table 2.

(Copper foil surface roughness evaluation test)
Copper surface roughness Rz was measured using the copper foil surface roughness evaluation substrate described in Examples 12 to 22 and Comparative Examples 4 to 6. The case where the value of Rz showed a value of 1 μm or less was marked as ◯, and the case where the value exceeding 1 μm was shown as x. The results are also shown in Table 2.

(Insulation reliability test between wires)
Using the evaluation substrates described in Examples 23 to 33 and Comparative Examples 7 to 9, the insulation resistance value between the L / S = 10 μm / 10 μm and L / S = 15 μm / 15 μm wirings after being left was measured. The case where the resistance value showed a value of 1.0 × 10 ⁹ Ω or more was evaluated as “◯”, and the case where the resistance value was less than 1.0 × 10 ⁹ Ω was evaluated as “X”. The results are shown in Tables 3 and 4.

(Wiring formation evaluation test)
Using the evaluation board | substrate described in Examples 34-44 and Comparative Examples 10-12, the top width (WT) of the wiring after L / S = 30micrometer / 30micrometer wiring formation shown in FIG. 12 was measured. The results are shown in Table 5.

(Inter-wiring remaining copper confirmation test)
Using the evaluation boards described in Examples 34 to 44 and Comparative Examples 10 to 12, the presence or absence of residual copper between wirings was confirmed. The case where there was no remaining copper was marked with ◯, and the case where there was remaining copper was marked with X. The results are also shown in Table 5.

  As shown in Examples 1 to 44, in the case of the present invention, fine irregularities having a surface roughness Rz of 1.0 μm or less are formed on the copper foil surface, and even in the case of such a smooth copper foil surface, The adhesive strength (peel strength) with the insulating layer was 800 N / m or more after standing at 150 ° C. for 240 hours and was good. In addition, the reliability of the manufactured semiconductor package was extremely good. The inter-wiring insulation reliability of L / S = 10/10 μm and L / S = 15/15 μm by the electrolytic corrosion test was also very good.

  In addition, the wiring formability by etching was extremely good from the measurement results of the top width of wiring and the presence or absence of residual copper between wirings. On the other hand, in the prior art, as shown in Comparative Examples 1 to 12, it was not possible to satisfy all of smoothness, adhesiveness, semiconductor package reliability, inter-wiring insulation reliability, and wiring formability. .

Therefore, according to the present invention, fine irregularities having good adhesive strength between the copper foil surface and the insulating layer can be formed on the copper foil surface.
In addition, according to the present invention, it is possible to manufacture a multilayer wiring board and a semiconductor chip mounting board excellent in insulation reliability between wirings and wiring formability by etching, and a semiconductor package excellent in reflow resistance and temperature cycle characteristics.

It is sectional drawing of the semiconductor chip mounting substrate to which one Embodiment of this invention is applied. (A)-(g) is process drawing which shows one Embodiment of the semiconductor chip mounting substrate manufacturing method of this invention. 1 is a cross-sectional view of a flip chip type semiconductor package to which an embodiment of the present invention is applied. 1 is a cross-sectional view of a wire bond type semiconductor package to which an embodiment of the present invention is applied. It is a top view of the fan-in type semiconductor chip mounting board | substrate of this invention. It is a top view of the fan-out type semiconductor chip mounting substrate of the present invention.

It is a top view showing the frame shape of the semiconductor chip mounting substrate of this invention. It is sectional drawing of the semiconductor chip mounting substrate to which one Embodiment of this invention is applied. It is a top view of the comb type evaluation board for insulation reliability tests to which one embodiment of the present invention is applied. It is a top view of the comb type evaluation board for insulation reliability tests to which one embodiment of the present invention is applied. It is a top view of the comb type evaluation board for wiring form evaluation to which one embodiment of the present invention is applied. It is sectional drawing of the comb-type evaluation board | substrate for wiring form property evaluation with which one Embodiment of this invention is applied. (a ')-(d') is process drawing which shows one Embodiment of the evaluation board | substrate manufacturing method for electrolytic corrosion tests of this invention.

Explanation of symbols

11 Positioning mark (Guide hole for positioning)
13 Semiconductor package area 14 Die bond film adhesion area (flip chip type)
15 Semiconductor chip mounting area (flip chip type)
16 Semiconductor chip connection terminal 17 Die bond film adhesion area (wire bond type)
18 Semiconductor chip mounting area (wire bond type)
19 External connection terminal 20 Expanded wiring 21 Dummy pattern 22 Semiconductor chip mounting board 23 Block 24 Reinforcement pattern 25 Cutting alignment mark

100 Core substrate 101 First interlayer connection terminal 102 First interlayer connection IVH (via hole)
103 Second interlayer connection terminal 104 Interlayer insulating layer (build-up layer)
105 Third layer connection IVH (via hole)
106 wiring 106a first wiring 106b second wiring 106c third wiring 107 external connection terminal 108 second interlayer connection IVH (via hole)
109 Insulation coating (solder resist)

111 Semiconductor chip 112 Connection bump 113 Underfill material 114 Solder ball 115 Gold wire 116 Semiconductor sealing resin 117 Die bond film 118a First copper layer 118b Second copper layer 118c Third copper layer

Claims (10)

A step than copper discretely forming a metal nobler copper foil table surface,
A step of oxidation treatment with an alkaline solution containing an oxidizing agent to the copper foil surface,
A method for producing a substrate having a copper foil, comprising the step of adhering the surface-treated copper foil surface and a core base material . 2. The method further comprises a step of performing one or more treatments selected from the group consisting of reduction treatment, coupling treatment, corrosion inhibition treatment, galvanization treatment, and chromate treatment after the step of oxidizing the copper foil surface. The manufacturing method of the board | substrate which has the copper foil of description. The said oxidizing agent is 1 or more types selected from the group which consists of a chlorate, a chlorite, a hypochlorite, a perchlorate, and peroxodisulfate, The claim 1 or 2 A method for producing a substrate having a copper foil. 4. The metal according to claim 1, wherein the metal nobler than copper is a metal selected from the group consisting of gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium and iridium or an alloy containing the metal. The manufacturing method of the board | substrate which has the copper foil of crab. Forming amount of noble metal than the copper is 0.001μmol / dm ² or more and 40 [mu] mol / dm ² or less, the manufacturing method of a substrate having a copper foil according to claim 1. A step of discretely forming a metal nobler than copper on the copper foil surface, a step of oxidizing the copper foil surface with an alkaline solution containing an oxidizing agent, and the surface-treated copper foil surface and core The board | substrate which has a copper foil obtained by passing through the process of adhere | attaching a base material . The board | substrate which has a copper foil of Claim 6 which performs one or more processes selected from the group which consists of a reduction process, a coupling process, and a corrosion suppression process after the said oxidation process. The oxidant is at least one selected from the group consisting of chlorate, chlorite, hypochlorite, perchlorate, and peroxodisulfate. A substrate having a copper foil. 7. The metal more precious than copper is a metal selected from the group consisting of gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium and iridium or an alloy containing the metal. The board | substrate which has the copper foil in any one of -8. The amount of noble metal than the copper formed on the copper foil surface is 0.001μmol / dm ² or more and 40 [mu] mol / dm ² or less, a substrate having a copper foil according to any one of claims 6-9 .

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