JP4872368B2 - Copper surface pretreatment method and wiring board using this method - Google Patents

Description

  The present invention relates to a copper surface pretreatment method and a wiring board using this method.

  The development of the information society in recent years has been remarkable, and consumer devices have been reduced in size, weight, performance, and functionality, such as personal computers and mobile phones. Industrial equipment includes wireless base stations, optical communication devices, and servers. In addition, there is a demand for improvement in functions in the same way regardless of whether it is large or small, such as routers and other network-related devices. In addition, with the increase in the amount of information transmitted, the frequency of signals handled tends to increase year by year, and high-speed processing and high-speed transmission technology are being developed. With regard to mounting relations, the development of system-on-chip (SoC), system-in-package (SiP), etc., as new high-density mounting technologies, as well as higher-speed and higher-performance LSIs such as CPUs, DSPs, and various types of memory are actively developed. Has been done. In order to mount a plurality of semiconductor chips in a small mounting area, a semiconductor chip mounting substrate on which fine wiring of L / S = 30 μm / 30 μm or less has been used.

  A semiconductor chip mounting substrate on which fine wiring is formed is performed by a subtractive method or a semi-additive method.

  In a general wiring formation process by the subtractive method, an etching resist is formed on the copper surface, and then exposure and development are performed to form a resist pattern. Next, unnecessary copper is etched and a resist is removed to form wiring.

  In a general wiring forming process by a semi-additive method, a plating resist is formed on the copper (seed layer) surface, and then exposure and development are performed to form a resist pattern. Next, wiring is formed by performing electroplating, resist stripping, and etching.

  In addition, after these wirings are formed, a solder resist or a coverlay can be formed on the wirings in order to protect the wirings other than the external connection terminals and the semiconductor chip connection terminals.

In order to increase the formation rate of fine wiring with respect to the design value of L / S width by these methods, it is necessary to form a resist pattern as designed. However, in the formation of fine wiring with L / S = 30 μm / 30 μm or less, there is a problem that it is difficult to obtain the accuracy of the resist pattern on the glossy copper surface due to the influence of halation caused by light reflection.
In particular, in the subtractive method, there is a problem that the adhesion between the copper surface and the resist pattern is reduced during the etching, and the resist pattern is peeled off. On the other hand, there is a problem that sufficient adhesion cannot be obtained between the wiring / solder resist and between the wiring / coverlay as the wiring becomes finer.

  In order to solve the above problems, it is important to make the copper surface non-glossy and to strengthen the adhesion between the copper surface and the resist. In order to realize these, the following copper surface treatment method has been performed as a conventional method.

  That is, this is a method in which a roughened shape on the order of microns is imparted to the copper surface to make the copper surface non-glossy, and an adhesive force between the copper surface and the resist is obtained by the anchor effect. For example, using an aqueous solution containing a main agent containing an inorganic acid and a copper oxidizing agent and an auxiliary agent containing at least one azole and at least one etching inhibitor, a continuous 2-3 μm height on the copper surface. There is a method of imparting a rough rough shape (see Patent Document 1).

  In addition, there is a method in which fine copper oxide needle-like crystals are imparted to the copper surface to make the copper surface non-glossy and obtain an adhesive force between the copper surface and the resist by an anchor effect. For example, it is a method of imparting fine copper oxide needle-like crystals by immersion at around 80 ° C. using an alkaline aqueous solution containing an oxidizing agent such as sodium chlorite (see Patent Document 2).

  In addition, there is a method in which fine metallic copper needle-like crystals are provided on the copper surface to make the copper surface non-glossy, and an adhesive effect is obtained between the copper surface and the resist by an anchor effect. For example, by using an alkaline aqueous solution containing an oxidizing agent such as sodium chlorite and soaking at about 80 ° C., fine needle-like crystals of copper oxide are imparted, and then at least one amine borane and boron. This is a method of imparting fine metallic copper needle crystals by performing a reduction treatment with an acidic solution mixed with a chemical (see Patent Document 3).

JP 2000-282265 A Japanese Patent Publication No. 7-13304 Japanese Patent No. 2656622

As shown in Patent Document 1 described above, the first conventional technique for forming a continuous roughened rough shape having a height of 2 to 3 μm on the copper surface and improving the adhesion between the copper surface and the resist is an anchor effect. The adhesion was secured.
However, in the formation of fine wiring by the subtractive method, when the roughness of the copper interface with narrow lines / spaces and in close contact with the resist becomes a rough shape exceeding 1 μm, the etching resist is completely removed from the copper surface during development. Since it is difficult to remove, there is a problem that a short circuit occurs between the copper wirings during the subsequent etching process. Further, when the resist is peeled off, it is difficult to completely remove the etching resist from the copper surface, so that there is a problem that the adhesion between the wiring / insulating resin or the solder resist after that cannot be obtained. In addition, there is a problem that non-precipitation of plating or uneven plating occurs during gold plating processing of external connection terminals and the like. Furthermore, since the unevenness on the surface of the copper wiring exceeds 1 μm, when a high-speed electric signal is applied to such a copper wiring, the electric signal is concentrated and flows near the surface of the wiring due to the skin effect. There is a problem that transmission loss increases.

  In addition, in the fine wiring formation by the semi-additive method, the copper seed layer is thin, and particularly the thickness of the copper seed layer formed by sputtering is 0.1 μm to 1.0 μm. There is a problem that unevenness cannot be formed on the copper surface.

As shown in the aforementioned Patent Documents 2 and 3, a fine copper oxide needle crystal or a metal copper needle crystal having a height of less than 1.0 μm is imparted to the wiring surface, and the adhesive strength between the copper surface and the resist is increased. The second and third conventional techniques to be improved also ensure the adhesion by the anchor effect as in the first conventional technique.
However, in the formation of fine wiring by the subtractive method, if the unevenness of the copper interface that is in close contact with the resist becomes a needle-like shape, there is a problem that a short circuit occurs between the copper wiring due to the resist residue as described above. There is a problem that adhesion between the resin or the solder resist cannot be obtained, a problem that gold plating is not deposited or gold plating is uneven.

  Further, in the formation of fine wiring by the semi-additive method, it is possible to form irregularities on the copper seed layer formed by sputtering or the like. However, since the resist cannot be completely removed from the copper surface as described above, the connection reliability between the seed layer / wiring cannot be obtained, the short circuit occurs between the copper wiring, the wiring / insulating resin or There are problems that adhesion between solder resists cannot be obtained, gold plating is not deposited, or gold plating unevenness occurs.

  The object of the present invention was made to improve the above-mentioned problems of the prior art, and ensure the copper surface matte and ensure adhesion between the copper surface and the resist. It is an object to provide a pretreatment method for a copper surface and a wiring board using this method, in which no resist remains on the substrate.

In order to achieve the above object, the present invention provides a method for forming a fine and uniform fine irregularities by discretely forming a metal nobler than copper on a copper surface and then oxidizing the copper surface. Is basically made to be matte and a resist is formed on it.
1. A pretreatment method for forming a resist or coverlay on a copper surface, wherein a step of discretely forming a metal nobler than copper on the copper surface, and then oxidizing with an alkaline aqueous solution containing an oxidizing agent on the copper surface A method of pretreating a copper surface, comprising a step of treating.
2. 2. The copper surface pretreatment method according to 1, further comprising a step selected from a reduction treatment, a coupling treatment, and a corrosion inhibition treatment after the oxidation treatment step.
3. The step of oxidizing with an alkaline aqueous solution containing the oxidizer includes an alkaline aqueous solution containing an alkali metal or an alkaline earth metal, and chlorate, chlorite, hypochlorite, perchlorate as an oxidant. And a copper surface pretreatment method according to 1 or 2, wherein the treatment is performed with an alkaline aqueous solution containing at least one salt selected from peroxodisulfate.
4). Any one of 1 to 3 characterized in that the metal nobler than copper is a metal selected from gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium and iridium, or an alloy containing the metal. A method for pretreating a copper surface according to claim 1.
5. The step of discretely forming a metal nobler than copper is discretely formed so that the metal nobler than copper is 0.001 μmol / dm ² or more and 40 μmol / dm ² or less on the surface of the copper. The pretreatment method for a copper surface according to any one of 1 to 4, wherein:
6). 6. The copper surface pretreatment method according to any one of 1 to 5, wherein the surface roughness produced by the copper surface pretreatment method is 1 nm or more and 1000 nm or less in terms of Rz.
7). A wiring substrate obtained by discretely forming a metal nobler than copper on a copper surface, thereafter performing an oxidation treatment with an alkaline aqueous solution containing an oxidizing agent on the copper surface, and then forming a resist.
8). 8. The wiring board according to 7, obtained by performing a treatment selected from a reduction treatment, a coupling treatment, and a corrosion inhibition treatment after the oxidation treatment.
9. Oxidation treatment with an alkaline aqueous solution containing the oxidant is carried out by adding chlorate, chlorite, hypochlorite, perchlorate and peroxo as an oxidant to an alkaline aqueous solution containing an alkali metal or an alkaline earth metal. The wiring board according to 7 or 8, which is treated with an alkaline aqueous solution containing at least one salt selected from disulfates.
10. Any one of 7 to 9, wherein the metal nobler than copper is a metal selected from gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium and iridium, or an alloy containing the metal. A wiring board according to the above.
11. The multilayer wiring board 12 according to any one of 7 to 10, wherein a metal nobler than the copper is discretely formed on the surface of the copper so as to be 0.001 μmol / dm ² or more and 40 μmol / dm ² or less. . The wiring board according to 7 to 11, wherein the surface roughness of the copper after the surface treatment is 1 nm or more and 1000 nm or less in terms of Rz.

  A copper surface pretreatment method that makes the copper surface non-glossy and ensures adhesion between the copper surface and the resist so that no resist remains on the copper surface during development or resist stripping, and wiring using this method It became possible to provide a substrate.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Here, the pretreatment method of the copper surface of the present invention will be described. Furthermore, as an application example of a wiring board using this method, a semiconductor chip mounting board will be described as an example, but the present invention can be similarly applied to other multilayer wiring boards and semiconductor packages.

(Copper surface unevenness forming method)
By finely forming a metal nobler than copper on the copper surface and then performing an oxidation treatment, fine irregularities due to dense and uniform copper oxide crystals can be formed on the copper surface. Further, by performing a reduction treatment after the oxidation treatment, fine irregularities due to dense and uniform metal copper crystals can be formed. Furthermore, after the reduction treatment, at least one of a coupling treatment and a corrosion inhibition treatment can be performed. After oxidation treatment, after reduction treatment, after coupling treatment or corrosion inhibition treatment, the copper surface roughness produced by the surface treatment of copper is 1 nm or more and 1,000 nm or less in terms of Rz (10-point average roughness). It is preferable that Further, Rz is more preferably 1 nm or more and 100 nm or less, and further preferably 1 nm or more and 50 nm or less. If Rz is less than 1 nm, the wiring formation rate tends to deteriorate due to a decrease in adhesion to the resist and reflection of light on the copper surface during exposure. If Rz exceeds 1,000 nm, the resist is removed during development. Since it is difficult to remove completely from the copper surface, a short circuit tends to occur between the copper wirings during the subsequent etching process. Similarly, when removing the resist, it is difficult to completely remove the resist from the copper surface, so that there is a tendency that the subsequent adhesion between the wiring / insulating resin or the solder resist cannot be obtained. In addition, there is a tendency that non-precipitation of plating or uneven plating occurs during gold plating treatment of external connection terminals and the like. Furthermore, since the unevenness on the surface of the copper wiring exceeds 1 μm, when a high-speed electric signal is applied to such a copper wiring, the electric signal is concentrated and flows near the surface of the wiring due to the skin effect. Therefore, there is a tendency that the problem of the prior art that the transmission loss becomes large is likely to occur.

(Metal forming method nobler than copper)
The amount of discretely forming a noble metal on the copper surface is preferably 0.001 μmol / dm ² or more and 40 μmol / dm ² or less. The formation amount is more preferably at 0.01μmol / dm ² or more and 10 .mu.mol / dm ² or less, more preferably 0.1 [mu] mol / dm ² or more and is 4μmol / dm ² or less. If the formation amount is less than 0.001 μmol / dm ² , it tends to be difficult to form dense and uniform fine irregularities, and if it exceeds 40 μmol / dm ² , the adhesion force tends to decrease and the wiring formation rate tends to deteriorate. is there.
As the metal nobler than copper, a metal selected from gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium and iridium, or a metal selected from an alloy containing these metals can be used. Also, the method of discretely forming a noble metal on copper on the copper surface is such that the underlying copper surface is completely made of copper by electroless plating, electroplating, displacement plating, spray spraying, coating, sputtering or vapor deposition. In addition, it is preferable that they are uniformly dispersed on the copper surface without being covered with a noble metal. A more preferable method is a method in which a metal selected from gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium and iridium, or an alloy containing these metals is formed by displacement plating. In addition, the amount of the precious metal that is more precious than copper is discretely formed on the surface of the copper by dissolving the precious metal with aqua regia, and then quantitatively analyzing the solution with an atomic absorption photometer. The amount of precious metal can be obtained.

(Oxidation treatment method)
As an oxidation treatment method, there is a method using an alkaline aqueous solution containing an oxidizing agent as a treatment liquid.

As an alkaline aqueous solution containing an oxidizing agent used in the present invention, an alkaline aqueous solution containing an alkali metal or alkaline earth metal, an oxidizing agent such as chlorate, chlorite, hypochlorite, perchlorate and An alkaline aqueous solution containing at least one peroxodisulfate can be used. Furthermore, the alkaline aqueous solution containing an oxidizing agent is preferably an alkaline aqueous solution containing a phosphate.
Specific examples of the phosphate herein include trisodium phosphate, tripotassium phosphate, and trilithium phosphate. Further, the alkali metal or alkaline earth metal referred to here may be a compound containing these, and specific examples of the compound containing alkali metal or the compound containing alkaline earth metal include sodium hydroxide and potassium hydroxide. And sodium carbonate. Furthermore, specific examples of the oxidizing agent herein include sodium hypochlorite, sodium chlorite, sodium chlorate, sodium perchlorate, potassium hypochlorite, potassium chlorite, potassium chlorate, Examples include potassium chlorate, ammonium peroxodisulfate, potassium peroxodisulfate, and sodium peroxodisulfate.

With an alkaline aqueous solution containing these oxidizing agents, irregularities due to copper oxide crystals can be formed on the copper surface. The amount of crystal of copper oxide is preferably 0.001 mg / cm ² or more and 0.3 mg / cm ² or less. Further, the copper oxide crystal amount is more preferably from ² under 0.01 mg / cm ² or more and 0.2 mg / cm, further not less on 0.03 mg / cm ² and 0.1 mg / cm ² or less preferable. When the amount of copper oxide crystals is less than 0.001 mg / cm ² , the wiring formation rate tends to deteriorate due to a decrease in adhesion to the resist and reflection of light on the copper surface during exposure, and 0.3 mg / cm ^2. If it exceeds 1, it is difficult to completely remove the resist from the copper surface at the time of development, so that a short circuit tends to occur between the copper wirings during the subsequent etching process. Similarly, when removing the resist, it is difficult to completely remove the resist from the copper surface, so that there is a tendency that the subsequent adhesion between the wiring / insulating resin or the solder resist cannot be obtained. In addition, there is a tendency that non-precipitation of plating or uneven plating occurs during gold plating treatment of external connection terminals and the like. Furthermore, since the unevenness on the surface of the copper wiring exceeds 1 μm, when a high-speed electric signal is applied to such a copper wiring, the electric signal is concentrated and flows near the surface of the wiring due to the skin effect. Therefore, there is a tendency that the problem of the prior art that the transmission loss becomes large is likely to occur.

The amount of copper oxide crystals formed on the copper surface can be examined by measuring the amount of electrolytic reduction. For example, using oxidized copper as a working electrode (cathode), a constant amount of electricity of 0.5 mA / cm ² is applied, and the surface potential of copper completely changes from the potential of copper oxide to the potential of metallic copper. The amount of copper oxide crystals can be determined from the amount of electrolytic reduction by measuring the time until a stable potential is exceeded. About the processing temperature of alkaline aqueous solution containing these oxidizing agents, it is preferable to carry out at 20-95 degreeC. Furthermore, it is more preferable to carry out at 30-80 degreeC, and it is especially preferable to carry out at 40-60 degreeC. Regarding the concentration and the treatment time of these treatment liquids, it is preferable to appropriately select and use conditions so that the crystal amount of copper oxide is 0.001 mg / cm ² or more and 0.3 mg / cm ² or less. Furthermore, 0.01 mg / cm ² or more and 0.2 mg / cm ² or less are more preferable in terms of copper oxide crystal amount, and 0.03 mg / cm ² or more and 0.1 mg / cm ² or less are more preferable.

  Further, as a pretreatment of these treatments, a degreasing treatment for cleaning the copper surface, a pickling treatment, or a combination thereof may be performed as appropriate.

(Reduction treatment)
The unevenness due to the copper oxide crystals formed on the copper surface by the oxidation treatment can be made uneven by the reduction treatment.
As the aqueous solution for the reduction treatment, an alkaline aqueous solution adjusted to pH 9.0 to 13.5 can be used. This aqueous solution contains aldehydes, phosphorus-containing compounds or boron-containing compounds. Examples of aldehydes include formaldehyde, paraformaldehyde, paraformaldehyde, or aromatic aldehyde compounds. Examples of the phosphorus-containing compound include hypophosphorous acid and hypophosphite. Examples of the boron-containing compound include dimethylamine borane and borohydride salt. Examples of the treatment method include dipping, spraying, or application.

(Coupling process)
By using a coupling agent, the adhesive strength between the copper surface and the insulating layer (build-up layer, etc.) can be improved. Examples of the coupling agent to be used include a silane coupling agent, an aluminum coupling agent, a titanium coupling agent, and a zirconium coupling agent, and among them, a silane coupling agent is preferable. For example, the silane coupling agent may have a functional group such as an epoxy group, amino group, mercapto group, imidazole group, vinyl group, or methacryl group in the molecule. A solution containing at least one of these silane coupling agents or a mixture of two or more thereof can be used. As the solvent used for the preparation of the silane coupling agent solution, water, alcohol or ketones can be used. A small amount of acid such as acetic acid or hydrochloric acid can be added to promote hydrolysis of the coupling agent. The content of the coupling agent is preferably 0.01% by weight to 5% by weight and more preferably 0.1% by weight to 1.0% by weight with respect to the entire solution. Examples of the treatment with the coupling agent include dipping, spraying, or application. The substrate treated with the above silane coupling agent is dried by natural drying, heat drying, or vacuum drying. Depending on the type of coupling agent used, it may be washed with water or ultrasonically before drying. It is.

(Corrosion suppression treatment)
The corrosion inhibitor used for the corrosion inhibition treatment only needs to contain at least one S-containing organic compound or N-containing organic compound. Specific examples of the S-containing organic compound herein include organic compounds containing a group having a sulfur atom such as a mercapto group, sulfide group or disulfide group. Examples of the N-containing organic compound include organic compounds containing a group having a nitrogen atom selected from —N═, N═N, and —NH ₂ in the molecule. The corrosion inhibitor can be used in addition to the above acidic solution, alkaline aqueous solution or coupling agent solution. Moreover, it is possible to perform the treatment using the solution containing the corrosion inhibitor before or after the treatment with the solution containing the coupling agent. Examples of the treatment method include dipping, spraying, or application.

(S-containing organic compound)
As described above, the S-containing organic compound is a compound containing a sulfur atom such as a mercapto group, a sulfide group, or a disulfide group, for example, an aliphatic thiol (HS— (CH ₂ ) _n —R (where, Wherein n is an integer from 1 to 23, R represents a monovalent organic group, a hydrogen group or a halogen atom), and R is an amino group, an amide group, a carboxyl group, a carbonyl group It is preferably any of hydroxyl groups, but is not limited thereto, but is not limited thereto, but is an alkyl group having 1 to 18 carbon atoms, an alkoxy group having 1 to 8 carbon atoms, an acyloxy group, a haloalkyl group, a halogen atom, or a hydrogen group. , A thioalkyl group, a thiol group, an optionally substituted phenyl group, a biphenyl group, a naphthyl group, a heterocyclic ring, and the like. It is sufficient that one or more hydroxyl groups and hydroxyl groups are present, preferably one or more, and may further have a substituent such as the above alkyl group, wherein n is an integer from 1 to 23 In addition, compounds in which n is an integer from 4 to 15 are more preferable, and compounds having an integer from 6 to 12 are particularly preferable.), Thiazole derivatives ( For example, thiazole, 2-aminothiazole, 2-aminothiazole-4-carboxylic acid, aminothiophene, benzothiazole, 2-mercaptobenzothiazole, 2-aminobenzothiazole, 2-amino-4-methylbenzothiazole, 2-benzo Thiazolol, 2,3-dihydroimidazo [2,1-b] benzothiazol-6-amine, 2- (2-aminothia -4-yl) -2-hydroxyiminoacetic acid ethyl, 2-methylbenzothiazole, 2-phenylbenzothiazole, 2-amino-4-methylthiazole, etc.), thiadiazole derivatives (for example, 1,2,3-thiadiazole) 1,2,4-thiadiazole, 1,2,5-thiadiazole, 1,3,4-thiadiazole, 2-amino-5-ethyl-1,3,4-thiadiazole, 5-amino-1,3,4 -Thiadiazole-2-thiol, 2,5-mercapto-1,3,4-thiadiazole, 3-methylmercapto-5-mercapto-1,2,4-thiadiazole, 2-amino-1,3,4-thiadiazole, 2- (ethylamino) -1,3,4-thiadiazole, 2-amino-5-ethylthio-1,3,4-thiadiazole, etc.), merca Tobenzoic acid, mercaptonaphthol, mercaptophenol, 4-mercaptobiphenyl, mercaptoacetic acid, mercaptosuccinic acid, 3-mercaptopropionic acid, thiouracil, 3-thiourazol, 2-thiouramil, 4-thiouramil, 2-mercaptoquinoline, thioformic acid, 1-thiocoumarin, thiocouthiazone, thiocresol, thiosalicylic acid, thiothianuric acid, thionaphthol, thiotolene, thionaphthene, thionaphthene carboxylic acid, thionaphthenequinone, thiobarbituric acid, thiohydroquinone, thiophenol, thiophene, thiophthalide, thiobutene, thiothione carbonate, Thiolutidone, thiol histidine, 3-carboxypropyl disulfide, 2-hydroxyethyl disulfide, 2-aminopropionic acid, dithiodi Examples include glycolic acid, D-cysteine, di-t-butyl disulfide, thiocyanate, and thiocyanic acid.

(N-containing organic compound)
As described above, the N-containing organic compound is a compound having a nitrogen atom selected from —N═, N═N and —NH ₂ in the molecule, and includes, for example, a triazole derivative (eg, 1H-1,2, 3-triazole, 2H-1,2,3-triazole, 1H-1,2,4-triazole, 4H-1,2,4-triazole, benzotriazole, 1-aminobenzotriazole, 3-amino-5-mercapto -1,2,4-triazole, 3-amino-1H-1,2,4-triazole, 3,5-diamino-1,2,4-triazole, 3-oxy-1,2,4-triazole, amino Urazole, etc.), tetrazole derivatives (eg, tetrazolyl, tetrazolylhydrazine, 1H-1,2,3,4-tetrazole, 2H-1,2,3,4-tetrazole, 5-amino-1H-tetrazole, 1-ethyl-1,4-dihydroxy-5H-tetrazol-5-one, 5-mercapto-1-methyltetrazole, tetrazole mercaptan, etc.), oxazole derivatives (eg, oxazole, oxazolyl, oxazoline, Benzoxazole, 3-amino-5-methylisoxazole, 2-mercaptobenzoxazole, 2-aminooxazoline, 2-aminobenzoxazole, etc.), oxadiazole derivatives (for example, 1,2,3-oxadiazole, 1 , 2,4-oxadiazole, 1,2,5-oxadiazole, 1,3,4-oxadiazole, 1,2,4-oxadiazolone-5, 1,3,4-oxadiazolone -5), oxatriazole derivatives (for example, 1,2,3,4-oxa Riazole, 1,2,3,5-oxatriazole, etc.), purine derivatives (eg, purine, 2-amino-6-hydroxy-8-mercaptopurine, 2-amino-6-methylmercaptopurine, 2-mercaptoadenine, Mercaptohypoxanthine, mercaptopurine, uric acid, guanine, adenine, xanthine, theophylline, theobromine, caffeine, etc.), imidazole derivatives (eg, imidazole, benzimidazole, 2-mercaptobenzimidazole, 4-amino-5-imidazolecarboxylic acid amide) , Histidine, etc.), indazole derivatives (eg, indazole, 3-indazolone, indazolol, etc.), pyridine derivatives (eg, 2-mercaptopyridine, aminopyridine, etc.), pyrimidine derivatives (eg, 2-merca) Topyrimidine, 2-aminopyrimidine, 4-aminopyrimidine, 2-amino-4,6-dihydroxypyrimidine, 4-amino-6-hydroxy-2-mercaptopyrimidine, 2-amino-4-hydroxy-6-methylpyrimidine, 4 -Amino-6-hydroxy-2-methylpyrimidine, 4-amino-6-hydroxypyrazolo [3,4-d] pyrimidine, 4-amino-6-mercaptopyrazolo [3,4-d] pyrimidine, 2- Hydroxypyrimidine, 4-mercapto-1H-pyrazolo [3,4-d] pyrimidine, 4-amino-2,6-dihydroxypyrimidine, 2,4-diamino-6-hydroxypyrimidine, 2,4,6-triaminopyrimidine ), Thiourea derivatives (eg, thiourea, ethylenethiourea, 2-thiobarbituric acid, etc.), Mino acid (for example, glycine, alanine, tryptophan, proline, oxyproline, etc.), 1,3,4-thiooxadiazolone-5, thiocoumazone, 2-thiocoumarin, thiosaccharin, thiohydantoin, thiopyrine, γ-thiopyrine, guanazine Guanazole, guanamine, oxazine, oxadiazine, melamine, 2,4,6-triaminophenol, triaminobenzene, aminoindole, aminoquinoline, aminothiophenol, aminopyrazole and the like.

(Corrosion inhibitor solution)
Water and an organic solvent can be used for the preparation of the solution containing the corrosion inhibitor used in the present invention. The type of the organic solvent is not particularly limited, and examples thereof include alcohols such as methanol, ethanol, n-propyl alcohol, and n-butyl alcohol, and ethers such as di-n-propyl ether, di-n-butyl ether, and diallyl ether. , Aliphatic hydrocarbons such as hexane, heptane, octane, and nonane, aromatic hydrocarbons such as benzene, toluene, and phenol can be used, and these solvents can be used alone or in combination of two or more. .

(Corrosion inhibitor concentration and treatment time)
The concentration of the corrosion inhibitor in the corrosion inhibitor solution used in the present invention is preferably 0.1 to 5000 ppm. Furthermore, 0.5 to 3000 ppm is more preferable, and 1 to 1000 ppm is particularly preferable. When the concentration of the corrosion inhibitor is less than 0.1 ppm, the ion migration suppressing effect and the adhesive strength between the copper surface and the insulating layer tend to decrease. When the concentration of the corrosion inhibitor exceeds 5000 ppm, an ion migration suppressing effect can be obtained, but the adhesive strength between the copper surface and the insulating layer tends to decrease. The treatment time in the solution containing the corrosion inhibitor is not particularly limited, but it is preferable to change it appropriately according to the type and concentration of the corrosion inhibitor. It is also possible to perform ultrasonic cleaning after the treatment.

(Resist or coverlay)
Examples of the resist used in the present invention include an etching resist, a plating resist, and a solder resist. The etching resist and the plating resist are peeled off after forming the wiring and are not left on the substrate or the like in order to use for the purpose of wiring formation. The solder resist or coverlay is formed on the substrate surface for the purpose of wiring protection other than external connection terminals and semiconductor chip connection terminals. These resists or coverlays can be used in liquid or film form, and preferably have photosensitivity.

(Semiconductor chip mounting substrate)
FIG. 1 shows a schematic cross-sectional view of an embodiment (two-sided build-up layer 2 layers) of a semiconductor chip mounting substrate of the present invention. Here, the embodiment in which the buildup layer (interlayer insulating layer) is formed only on one side will be described. However, the buildup layer may be formed on both sides as shown in FIG.

  As shown in FIG. 1, the semiconductor chip mounting substrate of the present invention includes a semiconductor chip connection terminal and a first interlayer connection terminal 101 on a core substrate 100 which is an insulating layer on the side where the semiconductor chip is mounted. Wiring 106a is formed. A second wiring 106b including the second interlayer connection terminal 103 is formed on the other side of the core substrate, and the first interlayer connection terminal and the second interlayer connection terminal are connected to the first interlayer connection of the core substrate. It is electrically connected via an IVH (interstitial via hole) 102. A buildup layer 104 is formed on the second wiring side of the core substrate, and a third wiring 106c including a third interlayer connection terminal is formed on the buildup layer. The three interlayer connection terminals are electrically connected via the second interlayer connection IVH 108.

  When a plurality of buildup layers are formed, the same structure is stacked, and external connection terminals 107 connected to the motherboard are formed on the outermost buildup layer. The shape of the wiring, the arrangement of each connection terminal, and the like are not particularly limited, and can be appropriately designed for manufacturing a semiconductor chip to be mounted and a target semiconductor package. Further, the semiconductor chip connection terminal and the first interlayer connection terminal can be shared. The external connection terminal and the third interlayer connection terminal are electrically connected via the third interlayer connection IVH 105. Furthermore, an insulating coating 109 such as a solder resist can be provided on the outermost buildup layer as necessary.

(Core substrate)
The material of the core substrate is not particularly limited, but an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, or the like can be used. In consideration of the thermal expansion coefficient and insulation, it is preferable to use ceramic or glass. Among the non-photosensitive glasses, soda lime glass (component example: SiO ₂ 65 to 75 wt%, Al ₂ O ₃ 0.5 to ₄ wt%, CaO 5 to 15 wt%, MgO 0.5 to 4 wt%, Na ₂ O 10-20 wt%), borosilicate glass (component example: SiO ₂ 65-80 wt%, B ₂ O ₃ 5-25 wt%, Al ₂ O ₃ 1-5 wt%, CaO 5-8 wt%, MgO 0.5 ˜2 wt%, Na ₂ O 6-14 wt%, K ₂ O 1-6 wt%) and the like. Also, it includes those containing gold ions and silver ions as a photosensitive agent into Li _{2 O-SiO} 2 based crystallized glass as photosensitive glass.

  As the organic substrate, a substrate or a resin film obtained by laminating a material obtained by impregnating a glass cloth with a resin can be used. Examples of the resin to be used include a thermosetting resin, a thermoplastic resin, or a mixed resin thereof, and an organic insulating material made of a thermosetting resin is preferable. Examples of the thermosetting resin include phenol resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, polybenzimidazole resin, polyamide resin, polyamideimide resin, and silicon resin. , Resin synthesized from cyclopentadiene, resin containing tris (2-hydroxyethyl) isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimetallate, furan resin, ketone Resins, xylene resins, resins containing condensed polycyclic aromatics, benzocyclobutene resins, and the like can be used. Examples of the thermoplastic resin include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, and liquid crystal polymer.

  A filler may be added to these resins. Examples of the filler include silica, talc, aluminum hydroxide, aluminum borate, aluminum nitride, and alumina.

  The thickness of the core substrate is preferably 100 to 800 μm from the viewpoint of IVH formation, and more preferably 150 to 500 μm.

(Build-up layer)
The interlayer insulating layer (build-up layer) 104 is made of an insulating material, and a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used as the insulating material. Among these, an organic insulating material made of a thermosetting resin is preferable as a main component. Examples of the thermosetting resin include phenol resin, urea resin, melamine resin, alkyd resin, acrylic resin, unsaturated polyester resin, diallyl phthalate resin, epoxy resin, polybenzimidazole resin, polyamide resin, polyamideimide resin, and silicon resin. , Resin synthesized from cyclopentadiene, resin containing tris (2-hydroxyethyl) isocyanurate, resin synthesized from aromatic nitrile, trimerized aromatic dicyanamide resin, resin containing triallyl trimetallate, furan resin, ketone Resins, xylene resins, resins containing condensed polycyclic aromatics, benzocyclobutene resins, and the like can be used. Examples of the thermoplastic resin include polyimide resin, polyphenylene oxide resin, polyphenylene sulfide resin, aramid resin, and liquid crystal polymer.

  A filler may be added to the insulating material. Examples of the filler include silica, talc, aluminum hydroxide, aluminum borate, aluminum nitride, and alumina.

(Coefficient of thermal expansion)
It is preferable that the thermal expansion coefficient of the semiconductor chip and the thermal expansion coefficient of the core substrate are approximated, and that the thermal expansion coefficient of the core substrate and the thermal expansion coefficient of the buildup layer are approximated. It is not a thing. Further, when the thermal expansion coefficients of the semiconductor chip, the core substrate, and the buildup layer are α1, α2, and α3 (ppm / ° C.), it is more preferable that α1 ≦ α2 ≦ α3.

  Specifically, the thermal expansion coefficient α2 of the core substrate is preferably 7 to 13 ppm / ° C, more preferably 9 to 11 ppm / ° C. The thermal expansion coefficient α3 of the buildup layer is preferably 10 to 40 ppm / ° C, more preferably 10 to 20 ppm / ° C, and particularly preferably 11 to 17 ppm / ° C.

(Young's modulus)
The Young's modulus of the buildup layer is preferably 1 to 5 GPa in terms of stress relaxation against thermal stress. It is preferable to add the filler in the buildup layer by appropriately adjusting the addition amount so that the thermal expansion coefficient of the buildup layer is 10 to 40 ppm / ° C. and the Young's modulus is 1 to 5 GPa.

(Manufacturing method of semiconductor chip mounting substrate)
The semiconductor chip mounting substrate can be manufactured by a combination of the following manufacturing methods. The order of the manufacturing process is not particularly limited as long as it does not depart from the object of the present invention.

(Wiring formation method)
As a method of forming wiring, a metal foil is formed on the core substrate surface or build-up layer, and unnecessary portions of the metal foil are removed by etching (subtract method). A method of forming wiring by plating only at locations (additive method), forming a thin metal layer (seed layer) on the core substrate surface or build-up layer, and then forming the necessary wiring by electrolytic plating, then thin metal There is a method of removing the layer by etching (semi-additive method).

(Subtract method)
An etching resist can be formed at a location to be a wiring on the metal foil, and a chemical etching solution can be sprayed and sprayed onto a portion exposed from the etching resist to remove an unnecessary metal foil to form a wiring. For example, when a copper foil is used as the metal foil, an etching resist material that can be used for an ordinary wiring board can be used as the etching resist. For example, a resist ink is silk-screen printed to form an etching resist, or a negative photosensitive dry film for etching resist is laminated on a copper foil, and a photomask that transmits light is superimposed on the wiring shape. Then, an etching resist is formed by exposing with ultraviolet light and removing the unexposed portion with a developer. As the chemical etching solution, a chemical etching solution used for a normal wiring board, such as a solution of cupric chloride and hydrochloric acid, a ferric chloride solution, a solution of sulfuric acid and hydrogen peroxide, and an ammonium persulfate solution can be used.

(Semi-additive method)
There are two methods for forming the seed layer of the semi-additive method on the surface of the core substrate or the build-up layer, such as vapor deposition or plating, and a method of bonding a metal foil. Also, a subtractive metal foil can be formed by the same method.

  In the case of the method by vapor deposition, for example, when a base metal and a thin film copper layer are formed by sputtering as a seed layer, the sputtering apparatus used to form the thin film copper layer is a bipolar sputtering, a three-polar sputtering, Polar sputtering, magnetron sputtering, mirrortron sputtering, or the like can be used. A target used for sputtering is sputtered 5 to 50 nm using, for example, a metal such as Cr, Ni, Co, Pd, Zr, Ni / Cr, or Ni / Cu as a base metal in order to ensure adhesion. Thereafter, a seed layer can be formed by sputtering 0.1 to 1.0 μm using copper as a target.

  Moreover, in the case of the method by plating, it can also form by plating 0.5-3 micrometers electroless copper plating on the core substrate surface or a buildup layer.

  The bonding method is used when the core substrate or the build-up layer has an adhesive function, and the seed layer can also be formed by bonding metal foils by pressing or laminating. However, since it is very difficult to directly bond a thin metal layer, there are a method of thinning a metal foil with a carrier after laminating a thick metal foil, a method of peeling a carrier layer after laminating a metal foil with a carrier, etc. is there. For example, as the former, there is a three-layer copper foil of carrier copper / nickel / thin film copper, and carrier copper can be removed with an alkali etching solution and nickel can be removed with a nickel etching solution. As the latter, a peelable copper foil using aluminum, copper, an insulating material or the like as a carrier can be used, and a seed layer of 5 μm or less can be formed. Alternatively, a 9 to 18 μm thick copper foil may be attached, and the seed layer may be formed by etching so that the thickness is 5 μm or less.

  A plating resist is formed in a necessary pattern on the seed layer formed by the above-described method, and wiring is formed by electrolytic copper plating through the seed layer. Thereafter, the plating resist is peeled off, and finally the seed layer is removed by etching or the like to form a wiring.

(Wiring shape)
The shape of the wiring is not particularly limited, but as shown in FIGS. 5 and 6, at least the semiconductor chip mounting terminal 16 (wire bond terminal or the like) is provided on the semiconductor package region 13 on the side where the semiconductor chip is mounted. The surface is provided with external connection terminals 19 (locations where solder balls or the like are mounted) that are electrically connected to the mother board, developed wiring 20 that connects them, interlayer connection terminals, and the like.
The wiring arrangement is not particularly limited, but as shown in FIG. 5 (inner layer wiring, interlayer connection terminals, etc. are omitted), a fan-in type in which external connection terminals are formed inside the semiconductor chip connection terminals, FIG. 6 may be a fan-out type in which external connection terminals are formed outside the semiconductor chip connection terminals as shown in FIG. 6, or a combination of these. FIG. 5 is a plan view of the fan-in type semiconductor chip mounting substrate, and FIG. 6 is a plan view of the fan-out type semiconductor chip mounting substrate. The shape of the semiconductor chip connection terminal 16 is not particularly limited as long as wire bond connection or flip chip connection is possible. In addition, wire-bond connection or flip-chip connection is possible for both fan-out and fan-in types. Further, if necessary, a dummy pattern 21 (see FIG. 6) that is not electrically connected to the semiconductor chip may be formed. The shape and arrangement of the dummy patterns are not particularly limited, but it is preferable to arrange them uniformly in the semiconductor chip mounting regions 15 and 18. As a result, when the semiconductor chip is mounted with the die bond adhesive (die bond film bonding regions 14 and 17), voids are less likely to be generated, and the reliability can be improved.

(Bahia Hall)
Since the multilayer semiconductor chip mounting substrate has a plurality of wiring layers, via holes for electrically connecting the wirings of the respective layers can be provided. The via hole can be formed by providing a hole for connection in the core substrate or the build-up layer and filling the hole with a conductive paste or plating. Examples of the hole processing method include mechanical processing such as punching and drilling, laser processing, chemical etching processing using a chemical solution, and dry etching processing using plasma.

  In addition, as a method for forming a via hole in the buildup layer, there is a method in which a conductive layer is formed in advance on the buildup layer with a conductive paste or plating, and this is laminated on a core substrate by pressing or the like.

(Formation of insulation coating)
An insulating coating can be formed on the external connection terminal side of the semiconductor chip mounting substrate. The pattern can be formed by printing if it is a varnish-like material, but it is preferable to use a photosensitive solder resist, a coverlay film or a film-like resist in order to ensure higher accuracy. As the material, for example, an epoxy, polyimide, epoxy acrylate, or fluorene material can be used.

  Since such an insulating coating has shrinkage at the time of curing, if it is formed only on one side, a large warp tends to occur on the substrate. Therefore, an insulating coating can be formed on both surfaces of the semiconductor chip mounting substrate as necessary. Furthermore, since the warpage varies depending on the thickness of the insulating coating, it is more preferable to adjust the thickness of the insulating coating on both sides so that no warpage occurs. In that case, it is preferable to conduct preliminary examination and determine the thicknesses of the insulating coatings on both sides. In order to obtain a thin semiconductor package, the thickness of the insulating coating is preferably 50 μm or less, and more preferably 30 μm or less.

(Plating of wiring)
Nickel and gold plating can be sequentially applied to necessary portions of the wiring. Further, nickel, palladium and gold plating may be applied as necessary. These platings are applied to the semiconductor chip connection terminals of the wiring and the external connection terminals for electrical connection with the mother board or other semiconductor package. For this plating, either electroless plating or electrolytic plating may be used.

(Manufacturing method of semiconductor chip mounting substrate)
Such a semiconductor chip mounting substrate can be manufactured by the following processes. FIGS. 2A to 2G are cross-sectional schematic views showing an example of an embodiment of the copper wiring formation processing method and the semiconductor chip mounting substrate manufacturing method using the copper wiring of the present invention. However, the order of the manufacturing process is not particularly limited as long as it does not depart from the object of the present invention.

(Process a)
(Step a) is a step of forming the first wiring 106a on the core substrate 100 as shown in FIG. First, a copper layer is formed on one side of the core substrate. In order to produce a copper layer on a core substrate, a copper layer can be obtained by forming a thin film by sputtering, vapor deposition, plating, or the like and then plating the film to a desired thickness by electrolytic copper plating.

  Next, the degreasing treatment is performed on the copper layer formed on one side of the core substrate, and then cleaning with hydrochloric acid or sulfuric acid is performed. Next, a metal selected from gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium and iridium, which are noble metals than copper, or an alloy containing these metals is discretely formed, and an oxidizing agent Oxidation treatment is performed by immersing in an alkaline aqueous solution containing. Thereafter, at least one of a reduction process, a coupling process, and a corrosion inhibition process may be performed. In any case, the processing is performed so that the Rz on the wiring surface is 1 nm or more and 1,000 nm or less.

  Thereafter, an etching resist is formed in a first wiring shape on the treated copper layer, and wiring is produced using an etching solution such as copper chloride, iron chloride, sulfuric acid-hydrogen peroxide, and nitric acid-hydrogen peroxide. Can do.

  Note that the first wiring 106a includes the first interlayer connection terminal 101 and the semiconductor chip connection terminal (portion electrically connected to the semiconductor chip), and a semi-additive method is used as a method for forming the fine wiring. May be.

(Process b)
In step (b), as shown in FIG. 2B, a first interlayer connection IVH 102 (via hole) for connecting the first interlayer connection terminal 101 and a second wiring to be described later is used. Is a step of forming.

The via hole can be formed by using laser light when the core substrate is a non-photosensitive substrate. Examples of the non-photosensitive substrate include the non-photosensitive glass described above, but are not limited thereto. In this case, the laser beam to be used is not limited, and a CO ₂ laser, a YAG laser, an excimer laser, or the like can be used. When the core substrate is a photosensitive base material, a region other than the via hole is masked, and the via hole portion is irradiated with ultraviolet light. Examples of the photosensitive base material include the above-described photosensitive glass, but are not limited thereto. In this case, via holes are formed by heat treatment and etching after irradiation with ultraviolet light. Further, when the core substrate is a base material that can be chemically etched by a chemical solution such as an organic solvent, a via hole can be formed by chemical etching. The formed via hole can be filled with a conductive paste or plating to form an electrically conductive layer for interlayer connection in order to electrically connect the interlayer.

(Process c)
Step (c) is a step of forming the second wiring 106b on the surface of the core substrate opposite to the first wiring 106a, as shown in FIG. 2 (c). A copper layer is formed on the surface opposite to the first wiring of the core substrate in the same manner as in (Step a), and then the degreasing treatment is performed on the copper layer, followed by cleaning with hydrochloric acid or sulfuric acid. Next, a metal selected from gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium and iridium, which are noble metals than copper, or an alloy containing these metals is discretely formed, and an oxidizing agent Oxidation treatment is performed by immersing in an alkaline aqueous solution containing. Thereafter, at least one of a reduction process, a coupling process, and a corrosion inhibition process may be performed. In any case, the processing is performed so that the Rz on the wiring surface is 1 nm or more and 1,000 nm or less. After that, an etching resist is formed in a necessary wiring shape on the treated copper layer, and the second wiring is formed using an etching solution such as copper chloride, iron chloride, sulfuric acid-hydrogen peroxide, and nitric acid-hydrogen peroxide. Form. As a method for forming a copper layer, a copper layer is obtained by forming a copper thin film by sputtering, vapor deposition, electroless plating or the like in the same manner as in (Step a) and then copper plating to a desired thickness using electrolytic copper plating. It is done.

  Note that the second wiring includes the second interlayer connection terminal 103, and a semi-additive method may be used as a method for forming the fine wiring.

(Process d)
(Step d) is a step of forming a buildup layer (interlayer insulating layer) 104 on the surface on which the second wiring is formed as shown in FIG. First, the second wiring surface is degreased and then washed with hydrochloric acid or sulfuric acid. Next, a metal selected from gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium and iridium, which are noble metals than copper, or an alloy containing these metals is discretely formed, and an oxidizing agent Oxidation treatment is performed by immersing in an alkaline aqueous solution containing. Then, you may perform at least 1 process of a reduction process, a coupling process, and a corrosion suppression process. In any case, the processing is performed so that the Rz on the wiring surface is 1 nm or more and 1,000 nm or less.

  Next, the buildup layer 104 is formed on the surface of the core substrate 100 and the surface of the second wiring 106b. As the insulating material for the buildup layer 104, a thermosetting resin, a thermoplastic resin, or a mixed resin thereof can be used as described above, but it is preferable that the thermosetting resin is a main component. In the case of a varnish-like material, the build-up layer can be obtained by printing or spin coating, or in the case of a film-like insulating material, using a technique such as laminating or pressing. When the insulating material includes a thermosetting resin, it is desirable to further heat and cure.

(Process e)
(Step e) is a step of forming a second interlayer connection IVH (via hole) 108 in the build-up layer as shown in FIG. 2 (e). As a via hole forming means, A laser drilling device can be used. A CO ₂ laser, a YAG laser, an excimer laser, or the like can be used as the type of laser used in the laser drilling machine, but a CO ₂ laser is preferable in terms of productivity and hole quality. Further, when the IVH diameter is less than 30 μm, a YAG laser capable of focusing the laser beam is suitable. Further, when the build-up layer is a material that can be chemically etched by a chemical solution such as an organic solvent, a via hole can be formed by chemical etching.

(Process f)
(Step f) is a step of forming the third wiring 106c on the buildup layer in which the second via hole is formed, as shown in FIG. 2 (f). Further, as a process for forming a fine wiring with L / S = 30 μm / 30 μm or less, the above-described semi-additive method is preferable. A seed layer is formed on the build-up layer by a method such as vapor deposition or plating or a method of bonding a metal foil. Next, the seed layer is degreased and then washed with hydrochloric acid or sulfuric acid. Next, a metal selected from gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium and iridium, which are noble metals than copper, or an alloy containing these metals is discretely formed, and an oxidizing agent Oxidation treatment is performed by immersing in an alkaline aqueous solution containing. Thereafter, at least one of a reduction process, a coupling process, and a corrosion inhibition process may be performed. In any case, the processing is performed so that the Rz on the wiring surface is 1 nm or more and 1,000 nm or less. Thereafter, a plating resist is formed in a necessary pattern on the treated seed layer, and wiring is formed by electrolytic copper plating through the seed layer. Thereafter, the plating resist is peeled off, and finally the seed layer is removed by etching or the like to form fine wiring.

  (Step d) to (Step f) may be repeated to produce two or more buildup layers 104 as shown in FIG. 2 (g). In this case, the interlayer connection terminal formed in the outermost buildup layer becomes the external connection terminal 107.

(Process g)
(Step g) is a step of forming an insulating coating 109 for protecting the wiring and the like other than the external connection terminals as shown in FIG. As the insulating coating material, a solder resist is used, and a thermosetting type or an ultraviolet curing type can be used, but an ultraviolet curing type capable of finishing the resist shape with high accuracy is preferable. First, the external connection terminals and other wirings are degreased, and then washed with hydrochloric acid or sulfuric acid. Next, a metal selected from gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium and iridium, which are noble metals than copper, or an alloy containing these metals is discretely formed, and an oxidizing agent Oxidation treatment is performed by immersing in an alkaline aqueous solution containing. Thereafter, at least one of reduction treatment, coupling treatment, and corrosion inhibition treatment may be performed. In any case, the treatment is performed so that the Rz of the wiring surface is 1 nm or more and 1,000 nm or less. . Thereafter, a solder resist is formed on portions other than the external connection terminals, and the external connection terminals 107 are exposed. It is electrically connected to the third wiring via the third interlayer connection IVH 105.

(Shape of semiconductor chip mounting substrate)
The shape of the semiconductor chip mounting substrate 22 is not particularly limited, but is preferably a frame shape as shown in FIG. By making the shape of the semiconductor chip mounting substrate in this way, it is possible to efficiently assemble the semiconductor package. Hereinafter, a preferable frame shape will be described in detail.

  As shown in FIG. 7, a block 23 is formed in which a plurality of semiconductor package regions 13 (parts to be a single semiconductor package) are arranged in rows and columns at regular intervals. Further, such a block is formed in a plurality of rows and columns. Although only two blocks are shown in FIG. 7, the blocks may be arranged in a lattice shape as necessary. Here, the width of the space between the semiconductor package regions is preferably 50 to 500 μm, and more preferably 100 to 300 μm. Furthermore, it is most preferable that the blade width of the dicer used when the semiconductor package is cut later is made the same.

  By arranging the semiconductor package region in this way, the semiconductor chip mounting substrate can be effectively used. Further, a positioning mark 11 or the like is preferably formed at the end of the semiconductor chip mounting substrate, and more preferably a pin hole by a through hole. The shape and arrangement of the pin holes may be selected so as to match the forming method and the semiconductor package assembly apparatus.

  Furthermore, it is preferable to form a reinforcing pattern 24 in the space between the semiconductor package regions or outside the block. The reinforcing pattern may be separately manufactured and bonded to the semiconductor chip mounting substrate, but is preferably a metal pattern formed at the same time as the wiring formed in the semiconductor package region, and the surface thereof is similar to the wiring. More preferably, nickel or gold is plated or an insulating coating is applied. When the reinforcing pattern is such a metal, it can also be used as a plating lead for electrolytic plating. Moreover, it is preferable to form the cutting position alignment mark 25 at the time of cutting with a dicer outside the block. In this way, a frame-shaped semiconductor chip mounting substrate can be manufactured.

(Semiconductor package)
FIG. 3 is a schematic cross-sectional view showing an embodiment of the flip chip type semiconductor package of the present invention. As shown in FIG. 3, the semiconductor package of the present invention is such that a semiconductor chip 111 is further mounted on the semiconductor chip mounting substrate of the present invention (including the interlayer insulating layer 104 and the insulating coating 109). And the semiconductor chip connection terminals can be obtained by flip-chip connection using the connection bumps 112.

Further, in these semiconductor packages, it is preferable to seal between the semiconductor chip and the semiconductor chip mounting substrate with an underfill material 113 as shown in the figure. The thermal expansion coefficient of the underfill material is preferably close to the thermal expansion coefficient of the semiconductor chip and the core substrate 100, but is not limited thereto. More preferably, (thermal expansion coefficient of the semiconductor chip) ≦ (thermal expansion coefficient of the underfill material) ≦ (thermal expansion coefficient of the core substrate). Furthermore, the semiconductor chip can be mounted using an anisotropic conductive film (ACF) or an adhesive film (NCF) that does not contain conductive particles. In this case, since it is not necessary to seal with an underfill material, it is more preferable. Furthermore, it is particularly preferable to use ultrasonic waves together with the semiconductor chip because electrical connection can be made at a low temperature and in a short time.
For example, solder balls 114 can be mounted on the external connection terminals for electrical connection with the motherboard. For the solder balls, eutectic solder or Pb-free solder is used. As a method for fixing the solder balls to the external connection terminals, an N ₂ reflow device can be used, but the method is not limited to this.

  FIG. 4 shows a cross-sectional view of an embodiment of a wire bond type semiconductor package (including the core substrate 100, the interlayer insulating layer 104, and the insulating coating 109). For mounting the semiconductor chip 111, a general die bond paste can be used, but a die bond film 117 is more preferable. Electrical connection between the semiconductor chip and the semiconductor chip connection terminal is performed by wire bonding using a gold wire 115. The semiconductor chip can be sealed by transfer molding using a semiconductor sealing resin 116. In that case, at least the face surface of the semiconductor chip is sealed with a semiconductor sealing resin, but only a necessary portion of the sealing region may be sealed, but the entire semiconductor package region is sealed as shown in FIG. It is more preferable to stop. This is a particularly effective method in the case where a plurality of semiconductor package regions are arranged in rows and columns and the substrate and the sealing resin are cut simultaneously with a dicer or the like.

For example, solder balls 114 can be mounted on the external connection terminals for electrical connection with the motherboard. For the solder balls, eutectic solder or Pb-free solder is used. As a method for fixing the solder balls to the external connection terminals, an N ₂ reflow device can be used, but the method is not limited to this.

  In a semiconductor chip mounting substrate in which a plurality of semiconductor package regions are arranged in rows and columns, the semiconductor package region is finally cut into individual semiconductor packages using a dicer or the like.

  Hereinafter, the present invention will be described in detail based on examples, but the present invention is not limited thereto.

Example 1
(Process a)
(Step a-1)
A 0.4 mm thick soda glass substrate (coefficient of thermal expansion 11 ppm / ° C.) was prepared as a core substrate 100 (see FIG. 2; the same shall apply hereinafter), and after forming a 200 nm copper thin film by sputtering on one side, Plating was performed to a thickness of 10 μm by plating. In addition, sputtering was performed on condition 1 shown below using the apparatus model number MLH-6315 by Nippon Vacuum Technology Co., Ltd.
(Condition 1)
Current: 3.5A
Voltage: 500V
Argon flow rate: 35 SCCM (0.059 Pa · m ³ / s)
Pressure: 5 × 10 ⁻³ Torr (6.6 × 10 ⁻¹ Pa)
Deposition rate: 5 nm / second

(Step a-2)
After immersing the copper surface formed in (Step a-1) in acidic degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) adjusted to 200 ml / L with water at a liquid temperature of 50 ° C. for 2 minutes. Then, it was washed with hot water by immersing it in water at a liquid temperature of 50 ° C. for 2 minutes, and further washed with water for 1 minute. Subsequently, it was immersed in a 3.6 N sulfuric acid aqueous solution for 1 minute and washed with water for 1 minute.

(Step a-3)
After passing through the above pretreatment process, it is immersed in substituted palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. for 3 minutes to give 1.0 μmol / dm ² of substituted palladium plating for 1 minute. It was washed with water and immersed in an oxidation treatment solution in which sodium chlorite 15 g / L was added to an alkaline aqueous solution containing trisodium phosphate 10 g / L and potassium hydroxide 25 g / L at 50 ° C. for 3 minutes. Thereafter, it was washed with water for 5 minutes and dried at 85 ° C. for 30 minutes.

(Step a-4)
After that, an etching resist is formed, exposed and developed, a resist is formed in a portion to be the first wiring 106a, unnecessary copper is etched using a ferric chloride etchant, and the resist is removed to form a first resist. One wiring 106a (including the first interlayer connection terminal 101 and the semiconductor chip connection terminal) was formed.

(Process b)
An IVH hole having a hole diameter of 50 μm was formed with a laser until the first interlayer connection terminal 101 was reached from the surface opposite to the surface on which the first wiring of the glass substrate was formed. YAG laser LAVIA-UV2000 (manufactured by Sumitomo Heavy Industries, Ltd., trade name) was used as the laser, and IVH holes were formed under the conditions of a frequency of 4 kHz, a shot number of 50, and a mask diameter of 0.4 mm.

  The obtained IVH hole was filled with conductive paste MP-200V (trade name, manufactured by Hitachi Chemical Co., Ltd.), cured at 160 ° C. for 30 minutes, and electrically connected to the first interlayer connection terminal of the glass substrate. The first interlayer connection IVH (via hole) 102 was formed.

(Process c)
(Step c-1)
In order to electrically connect with the first interlayer connection IVH (first via hole) formed in (Step b), 200 nm copper is sputtered on the surface of the glass substrate opposite to the first wiring. After forming the thin film, plating was performed to a thickness of 10 μm by electrolytic copper plating. Sputtering was performed in the same manner as in (Step a-1).

(Step c-2)
After immersing the copper surface formed in (Step c-1) in acidic degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) adjusted to 200 ml / L with water at a liquid temperature of 50 ° C. for 2 minutes, the liquid It was washed with hot water by immersing it in water at a temperature of 50 ° C. for 2 minutes, and further washed with water for 1 minute. Subsequently, it was immersed in a 3.6 N sulfuric acid aqueous solution for 1 minute and washed with water for 1 minute.

(Step c-3)
After passing through the above pretreatment process, it is immersed in substituted palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. for 3 minutes to give 1.0 μmol / dm ² of substituted palladium plating for 1 minute. It was washed with water and immersed in an oxidation treatment solution obtained by adding 15 g / L of sodium chlorite to an alkaline aqueous solution containing 10 g / L of trisodium phosphate and 25 g / L of potassium hydroxide at 50 ° C. for 3 minutes. Thereafter, it was washed with water for 5 minutes and dried at 85 ° C. for 30 minutes.

(Step c-4)
Thereafter, a resist is formed in a portion to be the second wiring 106b as in (Step a), and unnecessary copper is etched using a ferric chloride etchant to form the second wiring 106b (second interlayer connection). Terminal 103).

(Process d)
The surface on the second wiring side formed in (Step c) was immersed in an acidic degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) adjusted to 200 ml / L with water at a liquid temperature of 50 ° C. for 2 minutes. Then, it was washed with hot water by immersing it in water having a liquid temperature of 50 ° C. for 2 minutes, and further washed with water for 1 minute. Subsequently, it was immersed in a 3.6 N sulfuric acid aqueous solution for 1 minute and washed with water for 1 minute.

After passing through the above pretreatment process, it is immersed in substituted palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. for 3 minutes to give 1.0 μmol / dm ² of substituted palladium plating for 1 minute. It was washed with water and immersed in an oxidation treatment solution obtained by adding 15 g / L of sodium chlorite to an alkaline aqueous solution containing 10 g / L of trisodium phosphate and 25 g / L of potassium hydroxide at 50 ° C. for 1 minute. Thereafter, it was washed with water for 3 minutes, immersed in a reduction treatment solution HIST-100D (manufactured by Hitachi Chemical Co., Ltd., trade name) for 1 minute at 35 ° C., and further washed with water for 5 minutes. After this treatment step, it was dried at 85 ° C. for 30 minutes.

  Next, an interlayer insulating layer (build-up layer) 104 was formed as follows. That is, an insulating varnish of a cyanate ester resin composition was applied onto a glass substrate by spin coating at a condition of 1500 rpm to form a resin layer having a thickness of 20 μm, and then from room temperature (25 ° C.) to 6 ° C./min. It heated to 230 degreeC with the temperature increase rate, was thermoset by hold | maintaining at 230 degreeC for 80 minutes, and formed the 15-micrometer buildup layer.

(Process e)
An IVH hole having a hole diameter of 50 μm was formed with a laser until reaching the second interlayer connection terminal 103 from the surface of the buildup layer 104. YAG laser LAVIA-UV2000 (manufactured by Sumitomo Heavy Industries, Ltd., trade name) was used as the laser, and IVH holes were formed under the conditions of a frequency of 4 kHz, a shot number of 20 and a mask diameter of 0.4 mm.

(Process f)
(Process f-1)
In order to form the third wiring 106c and the second via hole 108, a base metal Ni layer 20 nm serving as a seed layer was formed by sputtering, and a thin film copper layer 200 nm was further formed. Sputtering was performed under the condition 2 shown below using MLH-6315 manufactured by Nippon Vacuum Technology Co., Ltd.
(Condition 2)
(nickel)
Current: 5.0A
Current: 350V
Voltage argon flow rate: 35 SCCM (0.059 Pa · m ³ / s)
Pressure: 5 × 10 ⁻³ Torr (6.6 × 10 ⁻¹ Pa)
Deposition rate: 0.3 nm / second (copper)
Current: 3.5A
Voltage: 500V
Argon flow rate: 35 SCCM (0.059 Pa · m ³ / s)
Pressure: 5 × 10 ⁻³ Torr (6.6 × 10 ⁻¹ Pa)
Deposition rate: 5 nm / second

(Process f-2)
After immersing the copper surface formed in (Step f-1) in acidic degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) adjusted to 200 ml / L with water at a liquid temperature of 50 ° C. for 2 minutes, the liquid It was washed with hot water by immersing it in water at a temperature of 50 ° C. for 2 minutes, and further washed with water for 1 minute. Subsequently, it was immersed in a 3.6 N sulfuric acid aqueous solution for 1 minute and washed with water for 1 minute.

(Process f-3)
After passing through the above pretreatment process, it is immersed in substituted palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. for 3 minutes to give 1.0 μmol / dm ² of substituted palladium plating for 1 minute. It was washed with water and immersed in an oxidation treatment solution in which sodium chlorite 15 g / L was added to an alkaline aqueous solution containing trisodium phosphate 10 g / L and potassium hydroxide 25 g / L at 50 ° C. for 3 minutes. Thereafter, it was washed with water for 5 minutes and dried at 85 ° C. for 30 minutes.

(Process f-4)
Next, a film thickness is formed on the seed layer processed in (Step f-2) and (Step f-3) by a spin coat method using a plating resist PMER P-LA900PM (trade name, manufactured by Tokyo Ohka Kogyo Co., Ltd.). A 20 μm plating resist layer was formed. Exposure was performed at 1000 mJ / cm ² , and immersion rocking was performed at 23 ° C. for 6 minutes using PMER developer P-7G to form a resist pattern of L / S = 10 μm / 10 μm. Then, pattern copper plating was performed about 5 micrometers using the copper sulfate plating solution. The plating resist was removed by dipping for 1 minute at room temperature (25 ° C.) using methyl ethyl ketone. For quick etching of the seed layer, a 5-fold diluted solution of CPE-700 (manufactured by Mitsubishi Gas Chemical Co., Ltd., trade name) is used for etching removal by immersing and shaking at 30 ° C. for 30 seconds, and wiring. Formed.

(Process g)
(Process g-1)
Thereafter, the steps (d) to (step f) were repeated again to form a further outermost layer wiring including the buildup layer and the external connection terminal 107.

(Process g-2)
Next, the wiring formed in (Step g-1) is immersed in an acidic degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) adjusted to 200 ml / L for 2 minutes at a liquid temperature of 50 ° C. It was washed with hot water by immersing it in water at a temperature of 50 ° C. for 2 minutes, and further washed with water for 1 minute. Subsequently, it was immersed in a 3.6 N sulfuric acid aqueous solution for 1 minute and washed with water for 1 minute.

(Process g-3)
After passing through the above pretreatment process, it is immersed in substituted palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. for 3 minutes to give 1.0 μmol / dm ² of substituted palladium plating for 1 minute. It was washed with water and immersed in an oxidation treatment solution obtained by adding 15 g / L of sodium chlorite to an alkaline aqueous solution containing 10 g / L of trisodium phosphate and 25 g / L of potassium hydroxide at 50 ° C. for 3 minutes. Thereafter, it was washed with water for 5 minutes and dried at 85 ° C. for 30 minutes.

(Step g-4)
Finally, a solder resist 109 is formed, and a fan-in as shown in FIG. 1 (sectional view of one package), FIG. 5 (plan view of one package), and FIG. A semiconductor chip mounting substrate for type BGA was produced.

(Process h)
A semiconductor chip 111 having connection bumps 112 (see FIG. 3; the same shall apply hereinafter) formed on the semiconductor chip mounting region of the semiconductor chip mounting substrate manufactured by the above-described (step a) to (step g) is flip-chiped. A required number of ultrasonic waves were applied using a bonder. Furthermore, an underfill material is injected from the end of the semiconductor chip into the gap between the semiconductor chip mounting substrate and the semiconductor chip, and primary curing is performed at 80 ° C. for 1 hour and secondary curing at 150 ° C. for 4 hours using an oven. It was. Next, a lead / tin eutectic solder ball 114 having a diameter of 0.45 mm was fused to the external connection terminal using an N ₂ reflow apparatus. Finally, the semiconductor chip mounting substrate was cut with a dicer equipped with a blade having a width of 200 μm to produce the semiconductor package shown in FIG.

Example 2
In (Step a-3), (Step c-3), (Step f-3), and (Step g-3), the replacement palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. Immerse for 3 minutes, apply 1.0 μmol / dm ² of substituted palladium plating, wash with water for 1 minute, add 15 g / L of sodium chlorite to an alkaline aqueous solution containing trisodium phosphate 10 g / L and potassium hydroxide 25 g / L It was immersed in the oxidized treatment solution at 50 ° C. for 3 minutes. Thereafter, it was washed with water for 5 minutes, immersed in a reduction treatment solution HIST-100 (manufactured by Hitachi Chemical Co., Ltd., trade name) for 3 minutes at 40 ° C., and further washed with water for 10 minutes. After this treatment step, it was dried at 85 ° C. for 30 minutes. Other steps were performed in the same manner as in Example 1.

Example 3
In (Step a-3), (Step c-3), (Step f-3), and (Step g-3), the replacement palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. Immerse for 3 minutes, apply 1.0 μmol / dm ² of substituted palladium plating, wash with water for 1 minute, add 15 g / L of sodium chlorite to an alkaline aqueous solution containing trisodium phosphate 10 g / L and potassium hydroxide 25 g / L The film was immersed in the oxidized treatment solution at 50 ° C. for 3 minutes and then washed with water for 5 minutes. After passing through these steps, it was immersed in a 0.5% aqueous solution of γ-aminopropyltriethoxysilane at 30 ° C. for 3 minutes to give a coupling treatment and washed with water for 1 minute. After this treatment step, it was dried at 85 ° C. for 30 minutes. Other steps were performed in the same manner as in Example 1.

Example 4
In (Step a-3), (Step c-3), (Step f-3), and (Step g-3), the replacement palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. Immerse for 3 minutes, apply 1.0 μmol / dm ² of substituted palladium plating, wash with water for 1 minute, add 15 g / L of sodium chlorite to an alkaline aqueous solution containing trisodium phosphate 10 g / L and potassium hydroxide 25 g / L The film was immersed in the oxidized treatment solution at 50 ° C. for 3 minutes and then washed with water for 5 minutes. After passing through these steps, 2-amino-6-hydroxy-8-mercaptopurine (trade name, manufactured by Wako Pure Chemical Industries, Ltd.) was immersed in an ethanol solution having a concentration of 10 ppm at 25 ° C. for 10 minutes, Washed with water for 1 minute. After this treatment step, it was dried at 85 ° C. for 30 minutes. Other steps were performed in the same manner as in Example 1.

Example 5
In (Step a-3), (Step c-3), (Step f-3), and (Step g-3), the replacement palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. Immerse for 3 minutes, apply 1.0 μmol / dm ² of substituted palladium plating, wash with water for 1 minute, add 15 g / L of sodium chlorite to an alkaline aqueous solution containing trisodium phosphate 10 g / L and potassium hydroxide 25 g / L It was immersed in the oxidized treatment solution at 50 ° C. for 3 minutes and then washed with water for 5 minutes. After passing through these steps, the concentration of 3-amino-5-mercapto-1,2,4-triazole (made by Wako Pure Chemical Industries, Ltd., trade name) is 10 ppm in an ethanol solution at 25 ° C. for 10 minutes. Immersion and water washing for 1 minute. After this treatment step, it was dried at 85 ° C. for 30 minutes. Other steps were performed in the same manner as in Example 1.

Example 6
In (Step a-3), (Step c-3), (Step f-3), and (Step g-3), the replacement palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. Immerse for 3 minutes, apply 1.0 μmol / dm ² of substituted palladium plating, wash with water for 1 minute, add 15 g / L of sodium chlorite to an alkaline aqueous solution containing trisodium phosphate 10 g / L and potassium hydroxide 25 g / L It was immersed in the oxidized treatment solution at 50 ° C. for 3 minutes and then washed with water for 5 minutes. After passing through these steps, 2-amino-6-hydroxy-8-mercaptopurine (trade name, manufactured by Wako Pure Chemical Industries, Ltd.) was immersed in an ethanol solution having a concentration of 10 ppm at 25 ° C. for 10 minutes, Washed with water for 1 minute. Furthermore, it was immersed in a 0.5% aqueous solution of γ-aminopropyltriethoxysilane at 30 ° C. for 3 minutes for coupling treatment, and washed with water for 1 minute. After this treatment step, it was dried at 85 ° C. for 30 minutes. Other steps were performed in the same manner as in Example 1.

Example 7
In (Step a-3), (Step c-3), (Step f-3), and (Step g-3), the replacement palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. Immerse for 3 minutes, apply 1.0 μmol / dm ² of substituted palladium plating, wash with water for 1 minute, add 15 g / L of sodium chlorite to an alkaline aqueous solution containing trisodium phosphate 10 g / L and potassium hydroxide 25 g / L It was immersed in the oxidized treatment solution at 50 ° C. for 3 minutes and then washed with water for 5 minutes. Furthermore, it was immersed in a 0.5% aqueous solution of γ-aminopropyltriethoxysilane at 30 ° C. for 3 minutes for coupling treatment, and washed with water for 1 minute. After passing through these steps, the concentration of 3-amino-5-mercapto-1,2,4-triazole (made by Wako Pure Chemical Industries, Ltd., trade name) is 10 ppm in an ethanol solution at 25 ° C. for 10 minutes. Immersion and water washing for 1 minute. After this treatment step, it was dried at 85 ° C. for 30 minutes. Other steps were performed in the same manner as in Example 1.

Example 8
In (Step a-3), (Step c-3), (Step f-3), and (Step g-3), the replacement palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. Immerse for 3 minutes, apply 1.0 μmol / dm ² of substituted palladium plating, wash with water for 1 minute, add 15 g / L of sodium chlorite to an alkaline aqueous solution containing trisodium phosphate 10 g / L and potassium hydroxide 25 g / L It was immersed in the oxidized treatment solution at 50 ° C. for 3 minutes. Thereafter, it was washed with water for 5 minutes, immersed in a reduction treatment solution HIST-100 (manufactured by Hitachi Chemical Co., Ltd., trade name) for 3 minutes at 40 ° C., and further washed with water for 10 minutes. After passing through these steps, it was immersed in a 0.5% aqueous solution of γ-aminopropyltriethoxysilane at 30 ° C. for 3 minutes to give a coupling treatment and washed with water for 1 minute. After this treatment step, it was dried at 85 ° C. for 30 minutes. Other steps were performed in the same manner as in Example 1.

Example 9
In (Step a-3), (Step c-3), (Step f-3), and (Step g-3), the replacement palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. Immerse for 3 minutes, apply 1.0 μmol / dm ² of substituted palladium plating, wash with water for 1 minute, add 15 g / L of sodium chlorite to an alkaline aqueous solution containing trisodium phosphate 10 g / L and potassium hydroxide 25 g / L It was immersed in the oxidized treatment solution at 50 ° C. for 3 minutes. Thereafter, it was washed with water for 5 minutes, immersed in a reduction treatment solution HIST-100 (manufactured by Hitachi Chemical Co., Ltd., trade name) for 3 minutes at 40 ° C., and further washed with water for 10 minutes. After passing through these steps, 2-amino-6-hydroxy-8-mercaptopurine (trade name, manufactured by Wako Pure Chemical Industries, Ltd.) was immersed in an ethanol solution having a concentration of 10 ppm at 25 ° C. for 10 minutes, Washed with water for 1 minute. After this treatment step, it was dried at 85 ° C. for 30 minutes. Other steps were performed in the same manner as in Example 1.

Example 10
In (Step a-3), (Step c-3), (Step f-3), and (Step g-3), the replacement palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. Immerse for 3 minutes, apply 1.0 μmol / dm ² of substituted palladium plating, wash with water for 1 minute, add 15 g / L of sodium chlorite to an alkaline aqueous solution containing trisodium phosphate 10 g / L and potassium hydroxide 25 g / L It was immersed in the oxidized treatment solution at 50 ° C. for 3 minutes. Thereafter, it was washed with water for 5 minutes, immersed in a reduction treatment solution HIST-100 (manufactured by Hitachi Chemical Co., Ltd., trade name) for 3 minutes at 40 ° C., and further washed with water for 10 minutes. After passing through these steps, the concentration of 3-amino-5-mercapto-1,2,4-triazole (made by Wako Pure Chemical Industries, Ltd., trade name) is 10 ppm in an ethanol solution at 25 ° C. for 10 minutes. Immersion and water washing for 1 minute. After this treatment step, it was dried at 85 ° C. for 30 minutes. Other steps were performed in the same manner as in Example 1.

Example 11
In (Step a-3), (Step c-3), (Step f-3), and (Step g-3), the replacement palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. Immerse for 3 minutes, apply 1.0 μmol / dm ² of substituted palladium plating, wash with water for 1 minute, add 15 g / L of sodium chlorite to an alkaline aqueous solution containing trisodium phosphate 10 g / L and potassium hydroxide 25 g / L It was immersed in the oxidized treatment solution at 50 ° C. for 3 minutes. Thereafter, it was washed with water for 5 minutes, immersed in a reduction treatment solution HIST-100 (manufactured by Hitachi Chemical Co., Ltd., trade name) for 3 minutes at 40 ° C., and further washed with water for 10 minutes. After passing through these steps, 2-amino-6-hydroxy-8-mercaptopurine (trade name, manufactured by Wako Pure Chemical Industries, Ltd.) was immersed in an ethanol solution having a concentration of 10 ppm at 25 ° C. for 10 minutes, Washed with water for 1 minute. Furthermore, it was immersed in a 0.5% aqueous solution of γ-aminopropyltriethoxysilane at 30 ° C. for 3 minutes for coupling treatment, and washed with water for 1 minute. After this treatment step, it was dried at 85 ° C. for 30 minutes. Other steps were performed in the same manner as in Example 1.

Example 12
In (Step a-3), (Step c-3), (Step f-3), and (Step g-3), the replacement palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. Immerse for 3 minutes, apply 1.0 μmol / dm ² of substituted palladium plating, wash with water for 1 minute, add 15 g / L of sodium chlorite to an alkaline aqueous solution containing trisodium phosphate 10 g / L and potassium hydroxide 25 g / L It was immersed in the oxidized treatment solution at 50 ° C. for 3 minutes. Thereafter, it was washed with water for 5 minutes, immersed in a reduction treatment solution HIST-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.) at 40 ° C. for 3 minutes, and further washed with water for 10 minutes. Furthermore, it was immersed in a 0.5% aqueous solution of γ-aminopropyltriethoxysilane at 30 ° C. for 3 minutes for coupling treatment, and washed with water for 1 minute. After passing through these steps, the concentration of 3-amino-5-mercapto-1,2,4-triazole (made by Wako Pure Chemical Industries, Ltd., trade name) is 10 ppm in an ethanol solution at 25 ° C. for 10 minutes. Immersion and water washing for 1 minute. After this treatment step, it was dried at 85 ° C. for 30 minutes. Other steps were performed in the same manner as in Example 1.

Example 13
In (Step a-3), (Step c-3), (Step f-3), and (Step g-3), the substitution gold plating solution HGS-500 (Hitachi Chemical Industry Co., Ltd., product name) at 30 ° C. Immerse for 1 minute, apply substitution gold plating of 1.0 μmol / dm ² , wash with water for 1 minute, add 15 g / L of sodium chlorite to alkaline aqueous solution containing 10 g / L of trisodium phosphate and 25 g / L of potassium hydroxide It was immersed in the oxidized treatment solution at 50 ° C. for 3 minutes. Thereafter, it was washed with water for 5 minutes and dried at 85 ° C. for 30 minutes. Other steps were performed in the same manner as in Example 1.

Example 14
In (Step a-3), (Step c-3), (Step f-3), and (Step g-3), silver nitrate 7.5 g / L, ammonia hydroxide 75 g / L, sodium thiosulfate pentahydrate Substituted in a silver plating solution containing 30 mg at 30 ° C. for 20 seconds to give 1.0 μmol / dm ² of substitution silver plating, washed with water for 1 minute, and containing trisodium phosphate 10 g / L and potassium hydroxide 25 g / L It was immersed in an oxidation treatment solution obtained by adding 15 g / L of sodium chlorite to an alkaline aqueous solution at 50 ° C. for 3 minutes. Thereafter, it was washed with water for 5 minutes and dried at 85 ° C. for 30 minutes. Other steps were performed in the same manner as in Example 1.

Example 15
(Process a ′)
(Step a′-1)
A 0.4 mm thick soda glass substrate (thermal expansion coefficient 11 ppm / ° C.) was prepared as a core substrate 100 (see FIG. 9, the same applies hereinafter), and an insulating layer 104 was formed on one side as follows. That is, an insulating varnish of a cyanate ester resin composition was applied onto a glass substrate by spin coating at a condition of 1500 rpm to form a resin layer having a thickness of 20 μm, and then from room temperature (25 ° C.) to 6 ° C./min. The insulating layer 104 was formed by heating to 230 ° C. at a rate of temperature rise and thermosetting by holding at 230 ° C. for 80 minutes.

(Step a′-2)
The plated surface 118 was formed by (Step a-1) of Example 1. Next, (Step a-2) of Example 1 was performed.

(Step a′-3)
(Step a-3) of Example 1 was performed to form a dry film etching resist (Sunfort SPG-152 film thickness 15 μm manufactured by Asahi Kasei Electronics Co., Ltd., or EKIRESIN PER-800 negative type manufactured by Liquid Etching Resistant Chemical Industries) After that, exposure and development were performed, and a resist 119 was formed in a portion to be the wiring 106.

(Process d ')
Unnecessary plating was etched using a ferric chloride etchant, and then the resist was removed to form the wiring 106. Thereafter, an insulating layer (build-up layer) 104 is formed in the same manner as (step a′-1), and L / S = 5 μm / 5 μm (25 pairs of wires, 50 wires) shown in FIG. 12, L / S = 7 μm / 7 μm (wire pairs: 25 pairs, number of wires: 50), L / S = 10 μm / 10 μm (wire pairs: 25 pairs, number of wires: 50), FIG. A comb-type wiring board with L / S = 15 μm / 15 μm (wire pairs: 25 pairs, number of wires: 50) shown in FIG.

Example 16
Example 15 (Step a′-3) In the same manner as Example 15 except that Example 2 (Step a-3) was performed instead of Example 1 (Step a-3). went.

Example 17
As in Example 15, except that (Step a-3) in Example 3 was performed instead of (Step a-3) in Example 1 in (Step a′-3) in Example 15. went.

Example 18
Example 15 (Step a′-3) In the same manner as Example 15 except that Example 4 (Step a-3) was performed instead of Example 1 (Step a-3). went.

Example 19
The same procedure as in Example 15 was performed except that (Step a-3) in Example 5 was performed instead of performing (Step a-3) in Example 1 in (Step a′-3) in Example 15. It was.

Example 20
The same procedure as in Example 15 was performed except that (Step a-3) of Example 6 was performed instead of (Step a-3) of Example 1 in (Step a′-3) of Example 15. .

Example 21
The same procedure as in Example 15 was performed except that (Step a-3) in Example 7 was performed instead of performing (Step a-3) in Example 1 in (Step a′-3) in Example 15. It was.

Example 22
The same procedure as in Example 15 was performed except that (Step a-3) in Example 8 was performed instead of (Step a-3) in Example 1 in (Step a′-3) in Example 15. It was.

Example 23
The same procedure as in Example 15 was performed except that (Step a-3) in Example 9 was performed instead of performing (Step a-3) in Example 1 in (Step a′-3) in Example 15. It was.

Example 24
The same procedure as in Example 15 was performed except that (Step a-3) in Example 10 was performed instead of (Step a-3) in Example 1 in (Step a′-3) in Example 15. It was.

Example 25
The same procedure as in Example 15 was performed except that (Step a-3) in Example 11 was performed instead of (Step a-3) in Example 1 in (Step a′-3) in Example 15. It was.

Example 26
The same procedure as in Example 15 was performed except that (Step a-3) in Example 12 was performed instead of (Step a-3) in Example 1 in (Step a′-3) in Example 15. It was.

Example 27
As in Example 15, except that (Step a-3) in Example 13 was performed instead of (Step a-3) in Example 1 in (Step a′-3) in Example 15. went.

Example 28
The same procedure as in Example 15 was performed except that (Step a-3) in Example 14 was performed instead of (Step a-3) in Example 1 in (Step a′-3) in Example 15. It was.

Example 29
(Process a ″)
(Process a ″ -1)
A 25 μm-thick polyimide film (Kapton 100V manufactured by Toray DuPont) was prepared as an insulating layer 104 ′ (see FIG. 10, the same applies hereinafter).

(Process a ″ -2)
The plated surface 118 was formed by (Step a-1) of Example 1. Next, (Step a-2) of Example 1 was performed.

(Process a ″ -3)
(Step a-3) of Example 1 was performed to form a dry film etching resist (Sunfort SPG-152 film thickness 15 μm manufactured by Asahi Kasei Electronics Co., Ltd., or EKIRESIN PER-800 negative type manufactured by Liquid Etching Resistant Chemical Industries) After that, exposure and development were performed, and a resist 119 was formed in a portion to be the wiring 106.

(Process d ″)
(Process d ″ -1)
Etching was performed using a ferric chloride etchant, and then the resist was removed to form the wiring 106. Next, (Step a-2) of Example 1 was performed.

(Process d ″ -2)
(Step a-3) of Example 1 is performed to form an insulating coating (solder resist), and thereafter, exposure and development are performed to form a solder resist 109 covering the wiring 106, and the L / S shown in FIG. = 5 μm / 5 μm (wire pairs: 25 pairs, number of wires: 50), L / S shown in FIG. 12 = 7 μm / 7 μm (wire pairs: 25 pairs, number of wires: 50), L / S shown in FIG. = 10 μm / 10 μm (wire pairs: 25 pairs, number of wires: 50), and a comb-type wiring board of L / S = 15 μm / 15 μm (wire pairs: 25 pairs, number of wires: 50) shown in FIG. .

Example 30
Similar to Example 29 except that (Step a-3) of Example 2 was performed instead of (Step a-3) of Example 1 in (Step d ″ -2) of Example 29. Went to.

Example 31
Similar to Example 29 except that (Step a-3) of Example 3 was performed instead of (Step a-3) of Example 1 in (Step d ″ -2) of Example 29. Went to.

Example 32
Similar to Example 29 except that (Step a-3) of Example 4 was performed instead of (Step a-3) of Example 1 in (Step d ″ -2) of Example 29. Went to.

Example 33
Similar to Example 29 except that (Step a-3) of Example 5 was performed instead of (Step a-3) of Example 1 in (Step d ″ -2) of Example 29. Went to.

Example 34
Similar to Example 29 except that (Step a-3) of Example 6 was performed instead of (Step a-3) of Example 1 in (Step d ″ -2) of Example 29. Went to.

Example 35
Similar to Example 29 except that (Step a-3) of Example 7 was performed instead of (Step a-3) of Example 1 in (Step d ″ -2) of Example 29. Went to.

Example 36
Similar to Example 29 except that (Step a-3) of Example 8 was performed instead of (Step a-3) of Example 1 in (Step d ″ -2) of Example 29. Went to.

Example 37
Similar to Example 29 except that (Step a-3) of Example 9 was performed instead of (Step a-3) of Example 1 in (Step d ″ -2) of Example 29. Went to.

Example 38
Similar to Example 29 except that (Step a-3) of Example 10 was performed instead of (Step a-3) of Example 1 in (Step d ″ -2) of Example 29. Went to.

Example 39
Similar to Example 29 except that (Step a-3) of Example 11 was performed instead of (Step a-3) of Example 1 in (Step d ″ -2) of Example 29. Went to.

Example 40
Similar to Example 29 except that (Step a-3) of Example 12 was performed instead of (Step a-3) of Example 1 in (Step d ″ -2) of Example 29. Went to.

Example 41
Similar to Example 29 except that (Step a-3) of Example 13 was performed instead of (Step a-3) of Example 1 in (Step d ″ -2) of Example 29. Went to.

Example 42
Similar to Example 29 except that (Step a-3) of Example 14 was performed instead of (Step a-3) of Example 1 in (Step d ″ -2) of Example 29. Went to.

Example 43
A 25 μm-thick polyimide film (Kapton 100V manufactured by Toray DuPont Co., Ltd.) as the insulating layer 104 ′ was subjected to the treatment (step a-3) shown in Example 1.

Example 44
A 25 μm-thick polyimide film (Kapton 100V, manufactured by Toray DuPont Co., Ltd.) as the insulating layer 104 ′ was subjected to the treatment (step a-3) shown in Example 2.

Example 45
A 25 μm-thick polyimide film (Kapton 100V manufactured by Toray DuPont Co., Ltd.) as the insulating layer 104 ′ was subjected to the treatment (step a-3) shown in Example 3.

Example 46
A 25 μm-thick polyimide film (Kapton 100V manufactured by Toray DuPont Co., Ltd.) as the insulating layer 104 ′ was subjected to the treatment (step a-3) shown in Example 4.

Example 47
A 25 μm-thick polyimide film (Kapton 100V manufactured by Toray DuPont Co., Ltd.) as the insulating layer 104 ′ was subjected to the treatment of (Step a-3) shown in Example 5.

Example 48
A 25 μm-thick polyimide film (Kapton 100V manufactured by Toray DuPont Co., Ltd.) as the insulating layer 104 ′ was subjected to the treatment (step a-3) shown in Example 6.

Example 49
A 25 μm-thick polyimide film (Kapton 100V manufactured by Toray DuPont Co., Ltd.) as the insulating layer 104 ′ was subjected to the treatment (step a-3) shown in Example 7.

Example 50
A 25 μm-thick polyimide film (Kapton 100V manufactured by Toray DuPont Co., Ltd.) as the insulating layer 104 ′ was subjected to the treatment of (Step a-3) shown in Example 8.

Example 51
A 25 μm-thick polyimide film (Kapton 100V manufactured by Toray DuPont Co., Ltd.) as the insulating layer 104 ′ was subjected to the treatment (step a-3) shown in Example 9.

Example 52
A 25 μm-thick polyimide film (Kapton 100V manufactured by Toray DuPont Co., Ltd.) as the insulating layer 104 ′ was subjected to the treatment of (Step a-3) shown in Example 10.

Example 53
A 25 μm-thick polyimide film (Kapton 100V manufactured by Toray DuPont Co., Ltd.) as the insulating layer 104 ′ was subjected to the treatment of (Step a-3) shown in Example 11.

Example 54
A 25 μm-thick polyimide film (Kapton 100V manufactured by Toray DuPont Co., Ltd.) as the insulating layer 104 ′ was subjected to the treatment (step a-3) shown in Example 12.

Example 55
A 25 μm-thick polyimide film (Kapton 100V manufactured by Toray DuPont Co., Ltd.) as the insulating layer 104 ′ was subjected to the treatment (step a-3) shown in Example 13.

Example 56
A 25 μm-thick polyimide film (Kapton 100V manufactured by Toray DuPont Co., Ltd.) as the insulating layer 104 ′ was subjected to the treatment (step a-3) shown in Example 14.

Comparative Example 1
Instead of (Step a-3), (Step c-3), (Step f-3) and (Step g-3) of Example 1, trisodium phosphate 10 g / L and hydroxylation were used in each step. It was immersed for 3 minutes at 85 ° C. in an oxidation treatment solution in which 15 g / L of sodium chlorite was added to an alkaline aqueous solution containing 25 g / L of potassium. Thereafter, it was washed with water for 5 minutes and dried at 85 ° C. for 30 minutes. Otherwise, the same procedure as in Example 1 was performed.

Comparative Example 2
Instead of (Step a-3), (Step c-3), (Step f-3) and (Step g-3) in Example 1, in each step, trisodium phosphate 10 g / L and potassium hydroxide were used. It was immersed at 85 ° C. for 3 minutes in an oxidation treatment solution obtained by adding 15 g / L of sodium chlorite to an alkaline aqueous solution containing 25 g / L. Thereafter, it was washed with water for 5 minutes, immersed in a reduction treatment solution HIST-100 (manufactured by Hitachi Chemical Co., Ltd., trade name) for 3 minutes at 40 ° C., and further washed with water for 10 minutes. After this treatment step, it was dried at 85 ° C. for 30 minutes. Otherwise, the same procedure as in Example 1 was performed.

Comparative Example 3
Instead of (Step a-3), (Step c-3), (Step f-3), and (Step g-3) in Example 1, in each step, Mec Etch Bond CZ8100 (Mec The product was soaked in 40 ° C for 1 minute and 30 seconds, washed with water, then immersed in a 3.6 N sulfuric acid aqueous solution at room temperature for 60 seconds, and further washed with water for 1 minute. After this treatment step, it was dried at 85 ° C. for 30 minutes. Otherwise, the same procedure as in Example 1 was performed.

Comparative Example 4
The respective steps of (Step a-3), (Step c-3), (Step f-3) and (Step g-3) of Example 1 were not performed. That is, the unevenness forming process was not performed. Otherwise, the same procedure as in Example 1 was performed.

Comparative Example 5
Instead of (Step a′-3) of Example 15, (Step a-3) of Comparative Example 1 was carried out, and otherwise, the same procedure as in Example 15 was performed.

Comparative Example 6
Instead of (Step a′-3) of Example 15, (Step a-3) of Comparative Example 2 was performed, and otherwise, the same procedure as in Example 15 was performed.

Comparative Example 7
Instead of (Step a′-3) in Example 15, (Step a-3) in Comparative Example 3 was carried out, and otherwise, the same procedure as in Example 15 was performed.

Comparative Example 8
In (Step a′-3) of Example 15, (Step a-3) of Example 1 was not performed. Except this, the same procedure as in Example 15 was performed.

Comparative Example 9
In (Step d ″ -2) of Example 29, instead of (Step a-3) of Example 1, (Step a-3) of Comparative Example 1 was carried out, and otherwise the same as Example 29 went.

Comparative Example 10
In (Step d ″ -2) of Example 29, instead of (Step a-3) of Example 1, (Step a-3) of Comparative Example 2 was carried out, and otherwise the same as Example 29 went.

Comparative Example 11
In Example 29 ((Step d ″ -2)), (Step a-3) in Comparative Example 3 was performed instead of (Step a-3) in Example 1, and the others were the same as Example 29. Went to.

Comparative Example 12
In (Step d ″ -2) of Example 29, (Step a-3) of Example 1 was not performed. Except this, the same procedure as in Example 29 was performed.

Comparative Example 13
As the insulating layer 104 ′, a 25 μm-thick polyimide film (Kapton 100V manufactured by Toray DuPont Co., Ltd.) was subjected to the treatment (step a-3) shown in Comparative Example 1.

Comparative Example 14
A 25 μm-thick polyimide film (Kapton 100V manufactured by Toray DuPont Co., Ltd.) as the insulating layer 104 ′ was subjected to the treatment (step a-3) shown in Comparative Example 2.

Comparative Example 15
A 25 μm-thick polyimide film (Kapton 100V manufactured by Toray DuPont Co., Ltd.) as the insulating layer 104 ′ was subjected to the treatment (step a-3) shown in Comparative Example 3.

Comparative Example 16
No treatment was performed on a 25 μm-thick polyimide film (Kapton 100V manufactured by Toray DuPont) as the insulating layer 104 ′.

  The following tests were performed on the test samples prepared as described above.

(Copper surface smoothness, shape, matte evaluation test)
After processing to (Step a-3) described in Examples 1 to 14 and Comparative Examples 1 to 4, a copper surface smoothness evaluation test was performed. When Rz is 1 nm or more and 100 nm or less, ◎, when Rz exceeds 100 nm and 1000 nm or less, ◯, and when Rz is less than 1 nm or more than 1000 nm, Δ. The results are shown in Table 1. Next, the copper surface shape was examined. According to the observation with an electron microscope, a copper surface having a dense and uniform unevenness was indicated as “◯”, and a copper surface shape was indicated as “X”. The results are also shown in Table 1. However, in Comparative Example 4, since (Step a-3) was not performed, unevenness could not be formed on the copper surface. Furthermore, the presence or absence of gloss was examined visually. A matte one was marked with ◯, and a glossy one with x. The results are also shown in Table 1.

(Resist pattern formation rate evaluation test)
After processing to (Step a′-3) described in Examples 15 to 28 and Comparative Examples 5 to 8, evaluation of the resist pattern formation rate of each L / S by dry film / etching resist and liquid / etching resist was performed. did. In the evaluation method, the resist width in which the resist of each L / S was formed was measured, and those having an error with respect to the design value of each L / S resist width within ± 10% were determined as non-defective products, and the ratio was examined. The results are shown in Table 2 for the dry film / etch resist and in Table 3 for the liquid / etch resist.

(Short-circuit evaluation test between wires)
After the processes of (Step a ′) and (Step d ′) described in Examples 15 to 28 and Comparative Examples 5 to 8, each of the L / S comb-type wiring boards with dry film / etch resist and liquid / etch resist was used. The number of short circuits between wires was examined. The results are shown in Table 4 for the dry film / etch resist and in Table 5 for the liquid / etch resist.

(Electrical corrosion test)
After the processes of (Step a ′) and (Step d ′) described in Examples 15 to 28 and Comparative Examples 5 to 8, each of the L / S comb-type wiring boards with dry film / etch resist and liquid / etch resist was used. The insulation resistance value between wirings was measured, and a value less than 1.0 × 10 ⁹ Ω was determined as NG.
The results are shown in Table 6 for the dry film / etch resist and in Table 7 for the liquid / etch resist. The insulation resistance between wirings of each L / S comb-type wiring board was measured by applying a DC 5V voltage at room temperature for 30 seconds using an R-8340A type digital ultra-high resistance microammeter manufactured by Advantest Co., Ltd. The resistance value was measured. A digital multimeter 3457A manufactured by Hewlett-Packard (HP) Co., Ltd. was used for measuring the insulation resistance of 1 GΩ or less. Next, voltage DC5V was continuously applied in a constant humidity and constant temperature layer maintained at 85 ° C. and a relative humidity of 85%, and the insulation resistance value between the L / S wirings was measured at regular intervals in the same manner as described above. The constant temperature and humidity chamber was an EC-10HHPS type constant temperature and humidity made by Hitachi, Ltd., and was measured up to 1000 hours after being charged. However, in Comparative Example 8, wiring could not be formed and a test board could not be created.

(Gold plating test)
After processing to (Step g) described in Examples 1 to 14 and Comparative Examples 1 to 4, gold plating treatment was performed on the external connection terminal portion. As a gold plating treatment method, after immersing in acidic degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) adjusted to 200 ml / L with water at a liquid temperature of 50 ° C. for 2 minutes, It was washed with hot water by dipping for 2 minutes, and further washed with water for 1 minute. Subsequently, it was immersed in a 3.6 N sulfuric acid aqueous solution for 1 minute and washed with water for 1 minute. Next, it was immersed in substitutional palladium plating solution SA-100 (Hitachi Chemical Industry Co., Ltd., product name) for 3 minutes at 30 ° C., palladium was selectively applied to the external connection terminal portion, and washed with water for 1 minute. Next, it was immersed in electroless nickel plating solution NIPS-100 (Hitachi Chemical Industry Co., Ltd., product name) at 85 ° C. for 15 minutes, and 5 μm of nickel was selectively applied to the external connection terminal portion, followed by washing with water for 1 minute. Next, it was immersed in a displacement gold plating solution HGS-500 (Hitachi Chemical Industry Co., Ltd., product name) at 85 ° C. for 10 minutes, and 0.05 μm of gold was selectively applied to the external connection terminal portion, followed by washing with water for 1 minute. Next, it is immersed in electroless gold plating solution HGS-2000 (Hitachi Chemical Industry Co., Ltd., product name) for 40 minutes at 60 ° C., and gold is selectively applied to the external connection terminal portion by 0.5 μm and washed with water for 5 minutes. , And dried at 85 ° C. for 30 minutes. As for the gold plating evaluation method, it was determined by visual observation or microscopic observation that the gold plating unevenness was ○, the gold plating unevenness was Δ, and the gold plating non-deposition was ×. The results are shown in Table 8.

(PCT resistance evaluation test)
After processing to (step d ″) described in Examples 29 to 42 and Comparative Examples 9 to 12, a PCT resistance test (121 ° C., 200 h, 2 atm) was performed. The evaluation method was to examine the presence or absence of swelling between the wiring (Cu) / solder resist (SR) and the polyimide film (PI) / solder resist after the test. The results are shown in Table 9. However, in Comparative Example 11, wiring could not be formed and a test substrate could not be created.

(Dissolution resistance evaluation test)
The weight loss before and after the treatment of PI described in Examples 43 to 56 and Comparative Examples 13 to 16 was measured, and the dissolution amount per m ² was calculated. In the evaluation method, the dissolution amount of PI was less than 100 mg / m ² , and the dissolution amount of PI of 100 mg / m ² or more was evaluated as x. The results are shown in Table 10.

(Semiconductor package reliability test)
Each of the semiconductor packages described in Examples 1 to 14 and Comparative Examples 1 to 4 was subjected to moisture absorption treatment, and then flowed in a reflow furnace having an ultimate temperature of 240 ° C. and a length of 2 m under conditions of 0.5 m / min. Twenty-two samples were reflowed to examine the occurrence of cracks. The results are shown in Table 11. However, in Comparative Example 3, the wiring accuracy could not be maintained and the test substrate could not be manufactured.

  As shown in Examples 1 to 56, in the case of the present invention, the copper surface could be made dull by forming dense and uniform unevenness of several tens of nanometers on the copper surface. Further, it was found that by forming a resist on the copper surface, the formation rate of the resist pattern was good and there was no short circuit between the wirings. In addition, the reliability of the manufactured semiconductor package was extremely good. In addition, the inter-wiring insulation reliability, PCT resistance, and dissolution resistance of each L / S in the electrolytic corrosion test were extremely good. On the other hand, in the prior art, as shown in Comparative Examples 1 to 16, matte copper surface and uneven shape, resist pattern formation rate, number of short circuits between wires, reliability of semiconductor package, insulation reliability between wires The PCT resistance and the dissolution resistance could not all be satisfied. Therefore, according to the present invention, a good wiring can be formed by forming dense and uniform fine irregularities of several tens of nanometer level on the copper surface. Further, according to the present invention, a solder resist or a cover lay can be formed with good adhesiveness, and various wiring substrates, semiconductor chip mounting substrates, and semiconductor packages having excellent reliability can be manufactured.

1 is a cross-sectional view of a semiconductor chip mounting substrate to which an embodiment of the present invention is applied. (A)-(g) is process drawing which shows one Embodiment of the manufacturing method of the semiconductor chip mounting substrate of this invention. 1 is a cross-sectional view of a flip chip type semiconductor package to which an embodiment of the present invention is applied. 1 is a cross-sectional view of a wire bond type semiconductor package to which an embodiment of the present invention is applied. The top view of the fan-in type semiconductor chip mounting board | substrate of this invention. The top view of the fan-out type semiconductor chip mounting substrate of this invention. The top view showing the frame shape of the semiconductor chip mounting substrate of this invention. 1 is a cross-sectional view of a semiconductor chip mounting substrate to which an embodiment of the present invention is applied. (A ')-(d') is process drawing which shows one Embodiment of the evaluation board | substrate manufacturing method for electrolytic corrosion tests of this invention. (A ")-(d") is process drawing which shows one Embodiment of the PCT-proof evaluation board | substrate manufacturing method of this invention. The top view of the evaluation board for electric corrosion tests to which one embodiment of the present invention is applied. The top view of the evaluation board for electric corrosion tests to which one embodiment of the present invention is applied. The top view of the evaluation board for electric corrosion tests to which one embodiment of the present invention is applied. The top view of the evaluation board for electric corrosion tests to which one embodiment of the present invention is applied.

Explanation of symbols

11. Positioning mark (guide hole for alignment)
13. Semiconductor package region 14. Die bond film bonding area (flip chip type)
15. Semiconductor chip mounting area (flip chip type)
16. Semiconductor chip connection terminal 17. Die bond film bonding area (wire bond type)
18. Semiconductor chip mounting area (wire bond type)
19. External connection terminal 20. Expanded wiring 21. Dummy pattern 22. Semiconductor chip mounting substrate 23. Block 24. Reinforcing pattern 25. Cutting alignment mark 100 Core substrate 101 First interlayer connection terminal 102 IVH (via hole) for first interlayer connection
103 Second interlayer connection terminal 104 Interlayer insulating layer (build-up layer)
104 'Insulating layer (polyimide film)
105 Third layer connection IVH (via hole)
106 wiring 106a first wiring 106b second wiring 106c third wiring 107 external connection terminal 108 IVH (via hole) for second interlayer connection
109 Insulation coating (solder resist)
111 Semiconductor chip 112 Connection bump 113 Underfill material 114 Solder ball 115 Gold wire 116 Sealing resin for semiconductor 117 Die bond film 118 Plating surface 119 Resist

Claims (12)

A pretreatment method for forming a resist or coverlay on a copper surface, the step of discretely forming a metal nobler than copper on the copper surface, and then the copper surface is an alkaline aqueous solution containing an oxidizing agent. And a step of oxidizing the copper surface. Wherein after the step of oxidizing process, reduction process, comprising at least one step selected from the coupling treatment and corrosion inhibiting treatment, pretreatment method of a copper surface as claimed in claim 1. Alkaline aqueous solution containing the oxidizing agent is an alkali metal or alkaline earth metal chlorate, chlorite, hypochlorite, at least a salt selected from perchlorate and peroxodisulfate and one or more, the pretreatment method of the copper surface as claimed in claim 1 or 2. Wherein the metal nobler than copper, gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, osmium and metal selected from iridium or an alloy containing the metal, and any one of claims 1 to 3 The copper surface pretreatment method as described. The amount of metal noble than copper formed discretely on the copper surface is 0 . The pretreatment method for a copper surface according to any one of claims 1 to 4 , which is 001 µmol / dm ² or more and 40 µmol / dm ² or less. The surface roughness caused by the pretreatment method of the copper surface is 1nm or more and 1000nm or less in Rz, the pretreatment method of the copper surface as claimed in any one of claims 1 to 5.   A wiring substrate obtained by discretely forming a metal nobler than copper on a copper surface, thereafter performing an oxidation treatment with an alkaline aqueous solution containing an oxidizing agent on the copper surface, and then forming a resist. Before even after the oxidation treatment to the resist formation, further reduction is obtained by performing at least one treatment selected from the coupling treatment and corrosion inhibiting treatment, a wiring board according to claim 7 . Alkaline aqueous solution containing the oxidizing agent is an alkali metal or alkaline earth metal chlorate, chlorite, hypochlorite, at least a salt selected from perchlorate and peroxodisulfate and one or more, the wiring board according to claim 7 or 8. Wherein the metal nobler than copper, gold, silver, platinum, palladium, rhodium, rhenium, ruthenium, metal selected from osmium and iridium or an alloy containing the metal, to any one of claims 7 to 9 The wiring board described. Are discretely formed on the copper surface, the amount of the metal nobler than the copper is 0.001μmol / dm ² or more and 40 [mu] mol / dm ² or less, the wiring board according to any one of claims 7 to 10 . The surface roughness of the copper surface after the oxidation treatment is 1nm or more and 1000nm or less in Rz, the wiring board according to any one of claims 7-11.

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