JP2000208903A - Printed wiring board and manufacturing of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed wiring board and method for manufacturing it which is superior in connectivity and reliability. SOLUTION: A solder film 75 is formed on the surface of a via hole 160 and conductor circuit 158 via a nickel plating layer 72 and gold plating layer 74, for rust-proof and protection of the surface of via hole 160 and the conductor circuit 158. Even if there is a certain period before mounting of an IC chip (formation of a solder bump) after the completion of the multilayer printed wiring board, a solder bump is appropriately formed on the surface of the solder film 75.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board for forming a package substrate or the like on which an integrated circuit chip is mounted via solder bumps, and a method for manufacturing the same.

[0002]

[Prior art]

2. Description of the Related Art A build-up multilayer wiring board is manufactured by a method disclosed in, for example, Japanese Patent Application Laid-Open No. 9-130050. That is, a roughened layer is formed on the surface of a conductive circuit by electroless plating or etching, and an interlayer insulating resin is applied by a roll coater or printing, exposed, and developed to form a via hole opening for interlayer conduction. To form UV
After curing and main curing, an interlayer resin insulating layer is formed. Furthermore, the interlayer insulating layer is subjected to a roughening treatment with an oxidizing agent or the like, a catalyst such as palladium is applied to the roughened surface, a thin electroless plating film is formed, and a pattern is formed on the plating film with a dry film. After being thickened by electrolytic plating, the dry film is peeled off and removed with an alkali and etched to form a conductor circuit. By repeating this, a build-up multilayer wiring board is obtained.

[0003] In the outermost layer, to protect the conductor circuit,
Apply a solder resist layer. The solder resist layer,
Partially open to expose conductive circuits for external connection.
A multilayer printed wiring board is completed by forming a metal layer on the conductor circuit (electrode) exposed at the opening. When the IC chip is mounted on the multilayer printed wiring board, a solder bump is formed on a conductor circuit (electrode) in the opening of the solder resist with a brazing material such as solder, and then the pad of the IC chip is attached to the solder bump. (External electrode) is connected to establish conduction. I
The mounting is completed by inserting a sealing resin (underfill) between the C chip and the substrate and curing the resin. On the other hand, when the package substrate is mounted on a printed wiring board as a motherboard, solder paste is printed on a conductor circuit (electrode) opposite to the IC chip mounting surface, or a solder ball is mounted.
Create solder balls in a reflow oven. The BGA board with the solder balls is mounted on a motherboard.

[0004]

However, the metal layer formed in the opening of the solder resist layer is discolored,
May deteriorate. The surface state of the metal changes due to the discoloration and alteration of the metal layer, and the wettability changes.
When forming solder bumps on the chip side and solder balls (BGA) on the motherboard side, the solder repels,
It happened that the solder balls could not be placed. Also, the solder balls once disposed may fall off or come off. A method of removing the deteriorated or discolored portion by etching, polishing, plasma treatment, or the like can be considered, but cannot be adopted because the metal layer is more damaged.

On the other hand, at the stage of manufacturing a multilayer printed wiring board, B
Such a problem does not occur if the printed wiring board is shipped with the GA installed. However, when attaching an IC chip,
In the step of pressing the C chip onto the multilayer printed wiring board, the BGA provided may be damaged by the applied force. In addition, at the time of thermocompression bonding, the substrate itself may not be heated well via the BGA. To address these issues, existing facilities for mounting IC chips on multilayer printed wiring boards without BGAs are
It is very difficult to cope with this because it is necessary to make a type of equipment in which the GA is mounted.

An object of the present invention is to propose a method for manufacturing a printed wiring board which can solve such a problem and has excellent connectivity and reliability.

[0007]

Means for Solving the Problems As a result of intensive studies, the present inventors have found the following facts. The discoloration and alteration of the metal layer are measured during the period from the completion of the printed wiring board by forming the metal layer at the manufacturing facility of the multilayer printed wiring board to the disposition of external electrodes such as BGA at the IC chip mounting facility. It was found that a metal coating was formed.
Further, during the period, oils and fats may adhere to the surface of the metal layer of the printed wiring board. Although no particular problem occurs in the handling at the normal level, it has been found that when left for a certain period (4 months) or more, the above-described problem is caused because the solder wettability of the metal layer is reduced.

Further, as a result of the research, the metal layer was protected,
It has been found that a solder film should be formed in order to reliably dispose the BGA or the like. In the case of a printed wiring board in which a solder film was provided in the opening of the solder resist, no problem such as peeling or falling off of the BGA occurred even after a period of 4 months or more. Further, since no discoloration or deterioration of the metal layer occurs, conduction in the opening can be secured.

Next, the solder film used in the present invention will be described. The solder film formed in the opening is 0.1 to 3
It is preferable that the thickness be within a range of 0 μm. If the thickness is too small, it is difficult to form a solder film. If the thickness is too large, the thickness of the solder resist is in the range of 5 to 40 μm. Contact and short circuit. In particular, 1-1
It is preferable that the film be formed in a range of 0 μm. This is because the metal layer can be protected and no problem occurs when the BGA is provided. Solder used is Pb / Sn 4: 6-9: 1
(The distribution ratio of Pb is 30% to 90%), and all the solders generally used for printed wiring boards can be used. In addition, SnAg, SnAgCu, S
A material that does not use lead, such as nCu, can be used.

[0010] Further, the forming method is performed by either plating or printing. In terms of the uniformity of the formed solder film, plating is superior to that formed by printing.

The metal layer formed in the opening is made of Cu, N
One or more layers of at least one alloy of i, Au, Ag, Sn, P, and Al are preferably formed. The formed metal is preferably a metal alloy mainly composed of Au from the viewpoint of protecting the conductor circuit. On the other hand, in terms of the adhesion to the solder film and the adhesion to the solder resist, C
It is preferable to use a metal alloy mainly composed of u or Ni and having an uneven surface. For example, it is desirable to provide an alloy layer made of Cu-Ni-P.

In the above configuration, when an external electrode such as a BGA is provided, the solder film formed in the opening is melted, so that the BGA may fall off or peel off due to the solder wettability of the metal layer. Does not occur. Even if the BGA is disposed after a certain period of time, there is no problem, and no discoloration or deterioration of the metal layer in the opening occurs, so that good connectivity can be maintained for a long time.

A method for manufacturing a printed wiring board according to the present invention will be described. The following method is based on the semi-additive method, but may use the full-additive method.

First, a wiring board having a conductor circuit formed on the surface of the board is prepared. As a substrate, an interlayer insulating layer is formed on a substrate such as a glass epoxy substrate, a polyimide substrate, a resin insulating substrate such as a bismaleimide-triazine resin substrate, a copper-clad laminate, a ceramic substrate, a metal substrate, and the like. Roughened to a roughened surface, a thin electroless plating is applied to the entire roughened surface to form a plating resist,
After applying a thick electrolytic plating to the plating resist non-formed part, the plating resist is removed and etched,
This is performed by a method of forming a conductor circuit composed of an electrolytic plating film and an electroless plating film. The conductor circuits are all copper patterns.
Is good.

On the substrate on which the conductor circuit is formed, a recess is formed by the conductor circuit or through hole. A resin filler is applied by printing or the like to fill the recess, and after drying, the unnecessary resin filler is ground by grinding to expose the conductive circuit, and then the resin filler is fully cured.

Next, a roughening layer is provided on the conductor circuit. The roughened layer to be formed is desirably a roughened surface of copper formed by an etching process, a polishing process, an oxidation process, or an oxidation-reduction process or a roughened surface formed by a plating film. The maximum height Ry of the unevenness of the roughened layer is preferably 1 to 10 μm.

Next, an interlayer insulating resin layer is provided on the roughened surface of the conductor circuit. Such an interlayer insulating resin layer can be formed using an electroless plating adhesive. Such an adhesive for electroless plating is based on a thermosetting resin, and in particular, heat-resistant resin particles cured, heat-resistant resin particles soluble in an acid or an oxidizing agent, inorganic particles or a fibrous filler, etc. It can be included as needed. When such a resin insulation layer is provided between the lower conductor circuit and the upper conductor circuit, it becomes an interlayer resin insulation layer.

As the thermosetting resin base, epoxy resin, phenol resin, polyimide resin and the like can be used. When a part of the thermosetting group is sensitized, it is preferable that a part of the thermosetting group is acrylated by reacting with methacrylic acid or acrylic acid. Among them, acrylate of epoxy resin is most suitable. As such an epoxy resin, a novolak type epoxy resin, an alicyclic epoxy resin, or the like can be used. Further, a thermoplastic resin such as polyethersulfone, polysulfone, polyphenylenesulfone, polyphenylene sulfide, polyphenylether, and polyetherimide can be added to the thermosetting resin base.

The heat-resistant resin particles include (1) a heat-resistant resin powder having an average particle size of 10 μm or less, and (2) an average particle size of 2 μm.
(3) a mixture of a heat-resistant resin powder having an average particle diameter of 2 to 10 μm or less and a heat-resistant resin powder having an average particle diameter of less than 2 μm; Pseudo particles in which at least one of a heat-resistant resin powder having an average particle diameter of 2 μm or less and an inorganic powder is attached to the surface of a heat-resistant resin powder having a diameter of 2 to 10 μm, (5) the average particle diameter exceeds 0.8.
Heat resistant resin powder of less than 2.0 μm and average particle size of 0.1 to 0.8
mixture with heat-resistant resin powder of μm, and (5) average particle size
It is desirable to use at least one kind of particles selected from the group consisting of heat-resistant resin powders of 0.1 to 1.0 μm. This is because these particles form more complex anchors.
The roughened surface obtained with these particles can have a maximum height (Ry) of 0.1 to 20 μm.

The most suitable heat-resistant resin particles soluble in an acid or an oxidizing agent are those cured with an amino resin (melamine resin, urea resin, guanamine resin) and an epoxy resin (bisphenol-type epoxy resin amine-based curing agent). ), Heat-resistant resin particles composed of a bismaleimide-triazine resin or the like can be used. The mixing ratio of the heat-resistant resin particles is 5 to 50% by weight, preferably 10 to 40% by weight of the solid content of the matrix made of the heat-resistant resin.

The resin insulating layer may have a plurality of layers. For example, the lower layer may be a reinforcing layer composed of inorganic particles or fibrous filler and a resin base, and the upper layer may be an adhesive layer for electroless plating. In addition, the average particle size is 0.1 to 2.0 μm
The lower layer may be formed by dispersing heat-resistant resin particles soluble in an acid or an oxidizing agent in a heat-resistant resin that is hardly soluble in an acid or an oxidizing agent, and the adhesive layer for electroless plating may be an upper layer.

As the inorganic particles, silica, alumina, talc and the like can be used. Examples of the fibrous filler include whiskers of calcium carbonate and whiskers of aluminum borate. At least one of aramid fiber and carbon fiber can be used.

A thin electroless plating film is formed on the entire surface of the interlayer insulating resin provided with the roughened catalyst nuclei. This electroless plating film is preferably formed by electroless copper plating.
The thickness is 5 to 5 μm, more preferably 1 to 3 μm. In addition,
As the electroless copper plating solution, those having a liquid composition adopted in a usual manner can be used. For example, copper sulfate: 29 g / l, sodium carbonate: 25 g / l, EDTA: 140 g / l, sodium hydroxide: 40 g / L, 37% formaldehyde: 150 ml,
(PH = 11.5) is preferred.

Next, a photosensitive resin film (dry film) is laminated on the electroless plating film thus formed by laminating.
And a photomask (preferably a glass substrate) on which a plating resist pattern is drawn on the photosensitive resin film.
Are placed in close contact with each other, exposed, and developed to form a non-conductive portion on which a plating resist pattern is provided.

Next, an electrolytic plating film is formed on a portion other than the non-conductor portion on the electroless copper plating film, and a conductor portion serving as a conductor circuit and a via hole is provided. As the electrolytic plating, it is desirable to use electrolytic copper plating, and its thickness is preferably 5 to 20 μm.

Further, the electroless plating film is removed with a mixed solution of sulfuric acid and hydrogen peroxide or an etching solution such as sodium persulfate, ammonium persulfate, ferric chloride, cupric chloride, etc.
An independent conductor circuit and a via hole having two layers of an electroless plating film and an electrolytic plating film are obtained.

The palladium catalyst nuclei on the roughened surface exposed to the non-conductive portion are dissolved and removed with chromic acid, sulfuric acid and hydrogen peroxide.

The printed circuit board on which the conductor circuit is formed by removing palladium is subjected to a heat treatment. Heat treatment temperature is 50-2
It is preferable to hold at 50 ° C. for 10 minutes or more.
The heat treatment may be held twice or more at different temperatures.

Next, a roughened layer is formed on the surface conductor circuit. Such a roughened layer is formed by plating an alloy composed of copper-nickel-phosphorus, or by spraying an etching solution composed of an aqueous solution of a cupric complex of azoles and an organic acid on the surface of a conductor circuit, or performing such etching. There is a method in which a conductor circuit is immersed in a liquid and formed by bubbling, or a method in which the circuit is formed by other etching, polishing, oxidation, or oxidation-reduction processing. Next, a roughened layer is formed on the surface conductor circuit. The roughened layer to be formed is desirably a roughened layer of copper formed by an etching process, a polishing process, an oxidation process, or an oxidation-reduction process, or a roughened layer formed by a plating film.

Next, a solder-resist layer is formed on the conductor circuit. The thickness of the solder resist layer in the present invention is preferably 5 to 40 μm. If it is too thin, it will not function as a solder dam, and if it is too thick, it will not be easy to open, and it will cause cracks in the solder body due to contact with the solder body. As the solder resist layer, various resins can be used. For example, bisphenol A type epoxy resin, acrylate of bisphenol A type epoxy resin, novolak type epoxy resin, acrylate of novolak type epoxy resin may be used as an amine curing agent or an imidazole curing agent. Can be used. In particular, when an opening is provided in the solder resist layer to form a solder bump, it is preferable that the solder bump be formed of "novolak-type epoxy resin or acrylate of novolak-type epoxy resin" and include "imidazole curing agent" as a curing agent. The solder resist layer having such a configuration has an advantage that migration of lead (a phenomenon in which lead ions diffuse in the solder resist layer) is small. Moreover, this solder resist layer is a resin layer obtained by curing an acrylate of a novolak type epoxy resin with an imidazole curing agent, has excellent heat resistance and alkali resistance, does not deteriorate even at a temperature at which solder is melted (around 200 ° C.), and does not deteriorate. It is not decomposed by a strongly basic plating solution such as plating or gold plating. However, since such a solder resist layer is formed of a resin having a rigid skeleton, peeling is likely to occur. The roughened layer according to the present invention is effective for preventing such peeling.

Here, as the acrylate of the novolak type epoxy resin, an epoxy resin obtained by reacting glycidyl ether of phenol novolak or cresol novolak with acrylic acid or methacrylic acid can be used. The imidazole curing agent is desirably liquid at 25 ° C. This is because a liquid can be uniformly mixed.

As such a liquid imidazole curing agent, 1-benzyl-2-methylimidazole (product name: 1B2MZ
), 1-cyanoethyl-2-ethyl-4-methylimidazole (product name: 2E4MZ-CN), and 4-methyl-2-ethylimidazole (product name: 2E4MZ). The addition amount of the imidazole curing agent is desirably 1 to 10% by weight based on the total solid content of the solder resist composition. The reason for this is that if the added amount is within this range, uniform mixing is easy. In the composition before curing of the solder resist, it is desirable to use a glycol ether-based solvent as a solvent. The solder resist layer using such a composition does not generate free oxygen and does not oxidize the copper pad surface. It is also less harmful to the human body.

As such a glycol ether-based solvent, one having the following structural formula, particularly preferably at least one selected from diethylene glycol dimethyl ether (DMDG) and triethylene glycol dimethyl ether (DMTG) is used. This is because these solvents can completely dissolve benzophenone and Michler's ketone as reaction initiators by heating at about 30 to 50 ° C. CH ₃ O— (CH ₂ CH ₂ O) _n —CH ₃ (n = 1 to 5) The glycol ether solvent is preferably 10 to 40% by weight based on the total weight of the solder resist composition.

The solder resist composition as described above may further include various defoaming agents and leveling agents, thermosetting resins for improving heat resistance and base resistance and imparting flexibility.
A photosensitive monomer or the like can be added to improve the resolution. For example, as the leveling agent, one made of a polymer of an acrylate ester is preferable. The initiator is preferably Irgacure I907 manufactured by Ciba-Geigy, and the photosensitizer is DETX-S manufactured by Nippon Kayaku.

Further, a dye or a pigment may be added to the solder resist composition. This is because the wiring pattern can be hidden. It is desirable to use phthalocyanine green as this dye. As the thermosetting resin as an additional component, a bisphenol-type epoxy resin can be used. This bisphenol type epoxy resin includes a bisphenol A type epoxy resin and a bisphenol F type epoxy resin, and when importance is attached to base resistance, the former is required to reduce viscosity (when importance is attached to coating properties). The latter is better.

As the photosensitive monomer as an additional component, a polyacrylic monomer can be used.
This is because the polyvalent acrylic monomer can improve the resolution. For example, Nippon Kayaku DPE-6
A, polyacrylic monomers such as R-604 manufactured by Kyoeisha Chemical Co., Ltd. are desirable. Further, these solder resist compositions are preferably 0.5 to 10 Pa · s at 25 ° C., more preferably 1 to 10 Pa · s. This is because the viscosity is easy to apply with a roll coater. After the formation of the solder resist, an opening for disposing a BGA for connection to an external semiconductor such as an IC chip is formed. Each opening is formed by exposure and development processing. The opening diameter is in the range of 80 to 150 μm for external electronic components such as IC chips, and is in the range of 100 to 700 μm for BGA arrangement.

Thereafter, a metal layer is formed in the opening after the formation of the solder-resist layer. The metal to be formed is preferably an alloy of at least one of copper, nickel, gold, silver, tin, phosphorus, and aluminum, and is preferably formed in one or more layers.
As an example, a case in which a gold plating layer is applied to a nickel plating layer will be described. First, a nickel plating layer is formed on a conductor circuit by electroless plating. As examples of the composition of the nickel plating solution, nickel sulfate 4.5 g / l, sodium hypophosphite 25 g / l, sodium citrate 40 g / l, boric acid 12 g / l, thiourea 0.1 g / l (PH = 11) There is. The opening and the surface of the solder-resist layer are washed with a degreasing solution, a catalyst such as palladium is applied to a conductor portion exposed to the opening, activated, and then immersed in a plating solution to form a nickel plating layer. . The thickness of the nickel plating layer is 0.5 to 20 μm, preferably 3 to 10 μm. Below this, it is difficult to make a connection between the solder bump and the nickel plating layer. On the other hand, above that, the solder bumps formed in the openings cannot be completely accommodated and are peeled off.

After forming the nickel plating layer, a gold plating layer is formed by gold plating. The thickness is 0.01 to 0.1 μm
And preferably about 0.03 μm.

Through various steps such as a solder bump forming step and a check step for checking conduction, a solder film of 0.5 to 30 μm is formed in the opening of the BGA by printing to obtain a printed wiring board.

[0040]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. First, the configuration of the multilayer printed wiring board 10 according to the first embodiment of the present invention will be described with reference to the cross-sectional view of FIG. As shown in FIG. 6, the multilayer printed wiring board 10
Then, the conductor circuits 34, 3
4 are formed, and further, build-up wiring layers 80A, 80B are formed on the conductor circuits 34, 34. The built-up layers 80A and 80B include an interlayer resin insulation layer 50 having via holes 60 and conductor circuits 58 formed therein, and an interlayer resin insulation layer 150 having via holes 160 and conductor circuits 158 formed therein. A solder resist 70 is formed on the upper layer of the via hole 160 and the conductor circuit 158. In the opening 71 of the solder resist 70, a nickel plating layer 72 and a gold plating layer 74 are formed in the via hole 160 and the conductor circuit 158. , A solder film 75 is formed.

FIG. 7 shows a state in which solder bumps 76U and 76D have been formed on a multilayer printed wiring board in an IC chip mounting process. FIG. 8 shows the solder bumps 76U, 7U.
IC chip 9 is attached to multilayer printed wiring board 10 on which 6D is formed.
0 is attached, and is placed on the daughter board 94.

The multilayer printed wiring board 10 shown in FIG.
Are shipped, first, at a mounting factory, solder balls are transferred to a solder film 75 in an opening 71 of a solder resist 70 as shown in FIG. 7 to form solder bumps 76U and 76D. The solder bumps 76U and 76D can be formed by printing and reflowing a solder paste using a screen mask (metal mask, plastic mask, or the like). Thereafter, as shown in FIG. 8, the IC chip 90 is connected to the multilayer printed wiring board via the solder bumps 76U on the upper surface side of the multilayer printed wiring board 10 and the lands 92 of the IC chip 90. Similarly, the multilayer printed wiring board 10
The multilayer printed wiring board is connected to the daughter board 94 via the lower solder bumps 76D and the lands 96 of the daughter board 94. Here, between the multilayer printed wiring board 10 and the IC chip 90, and between the multilayer printed wiring board 10 and the IC chip 90.
An underfill 88 is filled and resin-sealed between the substrate and the daughter board 94.

In the present embodiment, as shown in FIG. 6, a solder film 75 is formed on the surfaces of the via holes 160 and the conductive circuits 158 via the nickel plating layer 72 and the gold plating layer 74, and the via holes in the opening 71 are formed. 160 and conductor circuit 1
There are 58 anti-rust and protection measures. Therefore, as will be described later, even after a period from completion of the multilayer printed wiring board to mounting of an IC chip (formation of solder bumps), solder bumps are appropriately formed on the surface of the solder film 75. be able to.

FIG. 6 shows an example in which solder films 75 are formed on both the IC chip side and the motherboard side. In addition, as shown in FIG. 10, solder bumps 7 are provided on the IC chip side.
6U may be formed in advance. In this case, since the period until the formation of the solder bump is short, the solder film 75 on the IC chip side is unnecessary. Therefore, the solder film 75 may be formed only on the motherboard side.

The solder bumps 76 and the solder films 75 can be formed by printing the solder paste in the openings 71 of the solder resist 70 on the upper and lower surfaces and then performing reflow. Also, after printing the solder paste in the opening 71 of the solder resist 70 on the upper surface and reflowing to form a solder bump 76U, the opening 71 of the solder resist 70 on the lower surface is formed.
After printing the solder paste to the solder film 75
Can also be formed. Furthermore, the solder bumps 76U and the solder films 75 can be simultaneously formed on both surfaces by flow soldering.

Next, a method of manufacturing the multilayer printed wiring board 10 will be described. Here, first, A. A. used in the method of manufacturing the multilayer printed wiring board of the first embodiment is described. Adhesive for electroless plating, B. Interlayer resin insulation, C.I. Resin filler,
D. The composition of the solder resist raw material composition will be described.

A. Raw material composition for preparation of adhesive for electroless plating (adhesive for upper layer) [Resin composition] 80 wt% of 25% acrylate of cresol novolak type epoxy resin (Nippon Kayaku, molecular weight 2500)
35% by weight of a resin solution dissolved in DMDG at a concentration of 3.15% and a photosensitive monomer (Toa Gosei Co., Aronix M315) 3.15
Parts by weight, 0.5 parts by weight of an antifoaming agent (manufactured by San Nopco, S-65)
3.6 parts by weight of NMP were obtained by stirring and mixing. [Resin composition] Polyether sulfone (PES) 12
Parts by weight, epoxy resin particles (manufactured by Sanyo Chemical Industries, polymer pole) with an average particle size of 1.0 μm, 7.2 parts by weight, average particle size
After mixing 0.59 μm of 3.09 parts by weight,
30 parts by weight of MP was added, and the mixture was stirred and mixed with a bead mill to obtain. [Curing agent composition] Imidazole curing agent (Shikoku Chemicals,
2E4MZ-CN), 2 parts by weight of a photoinitiator (Circa Geigy, Irgacure I-907), 0.2 parts by weight of a photosensitizer (Nippon Kayaku, DETX-S), and 1.5 parts by weight of NMP are stirred and mixed. I got it.

B. Raw material composition for preparing interlayer resin insulation agent (adhesive for lower layer) [Resin composition] 80 wt% of 25% acrylate of cresol novolak type epoxy resin (Nippon Kayaku, molecular weight 2500)
% Of a resin solution dissolved in DMDG at a concentration of 35%, 4 parts by weight of a photosensitive monomer (Alonix M315, manufactured by Toagosei Co., Ltd.), 0.5 parts by weight of an antifoaming agent (S-65, manufactured by San Nopco), N
3.6 parts by weight of MP were obtained by stirring and mixing. [Resin composition] Polyether sulfone (PES) 12
After mixing 14.49 parts by weight of an epoxy resin particle (manufactured by Sanyo Chemical Industries, polymer pole) having an average particle size of 0.5 μm, 30 parts by weight of NMP was further added, and the mixture was stirred and mixed with a bead mill. [Curing agent composition] Imidazole curing agent (Shikoku Chemicals,
2E4MZ-CN), 2 parts by weight of a photoinitiator (Circa Geigy, Irgacure I-907), 0.2 parts by weight of a photosensitizer (Nippon Kayaku, DETX-S), 1.5 parts by weight of NMP I got it.

C. Raw material composition for resin filler preparation [Resin composition] 100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell, molecular weight 310, YL983U), having an average particle diameter of 1.6 μm coated with a silane coupling agent on the surface SiO ₂ spherical particles (Admatech, CRS
1101-CE, where the maximum particle size is 170 parts by weight of the inner layer copper pattern described below (15 μm or less) and 1.5 parts by weight of a leveling agent (manufactured by San Nopco, Perenol S4) by stirring and mixing. The viscosity of the mixture is 23 ±
It was obtained by adjusting to 45,000 to 49,000 cps at 1 ° C. [Curing agent composition] Imidazole curing agent (Shikoku Chemicals,
2E4MZ-CN) 6.5 parts by weight.

D. Raw Material Composition of Solder Resist A 60% by weight cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in DMDG was sensitized with an oligomer (molecular weight 4000) having a 50% epoxy group acrylated.
6.67 g, 15.0 g of 80 wt% bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001) dissolved in methyl ethyl ketone, imidazole curing agent (manufactured by Shikoku Chemicals,
2E4MZ-CN) 1.6 g, photosensitive acrylic monomer (Nippon Kayaku, R604) 3 g, polyvalent acrylic monomer (Kyoeisha Chemical, DPE6A) 1.5 g, dispersion defoamer (Sannopco) , S-65), and 2 g of benzophenone (Kanto Chemical) as a photoinitiator and 0.2 g of Michler's ketone (Kanto Chemical) as a photosensitizer were added to the mixture. 2.0P at 25 ° C
A solder resist composition adjusted to a · s was obtained. The viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL-B type).
Rotor No.4 for 60rpm, rotor for 6rpm
No.3.

Production of Printed Wiring Board (1) A substrate 1 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 1 mm
copper-clad laminate 30 on which copper foil 32 of μm is laminated
A was used as a starting material (step (A) in FIG. 1). First, this copper clad laminate is drilled and subjected to electroless plating.
The inner layer copper pattern 34 and the through-hole 36 were formed on both surfaces of the substrate by etching in a pattern (step (B)).

(2) The substrate 30 on which the inner layer copper pattern 34 and the through hole 36 are formed is washed with water and dried. Then, NaOH (10 g / l) and NaClO _{2 are used} as an oxidation bath (blackening bath).
(40 g / l), Na ₃ PO ₄ (6 g / l), and an oxidation-reduction treatment using NaOH (10 g / l) and NaBH ₄ (6 g / l) as a reducing bath to form the inner layer copper pattern 34 and the through hole. A roughened layer 38 was provided on the surface of Step 36 (Step (C)).

(3) The raw material composition for preparing the resin filler C was mixed and kneaded to obtain a resin filler.

(4) After preparing the resin filler obtained in the above (3),
The coating and filling were performed between the conductor circuits or in the through holes 36 within 24 hours. The coating was performed by a printing method using a squeegee. In the first printing application, the inside of the through hole 36 was mainly filled and dried at 100 ° C. in a drying furnace for 20 minutes. In the second printing application, the recess formed mainly by the formation of the conductor circuit (inner layer copper pattern) 34 is filled, and the resin filler 40 is filled between the conductor circuit 34 and the conductor circuit 34 and in the through hole 36. After that, it was dried under the above-mentioned drying conditions (step (D)).

(5) The surface of the inner layer copper pattern 34 and the through holes 36 are polished on one side of the substrate 30 after the treatment of the above (4) by belt sanding using # 600 belt polishing paper (manufactured by Sankyo Rikagaku). Was polished so that the resin filler did not remain on the surface of the land 36a, and then buffed to remove the scratches caused by the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate (step (E) in FIG. 2). Then at 100 ° C for 1 hour, 1
Heat treatment was performed at 50 ° C. for 1 hour to cure the resin filler 40.

The surface layer of the resin filler 40 filled in the through holes 36 and the like and the inner conductor circuit 3
(4) The roughened layer 38 on the upper surface is removed to smooth both surfaces of the substrate, and the resin filler 40 and the side surfaces of the inner conductor circuit 34 are roughened.
To obtain a wiring board in which the inner wall surface of the through-hole 36 and the resin filler 40 are firmly adhered to each other through the roughened layer 38. That is, by this step, the surface of the resin filler 40 and the surface of the inner layer copper pattern 34 are flush with each other.

(6) The substrate 30 on which the conductor circuit 34 is formed is alkali-degreased and soft-etched, and then treated with a catalyst solution comprising palladium chloride and an organic acid to form Pd.
After applying the catalyst and activating the catalyst, copper sulfate 3.9
× 10 ⁻² mol / l, nickel sulfate 3.8 × 10 ⁻³
mol / l, sodium citrate 7.8 × 10 ⁻³ mo
1 / l, sodium hypophosphite 2.3 × 10 ⁻¹ mol
/ L, surfactant (Surfir 46, manufactured by Nissin Chemical Industry Co., Ltd.)
5) Immersion in an electroless plating solution consisting of 1.1 × 10 ⁻⁴ mol / l, PH = 9, 1 minute after immersion, vertical and horizontal vibrations once every 4 seconds, and A coating layer of a needle-like alloy made of Cu-Ni-P and a roughened layer 42 were provided on the surface of the land of the circuit and the through hole (step (F)). Furthermore, tin borofluoride 0.1 mol / l,
Thiourea 1.0 mol / l, temperature 35 ° C, PH = 1.2
Under the conditions described above, a 0.3 μm thick Sn layer (not shown) was provided on the surface of the roughened layer.

(7) The raw material composition for preparing the interlayer resin insulating agent of B was stirred and mixed, and the viscosity was adjusted to 1.5 Pa · s to obtain an interlayer resin insulating agent (for lower layer). Next, the raw material composition for preparing the adhesive for electroless plating of A was stirred and mixed, and the viscosity was adjusted to 7 Pa · s to obtain an adhesive solution for electroless plating (for the upper layer).

(8) On both surfaces of the substrate 30 of (6),
The interlayer resin insulating agent (for lower layer) 44 having a viscosity of 1.5 Pa · s obtained in (7) was applied by a roll coater within 24 hours after preparation,
After standing for 20 minutes in a horizontal state, drying (prebaking) was performed at 60 ° C. for 30 minutes.
After preparing a Pa · s photosensitive adhesive solution (for upper layer) 46
Apply within 20 hours, leave it horizontal for 20 minutes, then
Drying (prebaking) was performed at 30 ° C. for 30 minutes to form an adhesive layer 50α having a thickness of 35 μm (step (G)).

(9) The substrate 3 on which the adhesive layer was formed in the above (8)
A photomask film 51 having a black circle 51a of 85 μmφ printed thereon is brought into close contact with both sides of
Exposure was performed at 00 mJ / cm ² (step (H)). This is DMT
G solution, and then exposed the substrate to 3000 mJ / cm ² with an ultra-high pressure mercury lamp,
Heat treatment (post-bake) at 120 ° C. for 1 hour and then at 150 ° C. for 3 hours to obtain an 85 μmφ opening (via hole forming opening) 48 with excellent dimensional accuracy equivalent to a photomask film A 35 μm interlayer resin insulating layer (two-layer structure) 50 was formed (step (I) in FIG. 3). Note that a tin plating layer (not shown) was partially exposed in the opening 48 serving as a via hole.

(10) The substrate 30 in which the openings 48 are formed is immersed in chromic acid for 19 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulating layer, thereby forming the interlayer resin insulating layer 50. The surface was roughened, and then immersed in a neutralizing solution (manufactured by Shipley) and then washed with water (step (J)). Further, by applying a palladium catalyst (manufactured by Atotech) to the surface of the substrate subjected to the surface roughening treatment (roughening depth: 6 μm), the catalyst is formed on the surface of the interlayer resin insulating layer 50 and the inner wall surface of the via hole opening 48. Attach a nucleus.

(11) The substrate is immersed in an aqueous electroless copper plating solution having the following composition, and a thickness of 0.6 to 1.2 μm
Was formed (step (K)). [Electroless plating aqueous solution] EDTA 0.08 mol / l Copper sulfate 0.03 mol / l HCHO 0.05 mol / l NaOH 0.05 mol / l α, α'-bipyridyl 80 mg / l PEG 0.10 g / l [Electroless plating conditions] 65 ° C 20 minutes at liquid temperature

(12) A commercially available photosensitive dry film is stuck on the electroless copper plating film 52 formed in the above (11), a mask is placed, and exposure is performed at 100 mJ / cm ² , followed by exposure to 0.8% sodium carbonate. Developed, 15μm thick plating resist 54
Was provided (step (L)).

(13) Next, electrolytic copper plating was applied to the non-resist-forming portion under the following conditions to form an electrolytic copper plating film 56 having a thickness of 15 μm (step (M) in FIG. 4). [Aqueous electrolytic plating solution] Sulfuric acid 2.24 mol / l Copper sulfate 0.26 mol / l Additive (captoside HL, manufactured by Atotech Japan) 19.5 ml / l [Electroplating conditions] Current density 1 A / dm ² hours 65 minutes Temperature 22 ± 2 ° C

(14) After the plating resist 54 is peeled and removed with 5% KOH, it is etched with a mixed solution of sulfuric acid and hydrogen peroxide.
Dissolve and remove the electroless plating film 52 under the plating resist,
A conductor circuit 58 and a via hole 60 each having a thickness of 18 μm (10 to 30 μm) composed of the electroless plating 52 and the electrolytic copper plating film 56 were obtained (step (N)).

Further, the adhesive layer 5 for electroless plating between the conductor circuits 58 was immersed in chromic acid of 80 g / L at 70 ° C. for 3 minutes.
The surface of No. 0 was etched at 1 μm to remove the palladium catalyst on the surface.

(15) The same processing as in (6) is performed, and the conductor circuit 5
A roughened surface 62 made of Cu—Ni—P was formed on the surfaces of the via holes 60 and via holes 60, and the surfaces thereof were further substituted with Sn (step (O)).

(16) By repeating the steps (7) to (14), an upper interlayer resin insulating layer 160, via holes 160 and conductor circuits 158 are further formed. Further, the roughened layer 16 is formed on the surface of the via hole 160 and the conductive circuit 158.
2 is formed (step (P)). Note that, in the step of forming the upper conductive circuit, Sn substitution was not performed.

(17) Then, a solder film is formed on the above-mentioned multilayer printed wiring board. On both surfaces of the substrate 30 obtained in the above (16), the above D.I. Solder resist composition 70 described in
α was applied in a thickness of 20 μm (step (Q) in FIG. 5). Next, after performing a drying process at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a thickness 5 on which a circular pattern (mask pattern) is drawn is formed.
A photomask film (not shown) having a thickness of 1 mm was placed in close contact with the substrate, exposed to ultraviolet light of 1000 mJ / cm ² , and subjected to a DMTG development treatment. And at 80 ° C for 1 hour, at 100 ° C for 1 hour,
Heat treatment at 120 ° C for 1 hour, 150 ° C for 3 hours,
A solder resist layer (thickness: 20 μm) 70 having an opening 71 (opening diameter: 133 μm on the IC chip side, 650 μm on the daughter board side) of the solder pad portion (including the via hole and its land portion) was formed (step (R)).

(18) Then, nickel chloride 2.3 × 10 ⁻¹ m
ol / l, sodium hypophosphite 2.8 × 10 ⁻¹ mol /
l, sodium citrate 1.6 × 10 ⁻¹ mol / l, was immersed in an electroless nickel plating solution having a pH of 4.5 for 20 minutes to form a nickel plating layer 72 having a thickness of 5 μm in the opening 71. . Further, the substrate was washed with 7.6 × 10 ⁻³ mol / l of potassium potassium cyanide and 1.9 × 10 ³ ammonium chloride.
10 ^-1 mol / l, sodium citrate 1.2 × 10 ^-1 m
ol / l, sodium hypophosphite 1.7 × 10 ^-1 mol /
Then, the substrate was immersed in an electroless gold plating solution composed of 1 for 7.5 minutes at 80 ° C. to form a gold plating layer 74 having a thickness of 0.03 μm on the nickel plating layer 72 (step (S)).

(19) Then, a 10 μm solder film 75 was formed on the solder resist opening 71 on the BGA side (the IC chip side and the daughter board side of the substrate) by screen printing (see FIG. 6). Here, first, a mask (not shown) formed with an aperture corresponding to the opening 71 of the solder resist 70 on the motherboard side is placed on the substrate 30, and the solder paste is printed into the opening 71 by printing using a normal method. Then, the substrate is inverted and the solder paste is similarly printed into the opening 71 of the solder resist 70 on the IC chip side. Thereafter, reflow was performed at 200 ° C. As a result, the exposed conductor, that is, the conductor (gold plating layer) 74 formed with the minimum thickness was protected, and the solder film 75 was applied so as not to protrude from the solder resist.
Note that the amount of solder can be adjusted by the thickness and the opening diameter of the screen mask. Thus, the thickness of the solder film 75 can be set to a predetermined thickness.

(20) The substrate was divided and cut into a corresponding size by a device having a router. That is, since the substrates in the above-described process are for multiple-piece production, they were divided into individual multilayer printed wiring boards. Thereafter, a corresponding multilayer printed wiring board was obtained through a checker process for inspecting a short circuit / break of the multilayer printed wiring board. Through the above steps, the printed wiring board 10 having the solder film 75 in the BGA side opening 71 was completed.

Next, a multilayer printed wiring board according to a comparative example configured for performance comparison with the multilayer printed wiring board of this embodiment will be described. Comparative Example 1 The multilayer printed wiring board of Comparative Example 1 was basically the same as the example, except that no solder film was formed in the opening on the BGA side. Other conditions are the same.

As described above, with respect to the printed wiring boards manufactured in Examples and Comparative Example 1, the wettability of the solder in the openings, the deterioration and discoloration of the metal layer, and the occurrence rate of BGA dropping (one week after the manufacture of the printed wiring boards) After 4 months and 6 months, BGA was installed). The printed wiring board according to the manufacturing method of the example has no problem in solder wettability, no deterioration and discoloration of the metal layer does not occur, and a problem occurs even when the BGA is disposed after leaving it for 4 months and 6 months. Did not. On the other hand, in the printed wiring board according to the comparative example, no problem occurred in one week, but when the BGA was disposed after 4 months, a defect occurred at a rate of several percent.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a multilayer printed wiring board according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 4 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 5 is a manufacturing process diagram of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 6 is a sectional view of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view in which solder bumps are formed on the multilayer printed wiring board shown in FIG. 6;

8 is a cross-sectional view showing a state where an IC chip is mounted on the multilayer printed wiring board shown in FIG. 7 and is mounted on a daughter board.

FIG. 9 is a table showing the results of testing the multilayer printed wiring boards according to the first embodiment and the first comparative example.

FIG. 10 is a cross-sectional view of a multilayer printed wiring board according to a modification of the first embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 30 core substrate 34 conductive circuit 36 through hole 50 interlayer resin insulating layer 58 conductive circuit 60 via hole 70 solder resist 72 nickel plating layer (metal layer) 74 gold plating layer (metal layer) 75 solder film 76U, 76D solder bump 71 opening 150 interlayer resin insulation layer 158 conductive circuit 162 roughened layer (roughened surface)

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E343 AA02 AA12 AA17 AA18 AA23 AA36 BB03 BB23 BB24 BB25 BB34 BB44 BB52 BB72 DD03 DD14 DD20 DD33 DD34 DD43 DD44 DD47 DD76 EE02 EE33 EE43 ER02 ER18 A02 ER18 ER18 ER18 A02 ER18 CC09 CC10 CC16 CC32 CC33 CC37 CC38 CC39 CC54 CC55 DD03 DD13 DD23 DD24 DD25 DD33 EE21 EE31 FF07 FF15 GG16 GG17 GG22 GG23 GG25 GG27 GG28 HH07 HH40

Claims (9)

[Claims] 1. A printed wiring board in which a solder resist layer is formed by providing an opening for exposing at least a part of a conductive circuit on a substrate on which a conductive circuit serving as an electrode for external connection is provided. A printed wiring board characterized in that a metal layer is applied to the conductor circuit of (1) and a solder film is formed. 2. The printed wiring board according to claim 1, wherein two or more metal layers are formed as the metal layer provided on the conductor circuit. 3. The method according to claim 1, wherein one of the metal layers comprises Cu, Ni,
The printed wiring board according to claim 2, wherein the printed wiring board is at least one of Au, Ag, Sn, P, and Al. 4. The printed wiring board according to claim 1, wherein the solder film is formed in a range of 0.1 to 30 μm. 5. The solder layer according to claim 1, wherein a mixing ratio of Pd is 30 to
The printed wiring board according to any one of claims 1 to 4, wherein the ratio is 90%. 6. The solder layer is made of SnAg, SnAgC.
The printed wiring board according to any one of claims 1 to 4, wherein the printed wiring board is one of u and SnCu. 7. On a substrate on which a conductor circuit serving as an electrode for connecting an IC chip is disposed on an upper surface and a conductor circuit serving as an electrode for connection to an external substrate is disposed on a lower surface, In a printed wiring board provided with an opening for exposing at least a part of the lower-side conductive circuit and forming a solder resist layer, a solder bump is formed on the conductive circuit in the upper-side opening,
A printed circuit board, wherein a metal layer is applied to a conductor circuit in the opening on the lower surface side to form a solder film. 8. A method for manufacturing a printed wiring board, comprising at least the following steps (a) to (c):
(A) forming a solder resist layer by providing an opening for exposing at least a part of the conductor circuit on a substrate on which a conductor circuit serving as an electrode for external connection is disposed; (b) providing a conductor in the opening A step of applying a metal layer to the circuit; and (c) a step of forming a solder film. 9. The method according to claim 6, wherein the solder film is formed by plating.