JP2000101246A - Multilayer built-up wiring board and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer built-up wiring board by which the number of built-up layers can be reduced. SOLUTION: Via holes 60 are formed in such a way that they cover a passing hole 16 of a through hole 36 formed in a core board 30. By using an area directly above the through hole 36 as an inner layer pad, there is no more dead space and the shape of a land 36a of the through hole 36 can be a perfect circle. As a result, arranging density of through holes formed in the multilayer core board is improved and wires can be integrated at the same pace between a built-up wiring layer 80A formed on the surface of the core board and a built-up wiring layer 80B formed on the reverse side. Accordingly, the number of layers can be minimized by equalizing the number of layers between the upper multilayer wiring layer and the lower multilayer wiring layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer build-up wiring board, and more particularly to a multilayer build-up wiring board in which a build-up wiring layer in which interlayer resin insulating layers and conductor layers are alternately laminated is formed on the upper surface of a core substrate. The present invention relates to a build-up wiring board.

[0002]

2. Description of the Related Art As shown in FIG.
A multilayer build-up wiring board 210 constituting a package board for mounting the “0” is formed by alternately building up interlayer resin insulation layers 250 and 350 and conductor layers 258 and 358 on a core board 230 having a through hole 236 formed therein. A bump 276U for connection to the IC chip 290 is provided on the upper surface, and a bump 27 for connecting to the motherboard is provided on the lower surface.
It is formed by disposing 6D. The connection between the upper and lower conductor layers is performed by forming via holes 260 and 360, and the via hole 260 on the IC chip 290 side of the core substrate 230 and the via hole 260 on the motherboard side are connected via through holes 236. Connection has been established. That is, the multilayer build-up wiring board 21
0, ie, the surface of the core substrate 230 of FIG.
As shown in FIG.
The inner layer pad 236b for connecting a via hole to the upper layer is added to the land 236a of No. 6, and the via hole 260 is connected to the inner layer pad 236b.

[0003]

However, FIG.
In the land shape of the prior art shown in FIG.
In order to maintain the mutual insulation between the 36b, the interval between the through holes becomes large, and this limits the number of through holes formed in the core substrate.

On the other hand, on the package substrate, more bumps are formed on the front surface than on the rear surface. This is because the wiring from the plurality of bumps on the front surface is connected to the bumps on the back surface while being integrated. For example, the number of power supply lines required to have a lower resistance than the signal lines was 20 at the bumps (IC chip side) on the front surface, but was integrated into one at the back surface (motherboard side). Is done.

Here, the fact that the wiring can be integrated at the same pace between the build-up wiring layer formed on the front side of the core substrate and the build-up wiring layer formed on the back side of the core substrate requires the upper build-up wiring layer and the lower build-up wiring layer. It is desirable to make the number of layers equal to the build-up wiring layer, that is, to minimize the number of layers. However, as described above, the number of through holes that can be formed in the multilayer core substrate is limited. For this reason, in the conventional package substrate, the wiring is integrated to some extent in the front build-up wiring layer, and then connected to the back build-up wiring layer through the through hole of the multilayer core substrate. That is, since the wiring density is lower in the back side build-up wiring layer, the same number of layers as the front side build-up wiring layer is not originally required. However, if the number of build-up wiring layers on the front and back is made different, warpage occurs due to asymmetry, so the number of layers on the front and back is made the same. That is, since the number of through holes formed in the multilayer core substrate is limited, the number of layers of the build-up wiring layer on the front side must be increased, and the number of layers is equal to the number of layers on the front side with the increased number of layers. A build-up wiring layer on the back side had to be formed.

That is, in the conventional multilayer build-up wiring board (package board), the number of build-up layers is increased, so that the reliability of connection between upper and lower layers is reduced and the cost of the package board is increased. In addition, there has been a problem that the size, thickness and weight of the package substrate become unnecessarily large.

Further, even when the build-up multilayer wiring layer is provided on one side of the core substrate, it is necessary to ensure the degree of freedom in wiring design on the back surface of the surface on which the build-up layer is formed.

Further, the connection between the through hole 236 and the via hole 260 is made as described above by the inner pad 236b.
, The wiring length in the multilayer build-up wiring board becomes longer, the signal transmission speed becomes slower, and the IC
It has been difficult to meet the demand for high-speed chips.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object of the present invention is to provide a multilayer build-up wiring board capable of reducing the number of build-up layers.

It is another object of the present invention to provide a multilayer build-up wiring board that can reduce the internal wiring length.

[0011]

According to a first aspect of the present invention, there is provided a multilayer build-up wiring board in which interlayer resin insulating layers and conductive layers are alternately laminated, and each conductive layer is formed by a via hole. In a multilayer build-up wiring board in which connected build-up wiring layers are formed on both sides of a core substrate, a via hole is formed so as to close a through-hole formed in the core substrate. Characteristic.

A second aspect of the present invention is characterized in that, in the first aspect, the through hole has a diameter of 200 μm or less.

[0013] A method of manufacturing a multilayer build-up wiring board according to a third aspect is characterized by including at least the following steps (1) to (4). (1) a step of forming a through hole having a diameter of 200 μm or less in a core substrate by a laser; (2) a step of plating the inside of the through hole to form a through hole; and (3) a step of forming a through hole in the core substrate. A step of forming an interlayer resin insulating layer having an opening, and (4) a step of forming a via hole so as to close the through hole by plating the opening of the interlayer resin insulating layer.

In the method for manufacturing a multilayer build-up wiring board according to the first aspect and the multilayer build-up wiring board according to the third aspect, a via hole is formed so as to close a through-hole formed in the core substrate, and the through-hole is formed. By making the area directly above function as an inner layer pad, there is no dead space, and since there is no need to wire the inner layer pad to connect from the through hole to the via hole, the land shape of the through hole can be a perfect circle. it can. As a result, the arrangement density of the through holes provided in the multilayer core substrate is improved, and the wiring can be integrated at the same pace between the multilayer wiring layer formed on the front side of the core substrate and the multilayer wiring layer formed on the back side of the core substrate. Therefore, the number of layers can be minimized by making the number of layers of the upper multilayer wiring layer equal to that of the lower multilayer wiring layer. In addition, since the via hole is provided immediately above the through hole, the wiring length can be reduced, and the signal transmission speed can be increased.

In the method for manufacturing a multilayer build-up wiring board according to claim 2 and the method for manufacturing a multilayer build-up wiring board according to claim 3, since the through hole has a diameter of 200 μm or less, the via hole is formed so as to close the through hole. Even if the via hole is formed, the via hole does not become too large, and the wiring density in the interlayer resin insulating layer where the via hole is formed does not decrease.

In the present invention, it is desirable to use an adhesive for electroless plating as the interlayer resin insulating layer. The most suitable adhesive for electroless plating is one in which heat-resistant resin particles soluble in a cured acid or oxidizing agent are dispersed in an uncured heat-resistant resin hardly soluble in an acid or oxidizing agent. is there. By treating with an acid or an oxidizing agent, the heat-resistant resin particles are dissolved and removed, and a roughened surface composed of an octopus-shaped anchor can be formed on the surface.

In the above-mentioned adhesive for electroless plating, the heat-resistant resin particles which have been particularly hardened include a heat-resistant resin powder having an average particle diameter of 10 μm or less, and an average particle diameter of 2 μm.
Aggregated particles obtained by aggregating the following heat-resistant resin powder, a heat-resistant powder resin powder having an average particle size of 2 to 10 μm and an average particle size of 2 μm
m and a mixture with a heat-resistant resin powder having a mean particle size of 2 or less.
Pseudo particles obtained by adhering at least one of a heat-resistant resin powder or an inorganic powder having an average particle diameter of 2 μm or less to the surface of a 10 μm heat-resistant resin powder, and an average particle diameter of 0.1 to
0.8μm heat resistant resin powder and average particle size 0.8μ
m, and a mixture with a heat-resistant resin powder of less than 2 μm,
It is desirable to use a heat-resistant resin powder having an average particle size of 0.1 to 1.0 μm. This is because they can form more complex anchors.

The depth of the roughened surface is Rmax = 0.01 to 2
0 μm is preferred. This is to ensure adhesion. Particularly, in the semi-additive method, the thickness is preferably 0.1 to 5 μm. This is because the electroless plating film can be removed while ensuring adhesion.

The heat-resistant resin hardly soluble in an acid or an oxidizing agent is selected from a “resin composite composed of a thermosetting resin and a thermoplastic resin” or a “resin composite composed of a photosensitive resin and a thermoplastic resin”. It is desirable to become. This is because the former has high heat resistance, and the latter can form an opening for a via hole by photolithography.

As the thermosetting resin, epoxy resin, phenol resin, polyimide resin and the like can be used. In the case of photosensitization, methacrylic acid, acrylic acid, or the like is subjected to an acrylate reaction with a thermosetting group. Particularly, acrylate of epoxy resin is most suitable. As the epoxy resin, a novolak type epoxy resin such as a phenol novolak type and a cresol novolak type, and an alicyclic epoxy resin modified with dicyclopentadiene can be used.

As the thermoplastic resin, polyether sulfone (PES), polysulfone (PSF), polyphenylene sulfone (PPS), polyphenylene sulfide (PPES), polyphenyl ether (PP
E), polyetherimide (PI) and the like can be used.
The mixing ratio of the thermosetting resin (photosensitive resin) and the thermoplastic resin is: thermosetting resin (photosensitive resin) / thermoplastic resin = 95
/ 5 to 50/50 is preferred. This is because a high toughness value can be secured without impairing the heat resistance.

The mixing weight ratio of the heat-resistant resin particles is 5 to 50% by weight based on the solid content of the heat-resistant resin matrix.
Desirably, the content is 10 to 40% by weight. As the heat-resistant resin particles, amino resin (melamine resin, urea resin, guanamine resin), epoxy resin and the like are preferable. The adhesive may be composed of two layers having different compositions.

As the solder resist layer to be added to the surface of the multilayer build-up wiring board, various resins can be used. For example, bisphenol A type epoxy resin, acrylate of bisphenol A type epoxy resin, novolak type epoxy resin, novolak A resin obtained by curing an acrylate of a type epoxy resin with an amine curing agent or an imidazole curing agent can be used.

On the other hand, such a solder resist layer
Since it is composed of a resin having a rigid skeleton, peeling may occur. Therefore, the provision of the reinforcing layer can also prevent the solder resist layer from peeling off.

Here, as the acrylate of the novolak type epoxy resin, an epoxy resin obtained by reacting glycidyl ether of phenol novolak or cresol novolak with acrylic acid, methacrylic acid or the like can be used.

The above imidazole curing agent is desirably liquid at 25 ° C. This is because a liquid can be uniformly mixed. As such a liquid imidazole curing agent,
1-benzyl-2-methylimidazole (product name: 1B2MZ),
1-cyanoethyl-2-ethyl-4-methylimidazole (product name: 2E4MZ-CN) and 4-methyl-2-ethylimidazole (product name: 2E4MZ) can be used.

The amount of the imidazole curing agent to be added is desirably 1 to 10% by weight based on the total solid content of the solder resist composition. The reason for this is that if the added amount is within this range, uniform mixing is easy.

The composition before curing of the solder resist is as follows:
It is desirable to use a glycol ether-based solvent as the solvent. The solder resist layer using such a composition does not generate free acid and does not oxidize the copper pad surface. It is also less harmful to the human body.

As such a glycol ether-based solvent, one having the following structural formula, particularly preferably at least one selected from diethylene glycol dimethyl ether (DMDG) and triethylene glycol dimethyl ether (DMTG) is used. This is because these solvents can completely dissolve benzophenone and Michler's ketone as reaction initiators by heating at about 30 to 50 ° C. CH ₃ O— (CH ₂ CH ₂ O) _n —CH ₃ (n = 1 to 5) The amount of the glycol ether solvent is preferably 10 to 70% by weight based on the total weight of the solder resist composition.

The solder resist composition described above may further include various defoamers and leveling agents, thermosetting resins for improving heat resistance and base resistance and imparting flexibility.
A photosensitive monomer or the like can be added to improve the resolution. For example, as the leveling agent, one made of a polymer of an acrylate ester is preferable. The initiator is preferably Irgacure I907 manufactured by Ciba-Geigy, and the photosensitizer is DETX-S manufactured by Nippon Kayaku. further,
A dye or pigment may be added to the solder resist composition. This is because the wiring pattern can be hidden. It is desirable to use phthalocyanine green as this dye.

As the thermosetting resin as an additional component, a bisphenol-type epoxy resin can be used. This bisphenol type epoxy resin includes a bisphenol A type epoxy resin and a bisphenol F type epoxy resin, and when importance is attached to base resistance, the former is required to reduce viscosity (when importance is attached to coating properties). The latter is better.

As the above-mentioned photosensitive monomer as an additional component, a polyvalent acrylic monomer can be used.
This is because the polyvalent acrylic monomer can improve the resolution. For example, Nippon Kayaku's DPE-6A and Kyoeisha Chemical's R-
604 can be used. Further, these solder resist compositions are preferably 0.5 to 10 Pa · s at 25 ° C., more preferably 1 to 10 Pa · s. This is because the viscosity is easy to apply with a roll coater.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a multilayer build-up wiring board according to an embodiment of the present invention and a method of manufacturing the same will be described with reference to the drawings. First, the configuration of the multilayer build-up wiring board 10 according to the first embodiment of the present invention will be described with reference to FIG. 5 (R), FIG. 5 (S) and FIG. FIG. 5 (R)
FIG. 6 shows a state before the IC chip is mounted on the multilayer build-up wiring board, and FIG. 6 shows a state where the IC chip 90 is mounted on the multilayer build-up wiring board 10 and mounted on the daughter board 94. On the other hand, FIG.
The land 36a of the through hole 36 formed on the surface of the core substrate 30 of the multilayer build-up wiring board 10 in the middle, that is, the SS cross section of FIG. 5 (R) is shown.

As shown in FIG. 5 (R), in the multilayer build-up wiring board 10, the build-up wiring layers 80A and 80B are formed on the front and back surfaces of the core substrate 30. The built-up layer 80A includes the via hole 60 and the conductive circuit 5.
8 and the via hole 1
60 and interlayer resin insulation layer 1 on which conductor circuit 158 is formed
50. Also, the build-up wiring layer 80B
The interlayer resin insulation layer 50 having the via hole 60 and the conductor circuit 58 formed thereon, and the via hole 160 and the conductor circuit 15
8 is formed.

As shown in FIG. 6, on the upper surface side of the multilayer build-up wiring board 10, solder bumps 76U for connection to the lands 92 of the IC chip 90 are provided. The solder bump 76U is connected to the via hole 160 and the via hole 60.
Is connected to the through-hole 36 via the. On the other hand, a solder bump 76D for connection to the land 96 of the daughter board 94 is provided on the lower surface side. The solder bump 76D is connected to the via hole 160 and the via hole 60.
Is connected to the through-hole 36 via the.

In the present embodiment, since the via hole 60 is formed immediately above the through hole 36, the wiring length in the multilayer build-up wiring board is minimized, and it is possible to cope with an increase in the speed of an IC chip.

The diameter D of the through hole 16 of the through hole 36
Is formed to have a thickness of 100 to 200 μm. In the multilayer build-up wiring board 10, the via holes 6 are formed so as to close the through holes 16 of the through holes 36 formed in the core substrate 30.
0 is formed, and the area immediately above the through hole 36 functions as an inner layer pad, thereby eliminating dead space. In addition, there is no need to wire an inner layer pad for connecting the through hole 36 to the via hole 60, so that
As shown in FIG. 5 (S), the land 36 of the through hole 36 is formed.
The shape of a can be a perfect circle. As a result, the arrangement density of the through holes 36 provided in the multilayer core substrate 30 is improved, and the build-up wiring layer 80A formed on the front side of the core substrate and the build-up wiring layer 8 formed on the back side of the core substrate are improved.
Since the wiring can be integrated at the same pace at 0B, the number of layers can be minimized by equalizing the number of layers in the upper multilayer wiring layer and the lower multilayer wiring layer. In the present embodiment, 20% to 50% of the bottom surface of the via hole 60 is
Sufficient electrical connection can be achieved by contacting the land 36a of the through hole 36.

Hereinafter, a method for manufacturing a multilayer build-up wiring board according to an embodiment of the present invention will be described with reference to the drawings. Here, A.E. used in the method for manufacturing a multilayer build-up wiring board of the first embodiment is described. Adhesive for electroless plating,
B. Interlayer resin insulation, C.I. Resin filler, D.I. The composition of the solder resist composition will be described.

A. Raw material composition for preparation of adhesive for electroless plating (adhesive for upper layer) [Resin composition] 80 wt% of 25% acrylate of cresol novolak type epoxy resin (Nippon Kayaku, molecular weight 2500)
35% by weight of a resin solution dissolved in DMDG at a concentration of 3.15% and a photosensitive monomer (Toa Gosei Co., Aronix M315) 3.15
Parts by weight, 0.5 parts by weight of an antifoaming agent (manufactured by San Nopco, S-65)
3.6 parts by weight of NMP were obtained by stirring and mixing.

[Resin composition] 12 parts by weight of polyether sulfone (PES), epoxy resin particles (manufactured by Sanyo Chemical Co., Ltd.)
After mixing 7.2 parts by weight of a polymer pole having an average particle size of 1.0 μm and 3.09 parts by weight of a polymer pole having an average particle size of 0.5 μm, 30 parts by weight of NMP was further added, followed by stirring and mixing with a bead mill.

[Curing agent composition] 2 parts by weight of imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), 2 parts by weight of photoinitiator (Irgacure I-907, manufactured by Ciba Geigy), photosensitizer (manufactured by Nippon Kayaku) , DETX-S) 0.2 parts by weight and NMP 1.5 parts by weight.

B. Raw material composition for preparing interlayer resin insulation agent (adhesive for lower layer) [Resin composition] 80 wt% of 25% acrylate of cresol novolak type epoxy resin (Nippon Kayaku, molecular weight 2500)
% Of a resin solution dissolved in DMDG at a concentration of 35%, 4 parts by weight of a photosensitive monomer (Alonix M315, manufactured by Toagosei Co., Ltd.), 0.5 parts by weight of an antifoaming agent (S-65, manufactured by San Nopco), N
3.6 parts by weight of MP were obtained by stirring and mixing.

[Resin Composition] 12 parts by weight of polyether sulfone (PES), epoxy resin particles (manufactured by Sanyo Chemical Industries, Ltd.)
After mixing 14.49 parts by weight of a polymer pole having an average particle size of 0.5 μm, 30 parts by weight of NMP were further added,
It was obtained by stirring and mixing with a bead mill.

[Curing Agent Composition] 2 parts by weight of an imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), 2 parts by weight of a photoinitiator (Irgacure I-907, manufactured by Ciba Geigy), and a photosensitizer (manufactured by Nippon Kayaku) , DETX-S) 0.2 parts by weight and NMP 1.5 parts by weight with stirring.

C. Raw material composition for resin filler preparation [Resin composition] 100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell, molecular weight 310, YL983U), having an average particle diameter of 1.6 μm coated with a silane coupling agent on the surface SiO ₂ spherical particles (Admatech, CRS 11
01-CE, where the maximum particle size is 170 parts by weight of the inner layer copper pattern described below (15 μm or less) and 1.5 parts by weight of a leveling agent (manufactured by San Nopco, Perenol S4) by stirring and mixing. The viscosity of the mixture is 23 ± 1
The temperature was adjusted to 45,000-49,000 cps at ℃. [Curing agent composition] Imidazole curing agent (Shikoku Chemicals,
2E4MZ-CN) 6.5 parts by weight.

D. Solder resist composition 60% by weight of cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in DMDG was sensitized with 50% of epoxy groups of acrylated oligomer (molecular weight 4000).
6.67 g, 15.0 g of 80 wt% bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001) dissolved in methyl ethyl ketone, imidazole curing agent (manufactured by Shikoku Chemicals,
2E4MZ-CN) 1.6 g, photosensitive acrylic monomer (Nippon Kayaku, R604) 3 g, polyvalent acrylic monomer (Kyoeisha Chemical, DPE6A) 1.5 g, dispersion defoamer (Sannopco) , S-65), and 2 g of benzophenone (Kanto Chemical) as a photoinitiator and 0.2 g of Michler's ketone (Kanto Chemical) as a photosensitizer were added to the mixture. 2.0P at 25 ° C
A solder resist composition adjusted to a · s was obtained. The viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL-B type).
Rotor No.4 for 60rpm, rotor for 6rpm
No.3.

Next, a manufacturing process of the multilayer build-up wiring board according to the first embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. In the first embodiment, a multilayer build-up wiring board is formed by a semi-additive method.

(1) As shown in FIG. 1A, an 18 μm copper foil 1 is formed on both surfaces of a substrate 30 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 1 mm.
2 was used as a starting material. First, a through hole 16 for forming a through hole is opened in the copper-clad laminate 30A by laser application (FIG. 1).
(B)).

As the laser beam machine, a carbon dioxide laser beam machine, a UV laser beam machine, an excimer laser beam machine or the like can be used. The diameter D of the through hole 16 is preferably 100 to 200 μm. Here, the carbon dioxide laser processing machine is most suitable for industrial use because it has a high processing speed and can be processed at low cost, and is the most desirable laser processing machine for the present invention. That is, when the through hole is formed by drilling, the hole diameter D is at least 300 μm, and the via hole 60 is formed so as to cover the through hole 16 in the embodiment described above with reference to FIG. When the via hole 60 is formed, the diameter of the via hole 60 becomes large, and the density of the via hole 60 and the conductor wiring 58 formed in the interlayer resin insulating layer 50 must be reduced.
For this reason, in the present embodiment, the diameter of the through hole 16 is suppressed to 200 μm or less using a laser, thereby preventing a decrease in the wiring density on the interlayer resin insulating layer 50 side. Here, the reason why the pore diameter is set to 100 μm or more is that 100 μm
This is because it is difficult to form through holes having the following diameters even by laser processing. Note that, here, 200
Although a through hole having a diameter of not more than μm is formed, a wiring length can be shortened by forming a through hole having a thickness of 300 μm by drilling and forming a via hole so as to cover the through hole as in the related art.

(2) Subsequently, the core substrate 30 is subjected to electroless plating to form a plating film 18 on the inner wall of the through hole 16 (see FIG. 1C).

(3) Next, the copper foil 12 of the core substrate 30 is etched into a pattern to form a through hole 36 and a conductor circuit (inner layer copper pattern) 34 (FIG. 1D).
reference).

(4) The substrate 30 on which the inner layer copper pattern 34 and the through hole 36 are formed is washed with water and dried, and then used as an oxidation bath (blackening bath) as NaOH (10 g / l) and NaClO.
₂ (40 g / l), Na ₃ PO ₄ (6 g / l), and NaOH (10 g / l) and NaBH ₄ (6 g / l) as a reducing bath were subjected to oxidation-reduction treatment to form the inner layer copper pattern 34 and the through-hole. A roughened layer 38 was provided on the surface of the hole 36 (see FIG. 1E).

(5) The raw material composition for preparing the resin filler C was mixed and kneaded to obtain a resin filler.

(6) By applying the resin filler 28 obtained in the above (5) to both surfaces of the substrate 30 using a roll coater within 24 hours after the preparation, the conductor circuit (inner layer copper pattern) 3
4 and the conductor circuit 34 and in the through-hole 36, and dried at 70 ° C. for 20 minutes. The resin filler 28 is similarly filled on the other surface between the conductor circuit 34 and the through-hole 36. And dried by heating at 70 ° C. for 20 minutes (see FIG. 2 (F)).

(7) One surface of the substrate 30 after the processing of (6) is sanded by a belt sander using # 600 belt abrasive paper (manufactured by Sankyo Rikagaku) to form the surface of the inner layer copper pattern 34 and the through holes 36. Filler 2 on the surface of land 36a
Polishing was performed so that No. 8 did not remain, and then buffing was performed to remove scratches due to the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate (see FIG. 2G). Then at 100 ° C for 1 hour,
Heat treatment was performed at 120 ° C. for 3 hours, 150 ° C. for 1 hour, and 180 ° C. for 7 hours to cure the resin filler 28.

Thus, the surface portion of the resin filler 28 filled in the through holes 36 and the like and the inner conductor circuit 3
4 After removing the roughened layer 38 on the upper surface and smoothing both surfaces of the substrate 30, the resin filler 28 and the side surface of the inner conductor circuit 34 are firmly adhered to each other through the roughened layer 38, and the through hole 3 is formed.
6, a wiring board in which the inner wall surface and the resin filler 28 were firmly adhered to each other via the roughened layer 38 was obtained. That is, by this process,
The surface of the resin filler 28 and the surface of the inner layer copper pattern 34 are flush with each other.

(8) The substrate 30 on which the conductor circuit 34 is formed is alkali-degreased and soft-etched, and then treated with a catalyst solution comprising palladium chloride and an organic acid to form Pd
After applying a catalyst and activating the catalyst, copper sulfate 3.2
× 10 ^-2 mol / l, nickel sulfate 3.9 × 10 ^-3 mo
1 / l, complexing agent 5.4 × 10 ^-2 mol / l, sodium hypophosphite 3.3 × 10 ^-1 mol / l, boric acid 5.0 ×
10 ^-1 mol / l, 0.1 g / l of surfactant (Surfir 465, manufactured by Nissin Chemical Co., Ltd.), immersion in an electroless plating solution consisting of PH = 9, 1 minute after immersion, 1 By vibrating vertically and horizontally at times, Cu-Ni- is formed on the surface of the land 36a of the conductor circuit 34 and the through hole 36.
A coating layer of a needle-shaped alloy made of P and a roughened layer 29 were provided (see FIG. 2H).

Further, tin borofluoride 0.1 mol /
1, thiourea 1.0 mol / l, temperature 35 ° C., PH =
A Cu—Sn substitution reaction was performed under the conditions of 1.2, and a 0.3 μm-thick Sn layer (not shown) was provided on the surface of the roughened layer.

(9) The raw material composition for preparing the interlayer resin insulating agent of B was stirred and mixed, and the viscosity was adjusted to 1.5 Pa · s to obtain an interlayer resin insulating agent (for lower layer). (10) Next, the raw material composition for preparing the adhesive for electroless plating of A was stirred and mixed, and the viscosity was 7 Pa ·
s to obtain an adhesive solution for electroless plating (for upper layer).

(11) The interlayer resin insulating material (for lower layer) having a viscosity of 1.5 Pa · s obtained in the above (9) is provided on both surfaces of the substrate of the above (8).
4 was coated with a roll coater within 24 hours after preparation, allowed to stand in a horizontal state for 20 minutes, dried at 60 ° C. for 30 minutes (prebaked), and then obtained with the viscosity of 7 Pa · s
Of the photosensitive adhesive solution (for upper layer) 46 is applied within 24 hours after preparation, and left in a horizontal state for 20 minutes.
Then, the adhesive layer 50α having a thickness of 35 μm was formed (see FIG. 2 (I)).

(12) The substrate 3 on which the adhesive layer was formed in the above (11)
A photomask film (not shown) on which a black circle of 85 μmφ (not shown) was printed was brought into close contact with both sides of the “0”, and was exposed at 500 mJ / cm ² by an ultra-high pressure mercury lamp. This is spray-developed with a DMTG solution, and the substrate 30 is exposed at 3000 mJ / cm ² using an ultra-high pressure mercury lamp.
A heat treatment (post-bake) at 0 ° C. for 1 hour and then at 150 ° C. for 3 hours has a thickness having an opening (via hole forming opening) 48 μmφ with excellent dimensional accuracy equivalent to a photomask film. A 35 μm interlayer resin insulating layer (two-layer structure) 50 was formed (see FIG. 3 (J)). Note that a tin plating layer (not shown) was partially exposed in the opening 48 serving as a via hole.

(13) The substrate 30 in which the openings 48 are formed is immersed in chromic acid for 19 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulating layer 50, thereby obtaining the interlayer resin insulating layer 50. Was roughened (see FIG. 3 (K)), and then immersed in a neutralizing solution (manufactured by Shipley) and then washed with water.

(14) By applying a palladium catalyst (manufactured by Atotech) to the surface of the substrate 30 whose surface has been roughened in the step (13), a catalyst nucleus is provided on the surface of the interlayer resin insulating layer 50. Thereafter, the substrate 30 was immersed in an aqueous electroless copper plating solution having the above composition to form an electroless copper plating film 52 having a thickness of 0.6 μm as a whole (FIG. 3 (L)). [Electroless plating aqueous solution] EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l [Electroless plating conditions] 70 ° C. 30 minutes at liquid temperature

(15) A commercially available photosensitive dry film is stuck on the electroless copper plating film 52 formed in the above (14), a mask is placed thereon, and exposure is performed at 100 mJ / cm ² , followed by exposure to 0.8% sodium carbonate. After development, a plating resist 54 having a thickness of 15 μm was provided (see FIG. 3 (M)).

(16) Next, electrolytic copper plating was applied to the non-resist-formed portion under the following conditions to form an electrolytic copper plating film 56 having a thickness of 15 μm (see FIG. 4 (N)). [Aqueous electrolytic plating solution] Sulfuric acid 180 g / l Copper sulfate 80 g / l Additive (Captoside GL, manufactured by Atotech Japan) 1 ml / l [Electroplating conditions] Current density 1 A / dm ² hours 30 minutes Temperature Room temperature

(17) After the plating resist 54 is peeled off with 5% KOH, the electroless plating film 52 under the plating resist is dissolved and removed by etching treatment with a mixed solution of sulfuric acid and hydrogen peroxide to remove the electroless copper. Plating film 52 and electrolytic copper plating film 5
6 and 18 μm thick conductive circuits 58 and via holes 60 were formed (FIG. 4 (O)).

(18) The same processing as in (8) is performed, and the conductor circuit 5
A roughened surface 62 made of Cu-Ni-P was formed on the surface of each of the via holes 60 and the via holes 60, and the surface was further substituted with Sn (see FIG. 4 (P)).

(19) By repeating the steps (9) to (17), an interlayer resin insulating layer 160 as an upper layer, a via hole 160 and a conductor circuit 158 are further formed. Further, the roughened layer 16 is formed on the surface of the via hole 160 and the conductive circuit 158.
2 to complete a multilayer build-up wiring board (FIG. 4).
(Q)). Note that, in the step of forming the upper conductive circuit, Sn substitution was not performed.

(20) Then, solder bumps are formed on the above-mentioned multilayer build-up wiring board. On both surfaces of the substrate 30 obtained in the above (19), Is applied in a thickness of 45 μm. Then at 70 ° C for 20
After performing a drying process at 70 ° C. for 30 minutes, a 5 mm-thick photomask film (not shown) on which a circular pattern (mask pattern) is drawn is placed in close contact with the substrate, and is placed at 1000 mJ /
Exposure to UV light of cm ² and DMTG development. And at 80 ° C for 1 hour, at 100 ° C for 1 hour, at 120 ° C for 1 hour,
Heat treatment is performed at 150 ° C. for 3 hours to form a solder resist layer (thickness: 20 μm) having openings (opening diameter: 200 μm) 71 in solder pad portions (including via holes and land portions thereof).
μm) 70 (see FIG. 5 (R)).

(21) Next, 2.31 × 10 ^-1 mol of nickel chloride
/ L, sodium hypophosphite 2.8 × 10 ^-1 mol / l, sodium citrate 1.85 × 10 ^-1 mol / l, pH
= 4.5 of the substrate 30 in an electroless nickel plating solution.
By immersing for 5 minutes, a nickel plating layer 72 having a thickness of 5 μm was formed in the opening 71. Further, the substrate was treated with 4.1 × 10 ^-2 mol / l of potassium gold cyanide and 1.87 mol of ammonium chloride.
× 10 ^-1 mol / l, sodium citrate 1.16 × 10 ^-1 mo
1 / l, sodium hypophosphite 1.7 × 10 ^-1 mol / l, immersed in electroless gold plating solution at 80 ° C. for 7 minutes and 20 seconds, and gold plating 0.03 μm thick on nickel plating layer By forming the layer 74, the solder pads 75 are formed in the via holes 160 and the conductor circuits 158 (see FIG. 5).

(22) Then, solder paste is printed on the opening 71 of the solder resist layer 70 and reflowed at 200 ° C., so that the solder bumps (solder bodies) 76U, 76D
To form a multilayer build-up wiring board 10 (see FIG. 5 (R)).

Finally, as shown in FIG. 6, the bumps 76U of the multilayer build-up wiring board 10 are mounted so that the pads 92 of the IC chip 90 are aligned with each other, and reflow is performed. The IC chip 92 is attached. Further, the multilayer build-up wiring board 10 is placed so as to correspond to the pad 96 of the daughter board 94, and is mounted on the daughter board by performing reflow.

In the above-described embodiment, the example in which the multilayer build-up wiring board is formed semi-additively has been described. However, it is needless to say that the configuration of the present invention can be used also when the multilayer build-up wiring board is formed fully additive.

[0074]

As described above, according to the present invention, since the land shape of the through hole can be made a perfect circle, the arrangement density of the through holes provided in the multilayer core substrate is improved. Therefore, wiring can be integrated at the same pace between the build-up wiring layer formed on the front side of the core substrate and the build-up wiring layer formed on the back side of the core substrate, so that the upper multilayer wiring layer and the lower multilayer wiring layer can be integrated. By making the number of layers equal, the number of layers can be minimized. Further, the via hole can be formed directly above the via hole, and the wiring length in the multilayer build-up wiring board can be reduced.

[Brief description of the drawings]

1 (A), 1 (B), 1 (C), 1
(D) and FIG. 1 (E) are manufacturing process diagrams of the multilayer build-up wiring board according to the embodiment of the present invention.

2 (F), 2 (G), 2 (H), 2
(I) is a manufacturing process diagram of the multilayer build-up wiring board according to the embodiment of the present invention;

FIG. 3 (J), FIG. 3 (K), FIG. 3 (L), FIG.
(M) is a manufacturing process diagram of the multilayer build-up wiring board according to the embodiment of the present invention.

4 (N), FIG. 4 (O), FIG. 4 (P), FIG.
(Q) is a manufacturing process diagram of the multilayer build-up wiring board according to the embodiment of the present invention;

FIG. 5 (R) is a view showing the manufacturing process of the multilayer build-up wiring board according to the embodiment of the present invention, and FIG.
It is SS cross section of (R).

FIG. 6 is a cross-sectional view of the multilayer build-up wiring board according to the embodiment of the present invention.

7A is a cross-sectional view showing a structure of a multilayer build-up wiring board according to a conventional technique, and FIG. 7B is a cross-sectional view taken along a line BB of FIG. 7A. .

[Explanation of symbols]

 Reference Signs List 16 through hole 18 plating film 30 core substrate 34 conductive circuit (conductive layer) 36 through hole 36a land 48 opening 50 interlayer resin insulating layer 52 electroless plating layer 56 electrolytic plating layer 58 conductive circuit (conductive layer) 60 via hole 80A, 80B Build-up wiring layer 150 Interlayer resin insulation layer 158 Conductor circuit (conductor layer)

Claims (3)

[Claims] 1. A multilayer build-up wiring board in which interlayer resin insulation layers and conductor layers are alternately laminated, and build-up wiring layers in which respective conductor layers are connected by via holes are formed on both surfaces of a core substrate. 2. The multilayer build-up wiring board according to claim 1, wherein a via hole is formed so as to close a through hole formed in the core substrate. 2. A through hole having a diameter of 200 μm.
2. The multilayer build-up wiring board according to claim 1, wherein the thickness is less than m. 3. A method for manufacturing a multilayer build-up wiring board, comprising at least the following steps (1) to (4). (1) a step of forming a through hole having a diameter of 200 μm or less in a core substrate by a laser; (2) a step of plating the inside of the through hole to form a through hole; and (3) a step of forming a through hole in the core substrate. A step of forming an interlayer resin insulating layer having an opening, and (4) a step of forming a via hole so as to close the through hole by plating the opening of the interlayer resin insulating layer.