JP3383759B2 - Multilayer printed wiring board and method of manufacturing multilayer printed wiring board - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board for forming a package substrate or the like on which an IC chip is mounted, and more specifically, a multilayer printed wiring board having solder pads formed on its upper and lower surfaces. And a method for manufacturing a multilayer printed wiring board.

[0002]

2. Description of the Related Art A highly integrated IC chip is mounted on a package substrate composed of a multilayer printed wiring board or the like and connected to a substrate such as a mother board or a sub board. In recent years, solder bumps have been widely used for connection between an IC chip and a package substrate and between a package substrate and a mother board.

Here, a part of the solder pads formed on the package substrate (multilayer printed wiring board) is shown in FIG.
They were connected via wiring as shown in (A). Here, as shown in the drawing, the solder pads 275 are connected to each other by two wirings 278 in order to improve the reliability of the connection.

The formation of the solder pads 275 and the wirings 278 on the surface layer of the multilayer printed wiring board by the semi-additive method will be described with reference to FIGS. 26, 27 and 28. First, as shown in FIG. 27B, the electroless plating layer 252 is uniformly formed on the surface of the interlayer resin insulation layer 250 in which the via hole opening 248 is formed on the substrate 230 shown in FIG. 27A. . After that, as shown in FIG. 27C, the electroless plating layer 252 is provided with an opening 254a for forming a solder pad and a wiring for connection, and the resist 2 is formed.
54 is formed. Next, as shown in FIG. 27D, an electrolytic plating layer 254 is deposited on the electroless plating layer 252 in the opening 254a of the resist 254 to form a solder pad 275 and a wiring 278. FIG. 26B is the same as FIG. 27D.
It is the figure which looked at the substrate shown in FIG. That is, FIG.
26D corresponds to a cross-sectional view taken along line DD of FIG. In addition, FIG. 28E corresponds to a cross-sectional view taken along line EE of FIG. Subsequently, as shown in FIG. 28F, the resist 254 and the electroless plating layer 25 below the resist 254 are formed.
2 is removed to complete the multilayer printed wiring board. here,
FIG. 26C is a diagram of the substrate shown in FIG. 28F as seen from the E arrow side. That is, FIG. 28 (F) corresponds to FIG. 26 (C).
Corresponds to a sectional view taken along line FF of FIG. 28G corresponds to a cross-sectional view taken along line GG of FIG. 26C.

[0005]

However, as shown in FIG.
In the step of removing the resist 254 and the electroless plating layer 252 below the resist 254 described above with reference to (E), the solvent of the resist is poured from above into a shower shape. Here, as shown in FIG.
Resist 254A sandwiched between 8A and wiring 278B
As shown in FIG. 28 (E), even if it is melted with a solvent, it stays between the wiring 278A and the wiring 278B protruding upward, and becomes difficult to flow out to the outside. Therefore, the resist remains in the vicinity of the solder pad 275, and the electroless plating layer 252 below the resist is formed as shown in FIG. 28C showing the GG cross section of FIGS. 26C and 26C. It may remain on the outer periphery of the solder pad 275. Where the solder pad 2
75 (electrolytic plating layer 256) outside the electroless plating layer 2
When 52 remains, the electrolytic plating layer 25 is formed at the site.
6 peeled off from the electroless plating layer 252, causing a failure of the solder pad.

Further, as shown in FIG.
At the corners K of 8 and the joints J between wirings, stress tends to concentrate due to heat cycles that occur when the substrate is dried and during use of the multilayer printed wiring board.
As shown in FIG. 28F, the stress concentration causes a crack L in the substrate, which causes the disconnection of the internal wiring 258.

The multi-layer printed wiring board of the present invention has been made to solve the above-mentioned problems, and an object thereof is to provide a multi-layer printed wiring board in which cracks are hard to enter.

Another object of the present invention is to provide a method for manufacturing a multilayer printed wiring board which does not cause peeling of solder pads.

[0009]

In order to achieve the above-mentioned object, a multilayer printed wiring board according to claim 1 has a conductor layer formed on a substrate on which a conductor layer is formed via an interlayer resin insulation layer, and a surface layer. In a multilayer printed wiring board in which a solder pad group for forming a solder bump is formed, the surface layer on which the solder pad is formed is covered with a solder resist having an opening for exposing the solder pad, A technical feature is that two or more solder pads of the solder pad group are connected by only one wire in the surface layer.

The multilayer printed wiring board according to claim 2 is
In Claim 1, said 2 connected by said 1 wiring
The above-mentioned solder bumps are further technically characterized in that they are connected to each other by a wiring formed in a conductor layer which is an inner layer of the interlayer resin insulation layer.

The method for manufacturing a multilayer printed wiring board according to claim 3 is technically characterized by including the following steps. (A) A step of providing an electroless plating layer on the interlayer resin insulation layer on the substrate on which the conductor layer is formed. (B) A step of forming a resist in the electroless plating layer by providing an opening for forming a plurality of solder pads and a wiring for connecting two or more of the plurality of solder pads with one wire. (C) A step of depositing an electrolytic plating layer on the electroless plating layer in the opening of the resist to form a solder pad and wiring. (D) A step of removing the resist and the electroless plating layer under the resist. (E) A step of forming a solder resist by providing an opening for exposing the solder pad on the surface layer. (F) A step of placing solder on the solder pads to form solder bumps.

In the multilayer printed wiring board according to the present invention, the solder pads are connected by only one wiring on the surface layer, and since there is no corner portion or a connecting portion between the wirings, a portion where stress is concentrated. Does not exist. Therefore, cracks due to stress concentration do not occur.

According to another aspect of the multilayer printed wiring board of the present invention, the solder pads are connected by a single wiring on the surface layer, and are further connected by the wiring formed on the inner conductor layer of the interlayer resin insulation layer. . Therefore, even if the connection cannot be properly made with the wiring on the surface layer, the solder pads can be connected with the wiring on the inner layer of the interlayer resin insulation layer.

According to the method of manufacturing a multilayer printed wiring board of claim 3, an opening is provided so as to connect two or more solder pads with one wiring, and a resist is formed, and electroless plating of the opening of the resist is performed. An electrolytic plating layer is deposited on the layer to form solder pads and wiring. Then, the resist and the electroless plating layer under the resist are removed. At this time, since the solder pads are connected by one wire and the resist is not surrounded by the wire, the resist and the electroless plating layer under the resist can be appropriately removed.
Therefore, by removing all the electroless plating layer under the resist, the peeling of the solder pad can be prevented.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION The structure of a multilayer printed wiring board according to a first embodiment of the present invention will be described with reference to FIGS. 23 and 24 (A). FIG. 23 shows a cross section of the multilayer printed wiring board of the first embodiment, and FIG. 24 (A) shows an X1-X1 cross section of the multilayer printed wiring board. As shown in FIG. 23, the multilayer printed wiring board has solder bumps 7 on its upper surface for connecting to the bump side of an IC chip (not shown).
6U is provided, and solder bumps 76D for connecting to bumps of a mother board (not shown) are provided on the lower surface side.
It plays a role of passing signals and the like between the IC chip and the mother board and relaying power supply from the mother board side.

As shown in FIG. 23, inner layer copper patterns 34U and 34D serving as ground layers are formed on the upper and lower surfaces of the core substrate 30 of the multilayer printed wiring board. Further, a conductor circuit 58U for forming a signal line with the interlayer resin insulation layer 50 interposed on the upper layer of the inner layer copper pattern 34U,
Also, a via hole 60 is formed through the interlayer resin insulation layer 50.
U is formed. The conductor circuit 1 of the outermost layer (surface layer) is provided on the upper layer of the conductor circuit 58U via the interlayer resin insulation layer 150.
A via hole 160U penetrating 58U and the interlayer resin insulation layer 150 is formed. Via hole 160U
A solder pad 75UA for supporting the solder bump 76U,
75UB (only solder pad 75UA is shown in FIG. 23)
Are formed.

That is, as shown in FIG. 24A corresponding to the X1-X1 cross section in FIG. 23, the via hole 160U.
The solder pads 75UA connected to each other by the conductor circuit 158U and the solder pads 75UB not connected by the conductor circuit 158U are formed on the. The solder pad 75
The UA and 75UB are formed to have a diameter of 120 to 170 μm.

In the multilayer printed wiring board according to the first embodiment of the present invention, since the solder pad 75UA is connected by one conductor circuit (wiring) 158U, FIG.
Unlike the conventional multi-layer printed wiring board described above with reference to FIG. 1, since the conductor circuit (wiring) 158U does not have a corner portion or a connecting portion between wirings, there is no stress concentration portion.
For this reason, cracks due to stress concentration do not occur in the multilayer printed wiring board, so that no disconnection occurs in the inner conductor circuit 58U.

On the other hand, the upper layer of the ground layer (inner layer copper pattern) 34D on the lower surface side of the core substrate 30 (here, the upper layer means the upper side with respect to the substrate 30 as the center and the lower side as the lower surface of the substrate). ) Is the interlayer resin insulation layer 50.
A conductor circuit 58D that forms a signal line is formed via. An interlayer resin insulation layer 1 is formed on the conductor circuit 58D.
Via holes 160D penetrating the outermost conductor circuit 158D and the interlayer resin insulation layer 150 via 50 are formed, and solder pads 75D supporting the solder bumps 76D are formed in the conductor circuit 158D and via holes 160D. There is. The solder pad 75D on the motherboard side has a diameter of 6
It is formed to have a thickness of 00 to 700 μm. Although not described in detail here, the solder pads connected to the motherboard side are also
Predetermined solder pads are connected by one wire (conductor circuit 158D).

Next, the manufacturing process of the multilayer printed wiring board shown in FIG. 23 will be described with reference to FIGS. (1) Starting material is a copper clad laminate 30A in which a 18 μm copper foil 32 is laminated on both sides of a core substrate 30 made of a glass epoxy resin or a BT (bismaleimide triazine) resin having a thickness of 1 mm (see FIG. 1). ). First, the copper clad laminate 30A is drilled, electroless plated, and patterned to form inner layer copper patterns 34U and 34D and through holes 36 on both surfaces of the substrate 30 (FIG. 2). reference).

(2) Further, the inner layer copper patterns 34U, 3
The substrate 30 on which the 4D and the through holes 36 are formed is washed with water, dried, and then subjected to oxidation-reduction treatment to provide a roughened layer 38 on the surfaces of the inner layer copper patterns 34U and 34D and the through holes 36 (see FIG. 3).

(3) On the other hand, a resin filler for smoothing the surface of the substrate is adjusted. Here, bisphenol F type epoxy monomer (made by Yuka Shell, molecular weight 310, YL
983 U) 100 parts by weight and 6 parts by weight of an imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Kasei) are mixed, and a silane coupling agent is coated on the surface of the mixture to form SiO ₂ having an average particle diameter of 1.6 μm. Spherical particles (manufactured by Admatech, CRS1101-CE, where the maximum particle size is the thickness of the inner layer copper pattern described later (15 μm
m) or less) 170 parts by weight and 0.5 parts by weight of an antifoaming agent (manufactured by San Nopco, Perenol S4) are mixed and kneaded with a three-roll mill to increase the viscosity of the mixture to 23 ±.
Adjust to 45,000 to 49,000 cps at 1 ° C,
Obtain a resin filler. This resin filler is solventless. If a resin filler containing a solvent is used, the solvent volatilizes from the resin filler layer when the interlayer agent is applied and heated / dried in a later step, and the space between the resin filler layer and the interlayer material is reduced. This is because peeling occurs.

(4) Resin filler 40 obtained in (3) above
Is coated on both surfaces of the substrate 30 using a roll coater so as to fill between the conductor circuits (inner layer copper patterns) 34U on the upper surface or through holes 36, and is dried at 70 ° C. for 20 minutes. Resin filler 4
0 is filled between the conductor circuits 34D or in the through holes 36 and dried at 70 ° C. for 20 minutes (see FIG. 4).

(5) Substrate 30 which has undergone the processing of (4) above
One side of the inner layer copper pattern 34 was polished by belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku).
Polishing is performed so that the resin filler 40 does not remain on the surface of U and 34D and the land surface of the through hole 36, and then buffing is performed to remove the scratches due to the belt sander polishing (see FIG. 5). Then, at 100 ° C. for 1 hour, 120
C. for 3 hours, 150.degree. C. for 1 hour, and 180.degree. C. for 7 hours to perform heat treatment to cure the resin filler 40.

In this way, the surface layer portion of the resin filler 40 filled in the through holes 36 and the conductor circuit 34.
By removing the roughening layer 38 on the upper surfaces of U and 34D and smoothing both surfaces of the substrate, the resin filler 40 and the conductor circuits 34U and 34D are formed.
The side surface of D is firmly adhered to the roughened layer 38 via the roughened layer 38, and the inner wall surface of the through hole 36 and the resin filler 40 are firmly bonded to each other.
A wiring board tightly adhered via 8 is obtained. That is, by this step, the surface of the greasing filler 40 and the inner layer copper pattern 3 are
The surfaces of 4U and 34D are flush with each other.

(6) A roughened layer (concavo-convex layer) having a thickness of 2.5 μm and made of a Cu—Ni—P alloy is formed on the upper surfaces of the lands of the conductor circuits 34U and 34D and the through holes 36 exposed by the treatment of the above (5). 42 is formed, and a Sn layer having a thickness of 0.3 μm is provided on the surface of the roughened layer 42 (see FIG. 6, but the Sn layer is not shown). The formation method is as follows. That is, the substrate 30 is acid-degreased and soft-etched, then treated with a catalyst solution consisting of palladium chloride and an organic acid to impart a Pd catalyst, and the catalyst is activated. Nickel 0.6g
/ L, citric acid 15g / l, sodium hypophosphite 29
g / l, boric acid 31 g / l, surfactant 0.1 g / l,
Plating is performed in an electroless plating bath of pH = 9, and Cu-on the upper surface of the land of the copper conductor circuit 4 and the through hole 9.
A roughened layer 42 of Ni-P alloy is formed. Then, tin borofluoride 0.1 mol / l, thiourea 1.0 mol / l
A Cu—Sn substitution reaction is performed under the conditions of 1, temperature of 50 ° C. and pH = 1.2 to provide a 0.3 μm thick Sn layer on the surface of the roughening layer 42 (Sn layer is not shown).

Subsequently, a photosensitive adhesive (for upper layer) and an interlayer resin insulating agent (for lower layer) for forming an insulating layer are prepared. (7) The photosensitive adhesive (for the upper layer) has a concentration of 80 w dissolved in DMDG (diethylene glycol dimethyl ether).
35 parts by weight of 25% acrylate of t% cresol novolac type epoxy resin (Nippon Kayaku, molecular weight 2500), 12 parts by weight of polyether sulfone (PES), imidazole curing agent (2E4MZ-CN manufactured by Shikoku Kasei) 2
Parts by weight, photosensitive monomer (Toagosei, Aronix M
315) 4 parts by weight, photoinitiator (manufactured by Ciba Geigy, Irgacure I-907) 2 parts by weight, photosensitizer (manufactured by Nippon Kayaku,
DETX-S) 0.2 parts by weight, and to the mixture, 7.2 parts by weight of epoxy resin particles (polymer pole manufactured by Sanyo Kasei Co., Ltd.) having an average particle diameter of 1.0 μm, and an average particle diameter of 0. After mixing 3.09 parts by weight of 0.5 .mu.m and 0.5 parts by weight of a defoaming agent (S-65 manufactured by San Nopco), 30 parts by weight of NMP are further added and mixed to obtain a viscosity of 7 Pa.
Obtain a photosensitive adhesive of s (for the upper layer).

(8) On the other hand, interlayer resin insulation agent (for lower layer)
Is a cresol novolac type epoxy resin (manufactured by Nippon Kayaku, molecular weight 2500) having a concentration of 80 wt% dissolved in DMDG (diethylene glycol dimethyl ether).
% Acrylate, 35 parts by weight, polyether sulfone (PES) 12 parts by weight, imidazole curing agent (Shikoku Kasei, 2E4MZ-CN) 2 parts by weight, photosensitive monomer (Toagosei, Aronix M315) 4 parts by weight, light 2 parts by weight of an initiator (manufactured by Ciba Geigy, Irgacure I-907) and 0.2 part by weight of a photosensitizer (manufactured by Nippon Kayaku, DETE-S) were mixed, and epoxy resin particles (Sanyo Chemical Co., Ltd.) were mixed with the mixture. Made of polymer pole) with an average particle size of 0.5 μm
14.49 parts by weight of antifoaming agent (San Nopco, S
-65) After mixing 0.5 parts by weight, further NMP30
By mixing while adding parts by weight, an interlayer resin insulating agent (for lower layer) having a viscosity of 1.5 Pa · s is obtained.

(9) On both surfaces of the substrate 30, an interlayer resin insulating agent (for lower layer) having a viscosity of 1.5 Pa · s obtained in (7) above.
Is applied by roll coating overnight, left standing in a horizontal state for 20 minutes, and then dried (prebaked) at 60 ° C. for 30 minutes to form an insulating agent layer 44. Further, a photosensitive adhesive (for upper layer) having a viscosity of 7 Pa · s obtained in (8) above is applied on the insulating agent layer 44 by using a roll coater, and left standing in a horizontal state for 20 minutes, Dry for 30 minutes at 60 ℃,
The adhesive layer 46 is formed (see FIG. 7).

As described above, the conductor circuits 34U, 34D
The roughened layer (concavo-convex layer) 42 is formed, that is, the roughening treatment is performed, so that the adhesiveness with the upper insulating agent layer 44 is improved.

(10) 100 μm on both sides of the substrate 30 on which the insulating layer 44 and the adhesive layer 46 are formed in (9) above.
A photomask film on which a φ black circle is printed is brought into close contact and exposed at 500 mJ / cm ² by an ultra-high pressure mercury lamp. This is spray-developed with a DMDG solution, and further, the substrate is exposed at 3000 mJ / cm ² by an ultra-high pressure mercury lamp, and subjected to heat treatment (post-baking) at 100 ° C. for 1 hour and then at 150 ° C. for 5 hours. A thickness 35 having an opening (via-hole forming opening 48) of 100 μmφ excellent in dimensional accuracy equivalent to a photomask film.
An interlayer resin insulation layer (two-layer structure) 50 of μm is formed (see FIG. 8). In addition, the tin plating layer is partially exposed in the opening 48 serving as a via hole.

(11) Substrate 30 on which the opening 48 is formed
Is immersed in chromic acid for 1 minute to dissolve and remove the epoxy resin particles on the surface of the adhesive layer 46 to roughen the surface of the interlayer resin insulation layer 50, and then to a neutralizing solution (manufactured by Shipley). Immerse and then wash with water (see FIG. 9). Further, a palladium catalyst (manufactured by Atotech Co., Ltd.) is applied to the surface of the roughened substrate to attach a catalyst nucleus to the surface of the interlayer resin insulating layer 50 and the inner wall surface of the via hole opening 48.

(12) The substrate is dipped in an electroless copper plating bath having the following composition to form an electroless copper plating film 52 having a thickness of 1.6 μm on the entire rough surface (see FIG. 10). [Electroless plating solution] EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α′-bipyridyl 80 mg / l PEG 0.1 g / l [Electroless plating conditions] 70 ° C. 30 minutes at the liquid temperature of

(13) A commercially available photosensitive dry film is attached on the electroless copper-plated film 52 formed in (12), a mask is placed, and exposure is performed at 100 mJ / cm ² .
Development is performed with 0.8% sodium carbonate to provide a plating resist 54 having a thickness of 15 μm (see FIG. 11).

(14) Next, electrolytic copper plating is applied to the resist non-formed portion under the following conditions to form an electrolytic copper plated film 56 having a thickness of 15 μm (see FIG. 12). [Electrolytic plating solution] Sulfuric acid 180 g / l Copper sulfate 80 g / l Additive (Atotech Japan, Kaparaside GL) 1 ml / l [Electrolytic plating conditions] Current density 1 A / dm ² hours 30 minutes Temperature room temperature

(15) The plating resist 54 is set to 5% KOH
After peeling and removing with, the electroless plating film 52 under the plating resist 54 is etched by a mixed solution of sulfuric acid and hydrogen peroxide to dissolve and remove, and a thickness formed of the electroless copper plating film 52 and the electrolytic copper plating film 56. 18 μm conductor circuit 58U, 5
8D and via holes 60U, 60D are formed (see FIG. 1).
3). Subsequently, the substrate 30 is immersed in 800 g / l of chromic acid for 3 minutes to remove the palladium catalyst nuclei remaining on the roughened surface.

(16) The substrate 30 on which the conductor circuits 58U and 58D and the via holes 60U and 60D are formed is copper sulfate 8 g / l, nickel sulfate 0.6 g / l, and citric acid 15 g.
/ L, sodium hypophosphite 29g / l, boric acid 31g
/ L, 0.1 g / l of a surfactant and pH = 9, and the surface of the conductor circuits 58U, 58D and the via holes 60U, 60D was dipped in an electroless plating solution of copper-nickel-phosphorus having a thickness of 3 μm. A roughened layer 62 is formed (see FIG. 14). Further, a Cu—Sn substitution reaction is performed under the conditions of tin borofluoride 0.1 mol / l, thiourea 1.0 mol / l, temperature 50 ° C. and pH = 1.2, and the surface of the roughened layer 62 has a thickness of 0. A Sn layer of 0.3 μm is provided (Sn layer is not shown).

(17) By repeating the steps (2) to (16), a conductor circuit in an upper layer is formed.
That is, an interlayer resin insulating agent (for lower layer) is applied to both surfaces of the substrate 30 by roll coating to form the insulating agent layer 144. In addition, a photosensitive adhesive (for the upper layer) is formed on the insulating agent layer 144.
Is applied using a roll coater to form an adhesive layer 146 (see FIG. 15). Insulating agent layer 144 and adhesive layer 1
A photomask film is adhered to both surfaces of the substrate 30 on which the 46 is formed, exposed and developed to form an interlayer resin insulating layer 150 having an opening (opening 148 for forming a via hole), and then the interlayer resin insulating layer 150 is formed. The surface is roughened (see FIG. 16). Then, an electroless copper plating film 152 is formed on the surface of the substrate 30 that has been roughened (see FIG. 17).

Subsequently, a plating resist 154 is provided on the electroless copper plating film 152 (see FIG. 18). This Figure 1
24B is a view of the substrate 30 shown in FIG. Figure 2
An X2-X2 cross section of FIG. 3B corresponds to FIG. The plating resist 154 is formed so as to provide a via hole forming opening 154a and a conductor circuit forming opening 154b. Here, of the plurality of openings 154a for forming via holes, those connected by a conductor circuit are shown in FIG.
As shown in (B), one conductor circuit forming opening 154 is formed.
Connect by b.

After that, a resist non-formed portion (via hole forming opening 154a, conductor circuit forming opening 154b)
Then, an electrolytic copper plating film 156 is formed on the substrate, and a conductor circuit 158U and a via hole 160U are formed (see FIG. 19). FIG. 24C shows the substrate 30 shown in FIG. 19 as viewed in the direction of arrow D. The X3-X3 cross section of FIG. 24C corresponds to FIG.

Then, KOH is poured like a shower from the upper side (along arrow D side) shown in FIG. 19 to remove the plating resist 154. At this time, in the multilayer printed wiring board of the first embodiment, the via holes for forming the solder pads are connected by one conductor circuit (wiring) 158U. Unlike the prior art multilayer printed wiring board described above, the plating resist is not surrounded by a plurality of wirings. Therefore, K
By pouring OH, the upper surface side plating resist can be completely peeled off without staying. Similarly, the plating resist on the lower surface side is peeled off.

After that, by pouring a solvent, the electroless plated film 152 at the portion where the plating resist 154 is peeled off is dissolved and removed to complete the conductor circuits 158U and 160U.
Similarly, the conductor circuit 158D and the via hole 160D on the lower surface side are completed (see FIG. 20). As described above, the plating resist 154 has been completely peeled off.
Unlike the conventional multilayer printed wiring board described above with reference to FIG. 24C, the via hole 16 is formed as shown in FIG.
The electroless plating film 152 does not remain on the outer periphery of 0 U.
Therefore, the electroless plated film 152 to the electrolytic plated film 15
6 does not peel off to cause peeling of the via hole 160U, that is, the solder pad described later.

Further, the roughening layer 16 is formed on the surfaces of the conductor circuits 158U and 158D and the via holes 160U and 160D.
By forming 2, the multilayer printed wiring board is completed (see FIG. 21).

(19) Then, solder bumps are formed on the above-mentioned multilayer printed wiring board. First, the preparation of the solder resist composition for solder bumps will be described. Here, 46.67 g of a photosensitizing oligomer (molecular weight 4000) obtained by acrylated 50% of epoxy groups of 60 wt% cresol novolac type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG was dissolved in methyl ethyl ketone. 80% by weight of bisphenol A type epoxy resin (Okaka Shell, Epicoat 1001) 15.0 g, imidazole curing agent (Shikoku Kasei, 2E4MZ-CN)
1.6 g, polyvalent acrylic monomer (R604, manufactured by Nippon Kayaku Co., Ltd.) which is a photosensitive monomer, 1.5 g of polyvalent acrylic monomer (manufactured by Kyoeisha Chemical Co., Ltd., DPE6A), dispersion type defoaming agent (San Nopco, S -65) 0.71 g was mixed, and 2 g of benzophenone (manufactured by Kanto Kagaku) as a photoinitiator and 0.2 g of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer were added to these mixtures. A solder resist composition having a viscosity adjusted to 2.0 Pa · s at 25 ° C. is obtained.

(20) The solder resist composition having a thickness of 20 μm is applied to both surfaces of the wiring board obtained in (18). Then, after performing a drying treatment at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a circular pattern (mask pattern)
A photomask film having a thickness of 5 mm, in which is drawn, is placed in close contact with it, exposed to ultraviolet rays of 1000 mJ / cm ² , and DMTG developed. And 1 more at 80 ℃
Hour, 100 ° C for 1 hour, 120 ° C for 1 hour, 150 ° C
Then, the solder resist layer (thickness 20 μm) 70 having a solder pad portion (including a via hole and its land portion) 71 opened (upper surface side opening diameter 200 μm, lower surface side opening diameter 700 μm) is formed by heating for 3 hours. Yes (Fig. 2
2).

(21) Next, the substrate 30 on which the solder resist layer 70 is formed is nickel chloride 30 g / l, sodium hypophosphite 10 g / l, sodium citrate 10 g.
20 for electroless nickel plating solution of pH = 5 consisting of 1 / l
By immersing for a minute, a nickel plating layer 72 having a thickness of 5 μm is formed in the opening 71 (see FIG. 23). Further, the substrate 30 was immersed in an electroless gold plating solution containing 2 g / l of potassium gold cyanide, 75 g / l of ammonium chloride, 50 g / l of sodium citrate and 10 g / l of sodium hypophosphite at 93 ° C. Immerse for 2 seconds, nickel plating layer 7
A gold plating layer 74 having a thickness of 0.03 μm is deposited on the upper surface of the substrate 2, solder pads 75U having a diameter of 133 to 170 μm are formed on the upper surface, and solder pads 75D having a diameter of 600 μm are formed on the lower surface.

(22) Then, the solder resist layer 70
Solder bumps 76U and 76D are formed by printing a solder paste on the solder pads 75U and 75D in the opening 71 of the solder paste and reflowing at 200 ° C.
Complete a multilayer printed wiring board with 6U and 76D.

In the first embodiment, the solder pad 75
The UAs are connected by a single conductor circuit (wiring) 158U provided on the surface layer (the surface of the outermost interlayer resin insulation layer 150). Since the surface layer is covered with the solder resist layer 70. Therefore, the wiring 158U is not broken.

Next, a multilayer printed wiring board according to the second embodiment of the present invention will be described with reference to FIG. In the above-described first embodiment, the solder pad 75UA is connected by one conductor circuit (wiring) 158U provided on the surface layer. On the other hand, in the multilayer printed wiring board of the second embodiment, the adjacent solder pads 75UA are connected to each other by one conductor circuit (wiring) 158U on the surface layer and are provided on the lower layer of the interlayer resin insulation layer 150. They are also connected by the inner layer conductor 58U provided. Therefore, even if the connection cannot be properly made with the wiring 158U on the surface layer, the solder pad 75U with the wiring 58U on the inner layer of the interlayer resin insulation layer 150U.
A can be connected.

In the above-described embodiment, the multilayer printed wiring board formed by the semi-additive method is illustrated, but it goes without saying that the configuration of the present invention can be applied to the multilayer printed wiring board formed by the full additive method. Yes. Further, in the above-described embodiment, the example in which the solder pads provided in the via holes are connected by one wire has been described, but the solder pads not provided with the via holes may be connected by one wire. It is possible.

[0051]

As described above, in the multilayer printed wiring board according to the first aspect, the solder pads are connected to each other by only one wiring on the surface layer, and the wiring has no corners or wiring interconnections. Therefore, there is no place where stress is concentrated. For this reason, cracks due to stress concentration do not occur and the conductor circuit is not broken.

In the multilayer printed wiring board according to the second aspect of the invention, the solder pads are connected by a single wiring on the surface layer, and further by the wiring formed on the conductor layer inside the interlayer resin insulation layer. . Therefore, even if the connection cannot be properly made with the wiring on the surface layer, the solder pads can be connected with the wiring on the inner layer of the interlayer resin insulation layer.

According to the method of manufacturing a multilayer printed wiring board of claim 3, an opening is provided so that two or more solder pads are connected by one wiring, and a resist is formed, and electroless plating of the opening of the resist is performed. An electrolytic plating layer is deposited on the layer to form solder pads and wiring. Then, the resist and the electroless plating layer under the resist are removed. At this time, since the solder pads are connected by one wire and the resist is not surrounded by the wire, the resist and the electroless plating layer under the resist can be appropriately removed.
Therefore, by removing all the electroless plating layer under the resist, the peeling of the solder pad can be prevented.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process of a multilayer printed wiring board according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 7 is a diagram showing a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 8 is a diagram showing a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 9 is a diagram showing a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 10 is a diagram showing a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 11 is a diagram showing a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 12 is a diagram showing a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 13 is a diagram showing a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 14 is a diagram showing a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 15 is a diagram showing a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 16 is a diagram showing a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 17 is a diagram showing a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 18 is a diagram showing a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 19 is a diagram showing a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 20 is a diagram showing a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 21 is a diagram showing a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 22 is a diagram showing a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 23 is a cross-sectional view showing the multilayer printed wiring board according to the first embodiment of the present invention.

24 (A) is a lateral cross-sectional view taken along the line X1-X1 of FIG. 23, and FIG. 24 (B) is a view taken in the direction of arrow C of FIG.
4C is a view taken in the direction of arrow D in FIG.

FIG. 25 is a cross-sectional view showing a multilayer printed wiring board according to a second embodiment of the present invention.

26 (A), FIG. 26 (B), and FIG. 26 (C)
FIG. 3 is an explanatory diagram of solder pads of a multilayer printed wiring board according to a conventional technique.

FIG. 27 (A), FIG. 27 (B), FIG.
27C and 27D are diagrams showing manufacturing steps of a conventional multilayer printed wiring board.

28 (E), 28 (F), and 28 (G).
FIG. 7 is a diagram showing a manufacturing process of a conventional multilayer printed wiring board.

[Explanation of symbols]

30 core substrate 34U, 34D Inner layer copper pattern (inner layer conductor circuit) 50 interlayer resin insulation layer 58U, 58D Conductor circuit 58M dummy pattern 60U, 60D via hole 75UA, 75UB Solder pad 76U, 76D Solder bump 78 wiring 150 interlayer resin insulation layer 158U Conductor circuit (wiring) 160U via hole

Claims (3)

(57) [Claims] 1. A multilayer printed wiring board comprising a conductor layer formed on a substrate on which a conductor layer is formed, with an interlayer resin insulation layer interposed therebetween, and a solder pad group for forming solder bumps formed on a surface layer. The surface layer on which the solder pad is formed is covered with a solder resist having an opening for exposing the solder pad, and two or more solder pads of the solder pad group are connected by only one wire in the surface layer. A multilayer printed wiring board characterized by being provided. 2. The two or more solder bumps connected by the one wire are further connected by a wire formed in a conductor layer which is an inner layer of the interlayer resin insulation layer. 1 multilayer printed wiring board. 3. A method for manufacturing a multilayer printed wiring board, comprising the following steps. (A) A step of providing an electroless plating layer on the interlayer resin insulation layer on the substrate on which the conductor layer is formed. (B) A step of forming a resist in the electroless plating layer by providing an opening for forming a plurality of solder pads and a wiring for connecting two or more of the plurality of solder pads with one wire. (C) A step of depositing an electrolytic plating layer on the electroless plating layer in the opening of the resist to form a solder pad and wiring. (D) A step of removing the resist and the electroless plating layer under the resist. (E) A step of forming a solder resist by providing an opening for exposing the solder pad on the surface layer. (F) A step of placing solder on the solder pads to form solder bumps.