JP5068830B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

  Some conventional semiconductor devices called CSP (chip size package) have columnar electrodes formed on the upper surface of connection pad portions of wiring formed on a semiconductor substrate (see, for example, Patent Document 1). In this case, as a method for manufacturing a semiconductor device, the upper surface of the base metal layer including the wiring formed on the base metal layer formed on the entire surface of the semiconductor substrate corresponds to the connection pad portion of the wiring, that is, the columnar electrode formation region. Forming a plating resist film having an opening in the portion to be formed, and performing electrolytic plating using the base metal layer as a plating current path, thereby forming a columnar electrode on the upper surface of the connection pad portion of the wiring in the opening of the plating resist film; A method is used in which a plating resist film is stripped using a resist stripping solution, and a base metal layer in a region other than under the wiring is etched away using the wiring as a mask.

JP 2004-281614 A

  However, in the above-described conventional method for manufacturing a semiconductor device, when the columnar electrode forming plating resist film is stripped using a resist stripping solution, the columnar electrode forming plating resist film is stripped mainly only from the upper surface side. When the interval between the two becomes narrow, a resist residue may be generated between the wirings. When the underlying metal layer is etched using the wiring as a mask, the resist residue becomes a mask and causes an etching failure, causing a short circuit between the wirings.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device and a method of manufacturing the same that can prevent resist residue from being generated when the columnar electrode forming plating resist film is peeled off.

A semiconductor device according to claim 1 is a semiconductor substrate having a plurality of connection pads on an upper surface, an insulating film provided on the semiconductor substrate and having an opening at a portion corresponding to the connection pads, A lower surface side upper insulating film provided on the upper surface of the insulating film and having an opening in a portion corresponding to the lower surface side wiring formation region, and the connection through the opening of the insulating film in the opening of the lower surface side upper insulating film A lower surface side wiring provided connected to a pad, a lower surface side upper layer insulating film and a lower surface side upper layer insulating film provided on the upper surface of the lower surface side wiring, and a rewiring upper layer insulating film having an opening in a portion corresponding to a rewiring formation region; Rewiring provided in the opening of the redistribution upper layer insulating film connected to the lower surface side wiring, the upper surface of which is provided so as to be flush with or lower than the upper surface of the rewiring upper layer insulating film, The rewiring connection pad And a part of the lower surface side wiring is composed only of the connection portion connected to the connection pad, and a part of the rewiring is formed of the remaining lower layer side wiring. A dummy connection pad portion is provided in an island shape below the connection pad portion of the rewiring connected to the lower surface side wiring formed of only the connection portion on the insulating film, and including only the connection pad portion connected to the connection pad portion. It is characterized by that.
A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the rewiring provided in the opening of the redistribution upper layer insulating film is formed in the opening of the rewiring upper insulating film. It includes a base metal layer formed on the bottom and side surfaces and an upper metal layer formed on the base metal layer.
A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first aspect, wherein a sealing film is provided around the columnar electrode.
A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the third aspect, wherein a solder ball is provided on the columnar electrode.

  According to the present invention, the rewiring is formed in the opening of the rewiring upper insulating film so that the upper surface thereof is flush with or lower than the upper surface of the rewiring upper insulating film, and the columnar electrode forming plating is formed thereon. Since the resist film is formed, there is no room for the columnar electrode forming plating resist film to enter between the rewirings, and as a result, resist residues are less likely to be generated when the columnar electrode forming plating resist film is peeled off. it can.

1 is a cross-sectional view of a semiconductor device as Reference Embodiment 1 of the present invention. Sectional drawing of what was prepared initially in an example of the manufacturing method of the semiconductor device shown in FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 9 is a cross-sectional view of the process following FIG. 8. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the semiconductor device as Reference Embodiment 2 of this invention. Sectional drawing of a predetermined | prescribed process in an example of the manufacturing method of the semiconductor device shown in FIG. Sectional drawing of the process following FIG. FIG. 15 is a sectional view of a step following FIG. 14. FIG. 16 is a cross-sectional view of the process following FIG. 15. FIG. 17 is a cross-sectional view of the process following FIG. 16. FIG. 18 is a cross-sectional view of the process following FIG. 17. FIG. 19 is a cross-sectional view of the process following FIG. 18. 1 is a cross-sectional view of a semiconductor device as a first embodiment of the present invention.

(Reference Embodiment 1)
FIG. 1 is a sectional view of a semiconductor device as a first embodiment of the present invention. This semiconductor device is called a CSP and includes a silicon substrate (semiconductor substrate) 1. An integrated circuit (not shown) is provided on the upper surface of the silicon substrate 1, and a plurality of connection pads 2 made of aluminum metal or the like are provided on the periphery of the upper surface so as to be connected to the integrated circuit.

  An insulating film 3 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 1 excluding the central portion of the connection pad 2, and the central portion of the connection pad 2 is exposed through an opening 4 provided in the insulating film 3. Yes. A protective film (insulating film) 5 made of polyimide resin or the like is provided on the upper surface of the insulating film 3. An opening 6 is provided in the protective film 5 at a portion corresponding to the opening 4 of the insulating film 3.

  An upper layer insulating film (rewiring upper layer insulating film) 7 made of polyimide resin or the like is provided on the upper surface of the protective film 5. An opening 8 is provided in the wiring formation region (rewiring formation region) on the upper surface of the upper insulating film 7 so as to communicate with the opening 6 of the protective film 5. A base metal layer 9 made of copper or the like is provided in a concave shape on the upper surface of the protective film 5 exposed through the opening 8 of the upper insulating film 7 and the inner wall surface of the opening 8 of the upper insulating film 7. An upper metal layer 10 made of copper is provided inside the concave base metal layer 9. The base metal layer 9 and the upper metal layer 10 are laminated to form a wiring (rewiring) 11. One end of the wiring 11 is connected to the connection pad 2 through the openings 4 and 6 of the insulating film 3 and the protective film 5.

  Here, the upper surfaces of both side portions of the recessed base metal layer 9 provided on the inner wall surface of the opening 8 of the upper insulating film 7 are flush with the upper surface of the upper insulating film 7. The upper surface of the upper metal layer 10 is flush with or slightly lower than the upper surface of the upper insulating film 7. The wiring 11 includes a connection portion 11a connected to the connection pad 2, a connection pad portion 11b at the tip, and a lead wire portion 11c therebetween.

  A columnar electrode 12 made of copper is provided on the upper surface of the connection pad portion 11 b of the wiring 11. A sealing film 13 made of an epoxy resin or the like is provided on the upper surface of the wiring 11 and the upper insulating film 7 so that the upper surface is flush with the upper surface of the columnar electrode 12. A solder ball 14 is provided on the upper surface of the columnar electrode 12.

  Next, an example of a method for manufacturing this semiconductor device will be described. First, as shown in FIG. 2, a connection pad 2 made of an aluminum-based metal or the like and an insulating film 3 made of silicon oxide or the like are formed on the upper surface of a silicon substrate (hereinafter referred to as a semiconductor wafer 21) in a wafer state. Is prepared in such a manner that the central portion is exposed through the opening 4 formed in the insulating film 3.

  In this case, an integrated circuit (not shown) having a predetermined function is formed in a region where each semiconductor device is formed on the upper surface of the semiconductor wafer 21, and the connection pad 2 is electrically connected to the integrated circuit formed in the corresponding region. Connected. In FIG. 2, an area indicated by reference numeral 22 is an area corresponding to a dicing line.

  Next, as shown in FIG. 3, a protective film forming film made of polyimide resin or the like formed by spin coating or the like is patterned on the upper surface of the insulating film 3 by photolithography to be cured. A film 5 is formed. In this state, an opening 6 is formed in the protective film 5 in a portion corresponding to the opening of the insulating film 3.

  Next, as shown in FIG. 4, an upper insulating film forming film made of a photosensitive polyimide resin or the like formed by spin coating or the like is formed on the upper surface of the protective film 5 using an exposure mask (not shown). The upper insulating film 7 is formed by curing by exposure, development. In this state, an opening 8 is formed in the wiring formation region of the upper insulating film 7 so as to communicate with the opening 6 of the protective film 5.

  Here, the protective film 5 may be formed of the same material as the upper insulating film 7 (for example, a negative photosensitive polyimide resin). In this case, the applied protective film forming film is exposed and developed, then the protective film forming film is temporarily cured, then the upper insulating film forming film is applied, and then the upper insulating film forming film is exposed and developed. Then, the protective film forming film and the upper insulating film forming film may be fully cured.

  Next, as shown in FIG. 5, the upper surface of the connection pad 2 exposed through the openings 4, 6, 8 of the insulating film 3, the protective film 5 and the upper insulating film 7, and the opening 8 of the upper insulating film 7. A base metal layer 9 is formed on the upper surface of the protective film 5 and the surface of the upper insulating film 7 exposed through the film. In this case, the base metal layer 9 is formed in a solid shape along the bottom surface of the opening 8 of the upper insulating film 7 and the side surface forming the periphery of the opening 8 and has a concave shape having a bottom surface and side portions. Yes. The base metal layer 9 may be only a copper layer formed by electroless plating, or may be only a copper layer formed by sputtering, and a thin film layer such as titanium formed by sputtering. A copper layer may be formed thereon by sputtering.

  Next, an upper metal layer forming plating resist film 23 is formed on the upper surface of the base metal layer 9 by patterning a positive resist film applied by spin coating or the like by photolithography. In this state, an opening 24 is formed in the upper metal layer forming plating resist film 23 in a portion corresponding to the upper metal layer 10 formation region. In this case, the size of the opening 24 of the plating resist film 23 for forming the upper metal layer is smaller than the size of the opening 8 of the upper insulating film 7 by the thickness of the base metal layer 9.

  Next, by performing electrolytic plating of copper using the base metal layer 9 as a plating current path, the upper metal layer is formed inside the concave base metal layer 9 in the opening 8 of the plating resist film 23 for forming the upper metal layer. 10 is formed. In this case, the upper surface of the upper metal layer 10 is made to be flush with or slightly lower than the upper surface of the upper insulating film 7. Next, the plating resist film 23 for forming the upper metal layer 10 is stripped using a resist stripping solution.

  Next, as shown in FIG. 6, a negative type dry film resist is laminated on the upper surface of the wiring 11, and the negative type dry film resist is patterned by a photolithography method, thereby forming a columnar electrode forming plating resist film. 25 is formed. In this state, an opening 26 is formed in the columnar electrode forming plating resist film 25 in a portion corresponding to the connection pad portion 11 b (columnar electrode 12 formation region) of the wiring 11.

  Next, the columnar electrode 12 is formed on the upper surface of the connection pad portion 11b of the wiring 11 in the opening 26 of the columnar electrode forming plating resist film 25 by performing electrolytic plating of copper using the base metal layer 9 as a plating current path. To do. Next, the columnar electrode forming plating resist film 25 is stripped using a resist stripping solution. In this case, the columnar electrode forming plating resist film 25 swells and peels from the surface in contact with the resist stripping solution.

  Here, in the state in which the columnar electrode forming plating resist film 25 is formed, the upper insulating film 7 exists between the wirings 11 having the laminated structure of the base metal layer 9 and the upper metal layer 10. There is no room for the electrode forming plating resist film 25 to enter. Therefore, even when the interval between the wirings 11 becomes narrow, no resist residue of the columnar electrode forming plating resist film 25 is generated between the wirings 11, and the resist residue of the columnar electrode forming plating resist film 25 is not generated. It is possible to reliably prevent occurrence of a short circuit between the wirings 11 due to the above.

  After the columnar electrode forming plating resist film 25 is peeled in this way, the base metal layer 9 in a region other than under the wiring 11 is then removed by etching using the wiring 11 as a mask, as shown in FIG. The base metal layer 9 remains only in the opening 8 of the upper insulating film 7. As a result, as shown in FIG. 1, the base metal layer 9 and the upper metal layer 10 have a laminated structure, and the connection portion 11 a connected to the connection pad 2, the connection pad portion 11 b at the tip, and the gap therebetween A wiring 11 composed of the lead wire portion 11c is formed.

  Next, as shown in FIG. 8, a sealing film 13 made of epoxy resin or the like is formed on the upper surface of the upper insulating film 7 including the wiring 11, the base metal layer 9 and the columnar electrode 12. It is formed to be slightly thicker than the thickness. Therefore, in this state, the upper surface of the columnar electrode 12 is covered with the sealing film 13. Next, by appropriately grinding the upper surface side of the sealing film 13, the upper surface of the columnar electrode 12 is exposed and the sealing film 13 including the exposed upper surface of the columnar electrode 12 as shown in FIG. 9. The upper surface of the substrate is flattened. Next, as shown in FIG. 10, solder balls 14 are formed on the upper surface of the columnar electrode 12. Next, as shown in FIG. 11, when the semiconductor wafer 21 and the like are cut along the dicing line 22, a plurality of semiconductor devices shown in FIG. 1 are obtained.

(Reference embodiment 2)
FIG. 12 is a sectional view of a semiconductor device as a second embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that the wiring and the upper insulating film have two layers. That is, a first upper insulating film (lower upper insulating film) 31 a made of polyimide resin or the like is provided on the upper surface of the protective film 5. An opening 32 is provided in the first wiring formation region on the upper surface of the first upper insulating film 31 a so as to communicate with the opening 6 of the protective film 5.

  A first base metal layer 33 made of copper or the like is formed on the upper surface of the protective film 5 exposed through the opening 32 of the first upper insulating film 31a and the inner wall surface of the opening 32 of the first upper insulating film 31a. Is provided in a concave shape. A first upper metal layer 34 made of copper is provided inside the concave first metal layer 33. The first base metal layer 33 and the first upper metal layer 34 are laminated to form a first wiring 35 (lower surface side wiring). One end of the first wiring 35 is connected to the connection pad 2 through the openings 4 and 6 of the insulating film 3 and the protective film 5.

  Also in this case, the upper surface of the first base metal layer 33 provided on the inner wall surface of the opening 32 of the first upper insulating film 31a is flush with the upper surface of the first upper insulating film 31a. The upper surface of the first upper metal layer 34 is flush with or slightly lower than the upper surface of the first upper insulating film 31a. The first wiring 35 includes a connection portion 35a connected to the connection pad 2, a tip connection pad portion 35b, and a lead wire portion 35c therebetween.

  Here, one end portions (connection portions 35a) of all the first wirings 35 are connected to the connection pads 2 through the openings 4 and 6 of the insulating film 3 and the protective film 5, but some of the first wirings 35 are connected. One wiring 35 includes only a connecting portion 35a. Therefore, the number of the routing line portions 35c of the first wiring 35 is smaller than the number of the routing line portions 11c of the wiring 11 shown in FIG.

  A second upper layer insulating film (rewiring upper layer insulating film) 31b made of polyimide resin or the like is provided on the upper surfaces of the first wiring 35 and the first upper layer insulating film 31a. An opening 36 is provided in the second wiring formation region on the upper surface of the second upper insulating film 31b. In this case, some of the openings 36 are provided only in a region corresponding to the connection pad portion 35 b of the first wiring 35.

  The upper surface of the first upper insulating film 31a exposed through the opening 36 of the second upper insulating film 31b and the inner wall surface of the opening 36 of the second upper insulating film 31b are made of copper or the like. A base metal layer 37 is provided in a concave shape. A second upper metal layer 38 made of copper is provided inside the concave second metal layer 37. The second base metal layer 37 and the second upper metal layer 38 are stacked to constitute a second wiring (rewiring) 39.

  Also in this case, the upper surface of the second base metal layer 37 provided on the inner wall surface of the opening 36 of the second upper insulating film 31b is flush with the upper surface of the second upper insulating film 31b. The upper surface of the second upper metal layer 38 is flush with or slightly lower than the upper surface of the second upper insulating film 31b. The second wiring 39 includes a connection portion 39a, a tip connection pad portion 39b, and a lead wire portion 39c therebetween.

  One end portion (connecting portion 39a) of a part of the second wiring 39 is connected to the upper surface of the first wiring 35 including only the connecting portion 35a. The remaining second wiring 39 is island-shaped and includes only the connection pad portion 39 b, and is provided only on the upper surface of the connection pad portion 35 b of the first wiring 35. Here, the total number of the routing lines 35c and 39c of the first and second wirings 35 and 39 is the same as the number of the routing lines 11c of the wiring 11 shown in FIG.

  A columnar electrode 12 made of copper is provided on the upper surface of the connection pad portion 39 b of the second wiring 39. A sealing film 13 made of an epoxy resin or the like is provided on the upper surfaces of the second wiring 39 and the second upper layer insulating film 31 b so that the upper surface thereof is flush with the upper surface of the columnar electrode 12. A solder ball 14 is provided on the upper surface of the columnar electrode 12.

  In this semiconductor device, some of the first wirings 35 are made up of only the connection portions 35a, and some of the second wirings 39 are made up of only the connection pad portions 39b, so that the first and second wirings 35 and 39 are routed. Since the total number of the line portions 35c and 39c is the same as the number of the routing line portions 11b of the wiring 11 shown in FIG. 1, the routing line portions 35c and 39c of the first and second wirings 35 and 39 are routed. The degree of freedom can be increased as compared with the semiconductor device shown in FIG.

  Next, an example of a method for manufacturing this semiconductor device will be described. In this case, after the step shown in FIG. 3, as shown in FIG. 13, a first upper insulating film forming film made of polyimide resin or the like formed by spin coating or the like is formed on the upper surface of the protective film 5 by photolithography. By patterning by the method, the first upper insulating film 31a is formed. In this state, the opening 32 is formed in the first wiring formation region of the first upper insulating film 31 a so as to communicate with the opening 6 of the protective film 5.

  Next, as shown in FIG. 14, the upper surface of the connection pad 2 exposed through the openings 4, 6, 32 of the insulating film 3, the protective film 5, and the first upper insulating film 31a, the first upper insulating layer. A first base metal layer 33 made of copper or the like is formed by sputtering or the like on the upper surface of the protective film 5 and the surface of the first upper insulating film 31a exposed through the opening 32 of the film 31a. In this case, the first base metal layer 33 formed inside the opening 32 of the first upper insulating film 31a has a concave shape.

  Next, the first upper metal layer forming plating resist film 41 is formed by patterning a positive resist film applied by spin coating or the like on the upper surface of the first base metal layer 33 by photolithography. Form. In this state, an opening 42 is formed in the first upper metal layer forming plating resist film 41 in a portion corresponding to the first upper metal layer forming region. Also in this case, the size of the opening 42 of the first upper metal layer forming plating resist film 41 is equal to the thickness of the first base metal layer 33 than the size of the opening 32 of the first upper insulating film 31a. Only getting smaller.

  Next, by performing electrolytic plating of copper using the first base metal layer 33 as a plating current path, a concave first base in the opening 42 of the first upper metal layer forming plating resist film 41 is formed. A first upper metal layer 34 is formed inside the metal layer 33. Also in this case, the upper surface of the first upper metal layer 34 is set to be flush with or slightly lower than the upper surface of the first upper insulating film 31a.

  Next, the first upper metal layer forming plating resist film 41 is stripped using a resist stripping solution, and then the first base metal in a region other than the region under the first wiring 35 using the first wiring 35 as a mask. When the layer 33 is removed by etching, as shown in FIG. 15, the first base metal layer 33 remains only in the opening 32 of the first upper insulating film 31a.

  Next, as shown in FIG. 16, the first wiring 14, the first base metal layer 33, and the first upper insulating film 31 a are made of a polyimide resin or the like formed on the upper surface of the first upper insulating film 31 a by spin coating or the like. The second upper insulating film 31b is formed by patterning the film for forming the upper insulating film 2 by photolithography. In this state, an opening 36 is formed in the second upper metal layer formation region of the second upper insulating film 31b.

  Next, as shown in FIG. 17, the upper surface of the first wiring 35 and the surface of the second upper insulating film 31b exposed through the opening 36 of the second upper insulating film 31b are sputtered or the like. Then, a second base metal layer 37 made of copper or the like is formed. In this case, the second base metal layer 37 formed inside the opening 36 of the second upper insulating film 31b has a concave shape.

  Next, a positive resist film applied by spin coating or the like is patterned on the upper surface of the second base metal layer 37 by photolithography to form a second upper metal layer forming plating resist film 43. Form. In this state, an opening 44 is formed in the second upper metal layer forming plating resist film 43 in a portion corresponding to the second upper metal layer forming region. Also in this case, the size of the opening 44 of the second upper metal layer forming plating resist film 43 is equal to the thickness of the second base metal layer 37 than the size of the opening 36 of the second upper insulating film 31b. Only getting smaller.

  Next, by performing copper electroplating using the second base metal layer 37 as a plating current path, a concave second base in the opening 44 of the second upper metal layer forming plating resist film 43 is formed. A second upper metal layer 38 is formed inside the metal layer 37. Also in this case, the upper surface of the second upper metal layer 38 is set to be flush with or slightly lower than the upper surface of the second upper insulating film 31b. Next, the second upper metal layer forming plating resist film 43 is stripped using a resist stripping solution.

  Next, as shown in FIG. 18, a negative type dry film resist is laminated on the upper surfaces of the second upper metal layer 38 and the second base metal layer 37, and the negative type dry film resist is photolithography-processed. The columnar electrode forming plating resist film 45 is formed by patterning by the above. In this state, an opening 46 is formed in the columnar electrode forming plating resist film 45 in a portion corresponding to the connection pad portion 39 b (columnar electrode 12 formation region) of the second wiring 39.

  Next, by performing copper electroplating using the second base metal layer 37 as a plating current path, the upper surface of the connection pad portion 39b of the second wiring 39 in the opening 46 of the columnar electrode forming plating resist film 45 The columnar electrode 12 is formed on the substrate. Next, the columnar electrode forming plating resist film 45 is stripped using a resist stripping solution. Also in this case, the columnar electrode forming plating resist film 45 swells and peels from the surface in contact with the resist stripping solution.

  Here, in the state in which the columnar electrode forming plating resist film 45 is formed, the second upper layer insulating film 31 b exists between the second wirings 39, so that the columnar electrode forming plating resist is present between the second wirings 39. There is no room for the membrane 45 to enter. Therefore, even when the interval between the second wirings 39 is narrow, the resist residue of the columnar electrode forming plating resist film 45 is not generated between the second wirings 39, and the columnar electrode forming plating is performed. The occurrence of a short circuit between the second wirings 39 due to the resist residue of the resist film 45 can be reliably prevented.

  After the columnar electrode forming plating resist film 45 is peeled in this way, the second base metal layer 37 in the region other than the area under the second wiring 39 is then removed by etching using the second wiring 39 as a mask. Then, as shown in FIG. 19, the second base metal layer 37 remains only in the opening 36 of the second upper insulating film 31b. Thereafter, similarly to the case of the first embodiment, a plurality of semiconductor devices shown in FIG. 12 are obtained through the sealing film 13 forming step, the solder ball 14 forming step, and the dicing step.

(First embodiment)
FIG. 20 is a sectional view of the semiconductor device as the first embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 12 in that an opening 51 is formed in the first upper insulating film 31a in a region corresponding to the connection pad portion 39b of the second wiring 39 on which the columnar electrode 12 is formed. In the opening 51, a dummy connection pad portion 54 including a dummy base metal layer 52 and a dummy upper metal layer 53 laminated thereon is provided in an island shape.

  In this semiconductor device, since the dummy connection pad portion 54 is provided in an island shape in the opening 51 of the first upper insulating film 31a below the connection pad portion 39b of the second wiring 39 below the columnar electrode 12, The heights of the pedestal portions of the columnar electrodes 12 can be made uniform. Note that the manufacturing method of the semiconductor device can be easily understood from the manufacturing method of the second embodiment, and thus the description thereof is omitted.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Connection pad 3 Insulating film 5 Protective film 7 Upper layer insulating film 9 Base metal layer 10 Upper metal layer 11 Wiring 12 Columnar electrode 13 Sealing film 14 Solder ball 21 Semiconductor wafer 23 Plated resist film for upper metal layer formation 25 Columnar Plating resist film for electrode formation

Claims (4)

A semiconductor substrate having a plurality of connection pads on the upper surface, an insulating film provided on the semiconductor substrate and having an opening in a portion corresponding to the connection pads, an upper surface of the insulating film, and a lower surface side wiring formation region A lower surface side upper insulating film having an opening in a portion corresponding to the lower surface side wiring provided in the opening of the lower surface side upper insulating film and connected to the connection pad through the opening of the insulating film, A rewiring upper layer insulating film provided on the upper surface of the lower surface side upper layer insulating film and the lower surface side wiring and having an opening in a portion corresponding to a rewiring formation region, and the lower surface side in the opening of the rewiring upper layer insulating film Re-wiring provided so as to be connected to the wiring and having an upper surface flush with or lower than the upper surface of the re-wiring upper insulating film, and a columnar shape provided on the connection pad portion of the re-wiring With electrodes ,
Some of the lower surface side wirings consist only of connection parts connected to the connection pads, and some of the rewirings consist only of connection pad parts connected to connection pad parts of the remaining lower layer side wirings,
A semiconductor device, wherein a dummy connection pad portion is provided in an island shape below a connection pad portion of the rewiring connected to the lower surface side wiring composed of only a connection portion on the insulating film.   2. The invention according to claim 1, wherein the rewiring provided in the opening of the rewiring upper insulating film includes a base metal layer formed on a bottom surface and a side surface of the opening of the rewiring upper insulating film, and the base A semiconductor device comprising an upper metal layer formed on a metal layer.   2. The semiconductor device according to claim 1, wherein a sealing film is provided around the columnar electrode.   4. The semiconductor device according to claim 3, wherein a solder ball is provided on the columnar electrode.

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