JP2004172163A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

Info

Publication number
JP2004172163A
JP2004172163A JP2002332732A JP2002332732A JP2004172163A JP 2004172163 A JP2004172163 A JP 2004172163A JP 2002332732 A JP2002332732 A JP 2002332732A JP 2002332732 A JP2002332732 A JP 2002332732A JP 2004172163 A JP2004172163 A JP 2004172163A
Authority
JP
Japan
Prior art keywords
electrode
post
post electrode
semiconductor device
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002332732A
Other languages
Japanese (ja)
Other versions
JP3664707B2 (en
Inventor
Kazumi Watase
和美 渡瀬
Hiroki Naraoka
浩喜 楢岡
Ryuichi Sawara
隆一 佐原
Minoru Fujisaku
実 藤作
Takahiro Nakano
高宏 中野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2002332732A priority Critical patent/JP3664707B2/en
Publication of JP2004172163A publication Critical patent/JP2004172163A/en
Application granted granted Critical
Publication of JP3664707B2 publication Critical patent/JP3664707B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the semiconductor device for alleviating stress on the mounting substrate and external terminal and for solving the missing failure of post electrode. <P>SOLUTION: The semiconductor device comprises: a semiconductor substrate (10); an element electrode (11) formed on the semiconductor substrate surface; an insulating resin layer (12) having an aperture; metal wirings (13, 15) including an external terminal forming land (21) which is continuously formed over the insulating resin layer (12) from the element electrode (11), a first post electrode (17) electrically connected to the metal wirings; a second post electrode (19) formed thereon and electrically connected thereto in the circumferential length shorter than that of the first post electrode; a sealing resin (22) formed on the insulating resin layer (12) to cover the side surface of the metal wirings(13, 15), first post electrode (17) and the second post electrode (19); and a solder bump (23) formed as an external terminal on the surface of the second post electrode (19). <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は、情報通信機器、事務用電子機器に利用される半導体の集積回路部を内蔵し、さらに外部電極としてポスト電極を有する半導体装置及びその製造方法に関する。特に外部電極と封止樹脂との密着性の向上及び印刷によって形成される半田バンプの狭ピッチ化、多ピン化を実現する半導体装置及びその製造方法に関するものである。
【0002】
【従来の技術】
近年、半導体装置及びその製造方法は電子機器の小型化、高密度化に伴い、小型化、高密度化を要求されるようになった。
【0003】
以下にウェハレベルCSP(Chip Size Package)のおいてポスト電極を外部電極とし、半田バンプ部を外部端子とする半導体装置及びその製造方法について断面図を参照しながら、説明する。
【0004】
図5(下記特許文献1の図面)において、101は半導体基板、102は素子電極、109はパッシベーション膜、103は絶縁樹脂層、104は金属配線、108は外部端子形成用ランド部、105はポスト電極、106は半田バンプ、107はモールド樹脂である。次に製造方法については、素子電極102から絶縁膜層103上に亘って金属配線104及び外部端子形成用ランド部108が形成され、外部端子形成用ランド部上にポスト電極105を形成する。絶縁樹脂層103及び金属配線104、ポスト電極105を覆う封止樹脂107を形成し、ポスト電極105表面上に半田バンプ106を形成する。ウェハレベルにより、小型化、高密度化が図れ、ポスト電極の構造により実装基板からの応力を緩和し、印刷による半田バンプ形成により、更なる狭ピッチ対応の外部端子を形成することができる。
【0005】
【特許文献1】
特開2001−223242
【0006】
【発明が解決すようとする課題】
しかしながら、前記従来の半導体装置においては、以下のような諸問題があった。前記従来の半導体装置は更なる狭ピッチ化、多ピン化への対応の為、外部端子である半田バンプにつながるポスト電極は小径化を要求される。ところが、実装基板及び外部端子である半田バンプから生じる応力によりポスト電極の側面を封止樹脂で覆っても、ポスト電極小径化に伴い、ポスト電極の抜け不良が発生する。また応力を緩和させる為にポスト電極の高さをかせぐ必要があるが、フォトリソ工程によるポスト電極形成にはアスペクト比による小径化の限界がある。
【0007】
本発明は、前記従来の問題を解決するため、実装基板及び外部端子の応力を緩和し、ポスト電極の抜け不良を解消する半導体装置及びその製造方法を提供することを目的とする。
【0008】
【課題を解決するための手段】
前記目的を達成するため本発明の半導体装置は、半導体基板と、前記半導体基板表面上に形成された素子電極と、前記素子電極を露出させるように部分的に開口した絶縁樹脂層と、前記素子電極上から前記絶縁樹脂層の上に亘って連続的に形成された外部端子形成用ランド部を含む金属配線と、前記外部端子形成用ランド部上に電気的に接続された少なくとも2層以上のポスト電極と、前記絶縁樹脂層上であって、かつ前記金属配線と前記2層以上のポスト電極側面上を覆うように形成された封止樹脂と、前記2層以上のポスト電極の最上電極表面に外部端子として形成された半田バンプを含む半導体装置であって、前記2層以上のポスト電極のうち、上層電極は下層電極に比べてポスト周辺長が短く形成されていることを特徴とする。
【0009】
次に本発明の半導体装置の製造方法は、半導体基板の素子電極の上方に位置する絶縁樹脂層の領域を選択的に除去して、前記素子電極を露出させる開口部を形成する第1の工程と、前記開口部に露出した前記素子電極上から前記絶縁樹脂層上に亘り、一部が外部端子形成用ランド部として素子電極に電気的に接続される金属配線を形成する第2の工程と、前記外部端子形成用ランド部上に電気的に接続された前記第一ポスト電極を形成する第3の工程と、前記第一ポスト電極上に電気的に接続されて外部電極の機能を有する少なくとも1層の第二ポスト電極を、上層電極は下層電極に比べてポスト周辺長が短く形成する第4の工程と、前記絶縁樹脂層及び前記金属配線及び前記少なくとも2層のポスト電極を保護する封止樹脂を形成する第5の工程と、前記ポスト電極の最表面上に半田バンプを形成する第6の工程とを含むことを特徴とする。
【0010】
前記本発明においては、前記外部端子形成用ランド部上に電気的に接続された前記第一ポスト電極及び第二ポスト電極の半導体基板表面に平行な断面形状は円形、楕円、正方形、長方形、及び前記以外の多角形から選ばれる少なくとも一つの形状であることが好ましい。
【0011】
【発明の実施の形態】
本発明によれば、実装基板及び外部端子の応力を、2層以上で形成された階段状のポスト電極構造により、下段と上段のポスト電極の直径及び断面形状の差による封止樹脂のかぶりで実装基板及び外部端子である半田バンプの応力を緩和し、ポスト電極の抜け不良を解消できる。また、外部電極としての機能を有する最上段のポスト電極以外のポスト電極は、外部端子のピッチに制約されず、ポスト電極の直径を大きくすることで、封止樹脂との密着性を増加し、実装基板及び外部端子である半田バンプの応力を分散できる。これにより、抜け不良を生じないポスト電極を確保できる。
【0012】
本発明において、外部端子形成用ランド部上に2層以上の階段状のポスト電極を形成するが、階段状のポスト電極は何層でも形成可能であると共に、フォトリソ工程によってポスト電極の形状を円、多角形、四角等に自由に形成できる。階段状にポスト電極を形成することによって、封止樹脂のポスト電極へのかぶりが生じ、ポスト電極の抜け不良を防ぐことができる。最上部のポスト電極以外のポスト電極はその直径をある程度自由に設定し、封止樹脂と接する表面積を大きくすることで更なる封止樹脂との密着性を向上できる。
【0013】
以下本発明の実施例について図面を参照しながら、説明する。
【0014】
図1は本実装形態における半導体装置を封止樹脂の一部を部分的に、また全部開封して示す上面図である。図2は本実装形態の半導体装置の断面図である。次に図3は(a)〜(d)、図4(a)〜(d)は本実装形態における半導体装置の製造工程を示す断面図である。
【0015】
まず図1、図2において10はトランジスタ等の半導体素子によって構成される半導体集積回路を内部に有する半導体基板である。11は半導体基板上にある素子電極、24はSG膜、12は絶縁樹脂層、17は第一ポスト電極、19は第二ポスト電極、20は外部端子形成用ランド部、21は金属配線、22は封止樹脂、23は半田バンプである。
【0016】
本実装形態ではポスト電極構造を有することで実装基板及び外部端子である半田バンプから生じる応力をポスト電極で緩和し、高い実装信頼性を確保することが可能である。また階段状のポスト電極構造により、ポスト電極の抜け不良を改善することができる。また外部電極としての機能を有する最上段のポスト電極は狭ピッチ化、及び多ピン化に対応するために電極の更なる小径化が要求されるが、最上段以外のポスト電極においては小径化すること無く、封止樹脂との接触面積を維持することで、更なる封止樹脂との密着性を向上させることが可能であり、更なる高信頼性の実装を確保できる。
【0017】
次に本実装形態の半導体装置での製造方法について、図3(a)〜(d)、図4(a)〜(d)を参照しながら説明する。図3(a)〜(d)、図4(a)〜(d)は、図1及び図2に示す半導体装置の構造を実現するための製造工程を示す断面図である。
【0018】
図3(a)に示すように、半導体基板上にスピンコートで感光性を有する絶縁材料を塗布、乾燥し、露光及び現像とを順次に行い、半導体基板10上の素子電極11における領域を選択的に除去し、複数の素子電極11を露出させた開口部を有する絶縁樹脂層12を形成する。尚、感光性を有する絶縁層12としてはエステル結合型ポリイミドまたはアクリレート系エポキシ等のポリマーでもよく、感光性であればよい。また感光性を有する絶縁樹脂層12はフィルム状に予め形成された材料を用いても構わない。その場合は絶縁樹脂層12を半導体基板10上に貼り合わせ、露光及び現像によって絶縁層12に開口部を形成し、素子電極11を露出させる。
【0019】
次に図3(b)に示すように、絶縁樹脂層12及び開口部が形成された素子電極11上全面において、スパッタリング法、真空蒸着法、CVD法または無電解メッキ法の薄膜形成技術により、例えば、厚みが0.2μm程度のTiW膜とその上に形成された厚みが0.5μm程度のCu膜からなる薄膜金属層13を形成する。
【0020】
次に図3(c)に示すように、スピンコートでポジ型感光性レジスト膜またはネガ型感光性レジスト膜を覆い、周知の露光、現像によりメッキレジスト14を形成する。パターン形成されたメッキレジスト14のパターン部以外において、薄膜金属層13上に電解メッキ等の厚膜形成技術により厚膜金属層15を選択的に形成する。例えば厚みが5μm程度のCu膜からなる厚膜金属層15を選択的に形成する。
【0021】
次に図3(d)に示すように、厚膜金属層15を形成し、メッキレジスト14を溶融除去後、ポジ型感光性レジスト膜またはネガ型感光性レジスト膜を多い、周知の露光、現像によりメッキレジスト16を形成する。ここで感光性を有するメッキレジスト16はフィルム状に予め形成された材料を用いても構わない。パターン形成されたメッキレジスト16のパターン部以外において、厚膜金属層15上に電解メッキ等のポスト形成技術により第一ポスト電極17を選択的に形成する。例えば、電極の材料はCuを用い、形成方法は電解メッキを用いると、0.4mmピッチの外部端子ピッチであれば、厚みが50μm程度のポスト電極の断面形状が円形の場合、直径が200μm程度の第一ポスト電極17を選択的に形成できる。なお、フォトリソ工程にて形成するポスト電極の断面形状は、封止樹脂との密着面積を大きくすることを目的に、多角形や星形に形成することも可能である。
【0022】
次に図4(a)に示すように、第一ポスト電極17を形成、メッキレジスト16を溶融除去後、更にポジ型感光性レジスト膜またはネガ型感光性レジスト膜を多い、周知の露光、現像によりメッキレジスト18を形成する。ここで感光性を有するメッキレジスト18はフィルム状に予め形成された材料を用いても構わない。パターン形成されたメッキレジスト18のパターン部以外において、第一ポスト電極17上に電解メッキ等の形成技術により第二ポスト電極19を選択的に形成する。例えば、第一ポスト電極17の直径が200μm程度であれば、第一ポスト電極17上に180μm程度の直径を持つ第二ポスト電極19を形成する。
【0023】
電極材料はCuを用いて、電解メッキを施しても良い。第一ポスト電極17上に形成された第二ポスト電極19は、電極中心部が第一ポスト電極17の中心部に位置していなくとも階段状の部分が形成されていれば構わない。なお、フォトリソ工程にて形成するポスト電極19の断面形状は、第一ポスト電極17の断面形状と同形でも異形でも構わない。
【0024】
次に図4(b)に示すように、第二ポスト電極19を形成後、メッキレジスト18を溶融除去し、薄膜金属層13を溶融除去できるエッチング液を施す。例えばCu膜に対しては塩化鉄第二銅溶液で、TiW膜に対しては過酸化水素水で全面エッチングすると、厚膜金属層15よりも層厚が薄い薄膜金属層13が先行して除去される。この工程により半導体基板10において所定の金属配線21、外部端子形成用ランド20が形成される。例えばCuメッキにて形成された金属配線21は厚み5μmに対して、Line/Space=20/20μmの配線形成が可能である。
【0025】
次に図4(c)に示すように、金属配線21及び絶縁樹脂層12上を樹脂で覆い、加圧、加温を施し、第二ポスト電極の表面が露出するように封止樹脂22を形成する。例えば封止樹脂はエポキシ樹脂を用いて、厚みは50〜100μmで形成する。封止樹脂22によって、金属配線22、外部端子形成用ランド20、第一ポスト電極17、第二ポスト電極19の側面は溶融したクリーム半田から保護される。
【0026】
次に図4(d)に示すように、第二ポスト電極19の表面上に酸化防止処理を施し、表面張力により接している第二ポスト電極19の表面に半田バンプ23が形成され、絶縁材料である封止樹脂22表面上には半田バンプは形成されない。この時の加熱温度はクリーム半田の融点以上である。印刷工程において、マスク20は一般的に用いられるマスクであっても、金属マスクを用いても構わない。
【0027】
【発明の効果】
以上説明したとおり、本発明の半導体装置は、を2層以上の階段状ポスト電極構造により、実装時の実装基板及び外部端子によって生じる応力を緩和し、ポスト電極抜け不良を解消することができる。また階段状ポスト電極により、最上段のポスト電極のみが外部端子である印刷による半田バンプ形成の影響を受けるが、最上段以外のポスト電極は電極の直径を大きくし、ポスト電極側面と封止樹脂との密着面積を増加させ、更なる応力緩和を図ることができる。
【図面の簡単な説明】
【図1】本発明の一実装形態における半導体装置の封止樹脂を部分的に及び全面開封して示す平面図である。
【図2】本発明の一実装形態における半導体装置の断面図である。
【図3】(a)〜(d)は、本発明の一実装形態における半導体装置の製造工程のうち絶縁樹脂層形成から第一ポスト電極部形成までの製造工程を示す断面図である。
【図4】(a)〜(d)は、本発明の一実装形態における半導体装置の製造工程のうち第二ポスト電極形成から半田バンプ形成までの製造工程を示す断面図である。
【図5】従来の金属バンプを形成した半導体装置の断面図である。
【符号の説明】
10,101 半導体基板
11,102 半導体素子電極
12,103 絶縁樹脂層
13 薄膜金属層
14 メッキレジスト
15 厚膜金属層
16 メッキレジスト
17 第一ポスト電極
18 メッキレジスト
19 第二ポスト電極
20 外部端子形成用ランド
21 金属配線
22,107 封止樹脂
23,106 半田バンプ
24,109 パッシベーション膜
104 金属配線
105 ポスト電極
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a built-in semiconductor integrated circuit portion used for information communication equipment and office electronic equipment, and further having a post electrode as an external electrode, and a method of manufacturing the same. In particular, the present invention relates to a semiconductor device that realizes improvement in adhesion between an external electrode and a sealing resin, narrowing of pitch of solder bumps formed by printing, and increase in number of pins, and a method of manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art In recent years, as a semiconductor device and a method for manufacturing the same have been required to be smaller and denser as electronic devices have become smaller and denser.
[0003]
Hereinafter, a semiconductor device using a post electrode as an external electrode and a solder bump portion as an external terminal in a wafer level CSP (Chip Size Package) and a method of manufacturing the same will be described with reference to cross-sectional views.
[0004]
In FIG. 5 (Patent Document 1 below), 101 is a semiconductor substrate, 102 is an element electrode, 109 is a passivation film, 103 is an insulating resin layer, 104 is a metal wiring, 108 is a land portion for forming external terminals, and 105 is a post. The electrodes, 106 are solder bumps, and 107 is a mold resin. Next, in the manufacturing method, a metal wiring 104 and an external terminal forming land portion 108 are formed from the element electrode 102 to the insulating film layer 103, and a post electrode 105 is formed on the external terminal forming land portion. A sealing resin 107 covering the insulating resin layer 103, the metal wiring 104, and the post electrode 105 is formed, and a solder bump 106 is formed on the surface of the post electrode 105. The miniaturization and high density can be achieved at the wafer level, the stress from the mounting substrate can be reduced by the structure of the post electrode, and external terminals corresponding to a further narrow pitch can be formed by forming solder bumps by printing.
[0005]
[Patent Document 1]
JP-A-2001-223242
[0006]
[Problems to be solved by the invention]
However, the conventional semiconductor device has the following problems. In the conventional semiconductor device, in order to cope with a further reduction in pitch and an increase in the number of pins, a post electrode connected to a solder bump, which is an external terminal, is required to have a smaller diameter. However, even if the side surface of the post electrode is covered with the sealing resin due to the stress generated from the mounting board and the solder bumps serving as the external terminals, the post electrode may fail to come off due to the reduction in the diameter of the post electrode. Further, it is necessary to increase the height of the post electrode in order to relieve the stress. However, there is a limit in reducing the diameter of the post electrode by the photolithography process due to the aspect ratio.
[0007]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which alleviate the stress of the mounting board and the external terminals and eliminate the post electrode disconnection failure in order to solve the conventional problem.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device according to the present invention includes a semiconductor substrate, an element electrode formed on a surface of the semiconductor substrate, an insulating resin layer partially opened so as to expose the element electrode, A metal wiring including an external terminal forming land portion formed continuously from over the electrode to the insulating resin layer; and at least two or more layers electrically connected to the external terminal forming land portion. A post electrode; a sealing resin formed on the insulating resin layer so as to cover the metal wiring and a side surface of the post electrode of the two or more layers; and a top electrode surface of the post electrode of the two or more layers. A semiconductor device including solder bumps formed as external terminals, wherein an upper electrode of the two or more layers of post electrodes is formed to have a shorter post peripheral length than a lower layer electrode.
[0009]
Next, in a method of manufacturing a semiconductor device according to the present invention, a first step of selectively removing a region of an insulating resin layer located above an element electrode of a semiconductor substrate to form an opening exposing the element electrode A second step of forming a metal wiring partially connected to the element electrode as a land part for forming an external terminal, from the element electrode exposed to the opening to the insulating resin layer; A third step of forming the first post electrode electrically connected to the external terminal forming land portion, and at least having a function of an external electrode electrically connected to the first post electrode. A fourth step of forming one layer of the second post electrode, the upper electrode having a shorter post peripheral length than the lower layer electrode, and a sealing step of protecting the insulating resin layer, the metal wiring, and the at least two layers of post electrodes. Fifth forming resin A step, characterized in that it comprises a sixth step of forming a solder bump on the top surface of the post electrode.
[0010]
In the present invention, the cross-sectional shape of the first post electrode and the second post electrode electrically connected on the external terminal forming land portion parallel to the semiconductor substrate surface is circular, elliptical, square, rectangular, and It is preferably at least one shape selected from polygons other than the above.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
According to the present invention, the stress of the mounting substrate and the external terminals is reduced by the fogging of the sealing resin due to the difference in diameter and cross-sectional shape between the lower and upper post electrodes due to the step-like post electrode structure formed of two or more layers. The stress of the mounting board and the solder bumps serving as the external terminals can be relaxed, and the failure in removing the post electrode can be eliminated. In addition, the post electrodes other than the uppermost post electrode having a function as an external electrode are not restricted by the pitch of the external terminals, and by increasing the diameter of the post electrode, the adhesion with the sealing resin is increased, The stress of the mounting board and the solder bumps as the external terminals can be dispersed. As a result, a post electrode that does not cause a detachment failure can be secured.
[0012]
In the present invention, a step electrode of two or more layers is formed on the land portion for forming the external terminal. However, any number of layers of the step electrode can be formed, and the shape of the post electrode is made circular by a photolithography process. , Polygons, squares, etc. By forming the post electrode in a stepwise manner, fogging of the sealing resin onto the post electrode occurs, and it is possible to prevent the post electrode from slipping out. The diameter of the post electrodes other than the uppermost post electrode can be set to some extent freely, and the surface area in contact with the sealing resin can be increased to further improve the adhesion with the sealing resin.
[0013]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0014]
FIG. 1 is a top view showing the semiconductor device according to the present embodiment with a part of a sealing resin partially or entirely opened. FIG. 2 is a cross-sectional view of the semiconductor device of the present embodiment. Next, FIGS. 3A to 3D are cross-sectional views showing manufacturing steps of the semiconductor device in the present embodiment.
[0015]
First, in FIGS. 1 and 2, reference numeral 10 denotes a semiconductor substrate having therein a semiconductor integrated circuit including a semiconductor element such as a transistor. 11 is an element electrode on the semiconductor substrate, 24 is an SG film, 12 is an insulating resin layer, 17 is a first post electrode, 19 is a second post electrode, 20 is a land portion for forming an external terminal, 21 is a metal wiring, 22 Is a sealing resin, and 23 is a solder bump.
[0016]
In this embodiment, the post electrode structure allows the post electrode to reduce the stress generated from the mounting board and the solder bumps as the external terminals, thereby ensuring high mounting reliability. Further, with the step-like post electrode structure, it is possible to improve the failure in removing the post electrode. In addition, the uppermost post electrode having the function as an external electrode is required to have a smaller pitch in order to cope with a narrow pitch and a multi-pin structure, but the post electrode other than the uppermost one has a smaller diameter. By maintaining the contact area with the sealing resin without any problem, it is possible to further improve the adhesiveness with the sealing resin, and it is possible to secure mounting with higher reliability.
[0017]
Next, a method of manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 3 (a) to 3 (d) and FIGS. 4 (a) to 4 (d). FIGS. 3A to 3D and 4A to 4D are cross-sectional views showing manufacturing steps for realizing the structure of the semiconductor device shown in FIGS.
[0018]
As shown in FIG. 3A, an insulating material having photosensitivity is applied on a semiconductor substrate by spin coating, dried, exposed and developed in order, and a region in the element electrode 11 on the semiconductor substrate 10 is selected. Then, an insulating resin layer 12 having an opening exposing the plurality of element electrodes 11 is formed. The insulating layer 12 having photosensitivity may be a polymer such as an ester bond type polyimide or an acrylate-based epoxy, and may be any photosensitivity. The insulating resin layer 12 having photosensitivity may be formed of a material formed in a film shape in advance. In that case, the insulating resin layer 12 is bonded on the semiconductor substrate 10, an opening is formed in the insulating layer 12 by exposure and development, and the element electrode 11 is exposed.
[0019]
Next, as shown in FIG. 3B, the entire surface of the element electrode 11 on which the insulating resin layer 12 and the opening are formed is formed by a thin film forming technique such as a sputtering method, a vacuum deposition method, a CVD method or an electroless plating method. For example, a thin metal layer 13 made of a TiW film having a thickness of about 0.2 μm and a Cu film formed thereon having a thickness of about 0.5 μm is formed.
[0020]
Next, as shown in FIG. 3C, the positive photosensitive resist film or the negative photosensitive resist film is covered by spin coating, and a plating resist 14 is formed by well-known exposure and development. A thick metal layer 15 is selectively formed on the thin metal layer 13 by using a thick film forming technique such as electrolytic plating, except for the patterned portion of the patterned plating resist 14. For example, the thick metal layer 15 made of a Cu film having a thickness of about 5 μm is selectively formed.
[0021]
Next, as shown in FIG. 3D, a thick metal layer 15 is formed, and after the plating resist 14 is melted and removed, a well-known exposure and development method including a lot of a positive photosensitive resist film or a negative photosensitive resist film is used. To form a plating resist 16. Here, as the plating resist 16 having photosensitivity, a material formed in a film shape in advance may be used. The first post electrode 17 is selectively formed on the thick metal layer 15 by a post forming technique such as electrolytic plating, except for the pattern portion of the patterned plating resist 16. For example, when the electrode material is Cu and the forming method is electrolytic plating, if the external terminal pitch is 0.4 mm, the post electrode having a thickness of about 50 μm is circular and the cross-sectional shape of the post electrode is about 200 μm. Of the first post electrode 17 can be selectively formed. Note that the cross-sectional shape of the post electrode formed in the photolithography step can be polygonal or star-shaped for the purpose of increasing the area of adhesion to the sealing resin.
[0022]
Next, as shown in FIG. 4A, the first post electrode 17 is formed, and the plating resist 16 is melted and removed. Then, the well-known exposure and development are further performed with a positive photosensitive resist film or a negative photosensitive resist film. To form a plating resist 18. Here, the plating resist 18 having photosensitivity may be a material formed in a film shape in advance. The second post electrode 19 is selectively formed on the first post electrode 17 by a forming technique such as electrolytic plating, except for the pattern portion of the patterned plating resist 18. For example, if the diameter of the first post electrode 17 is about 200 μm, the second post electrode 19 having a diameter of about 180 μm is formed on the first post electrode 17.
[0023]
Electrode plating may be performed using Cu as an electrode material. The second post electrode 19 formed on the first post electrode 17 may have a stepped portion even if the electrode center is not located at the center of the first post electrode 17. Note that the cross-sectional shape of the post electrode 19 formed in the photolithography process may be the same as or different from the cross-sectional shape of the first post electrode 17.
[0024]
Next, as shown in FIG. 4B, after forming the second post electrode 19, the plating resist 18 is melted and removed, and an etching solution capable of melting and removing the thin film metal layer 13 is applied. For example, when the Cu film is entirely etched with a cupric iron chloride solution, and the TiW film is entirely etched with a hydrogen peroxide solution, the thin film metal layer 13 thinner than the thick metal layer 15 is removed first. Is done. Through this process, predetermined metal wirings 21 and lands 20 for forming external terminals are formed on the semiconductor substrate 10. For example, for a metal wiring 21 formed by Cu plating, a line / space = 20/20 μm wiring can be formed for a thickness of 5 μm.
[0025]
Next, as shown in FIG. 4C, the metal wiring 21 and the insulating resin layer 12 are covered with a resin, pressure and heating are applied, and the sealing resin 22 is removed so that the surface of the second post electrode is exposed. Form. For example, the thickness of the sealing resin is 50 to 100 μm using an epoxy resin. The side surfaces of the metal wiring 22, the external terminal forming land 20, the first post electrode 17, and the second post electrode 19 are protected from the melted solder by the sealing resin 22.
[0026]
Next, as shown in FIG. 4D, an antioxidant treatment is performed on the surface of the second post electrode 19, and a solder bump 23 is formed on the surface of the second post electrode 19 that is in contact with the surface by the surface tension. No solder bump is formed on the surface of the sealing resin 22. The heating temperature at this time is equal to or higher than the melting point of the cream solder. In the printing process, the mask 20 may be a commonly used mask or a metal mask.
[0027]
【The invention's effect】
As described above, according to the semiconductor device of the present invention, the stepped post electrode structure of two or more layers can alleviate the stress generated by the mounting substrate and the external terminals at the time of mounting, and can eliminate the defective post electrode. In addition, the stepped post electrodes are affected by the formation of solder bumps by printing, in which only the uppermost post electrode is an external terminal. Can be further increased, and the stress can be further relaxed.
[Brief description of the drawings]
FIG. 1 is a plan view showing a sealing resin of a semiconductor device according to an embodiment of the present invention, partially and entirely opened.
FIG. 2 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
FIGS. 3A to 3D are cross-sectional views illustrating a manufacturing process from formation of an insulating resin layer to formation of a first post electrode portion in a manufacturing process of a semiconductor device according to an embodiment of the present invention.
FIGS. 4A to 4D are cross-sectional views illustrating a manufacturing process from the formation of a second post electrode to the formation of a solder bump in a manufacturing process of a semiconductor device according to an embodiment of the present invention.
FIG. 5 is a cross-sectional view of a conventional semiconductor device on which metal bumps are formed.
[Explanation of symbols]
10, 101 Semiconductor substrate 11, 102 Semiconductor element electrode 12, 103 Insulating resin layer 13 Thin metal layer 14 Plating resist 15 Thick metal layer 16 Plating resist 17 First post electrode 18 Plating resist 19 Second post electrode 20 For forming external terminals Land 21 Metal wiring 22, 107 Sealing resin 23, 106 Solder bump 24, 109 Passivation film 104 Metal wiring 105 Post electrode

Claims (4)

半導体基板と、
前記半導体基板表面上に形成された素子電極と、
前記素子電極を露出させるように部分的に開口した絶縁樹脂層と、
前記素子電極上から前記絶縁樹脂層の上に亘って連続的に形成された外部端子形成用ランド部を含む金属配線と、
前記外部端子形成用ランド部上に電気的に接続された少なくとも2層以上のポスト電極と、
前記絶縁樹脂層上であって、かつ前記金属配線と前記2層以上のポスト電極側面上を覆うように形成された封止樹脂と、
前記2層以上のポスト電極の最上電極表面に外部端子として形成された半田バンプを含む半導体装置であって、
前記2層以上のポスト電極のうち、上層電極は下層電極に比べてポスト周辺長が短く形成されていることを特徴とする半導体装置。
A semiconductor substrate;
An element electrode formed on the surface of the semiconductor substrate,
An insulating resin layer partially opened to expose the element electrode,
A metal wiring including an external terminal forming land portion continuously formed over the element electrode over the insulating resin layer;
At least two or more layers of post electrodes electrically connected to the external terminal forming lands,
A sealing resin formed on the insulating resin layer and so as to cover the metal wiring and the side surface of the post electrode of the two or more layers;
A semiconductor device including a solder bump formed as an external terminal on an uppermost electrode surface of the two or more layers of post electrodes,
The semiconductor device according to claim 2, wherein, of the post electrodes of the two or more layers, the upper layer electrode is formed to have a shorter post peripheral length than the lower layer electrode.
前記外部端子形成用ランド部上に電気的に接続された前記第一ポスト電極及び第二ポスト電極の半導体基板表面に平行な断面形状は円形、楕円、正方形、長方形、及び前記以外の多角形から選ばれる少なくとも一つの形状である請求項1に記載の半導体装置。The cross-sectional shape parallel to the semiconductor substrate surface of the first post electrode and the second post electrode electrically connected to the external terminal forming land portion is a circle, an ellipse, a square, a rectangle, and a polygon other than the above. The semiconductor device according to claim 1, wherein the semiconductor device has at least one shape selected. 半導体基板の素子電極の上方に位置する絶縁樹脂層の領域を選択的に除去して、前記素子電極を露出させて開口部を形成する第1の工程と、
前記開口部に露出した前記素子電極上から前記絶縁樹脂層上に亘り、一部が外部端子形成用ランド部として素子電極に電気的に接続される金属配線を形成する第2の工程と、
前記外部端子形成用ランド部上に電気的に接続された前記第一ポスト電極を形成する第3の工程と、
前記第一ポスト電極上に電気的に接続されて外部電極の機能を有する少なくとも1層の第二ポスト電極を、上層電極は下層電極に比べてポスト周辺長が短く形成する第4の工程と、
前記絶縁樹脂層及び前記金属配線及び前記少なくとも2層のポスト電極を保護する封止樹脂を形成する第5の工程と、
前記ポスト電極の最表面上に半田バンプを形成する第6の工程とを含むことを特徴とする半導体装置の製造方法。
A first step of selectively removing a region of the insulating resin layer located above the device electrode of the semiconductor substrate to expose the device electrode and form an opening;
A second step of forming a metal wiring that is partially connected to the element electrode as an external terminal formation land from the element electrode exposed to the opening to the insulating resin layer;
A third step of forming the first post electrode electrically connected to the external terminal forming land,
A fourth step of forming at least one layer of the second post electrode electrically connected to the first post electrode and having the function of an external electrode, wherein the upper layer electrode has a shorter post peripheral length than the lower layer electrode;
A fifth step of forming a sealing resin for protecting the insulating resin layer, the metal wiring, and the at least two layers of post electrodes;
Forming a solder bump on the outermost surface of the post electrode.
前記第一ポスト電極及び第二ポスト電極の半導体基板表面に平行な断面形状が円形、楕円、正方形、及び前記以外の多角形から選ばれる少なくとも一つの形状である請求項3に記載の半導体装置の製造方法。4. The semiconductor device according to claim 3, wherein a cross-sectional shape of the first post electrode and the second post electrode parallel to the semiconductor substrate surface is at least one shape selected from a circle, an ellipse, a square, and a polygon other than the above. 5. Production method.
JP2002332732A 2002-11-15 2002-11-15 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3664707B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002332732A JP3664707B2 (en) 2002-11-15 2002-11-15 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002332732A JP3664707B2 (en) 2002-11-15 2002-11-15 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2004172163A true JP2004172163A (en) 2004-06-17
JP3664707B2 JP3664707B2 (en) 2005-06-29

Family

ID=32697668

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002332732A Expired - Fee Related JP3664707B2 (en) 2002-11-15 2002-11-15 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP3664707B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005327994A (en) * 2004-05-17 2005-11-24 Oki Electric Ind Co Ltd Semiconductor device
JP2009060000A (en) * 2007-09-03 2009-03-19 Casio Comput Co Ltd Semiconductor device
CN102034769A (en) * 2009-10-06 2011-04-27 揖斐电株式会社 Circuit board and semiconductor module
JP5128712B1 (en) * 2012-04-13 2013-01-23 ラピスセミコンダクタ株式会社 Semiconductor device
US9293402B2 (en) 2012-04-13 2016-03-22 Lapis Semiconductor Co., Ltd. Device with pillar-shaped components

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005327994A (en) * 2004-05-17 2005-11-24 Oki Electric Ind Co Ltd Semiconductor device
JP4627632B2 (en) * 2004-05-17 2011-02-09 Okiセミコンダクタ株式会社 Semiconductor device
JP2009060000A (en) * 2007-09-03 2009-03-19 Casio Comput Co Ltd Semiconductor device
CN102034769A (en) * 2009-10-06 2011-04-27 揖斐电株式会社 Circuit board and semiconductor module
JP5128712B1 (en) * 2012-04-13 2013-01-23 ラピスセミコンダクタ株式会社 Semiconductor device
JP2013222753A (en) * 2012-04-13 2013-10-28 Lapis Semiconductor Co Ltd Semiconductor device
CN103378038A (en) * 2012-04-13 2013-10-30 拉碧斯半导体株式会社 Semiconductor device
US9293402B2 (en) 2012-04-13 2016-03-22 Lapis Semiconductor Co., Ltd. Device with pillar-shaped components
US9721879B2 (en) 2012-04-13 2017-08-01 Lapis Semiconductor Co., Ltd. Device with pillar-shaped components
US10424537B2 (en) 2012-04-13 2019-09-24 Lapis Semiconductor Co., Ltd. Device with pillar-shaped components
US10957638B2 (en) 2012-04-13 2021-03-23 Lapis Semiconductor Co., Ltd. Device with pillar-shaped components

Also Published As

Publication number Publication date
JP3664707B2 (en) 2005-06-29

Similar Documents

Publication Publication Date Title
US7981722B2 (en) Semiconductor device and fabrication method thereof
JP2005175317A (en) Semiconductor device and its manufacturing method
TW200832641A (en) Semiconductor device having projecting electrode formed by electrolytic plating, and manufacturing method thereof
JP2001110831A (en) External connecting protrusion and its forming method, semiconductor chip, circuit board and electronic equipment
JP2004158827A (en) Semiconductor wafer, semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
US6639314B2 (en) Solder bump structure and a method of forming the same
JP3945380B2 (en) Semiconductor device and manufacturing method thereof
US7741705B2 (en) Semiconductor device and method of producing the same
JP2008047732A (en) Semiconductor device and manufacturing method thereof
JP2004281898A (en) Semiconductor device and its producing method, circuit board and electronic apparatus
JP2004235420A (en) Electronic device, manufacturing method thereof, circuit board, manufacturing method thereof, electronic device, and manufacturing method thereof
JP3664707B2 (en) Semiconductor device and manufacturing method thereof
JP2004079797A (en) Method of forming wiring using electrolytic plating
JP3972211B2 (en) Semiconductor device and manufacturing method thereof
JP4631223B2 (en) Semiconductor package and semiconductor device using the same
JP3726906B2 (en) Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
JP2004072043A (en) Semiconductor wafer, semiconductor chip, and semiconductor device and its manufacturing method
JP3877691B2 (en) Semiconductor device
JP3928729B2 (en) Semiconductor device
JP2001148393A (en) Bump forming method, semiconductor device and its manufacturing method, wiring board, and electronic equipment
JP3526529B2 (en) Method for manufacturing semiconductor device
JP7335036B2 (en) Semiconductor package manufacturing method
JP2005038944A (en) Semiconductor device
JP2007258354A (en) Process for manufacturing semiconductor device
JP4016276B2 (en) Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20041111

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20041119

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20041224

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20050325

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20050329

R150 Certificate of patent (=grant) or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080408

Year of fee payment: 3

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090408

Year of fee payment: 4

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100408

Year of fee payment: 5

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110408

Year of fee payment: 6

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120408

Year of fee payment: 7

LAPS Cancellation because of no payment of annual fees