JP3256172B2 - Multilayer printed wiring board - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board having a conductor circuit formed as a power supply layer or a ground layer.

[0002]

2. Description of the Related Art In a multilayer printed wiring board in which a plurality of conductive circuits are insulated by an insulating layer, using one conductive circuit as a ground layer or a power supply layer can reduce noise and the like. It is done for the purpose. In such a multilayer printed wiring board, as shown in FIG. 26, the wiring 434 forming the ground layer (or power supply layer) is often formed in a mesh pattern having a conductor non-forming portion 435. Here, the conductor non-forming portion 435 is provided because the wiring 434 is formed of copper having low connectivity with the resin, so that the interlayer resin insulating layer (not shown) provided above the wiring 434 and the lower layer This is for improving the connectivity with the resin substrate (not shown) provided in the substrate by directly contacting the interlayer resin insulating layer and the resin substrate at the portion where the conductor is not formed.

Here, the present applicant has devised a method of smoothing a multilayer printed wiring board by filling a resin into the non-conductor-formed portion 435 when the wiring 434 of the mesh pattern is formed. Manufacturing of a multilayer printed wiring board for performing this smoothing will be described with reference to FIG. FIG.
FIG. 7A illustrates an FF cross section of the substrate 430 on which the wiring 434 illustrated in FIG. 26 is formed. The resin 440 is uniformly applied to the substrate 430, and the resin 440 is cured (see FIG. 27B). Then, the resin 440 is polished to smooth the substrate 430 (see FIG. 27C). Then, after forming the interlayer resin insulation layer 450 on the substrate,
The conductor circuit 458 is formed (see FIG. 27D).

[0004]

However, in the above configuration, since the wiring 434 is formed in a mesh pattern as shown in FIG. 26, the conductor non-formed portion 435 becomes rectangular and has a corner 435E. are doing. For this reason, in the step of filling the resin 40 into the non-conductor-formed portion 435 described above with reference to FIG.
In the corner 435E where the resin 40 could not be filled, the concave portion was formed on the surface of the substrate 430 as shown in FIG.
58 could not be formed as intended.

[0005] Further, a conductor circuit 434 made of metal such as copper,
The coefficient of thermal expansion is significantly different from that of the interlayer resin insulating layer 450 made of resin. Therefore, stress tends to concentrate at the corner 435E of the rectangular conductor-free portion 435. For this reason, when the multilayer printed wiring board repeats thermal expansion and contraction, the stress causes the interlayer resin insulating layer 45 as shown in FIG.
In some cases, cracks K were formed in the conductor circuit 458 in the upper layer of the interlayer resin insulating layer 450, causing a break in the circuit.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a multilayer printed wiring board which includes a power supply layer or a ground layer and does not cause disconnection in conductor wiring. Is to do.

[0007]

According to the first aspect of the present invention, there is provided a multilayer printed wiring comprising a substrate having an inner conductor circuit formed thereon and a conductor circuit formed thereon via an interlayer resin insulation layer. A plate, wherein the inner-layer conductor circuit or the conductor circuit is formed as a power supply layer or a ground layer, and the inner-layer conductor circuit or the conductor circuit formed as the power supply layer or the ground layer has a circular conductor non-forming portion Mesh pattern, via hole connection to the mesh pattern
A region is formed, and a resin-free portion of the power supply layer or the ground layer is filled with a resin, and the filled resin and the power supply layer or the ground layer are smoothed.

[0008]

According to a second aspect of the present invention, in the first aspect, an inner conductor circuit and a mesh of the mesh pattern are provided.
A technical feature of the conductor circuit of the pattern is that it is subjected to a roughening process.

In the multilayer printed wiring board according to the first aspect, since the conductor-free portion of the conductor circuit of the mesh pattern is formed in a circular shape and has no corners, stress is not concentrated, and the conductor wiring is disconnected. Does not occur.

According to the first aspect of the present invention, since the conductor-free portion to be filled with the resin is formed in a circular shape, the resin-filled portion without the gap can be filled with the resin.

In the multilayer printed wiring board according to the second aspect, since the inner conductor circuit of the mesh pattern and the conductor circuit of the mesh pattern are roughened, adhesion to the upper interlayer resin insulation layer is improved. Is high.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a multilayer printed wiring board according to a first embodiment of the present invention will be described with reference to FIG. The multilayer printed wiring board according to the first embodiment whose cross section is shown in FIG. 22 constitutes a so-called integrated circuit package for mounting on a motherboard (not shown) with an integrated circuit (not shown) mounted on the upper surface. Things. The multilayer printed wiring board is provided with solder bumps (76U) on the upper surface for connection to the bump side of the integrated circuit, and solder bumps (76D) for connection to the bumps on the motherboard on the lower surface side. It plays a role of transferring signals and the like between the terminals and relaying power supply from the motherboard.

An inner copper pattern 34 serving as a ground layer is provided on the upper and lower surfaces of the core substrate 30 of the multilayer printed wiring board.
U and 34D are formed. In addition, inner layer copper pattern 3
In the upper layer of 4U, a conductor circuit 58U for forming a signal line with an interlayer resin insulating layer 50 interposed is formed. In the upper layer of the conductor circuit 58U, a via hole 160U penetrating the outermost conductor circuit 158U and the interlayer resin insulation layer 150 via the interlayer resin insulation layer 150 is formed, and a solder bump 76U is formed in the via hole 160U. Have been.

On the other hand, the upper layer of the ground layer (inner layer copper pattern) 34D on the lower surface side of the core substrate 30 (here, the upper layer means the upper side with respect to the substrate 30 as the center and the lower side with respect to the lower surface of the substrate). ) Includes an interlayer resin insulation layer 50
, A conductor circuit 58D forming a signal line is formed. On the upper layer of the conductor circuit 58D, an interlayer resin insulating layer 1 is provided.
Via holes 160D are formed through the outermost conductive circuit 158D and the interlayer resin insulation layer 150 through the via holes 50. Solder bumps 76D are formed in the via holes 160D.

FIG. 23 shows a cross section taken along line X1-X1 of FIG.
That is, FIG. 23 shows a cross section of the multilayer printed wiring board,
The X2-X2 longitudinal section in FIG. 23 corresponds to FIG. FIG.
As shown in FIG. 3, the conductor circuit 34 constituting the ground layer
U is formed in a mesh pattern having a circular conductor non-forming portion 35. In the conductor non-formed portion 35,
A resin filler 40 described later is filled. Although not shown, the inner layer conductor circuit 34D on the lower surface side of the substrate 30 also
Similarly, it is formed in a mesh pattern having a circular conductor non-formed portion 35.

The conductor-free portion 35 formed on the mesh-patterned conductor circuit 34U is formed in a circular shape, as shown in FIG.
6 and FIG. 27 (E), there is no corner as in the prior art conductor circuit described above with reference to FIG. 27 and FIG. 27 (E), so that stress is not concentrated at the corner and formed via the interlayer resin insulating layer 50. The conductive wires 158U and 158D are not disconnected. Further, since the non-conductor-formed portion 35 filled with the resin filler is formed in a circular shape, unlike the conventional configuration having a corner portion, the non-conductor-formed portion 35 is filled with the resin filler without a gap.
Can be filled. Therefore, by flattening the substrate surface, it is possible to appropriately form a conductor circuit in the upper layer. Furthermore, as shown in FIG. 25 (C), it is desirable that the via-hole connection region 99 and the non-conductor-formed portion 35 are arranged so as not to overlap. This is because if the via-hole connection region 99 and the non-conductor-formed portion 35 overlap as shown in FIG. 25D, the area of the non-conductor-formed portion 35 becomes small, and it becomes difficult to fill the resin.

Next, the manufacturing process of the multilayer printed wiring board shown in FIG. 22 will be described with reference to FIGS. (1) The starting material is a copper-clad laminate 30A in which 18 μm copper foils 32 are laminated on both sides of a core substrate 30 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 1 mm (see FIG. 1). ). First, the copper-clad laminate 30A is drilled, subjected to an electroless plating process, and etched in a pattern to form an inner layer copper pattern 34U having a shape as described above with reference to FIG. , 34D and through holes 36 (see FIG. 2).

(2) Further, the inner layer copper patterns 34U, 3U
The substrate 30 having the 4D and the through-hole 36 formed thereon is washed with water and dried, and then subjected to an oxidation-reduction treatment to provide a roughened layer 38 on the surfaces of the inner copper patterns 34U and 34D and the through-hole 36 (see FIG. 3).

(3) On the other hand, a resin filler for smoothing the substrate surface is adjusted. Here, bisphenol F type epoxy monomer (manufactured by Yuka Shell, molecular weight 310, YL)
983U) of 100 parts by weight and 6 parts by weight of an imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals Co., Ltd.), and the mixture was mixed with SiO ₂ having an average particle diameter of 1.6 μm, the surface of which was coated with a silane coupling agent. Spherical particles (manufactured by Admatech, CRS1101-CE, where the maximum particle size is the thickness of the inner layer copper pattern described later (15 μm).
m) or less) 170 parts by weight and 0.5 parts by weight of an antifoaming agent (manufactured by San Nopco, Perenol S4) are mixed and kneaded with a three-roll mill to reduce the viscosity of the mixture to 23 ±
Adjust to 45,000-49,000 cps at 1 ° C,
Obtain resin filler. This resin filler is solventless. If a resin filler containing a solvent is used, the solvent is volatilized from the resin filler layer when the interlayer agent is applied, heated and dried in a later step, so that the space between the resin filler layer and the interlayer material is reduced. This causes peeling.

(4) The resin filler 40 obtained in the above (3)
Is applied to both surfaces of the substrate 30 using a roll coater to fill the space between the conductor circuits (inner copper patterns) 34U on the upper surface or in the through holes 36, and is dried at 70 ° C. for 20 minutes. And resin filler 4
0 is filled between the conductor circuits 34D or in the through holes 36 and dried at 70 ° C. for 20 minutes (see FIG. 4).

(5) The substrate 30 after the processing of the above (4)
Of the inner layer copper pattern 34 by belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku).
Polishing is performed so that the resin filler 40 does not remain on the surfaces of the U and 34D and the land surface of the through hole 36, and then buffing is performed to remove the scratches caused by the belt sander polishing (see FIG. 5). Then, at 100 ° C. for 1 hour, 120
The resin filler 40 is cured by performing a heat treatment at a temperature of 3 hours at 150 ° C. for 1 hour and at 180 ° C. for 7 hours.

The surface layer of the resin filler 40 filled in the through holes 36 and the like and the conductor circuit 34
By removing the roughened layer 38 on the upper surface of the U and 34D and smoothing both surfaces of the substrate, the resin filler 40 and the conductor circuits 34U and 34D are removed.
D is firmly adhered to the side surface of the roughened layer 38 via the roughened layer 38, and the inner wall surface of the through hole 36 and the resin filler 40 are bonded to the roughened layer 3.
Thus, a wiring board firmly adhered to the wiring board is obtained. That is, by this process, the surface of the grease filler 40 and the inner layer copper pattern 3
The surfaces of 4U and 34D are flush with each other. Here, the filled resin had a Tg point of 155.6 ° C. and a linear thermal expansion coefficient of 44.5 × 10 ⁻⁶ / ° C.

(6) A roughened layer (rough layer) made of a Cu-Ni-P alloy having a thickness of 2.5 μm is formed on the upper surfaces of the lands of the conductor circuits 34U and 34D and the through holes 36 exposed in the process (5). Then, an Sn layer having a thickness of 0.3 μm is provided on the surface of the roughened layer 42 (see FIG. 6, but the Sn layer is not shown). The formation method is as follows. That is, the substrate 30 is acid-degreased and soft-etched, and then treated with a catalyst solution comprising palladium chloride and an organic acid to provide a Pd catalyst. After activating this catalyst, copper sulfate 8 g / l, sulfuric acid Nickel 0.6g
/ L, citric acid 15g / l, sodium hypophosphite 29
g / l, boric acid 31 g / l, surfactant 0.1 g / l,
Plating is performed in an electroless plating bath having a pH of 9 and Cu-
The roughened layer 42 of the Ni-P alloy was formed. Then, tin borofluoride 0.1 mol / l, thiourea 1.0 mol / l
1, a Cu-Sn substitution reaction was performed under the conditions of a temperature of 50 ° C. and a pH of 1.2 to provide a 0.3 μm thick Sn layer on the surface of the roughened layer 42 (the Sn layer is not shown).

Subsequently, a photosensitive adhesive (for an upper layer) and an interlayer resin insulator (for a lower layer) for forming an insulating layer are prepared. (7) The photosensitive adhesive (for the upper layer) is dissolved in DMDG (diethylene glycol dimethyl ether) at a concentration of 80 w
35% by weight of 25% acrylate of t% cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., molecular weight 2500), 12 parts by weight of polyether sulfone (PES), imidazole curing agent (2E4MZ-CN) 2
Parts by weight, photosensitive monomer (Toa Gosei Co., Aronix M
315) 4 parts by weight, 2 parts by weight of a photoinitiator (manufactured by Ciba Geigy, Irgacure I-907), a photosensitizer (manufactured by Nippon Kayaku,
0.2 parts by weight of DETX-S) were mixed, and 7.2 parts by weight of epoxy resin particles (manufactured by Sanyo Chemical Industries, polymer pole) having an average particle diameter of 1.0 μm were added to these mixtures, and the average particle diameter was 0%. After mixing 3.09 parts by weight of a 0.5 μm-thick and 0.5 parts by weight of an antifoaming agent (S-65 manufactured by San Nopco), the mixture was further mixed while adding 30 parts by weight of NMP to obtain a viscosity of 7 Pa.
・ S photosensitive adhesive (for upper layer) is obtained.

(8) On the other hand, interlayer resin insulating material (for lower layer)
Is a 25% by weight cresol novolak type epoxy resin (manufactured by Nippon Kayaku, molecular weight 2500) dissolved in DMDG (diethylene glycol dimethyl ether).
% Acrylate, 35 parts by weight of polyethersulfone (PES), 12 parts by weight of imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), 4 parts by weight of photosensitive monomer (Aronix M315, manufactured by Toa Gosei), light 2 parts by weight of an initiator (Circa Geigy, Irgacure I-907) and 0.2 part by weight of a photosensitizer (DETE-S, Nippon Kayaku) were mixed, and the mixture was mixed with epoxy resin particles (Sanyo Chemical Co., Ltd.). 0.5μm average particle size
14.49 parts by weight of an antifoaming agent (manufactured by San Nopco, S
-65) After mixing 0.5 part by weight, NMP30
By mixing while adding parts by weight, an interlayer resin insulating agent (for lower layer) having a viscosity of 1.5 Pa · s is obtained.

(9) An interlayer resin insulating material having a viscosity of 1.5 Pa · s obtained in (7) above (for lower layer)
Is applied on a roll roll overnight, left for 20 minutes in a horizontal state, and then dried (prebaked) at 60 ° C. for 30 minutes to form an insulating layer 44. Further, the photosensitive adhesive (for the upper layer) having a viscosity of 7 Pa · s obtained in the above (8) is applied on the insulating layer 44 using a roll coater, and left for 20 minutes in a horizontal state. Dry at 60 ° C for 30 minutes,
An adhesive layer 46 is formed (see FIG. 7).

As described above, the conductor circuits 34U and 34D
The roughening layer (irregular layer) 42 is formed, that is, by performing a roughening process, the adhesion to the upper insulating layer 44 is enhanced.

(10) On both sides of the substrate 30 on which the insulating layer 44 and the adhesive layer 46 were formed in (9), a 100 μm
The photomask film on which the black circle of φ is printed is brought into close contact with the photomask film, and exposed at 500 mJ / cm ² using an ultra-high pressure mercury lamp. This is spray-developed with a DMDG solution, and further, the substrate is exposed to 3000 mJ / cm ² by an ultra-high pressure mercury lamp, and is subjected to a heat treatment (post-bake) at 100 ° C. for 1 hour, and then at 150 ° C. for 5 hours. Thickness 35 having 100 μmφ opening (via hole forming opening 48) having excellent dimensional accuracy equivalent to a photomask film
A μm interlayer resin insulating layer (two-layer structure) 50 is formed (see FIG. 8). Note that the tin plating layer is partially exposed in the opening 48 serving as a via hole.

(11) Substrate 30 with opening 48 formed
Is immersed in chromic acid for 1 minute to dissolve and remove the epoxy resin particles on the surface of the adhesive layer 46 to make the surface of the interlayer resin insulating layer 50 rough, and then to a neutralizing solution (manufactured by Shipley). After immersion, it is washed with water (see FIG. 9). Further, by applying a palladium catalyst (manufactured by Atotech) to the surface of the substrate subjected to the surface roughening treatment, a catalyst nucleus is attached to the surface of the interlayer resin insulating layer 50 and the inner wall surface of the via hole opening 48.

(12) The substrate is immersed in an electroless copper plating bath having the following composition to form an electroless copper plating film 52 having a thickness of 1.6 μm on the entire rough surface (see FIG. 10). [Electroless plating solution] EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l [Electroless plating conditions] 70 ° C. 30 minutes at liquid temperature

(13) A commercially available photosensitive dry film is adhered on the electroless copper plating film 52 formed in the above (12), a mask is placed, and exposure is performed at 100 mJ / cm ² .
A development process is performed with 0.8% sodium carbonate to provide a plating resist 54 having a thickness of 15 μm (see FIG. 11).

(14) Then, electrolytic copper plating is applied to the non-resist forming portion under the following conditions to form an electrolytic copper plating film 56 having a thickness of 15 μm (see FIG. 12). [Electroplating solution] Sulfuric acid 180 g / l Copper sulfate 80 g / l Additive (Capparaside GL, manufactured by Atotech Japan) 1
ml / l [Electroplating conditions] Current density 1A / dm ² hours 30 minutes Temperature Room temperature

(15) 5% KOH plating resist 54
Then, the electroless plating film 52 under the plating resist 54 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide to form a film comprising the electroless copper plating film 52 and the electrolytic copper plating film 56. 58 μm conductor circuit 58U, 5
8D and via holes 60U, 60D are formed (FIG. 1).
3). Subsequently, the substrate 30 is immersed in 800 g / l chromic acid for 3 minutes to remove the palladium catalyst nuclei remaining on the roughened surface.

(16) The substrate 30 on which the conductor circuits 58U and 58D and the via holes 60U and 60D are formed is replaced with copper sulfate 8 g / l, nickel sulfate 0.6 g / l, and citric acid 15 g.
/ L, sodium hypophosphite 29g / l, boric acid 31g
/ L, a surfactant of 0.1 g / l, immersed in an electroless plating solution having a pH of 9 and a surface of the conductor circuits 58U, 58D and via holes 60U, 60D formed of copper-nickel-phosphorus having a thickness of 3 μm. A roughened layer 62 is formed (see FIG. 14). Further, a Cu—Sn substitution reaction was performed under the conditions of tin borofluoride 0.1 mol / l, thiourea 1.0 mol / l, temperature 50 ° C., and pH = 1.2, and a thickness of 0 A Sn layer of 0.3 μm is provided (the Sn layer is not shown).

(17) By repeating the above steps (2) to (16), a conductor circuit in a further upper layer is formed.
That is, an interlayer resin insulating agent (for the lower layer) is applied to both surfaces of the substrate 30 with a roller to form an insulating agent layer 144. Also, a photosensitive adhesive (for the upper layer) is provided on the insulating layer 144.
Is applied using a roll coater to form an adhesive layer 146 (see FIG. 15). Insulating agent layer 144 and adhesive layer 1
A photomask film is brought into close contact with both surfaces of the substrate 30 on which the 46 has been formed, and exposed and developed to form an interlayer resin insulating layer 150 having an opening (via hole forming opening 148). The surface is made rough (see FIG. 16). Thereafter, an electroless copper plating film 152 is formed on the surface of the substrate 30 subjected to the surface roughening treatment (see FIG. 17). Subsequently, after a plating resist 154 is provided on the electroless copper plating film 152, an electrolytic copper plating film 156 is formed on a portion where no resist is formed (see FIG. 18). Then, after the plating resist 154 is peeled and removed with KOH, the electroless plating film 152 under the plating resist 54 is dissolved and removed, and the conductor circuits 158U and 158D and the via hole 160 are removed.
U, 160D are formed (see FIG. 19). Further, the conductor circuits 158U, 158D and via holes 160U,
A roughened layer 162 is formed on the surface of 160D to complete a multilayer printed wiring board (see FIG. 20).

(19) Then, solder bumps are formed on the above-mentioned multilayer printed wiring board. First, adjustment of the solder resist composition for a solder bump will be described. Here, 46.67 g of a photosensitizing oligomer (molecular weight 4000) in which 50% of epoxy groups of a cresol novolak type epoxy resin (manufactured by Nippon Kayaku) of 60% by weight dissolved in DMDG were dissolved in methyl ethyl ketone was dissolved. 15.0 g of 80% by weight of bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001), imidazole curing agent (manufactured by Shikoku Chemicals, 2E4MZ-CN)
1.6 g, 3 g of a polyacrylic monomer (R604, manufactured by Nippon Kayaku), which is a photosensitive monomer, 1.5 g of a polyvalent acrylic monomer (DPE6A, manufactured by Kyoeisha Chemical Co., Ltd.), a dispersion defoaming agent (manufactured by Sannopco, S -65) 0.71 g, and 2 g of benzophenone (Kanto Kagaku) as a photoinitiator and 0.2 g of Michler's ketone (Kanto Kagaku) as a photosensitizer were added to the mixture. A solder resist composition having a viscosity adjusted to 2.0 Pa · s at 25 ° C. is obtained.

(20) The solder resist composition is applied to both sides of the wiring board obtained in the above (18) in a thickness of 20 μm. Next, after performing a drying process at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a circular pattern (mask pattern)
Is placed in close contact with a 5 mm thick photomask film on which is drawn, exposed to ultraviolet light of 1000 mJ / cm ² , and subjected to DMTG development processing. And at 80 ° C for 1
Time, 1 hour at 100 ° C, 1 hour at 120 ° C, 150 ° C
And a heat treatment under conditions of 3 hours, a solder resist layer (opening diameter: 200 μm) with a solder pad portion (including a via hole and its land portion) 71 opened (opening diameter: 200 μm)
70 are formed (see FIG. 21).

(21) Next, the substrate 30 on which the solder resist layer 70 is formed is replaced with nickel chloride 30 g / l, sodium hypophosphite 10 g / l, and sodium citrate 10 g.
/ L of electroless nickel plating solution of pH = 5
Then, a nickel plating layer 72 having a thickness of 5 μm is formed in the opening 71 (see FIG. 22). Further, the substrate 30 was immersed in an electroless gold plating solution comprising 2 g / l of potassium gold cyanide, 75 g / l of ammonium chloride, 50 g / l of sodium citrate, and 10 g / l of sodium hypophosphite at 93 ° C. for 23 hours. Immersion for 2 seconds, nickel plating layer 7
A gold plating layer 74 having a thickness of 0.03 μm is formed on 2.

(22) The solder resist layer 70
The solder bumps 76U and 76D are formed by printing a solder paste in the opening 71 of the substrate and performing reflow at 200 ° C. to complete a multilayer printed wiring board having the solder bumps 76U and 76D.

Next, a multilayer printed wiring board according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 24 is a cross-sectional view illustrating a configuration of the multilayer printed wiring board according to the second embodiment of the present invention. Core substrate 2
Inner layer copper patterns 234U and 234D serving as ground layers are formed on the upper surface and the lower surface of 30. That is, the ground layer (inner layer copper pattern) 234U and the ground layer (inner layer copper pattern) 234 facing each other with the substrate 230 interposed therebetween.
D forms a capacitor.

In addition, a conductor circuit 258U for forming a signal line is formed above the inner layer copper pattern 234U with an interlayer resin insulating layer 250 interposed. The conductor circuit 25
Via holes 360U penetrating through interlayer resin insulation layer 350 are formed in the upper layer of 8U.
Are formed with solder bumps 376U.

On the other hand, the upper surface of the ground (inner copper pattern) 234D on the lower surface side of the substrate 230 (here, the upper layer means the upper surface with respect to the substrate 230 and the lower surface means the lower surface of the substrate). Is the interlayer resin insulation layer 25
A conductor circuit 258D serving as a signal line via 0 is formed. On the upper layer of the conductor circuit 258D, a conductor circuit 388D serving as a power supply layer is formed via an interlayer resin insulating layer 350. In the upper layer of the conductor circuit 388D, a via hole 380D penetrating the interlayer resin insulating layer 390 is formed, and a solder bump 376D is formed in the via hole 380D. That is, in the present embodiment, the via hole 3 attached to the conductor circuit 388D forming the power supply layer is used.
A solder bump 376D is formed on 80D so that the power supply layer can be directly connected to an external bump (not shown).

FIG. 25A is a plan view of a conductor circuit 388D forming a power supply layer. In the multilayer printed wiring board according to the second embodiment, similarly to the first embodiment described above with reference to FIG. 23, the conductor circuit 388D forming the power supply layer is formed in a mesh pattern having a conductor non-forming portion 359. It is. However, in the first embodiment, the conductor non-formed portion 35
Is formed in a circular shape, whereas in the second embodiment, the conductor non-formed portion 359 is formed in an elliptical shape.

In the multilayer printed wiring board according to the second embodiment, the conductor non-formed portion 359 is formed in an elliptical shape, and is similar to the conventional conductor circuit described above with reference to FIGS. 26 and 27 (E). Since there is no corner portion, stress is not concentrated at the corner portion, and disconnection occurs in the conductor wiring 358D formed through the interlayer resin insulation layer 350 and the via hole 380D formed through the interlayer resin insulation layer 390. Does not occur.

FIG. 25B is a plan view of a conductor circuit 388D according to a modification of the second embodiment. The multilayer printed wiring board according to the modified example of the second embodiment is formed in a mesh pattern having a rectangular conductor-free portion 359 whose corners are chamfered. In the multilayer printed wiring board according to the modification of the second embodiment, since there is no corner as in the above-described conductor circuit of the related art, stress is not concentrated at the corner, and the conductor wiring 358D and No disconnection occurs in the via hole 380D.

In the above-described embodiment, the multilayer printed wiring board formed by the semi-additive method is exemplified. However, it is needless to say that the structure of the present invention can be applied to the multilayer printed wiring board formed by the full-additive method. No.

[0048]

As described above, in the multilayer printed wiring board according to the first aspect, since the conductor-free portion of the conductor circuit of the mesh pattern is formed in a circular shape and has no corners, stress concentrates. It does not cause disconnection in the conductor wiring.

[0049]

In the multilayer printed wiring board according to the second aspect , the inner layer conductive circuit or the mesh pattern of the mesh pattern is provided.
Since the conductor circuit of the ground is roughened, the adhesiveness to the upper interlayer resin insulating layer is high, and peeling of the interlayer resin insulating layer does not occur.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a manufacturing process of a multilayer printed wiring board according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 7 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 8 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 9 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 10 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 11 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 12 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 13 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 14 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 15 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 16 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 17 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 18 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 19 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 20 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 21 is a diagram illustrating a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 22 is a sectional view showing the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 23 is a cross-sectional view of the multilayer printed wiring board shown in FIG.
FIG.

FIG. 24 is a cross-sectional view illustrating a configuration of a multilayer printed wiring board according to a second embodiment of the present invention.

25 (A) and 25 (B) are plan views of conductor circuits of the multilayer printed wiring board shown in FIG. 24, and FIG.
5 (C) and FIG. 25 (D) are plan views of the conductor circuit of the multilayer printed wiring board shown in FIG.

FIG. 26 is a plan view of a ground layer of a multilayer printed wiring board according to the related art.

27 (A), 27 (B), 27
(C), (D) and (E) of FIG. 27 are diagrams illustrating a manufacturing process of a multilayer printed wiring board according to a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 30 Substrate 34U, 34D Inner-layer copper pattern (inner conductor circuit) 35 Non-conductor part 38 Roughened layer 40 Resin filler 42 Roughened layer 48 Via hole opening 50 Interlayer resin insulation layer 58U, 58D Conductor circuit 60U, 60D Via hole 76U, 76D solder bump 150 interlayer resin insulation layer

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H05K 3/46 H05K 1/02 H05K 3/38

Claims (2)

(57) [Claims] 1. A multilayer printed wiring board comprising a conductor circuit formed on a substrate on which an inner conductor circuit is formed via an interlayer resin insulating layer, wherein the inner conductor circuit or the conductor circuit is a power supply layer or a ground. The inner conductor circuit or the conductor circuit formed as a power supply layer or the ground layer is a mesh pattern having a circular conductor non-formed portion, and a via hole connection region is formed in the mesh pattern.
Is, the resin is filled in the conductor non-formation portion of the power supply layer or a ground layer, a multilayer printed wiring board and the filled resin and the power supply layer or the ground layer is characterized in that it is smoothed. 2. A conductor circuit of the inner layer conductor circuit and the mesh patterns of the mesh pattern, a multilayer printed wiring board according to claim 1, characterized in that it is roughened.