JP3378185B2 - Package substrate - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package substrate for mounting an IC chip, more specifically,
The present invention relates to a package substrate having an IC chip and solder bumps for connection to a substrate such as a mother board formed on the upper and lower surfaces.

[0002]

2. Description of the Related Art A highly integrated IC chip is mounted on a package substrate and connected to a substrate such as a mother board or a sub board. FIG. 26 shows the structure of this package substrate.
Will be described with reference to. In FIG. 26A, the IC chip 80 is placed on the package substrate 300, and the motherboard 90
It is sectional drawing which shows the state attached to the. The package substrate 300 includes an interlayer resin insulation layer 3 on both surfaces of a core substrate 330.
A plurality of conductor circuits 358A, 358 with 50 interposed therebetween.
B chip, IC chip 8
The pad 8 on the IC chip 80 side is provided on the surface (upper surface) on the 0 side.
The solder bumps 376U for connecting to the second board 2 are formed, and the mother board 90 is provided on the surface (lower surface) on the sub board 90 side.
Solder bumps 376D for connecting to the pads 92 on the side are formed. Here, the solder bumps 376U, 376
In order to improve the connection reliability of D, a resin 84 is sealed between the IC chip 80 and the package substrate 300, and a resin 94 is similarly sealed between the package substrate 300 and the mother board 90. There is.

Solder bumps 376D on the mother board 90 side
Is an inner layer conductor circuit 358C and a via hole 360-.
The wiring 378 and the solder pad 375 are connected to each other. FIG. 26B shows the via hole 3 in FIG.
The state where the 60 and the solder bump 375 are viewed from the B side is shown in an enlarged manner. The solder bump 375 on which the solder bump 376D is mounted is formed in a circular shape, and is connected to the via hole 360 formed in a circular shape via the wiring 378 as described above.

[0004]

The IC chip 80 repeats a heat cycle in which it is in a high temperature state during operation and is cooled to room temperature when the operation is completed. Here, since the IC chip 80 made of silicon and the resin-made package substrate 300 have large thermal expansion coefficients, stress is generated in the package substrate 300 during the heat cycle, and the package substrate 300 and the mother board 90 are stressed. Sealing resin 94
A crack L is generated. Here, when a crack L occurs in the resin 94, the crack L expands, and the via hole 360 and the solder bump 370 of the package substrate 300.
I was sometimes disconnected from. That is, as shown in FIG. 26C, which is an enlarged view of the via hole 360 and the solder bump 375 in FIG. 26A viewed from the C side, the solder bump 375 on which the solder bump 3756D is mounted and the via hole. The wiring 378 connecting to 360 may be broken due to the crack L.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a package substrate which does not cause disconnection between solder bumps and via holes. .

[0006]

In order to achieve the above-mentioned object, a first aspect of the present invention is formed by forming a multi-layered conductor circuit with a plurality of interlayer resin insulation layers interposed, and a surface on the side where an IC chip is mounted. And a package substrate in which a solder bump is formed on the surface connected to another substrate, and a resin is sealed between the surface connected to the other substrate and the other substrate. The technical feature is that the solder bump on the side surface connected to the other substrate is formed in the via hole.

According to a second aspect of the present invention, a multilayer conductor circuit is formed by interposing a plurality of interlayer resin insulation layers, the surface on which the IC chip is mounted, and the side connected to another substrate. A package substrate in which a solder bump is formed on the surface of the package, and the surface of the side connected to the other substrate and the other substrate are resin-sealed, and the side surface connected to the other substrate The technical feature is that the solder bump of (1) is formed in a plurality of via holes.

In the package substrate according to claim 1, since the solder bump and the via hole are directly connected by forming the solder bump in the via hole, even if the package substrate is cracked, the solder bump and the via hole are formed. There is no disconnection between and. That is, in a package substrate in which a solder pad is connected to a via hole via a wiring and a solder bump is mounted on the solder pad, when a crack is generated inside, the via hole and the solder pad are connected by the crack. Although the wiring to be disconnected may be disconnected and the connection between the solder bump and the via hole may be disconnected, the disconnection does not occur due to the crack in the package substrate according to the first aspect.

In the package substrate of claim 2, since the solder bump and the via hole are directly connected by forming the solder bump in the via hole, even if the package substrate is cracked, the solder bump and the via hole are formed. There is no disconnection between and. Further, since the solder bumps are formed in the plurality of via holes, even if one of the plurality of via holes is not internally connected, the other via hole can be connected to the solder bump. Can realize phase-safe. Moreover, since the solder bumps are formed in the plurality of via holes, the solder bumps can be formed large with respect to the via holes.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION The structure of a package substrate according to a first embodiment of the present invention will be described with reference to FIGS. The package substrate 100 of the first embodiment whose cross section is shown in FIG. 22 constitutes a so-called integrated circuit package to be attached to the mother board 90 with the IC chip 80 placed on the upper surface as shown in FIG. . The package substrate is provided with solder bumps 76U for connecting to the solder pads 82 side of the IC chip 80 on the upper surface and solder bumps 76D for connecting to the solder pads 92 of the motherboard 90 on the lower surface side. It plays a role of passing signals and the like between the IC chip 80 and the mother board 90 and relaying power supply from the mother board 90 side.

On the upper surface and the lower surface of the core board 30 of the package board, inner layer copper patterns 34U, 3 and 3 serving as ground layers are formed.
4D is formed. Further, a conductor circuit 58U forming a signal line with the interlayer resin insulation layer 50 interposed, and a via hole 60U penetrating the interlayer resin insulation layer 50 are formed on the upper layer of the inner layer copper pattern 34U. . An uppermost conductor circuit 158U and a via hole 160U penetrating the interlayer resin insulation layer 150 via the interlayer resin insulation layer 150 are formed in the upper layer of the conductor circuit 58U, and the conductor circuit 158U and the via hole 160U are soldered. Bump 76U
A solder pad 75U for supporting the solder pad is formed. Here, the solder pad 75U on the IC chip side has a diameter of 133-
It is formed to have a thickness of 170 μm.

On the other hand, the upper layer of the ground layer (inner layer copper pattern) 34D on the lower surface side of the core substrate 30 (here, the upper layer means the upper side with respect to the substrate 30 as the center and the lower side as the lower surface of the substrate). ) Is the interlayer resin insulation layer 50.
A conductor circuit 58D that forms a signal line is formed via. An interlayer resin insulation layer 1 is formed on the conductor circuit 58D.
Via holes 160D penetrating the outermost conductor circuit 158D and the interlayer resin insulation layer 150 are formed via 50, and solder pads 75D for supporting the solder bumps 76D are formed in the via holes 160D. Here, the solder pad 75D on the motherboard side is formed to have a diameter of 600 μm.

In the package substrate of the first embodiment, since the solder bumps 76D on the motherboard 60 side are formed in the via holes 160D to directly connect the solder bumps and the via holes, the package substrate is not cracked. Solder bump 76D and via hole 16
No disconnection from 0D. That is, in the package substrate 300 in which the solder pad 375 is connected to the via hole 360 according to the conventional technique described above with reference to FIG. 26A via the wiring 378, and the solder bump 376D is mounted on the solder pad 375, When a crack L is formed inside, the wiring L 378 connecting the via hole 376D and the solder pad 376D may be broken by the crack L, and the connection between the solder bump 376D and the via hole 360 may be broken. . On the other hand, in the package substrate of the first embodiment, even if a crack occurs, the crack does not cause a disconnection between the solder bump 76D and the via hole 160D.

Next, the manufacturing process of the package substrate shown in FIG. 22 will be described with reference to FIGS. (1) Starting material is a copper clad laminate 30A in which a 18 μm copper foil 32 is laminated on both sides of a core substrate 30 made of a glass epoxy resin or a BT (bismaleimide triazine) resin having a thickness of 1 mm (see FIG. 1). ). First, the copper clad laminate 30A is drilled, electroless plated, and patterned to form inner layer copper patterns 34U and 34D and through holes 36 on both surfaces of the substrate 30 (FIG. 2). reference).

(2) Further, the inner layer copper patterns 34U, 3
The substrate 30 on which the 4D and the through holes 36 are formed is washed with water, dried, and then subjected to oxidation-reduction treatment to provide a roughened layer 38 on the surfaces of the inner layer copper patterns 34U and 34D and the through holes 36 (see FIG. 3).

(3) On the other hand, a resin filler for smoothing the surface of the substrate is adjusted. Here, bisphenol F type epoxy monomer (made by Yuka Shell, molecular weight 310, YL
983 U) 100 parts by weight and 6 parts by weight of an imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Kasei) are mixed, and a silane coupling agent is coated on the surface of the mixture to form SiO ₂ having an average particle diameter of 1.6 μm. Spherical particles (manufactured by Admatech, CRS1101-CE, where the maximum particle size is the thickness of the inner layer copper pattern described later (15 μm
m) or less) 170 parts by weight and 0.5 parts by weight of an antifoaming agent (manufactured by San Nopco, Perenol S4) are mixed and kneaded with a three-roll mill to increase the viscosity of the mixture to 23 ±.
Adjust to 45,000 to 49,000 cps at 1 ° C,
Obtain a resin filler. This resin filler is solventless. If a resin filler containing a solvent is used, the solvent volatilizes from the resin filler layer when the interlayer agent is applied and heated / dried in a later step, and the space between the resin filler layer and the interlayer material is reduced. This is because peeling occurs.

(4) Resin filler 40 obtained in (3) above
Is coated on both surfaces of the substrate 30 using a roll coater so as to fill between the conductor circuits (inner layer copper patterns) 34U on the upper surface or through holes 36, and is dried at 70 ° C. for 20 minutes. Resin filler 4
0 is filled between the conductor circuits 34D or in the through holes 36 and dried at 70 ° C. for 20 minutes (see FIG. 4).

(5) Substrate 30 that has undergone the process of (4) above
One side of the inner layer copper pattern 34 was polished by belt sander polishing using # 600 belt polishing paper (manufactured by Sankyo Rikagaku).
Polishing is performed so that the resin filler 40 does not remain on the surface of U and 34D and the land surface of the through hole 36, and then buffing is performed to remove the scratches due to the belt sander polishing (see FIG. 5). Then, at 100 ° C. for 1 hour, 120
C. for 3 hours, 150.degree. C. for 1 hour, and 180.degree. C. for 7 hours to perform heat treatment to cure the resin filler 40.

In this way, the surface layer portion of the resin filler 40 filled in the through holes 36 and the conductor circuit 34.
By removing the roughening layer 38 on the upper surfaces of U and 34D and smoothing both surfaces of the substrate, the resin filler 40 and the conductor circuits 34U and 34D are formed.
The side surface of D is firmly adhered to the roughened layer 38 via the roughened layer 38, and the inner wall surface of the through hole 36 and the resin filler 40 are firmly bonded to each other.
A wiring board tightly adhered via 8 is obtained. That is, by this step, the surface of the greasing filler 40 and the inner layer copper pattern 3 are
The surfaces of 4U and 34D are flush with each other.

(6) A roughened layer (unevenness layer) of Cu-Ni-P alloy having a thickness of 2.5 μm is formed on the land surfaces of the conductor circuits 34U and 34D and the through holes 36 exposed by the treatment of the above (5). 42 is formed, and a Sn layer having a thickness of 0.3 μm is provided on the surface of the roughened layer 42 (see FIG. 6, but the Sn layer is not shown). The formation method is as follows. That is, the substrate 30 is acid-degreased and soft-etched, then treated with a catalyst solution consisting of palladium chloride and an organic acid to impart a Pd catalyst, and the catalyst is activated. Nickel 0.6g
/ L, citric acid 15g / l, sodium hypophosphite 29
g / l, boric acid 31 g / l, surfactant 0.1 g / l,
Plating is performed in an electroless plating bath of pH = 9, and Cu-on the upper surface of the land of the copper conductor circuit 4 and the through hole 9.
A roughened layer 42 of Ni-P alloy is formed. Then, tin borofluoride 0.1 mol / l, thiourea 1.0 mol / l
A Cu—Sn substitution reaction is performed under the conditions of 1, temperature of 50 ° C. and pH = 1.2 to provide a 0.3 μm thick Sn layer on the surface of the roughening layer 42 (Sn layer is not shown).

Subsequently, a photosensitive adhesive (for upper layer) and an interlayer resin insulating agent (for lower layer) for forming an insulating layer are prepared. (7) The photosensitive adhesive (for the upper layer) has a concentration of 80 w dissolved in DMDG (diethylene glycol dimethyl ether).
35 parts by weight of 25% acrylate of t% cresol novolac type epoxy resin (Nippon Kayaku, molecular weight 2500), 12 parts by weight of polyether sulfone (PES), imidazole curing agent (2E4MZ-CN manufactured by Shikoku Kasei) 2
Parts by weight, photosensitive monomer (Toagosei, Aronix M
315) 4 parts by weight, photoinitiator (manufactured by Ciba Geigy, Irgacure I-907) 2 parts by weight, photosensitizer (manufactured by Nippon Kayaku,
DETX-S) 0.2 parts by weight, and to the mixture, 7.2 parts by weight of epoxy resin particles (polymer pole manufactured by Sanyo Kasei Co., Ltd.) having an average particle diameter of 1.0 μm, and an average particle diameter of 0. After mixing 3.09 parts by weight of 0.5 .mu.m and 0.5 parts by weight of a defoaming agent (S-65 manufactured by San Nopco), 30 parts by weight of NMP are further added and mixed to obtain a viscosity of 7 Pa.
Obtain a photosensitive adhesive of s (for the upper layer).

(8) On the other hand, interlayer resin insulation agent (for lower layer)
Is a cresol novolac type epoxy resin (manufactured by Nippon Kayaku, molecular weight 2500) having a concentration of 80 wt% dissolved in DMDG (diethylene glycol dimethyl ether).
% Acrylate, 35 parts by weight, polyether sulfone (PES) 12 parts by weight, imidazole curing agent (Shikoku Kasei, 2E4MZ-CN) 2 parts by weight, photosensitive monomer (Toagosei, Aronix M315) 4 parts by weight, light 2 parts by weight of an initiator (manufactured by Ciba Geigy, Irgacure I-907) and 0.2 part by weight of a photosensitizer (manufactured by Nippon Kayaku, DETE-S) were mixed, and epoxy resin particles (Sanyo Chemical Co., Ltd.) were mixed with the mixture. Made of polymer pole) with an average particle size of 0.5 μm
14.49 parts by weight of antifoaming agent (San Nopco, S
-65) After mixing 0.5 parts by weight, further NMP30
By mixing while adding parts by weight, an interlayer resin insulating agent (for lower layer) having a viscosity of 1.5 Pa · s is obtained.

(9) On both surfaces of the substrate 30, an interlayer resin insulating agent (for lower layer) having a viscosity of 1.5 Pa · s obtained in (7) above.
Is applied by roll coating overnight, left standing in a horizontal state for 20 minutes, and then dried (prebaked) at 60 ° C. for 30 minutes to form an insulating agent layer 44. Further, a photosensitive adhesive (for upper layer) having a viscosity of 7 Pa · s obtained in (8) above is applied on the insulating agent layer 44 by using a roll coater, and left standing in a horizontal state for 20 minutes, Dry for 30 minutes at 60 ℃,
The adhesive layer 46 is formed (see FIG. 7).

As described above, the conductor circuits 34U, 34D
The roughened layer (concavo-convex layer) 42 is formed, that is, the roughening treatment is performed, so that the adhesiveness with the upper insulating agent layer 44 is improved.

(10) 100 μm on both sides of the substrate 30 on which the insulating layer 44 and the adhesive layer 46 are formed in (9) above.
A photomask film on which a φ black circle is printed is brought into close contact and exposed at 500 mJ / cm ² by an ultra-high pressure mercury lamp. This is spray-developed with a DMDG solution, and further, the substrate is exposed at 3000 mJ / cm ² by an ultra-high pressure mercury lamp, and subjected to heat treatment (post-baking) at 100 ° C. for 1 hour and then at 150 ° C. for 5 hours. A thickness 35 having an opening (via-hole forming opening 48) of 100 μmφ excellent in dimensional accuracy equivalent to a photomask film.
An interlayer resin insulation layer (two-layer structure) 50 of μm is formed (see FIG. 8). In addition, the tin plating layer is partially exposed in the opening 48 serving as a via hole.

(11) Substrate 30 in which opening 48 is formed
Is immersed in chromic acid for 1 minute to dissolve and remove the epoxy resin particles on the surface of the adhesive layer 46 to roughen the surface of the interlayer resin insulation layer 50, and then to a neutralizing solution (manufactured by Shipley). Immerse and then wash with water (see FIG. 9). Further, a palladium catalyst (manufactured by Atotech Co., Ltd.) is applied to the surface of the roughened substrate to attach a catalyst nucleus to the surface of the interlayer resin insulating layer 50 and the inner wall surface of the via hole opening 48.

(12) The substrate is immersed in an electroless copper plating bath having the following composition to form an electroless copper plating film 52 having a thickness of 1.6 μm on the entire rough surface (see FIG. 10). [Electroless plating solution] EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α′-bipyridyl 80 mg / l PEG 0.1 g / l [Electroless plating conditions] 70 ° C. 30 minutes at the liquid temperature of

(13) A commercially available photosensitive dry film is attached to the electroless copper-plated film 52 formed in (12), a mask is placed, and exposure is performed at 100 mJ / cm ² .
Development is performed with 0.8% sodium carbonate to provide a plating resist 54 having a thickness of 15 μm (see FIG. 11).

(14) Next, electrolytic copper plating is applied to the resist non-formed portion under the following conditions to form an electrolytic copper plated film 56 having a thickness of 15 μm (see FIG. 12). [Electrolytic plating solution] Sulfuric acid 180 g / l Copper sulfate 80 g / l Additive (Atotech Japan, Kaparaside GL) 1 ml / l [Electrolytic plating conditions] Current density 1 A / dm ² hours 30 minutes Temperature room temperature

(15) The plating resist 54 is set to 5% KOH
After peeling and removing with, the electroless plating film 52 under the plating resist 54 is etched by a mixed solution of sulfuric acid and hydrogen peroxide to dissolve and remove, and a thickness formed of the electroless copper plating film 52 and the electrolytic copper plating film 56. 18 μm conductor circuit 58U, 5
8D and via holes 60U, 60D are formed (see FIG. 1).
3). Subsequently, the substrate 30 is immersed in 800 g / l of chromic acid for 3 minutes to remove the palladium catalyst nuclei remaining on the roughened surface.

(16) The substrate 30 on which the conductor circuits 58U and 58D and the via holes 60U and 60D are formed is copper sulfate 8 g / l, nickel sulfate 0.6 g / l, and citric acid 15 g.
/ L, sodium hypophosphite 29g / l, boric acid 31g
/ L, 0.1 g / l of a surfactant and pH = 9, and the surface of the conductor circuits 58U, 58D and the via holes 60U, 60D was dipped in an electroless plating solution of copper-nickel-phosphorus having a thickness of 3 μm. A roughened layer 62 is formed (see FIG. 14). Further, a Cu—Sn substitution reaction is performed under the conditions of tin borofluoride 0.1 mol / l, thiourea 1.0 mol / l, temperature 50 ° C. and pH = 1.2, and the surface of the roughened layer 62 has a thickness of 0. A Sn layer of 0.3 μm is provided (Sn layer is not shown).

(17) By repeating the above steps (2) to (16), an upper conductor circuit is formed.
That is, an interlayer resin insulating agent (for lower layer) is applied to both surfaces of the substrate 30 by roll coating to form the insulating agent layer 144. In addition, a photosensitive adhesive (for the upper layer) is formed on the insulating agent layer 144.
Is applied using a roll coater to form an adhesive layer 146 (see FIG. 15). Insulating agent layer 144 and adhesive layer 1
A photomask film is adhered to both surfaces of the substrate 30 on which the 46 is formed, exposed and developed to form an interlayer resin insulating layer 150 having an opening (opening 148 for forming a via hole), and then the interlayer resin insulating layer 150 is formed. The surface is roughened (see FIG. 16). Then, an electroless copper plating film 152 is formed on the surface of the substrate 30 that has been roughened (see FIG. 17). Subsequently, a plating resist 154 is provided on the electroless copper-plated film 152, and then an electrolytic copper-plated film 156 is formed on the resist non-formed portion (see FIG. 18). After removing the plating resist 154 with KOH, the electroless plating film 152 under the plating resist 54 is dissolved and removed, and the conductor circuits 158U, 158D and the via holes 160 are removed.
U and 160D are formed (see FIG. 19). Further, the conductor circuits 158U, 158D and the via holes 160U,
A roughening layer 162 is formed on the surface of 160D to complete the package substrate (see FIG. 20).

(19) Then, solder bumps are formed on the above-mentioned package substrate. First, the preparation of the solder resist composition for solder bumps will be described. Here, the epoxy group 50 of 60 wt% cresol novolac type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG is used.
% Acrylic acid-sensitized oligomer (molecular weight 4
000) 46.67 g, 80% by weight of a bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001) of 80% by weight dissolved in methyl ethyl ketone, 15.0 g of imidazole curing agent (manufactured by Shikoku Kasei, 2E4MZ-CN) 1.6.
g, a polyvalent acrylic monomer (R604, manufactured by Nippon Kayaku), which is a photosensitive monomer, 1.5 g of the same polyvalent acrylic monomer (DPE6A, manufactured by Kyoeisha Chemical Co., Ltd.), a dispersion type defoaming agent (S-65, manufactured by San Nopco). ) 0.71 g are mixed, and 2 g of benzophenone (manufactured by Kanto Kagaku) as a photoinitiator and 0.2 g of Michler's ketone (manufactured by Kanto Kagaku) as a photosensitizer are added to the mixture to obtain a viscosity. 25
A solder resist composition adjusted to 2.0 Pa · s at 0 ° C. is obtained.

(20) The solder resist composition is applied to both surfaces of the wiring board obtained in (18) above in a thickness of 20 μm. Then, after performing a drying treatment at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes, a circular pattern (mask pattern)
A photomask film having a thickness of 5 mm, in which is drawn, is placed in close contact with it, exposed to ultraviolet rays of 1000 mJ / cm ² , and DMTG developed. And 1 more at 80 ℃
Hour, 100 ° C for 1 hour, 120 ° C for 1 hour, 150 ° C
Then, the solder resist layer (thickness 20 μm) 70 having a solder pad portion (including a via hole and its land portion) 71 opened (upper surface side opening diameter 200 μm, lower surface side opening diameter 600 μm) is formed by heat treatment for 3 hours. Yes (Fig. 2
1).

(21) Next, the substrate 30 on which the solder resist layer 70 is formed is nickel chloride 30 g / l, sodium hypophosphite 10 g / l, sodium citrate 10 g.
20 for electroless nickel plating solution of pH = 5 consisting of 1 / l
By immersing for a minute, a nickel plating layer 72 having a thickness of 5 μm is formed in the opening 71 (see FIG. 22). Further, the substrate 30 was immersed in an electroless gold plating solution containing 2 g / l of potassium gold cyanide, 75 g / l of ammonium chloride, 50 g / l of sodium citrate and 10 g / l of sodium hypophosphite at 93 ° C. Immerse for 2 seconds, nickel plating layer 7
A gold plating layer 74 having a thickness of 0.03 μm is deposited on the upper surface of the substrate 2, solder pads 75U having a diameter of 133 to 170 μm are formed on the upper surface, and solder pads 75D having a diameter of 600 μm are formed on the lower surface.

(22) Then, the solder resist layer 70
Solder bumps 76U and 76D are formed by printing a solder paste on the solder pads 75U and 75D in the opening 71 of the solder paste and reflowing at 200 ° C.
The package substrate 100 having 6U and 76D is completed.

The package substrate 100 shown in FIG.
The IC chip 80 is attached as shown in FIG. Here, first, the solder bump 76U of the package substrate 100 is
The C chip 80 is placed so that the solder pads 82 of the IC chip correspond, and the solder pads 76U of the package substrate 100 are moved to the IC chip 8 by passing through the heating furnace.
The package substrate 100 and the IC chip 80 are connected to each other by being fused to the solder pad 82 of No. 0.

Thereafter, the solder flux exuded when the solder bumps 76U are fused and solidified on the solder pads 82 by heating is purified. Here, an organic solvent such as chlorocene is poured into the gap between the IC chip 80 and the package substrate 100 to remove the solder flux. After that, a resin is filled in a gap between the IC chip 80 and the package substrate 100 to perform resin sealing. Although not shown, mounting of the IC chip 80 is completed by simultaneously molding a resin on the entire IC chip 80.

Subsequently, the package substrate 100 is attached to the mother board 90. The solder bumps 76D of the package substrate 100 are placed so as to correspond to the solder pads 92 of the motherboard, and the solder pads 76D of the package substrate 100 are fused to the solder pads 92 of the motherboard 90 by passing through a heating furnace. , The package substrate 100 and the mother board 90 are connected. After that, as shown in FIG. 23, the package substrate 1
The resin 94 is filled in the gap between 00 and the mother board 90, the resin is sealed, and the mounting is completed.

Next, a package substrate 200 according to the second embodiment of the present invention will be described with reference to FIGS. 23 and 24. In the package substrate 100 of the first embodiment described above with reference to FIG. 22, one solder bump 76D is placed in one via hole 160D. On the other hand, in the package substrate 200 of the second embodiment, as shown in FIG. 24, one solder bump 276 is placed in the plurality (three) of via holes 260, 260, 260. That is, FIG. 2 corresponding to the X1-X1 cross section of FIG.
5 (X2-X2 line in FIG. 25 is X1-X1 in FIG. 24)
(Equivalent to a line), three via holes 260 are formed close to each other, and the nickel plating layer 72 and the gold plating layer 74 are formed on the common land portion 260a of the three via holes 260. One big land 2
75 is formed. And the big land 275
A large solder bump 276 is mounted on the.

The package substrate 200 of this second embodiment
In the above, by forming the solder bump 276 in the via hole 260, the solder bump 276 and the via hole 26 can be formed.
0 is directly connected to the package substrate 20.
Even if 0 is cracked, no disconnection occurs between the solder bump 276 and the via hole 260. Also, the solder bump 2
Since 76 is formed in the plurality of via holes 260, 260, 260, even if one of the plurality of via holes is not connected to the conductor circuit 58D in the inner layer, the solder bumps 27 are formed in the other via holes. And inner layer conductor circuit 58D
Since it can be connected, phase safety can be realized.

As described above, the solder pad 75U on the IC chip 80 side is formed to have a diameter of 133 to 170 μm, and the solder pad 75D on the motherboard side has a diameter of 60.
The size is 0 μm and the size is 4 to 5 times different, and one via hole has a large solder pad 75D on the motherboard side.
Difficult to form. Therefore, in the package substrate 200 of the second embodiment, the solder bumps 276 are formed in the plurality of via holes 260, 260, 260 to form large solder bumps. Here, the above-mentioned second
In the embodiment, one solder bump is formed in three via holes, but one solder bump can be formed in two via holes and one solder bump can be formed in four or more via holes. Is.

In the first embodiment described above, the package substrate formed by the semi-additive method is illustrated, but it goes without saying that the structure of the present invention can be applied to the package substrate formed by the full-additive method. Further, in the above-described embodiment, the example in which the package substrate is directly attached to the mother board is described, but the package substrate of the present invention can be preferably used even when the package substrate is connected to the mother board via a sub board or the like. it can.

[0044]

As described above, in the package substrate according to claim 1, since the solder bumps are directly connected to the via holes by forming the solder bumps in the via holes, the package substrate is cracked. However, no disconnection occurs between the solder bump and the via hole.

In the package substrate according to the second aspect, the solder bump and the via hole are directly connected by forming the solder bump in the via hole. Therefore, even if the package substrate is cracked, the solder bump and the via hole are formed. There is no disconnection between and. Further, since the solder bumps are formed in the plurality of via holes, even if one of the plurality of via holes is not internally connected, the other via hole can be connected to the solder bump. Can realize phase-safe. Moreover, since the solder bumps are formed in the plurality of via holes, the solder bumps can be formed large with respect to the via holes.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process of a package substrate according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of the package substrate according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a manufacturing process of the package substrate according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a manufacturing process of the package substrate according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a manufacturing process of the package substrate according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a manufacturing process of the package substrate according to the first embodiment of the present invention.

FIG. 7 is a diagram showing a manufacturing process of the package substrate according to the first embodiment of the present invention.

FIG. 8 is a diagram showing a manufacturing process of the package substrate according to the first embodiment of the present invention.

FIG. 9 is a diagram showing a manufacturing process of the package substrate according to the first embodiment of the present invention.

FIG. 10 is a diagram showing a manufacturing process of the package substrate according to the first embodiment of the present invention.

FIG. 11 is a diagram showing a manufacturing process of the package substrate according to the first embodiment of the present invention.

FIG. 12 is a diagram showing a manufacturing process of the package substrate according to the first embodiment of the present invention.

FIG. 13 is a diagram showing a manufacturing process of the package substrate according to the first embodiment of the present invention.

FIG. 14 is a diagram showing a manufacturing process of the package substrate according to the first embodiment of the present invention.

FIG. 15 is a diagram showing a manufacturing process of the package substrate according to the first embodiment of the present invention.

FIG. 16 is a diagram showing a manufacturing process of the package substrate according to the first embodiment of the present invention.

FIG. 17 is a diagram showing a manufacturing process of the package substrate according to the first embodiment of the present invention.

FIG. 18 is a diagram showing a manufacturing process of the package substrate according to the first embodiment of the present invention.

FIG. 19 is a diagram showing a manufacturing process of the package substrate according to the first embodiment of the present invention.

FIG. 20 is a diagram showing a manufacturing process of the package substrate according to the first embodiment of the present invention.

FIG. 21 is a diagram showing a manufacturing process of the package substrate according to the first embodiment of the present invention.

FIG. 22 is a sectional view showing a package substrate according to the first embodiment of the present invention.

23 is a cross-sectional view showing a state where an IC chip is placed on the package substrate shown in FIG. 22 and attached to a mother board.

FIG. 24 is a sectional view showing a package substrate according to a second embodiment of the present invention.

25 is a cross-sectional view taken along the line X1-X1 of the package substrate of FIG.

FIG. 26 (A) is a cross-sectional view of a package substrate according to a conventional technique, FIG. 26 (B) is a view on arrow B of FIG. 26 (A), and FIG. It is a C arrow line view of FIG. 26 (A).

[Explanation of symbols]

30 core substrate 34U, 34D inner layer copper pattern 50 interlayer resin insulation layer 58U, 58D Conductor circuit 60U, 60D via hole 75U, 75D solder pad 76U, 76D Solder bump 150 interlayer resin insulation layer 160U via hole 260 via holes 275 solder pad 276 Solder bump

Claims (2)

(57) [Claims] 1. A solder bump formed on a surface of a side on which an IC chip is mounted and a surface of a side connected to another substrate by forming a multi-layered conductor circuit with a plurality of interlayer resin insulation layers interposed therebetween. A package substrate in which a resin is sealed between the surface on the side connected to the other substrate and the other substrate, and solder bumps on the surface connected to the other substrate are A package substrate formed in a via hole. 2. A solder bump is formed on a surface of a side on which an IC chip is mounted and a surface of a side connected to another substrate by forming a multilayer conductor circuit with a plurality of interlayer resin insulation layers interposed. A package substrate in which a resin is sealed between the surface on the side connected to the other substrate and the other substrate, and solder bumps on the surface connected to the other substrate are A package substrate having a plurality of via holes.